Variable-Frequency Pulse Width Modulation Circuits for Resonant Wireless Power Transfer

energies

Article Variable-Frequency Pulse Width Modulation Circuits for Resonant Wireless Power Transfer

Li-Chuan Tang 1, Shyr-Long Jeng 2,* , Edward-Yi Chang 3 and Wei-Hua Chieng 1

1 Department of Mechanical Engineering, College of Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan; [email protected] (L.-C.T.); [email protected] (W.-H.C.) 2 Department of Mechanical Engineering, Lunghwa University of Science and Technology, Taoyuan City 333326, Taiwan 3 Department of Material Science and Engineering, College of Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan; [email protected] * Correspondence: [email protected]; Tel.: +886-2-82093211 (ext. 5113)

Abstract: In this paper, we develop a variable-frequency pulse width modulation (VFPWM) circuit for input control of 6.78-MHz resonant wireless power transfer (WPT) systems. The zero-voltage switching control relies on the adjustments of both duty cycle and switching frequency for the class-E amplifier used in the WPT as the power transmission unit. High-frequency pulse wave modulation integrated circuits exist, but some have insufficiently high frequency or unfavorable resolution for duty cycle tuning. The novelty of this work is the VFPWM circuit design that we put together. A voltage-controlled oscillator (VCO) of radio frequency and capacitor-coupled difference amplifiers are used to simultaneously perform the frequency and duty cycle tuning required in resonant WPT applications. Different circuit topologies of VFPWM are compared analytically and numerically. The most favorable circuit topology, enabling independent control of the frequency and duty cycle, is Citation: Tang, L.-C.; Jeng, S.-L.; employed in experiments. The experimental results demonstrate the validity of the novel VFPWM, Chang, E.-Y.; Chieng, W.-H. which is capable of operating at 6.78-MHz and has a duty ratio adjustable from 20% to 45% of the Variable-Frequency Pulse Width range applicable in the resonant WPT applications. Modulation Circuits for Resonant Wireless Power Transfer. Energies 2021, 14, 3656. https://doi.org/ Keywords: wireless power transfer (WPT); class-E amplifier; voltage-controlled oscillator (VCO); 10.3390/en14123656 variable-frequency pulse width modulation (VFPWM); difference amplifier

Academic Editors: Nicu Bizon and William Holderbaum 1. Introduction Received: 1 April 2021 Wireless power transfer (WPT) [1] offers a novel means of delivering energy from a Accepted: 15 June 2021 power source to a target load through the air instead of the wire that is conventionally Published: 19 June 2021 used for electricity-powered devices. The WPT method has excellent flexibility and non- contact characteristics. In the near future, it will be an ideal technical solution for powering Publisher’s Note: MDPI stays neutral electrical equipment in various applications within certain fields; for example, it will be with regard to jurisdictional claims in ideal for portable electronic devices, implantable medical devices, integrated circuits (ICs), published maps and institutional affil- solar-powered satellites, electric vehicles, and unmanned aerial vehicles. Inductive power iations. transfer (IPT) is based on the changing magnetic field generated by alternating currents in the primary coil when the voltage and current induced through the air gap in the secondary coil. IPT is the most widely used WPT technology. The class-E power amplifier [2,3] is simple and highly efficient in WPT applications, Copyright: © 2021 by the authors. providing an additional degree of design freedom that enables optimal WPT operation over Licensee MDPI, Basel, Switzerland. a wide range of operating conditions [4]. However, class-E power amplifiers still suffer This article is an open access article from sensitivity to the changes in load impedance values due to changing distance from distributed under the terms and the receiver to the transmitter or changes in the orientation of the receiver. Compensation conditions of the Creative Commons methods include replacing the capacitor on the receiver side and adjusting the switching Attribution (CC BY) license (https:// frequency, as proposed in [3], controlling the duty cycle and the DC feed inductance, as creativecommons.org/licenses/by/ proposed in [5,6], and implementing a voltage-controlled capacitor and a NIC (Negative 4.0/).

Energies 2021, 14, 3656. https://doi.org/10.3390/en14123656 https://www.mdpi.com/journal/energies Energies 2021, 14, 3656 2 of 25

Impedance Converter), as proposed in [7]. High efficiency can be achieved by apply- ing zero-voltage switching (ZVS) and zero-current switching (ZCS) by monitoring and tuning the inductive link dynamically. The ZVS produces soft switching at a switching frequency in the megahertz range. Furthermore, the impedance matching approach [8], charging/discharging the ultra-capacitor bank [9], and regulating the self/mutual inductance [10] are useful for tracking the maximum efficiency and improving system stability. Class-E power amplifiers belong to the class of high-frequency, high-efficiency electronic power circuits [11,12] that simultaneously consider the effects of the transistor’s parasitic elements [13,14]. Class-E power amplifiers use transformers with loosely coupled windings, where the coupling coefficient k can range from 0 to 0.9. Changes in the coupling coefficient over a wide range may cause the inverter to operate under non-ZVS conditions, thereby decreasing the efficiency. The challenging task is to ensure ZVS operation over a wide range of coupling coefficients. Because operation occurs in a relatively high-frequency range, the power efficiency is limited by the switching device and the associated control scheme. Compared with silicon-based devices, GaN high-electron-mobility transistors (HEMTs) have a much lower gate charge and lower output capacitance. GaN HEMTs have excellent performance for input signals with different duty cycles, making it possible to realize high-efficiency operations and considerably improve efficiency [15,16]. The currents flowing through the magnetizing inductance and load are distributed such that the transistor operates at ZVS over a wide range of loads and coupling coefficients. The adjustable duty cycle control scheme achieves maximum power transfer in the resonant wireless power transfer system. The pulse width modulation (PWM) duty control method is a widely used approach in IC design because digital signal processors can easily provide the required signal. However, most platforms for generating PWM signals only support applications in the tens of kilohertz range. These solutions are not suitable for applications where GaN operates in the megahertz frequency range. One means of overcoming this limitation is using a field- programmable gate array (FPGA) device, which can generate high-precision PWM signals with key parameters such as duty cycle and frequency even if the operating frequency increases to tens of megahertz [17]. The main advantages of FPGA-based controllers are rapid response, precise switching, and flexible adjustment of the dead time and switching frequency. These advantages are suitable for driving numerous semiconductor-switching devices in practical applications. Tavares et al. [18] presented a static power converter developed using an FPGA platform; this converter was able to generate a PWM gating signal with a frequency reaching 2 MHz for driving GaN power field-effect transistors (FETs). PWM is usually implemented using a voltage comparator that compares a reference voltage with a generated sawtooth signal. However, when the operating frequency increases, the comparator should complete the comparison within a few tens of nanoseconds. This causes PWM controllers based on the ramp comparator to malfunction, meaning that additional effort must be spent to adapt to megahertz operation. Digital PWM (DPWM) is implemented using a counter and comparison structure and resembles analog PWM based on sawtooth signals. The functionality is as follows: if the duty cycle command exceeds the counter value, which is equivalent to a sawtooth signal, the output is ON; when the counter reaches the duty cycle, the output turns OFF. Compared with the sequential encoding method, one-hot encoding and Gray encoding methods with fewer states are used to create varying pulses [19]. However, high resolution cannot be obtained, because the minimum time step is equal to the clock period of the counter. In addition, the power consumption is directly proportional to the clock frequency [20]. To address this issue, a delay-line-based voltage-to-duty-cycle (V2D) technique was presented that did not use any comparators. Cheng et al. [21] presented a delay-line DPWM architecture based on a phase-locked loop (PLL) and carry chain flag. This architecture had three parts: the first coarse delay module based on a counter, the second coarse delay module based on a PLL, Energies 2021, 14, 3656 3 of 25

and the fine delay module based on a carry chain. The main purpose is to compensate for the propagation delay through the tool command language, because propagation delays in the internal logics and interconnects may increase the duty cycle, thereby affecting the regulation performance of the converter, especially when the delay is of the same magnitude as the switching period. The duty-cycle increment phenomenon caused by superposition of critical path delays affects the regulation performance of converters with a switching frequency of tens of megahertz or higher. Huang et al. [22,23] used two voltage-to-delay cells to convert the voltage difference into a delay-time difference. A charge pump was used to charge or discharge the loop filter depending on whether the feedback voltage was larger or smaller than the reference voltage. A V2D controller based on delay-line control techniques was implemented to replace the classical ramp-comparator-based V2D controller and achieve a wide duty cycle, which was employed in a digitally controlled voltage-mode buck converter. The main advantages of delay-line DPWM are high resolution and low power consumption. However, this method exhibits low linearity and non-monotonic behavior in some cases. For a class-E dc–dc converter, the accuracy of the frequency, phase, and pulse width of the signal is critical in circuit applications. Within the similar context of delay-line DPWM, this paper proposes a PWM method enabling a switching frequency of up to 7 MHz for driving a GaN power FET. In the first stage, a voltage-controlled oscillator (VCO) is used to generate periodic square signals of variable frequency. The frequency of the output voltage can be varied using the input dc voltage. The duty cycle generator of the second stage is designed to have two functions: to generate a duty cycle of less than 50% and achieve wide range correction. This paper is organized as follows. Section2 briefly introduces the class-E amplifier circuit and the specifications and characteristics of the GaN FET. Section3 describes the proposed circuit and provides derivations. Then, we illustrate and simulate different capacitor-coupled difference amplifiers (CCDAs) in Section4. The experimental results obtained to validate the duty generation circuit are provided in Section5. Finally, the conclusions and some high-frequency GaN-based potential power applications that could take advantage of the present work are presented in Section6.

2. Class-E Amplifier Circuit and the Gate Drive The high-level block diagram for the resonant wireless power transfer system shown in Figure1a consists of four modules, including the tuning strategy for the WPT, the xCCDA design, the VFPWM feedback control, and the class-E amplifier for wireless power transfer. The class-E amplifier as shown in Figure1b, which consists of a VFPWM circuit that generates the switching signal to the gate drive, is used in resonant WPT applications. The nominal values of the circuit parameters on the switching power supply side (or the transmitter side) and the equivalent values on the impedance load side (or the receiver side together with the transmitter antenna) are shown in Table1. The load impedance is simplified into a resistor RL with a capacitor C2. The capacitor CDS is the parasitic capacitor of the D-mode GaN HEMT. A charge pump gate drive with output voltage vGS from 0 to a negative voltage (e.g., −7 V) is used to turn the GaN HEMT on and off according to the signal vs from 5 to 0 V. The GaN HEMT, which has no body diode, is periodically switched to form a sinusoidal resonant current i2. In the equivalent circuit, as shown Figure1, the power transfer efficiency (PTE) is defined as the output power on the receiver Pout = i2vL divided by the input power on the transmitter Pin = i1VDD. The switching of the GaN HEMT transistor M1, including the switching frequency and turn-on time duty, directly determines the distance and efficiency of the WPT application. The experimental layout is shown in Figure2. In our previous paper [ 24], the governing equations of the ZVS control for a class-E WPT unit was derived. The ZVS and its derivative, the zero- current switching (ZCS), conditions are achieved by adjusting the duty cycle and resonant frequency simultaneously. In the previously published paper [25], a minimum power input control strategy was proposed, which results in the switching frequency fo and the duty Energies 2021, 14, 3656 4 of 25

resonant frequency simultaneously. In the previously published paper [25], a minimum

power input control strategy was proposed, which results in the switching frequency fo and the duty cycle δ the WPT being based on empirical data or equations that can yield the optimal power transfer efficiency.

The switching frequency fo and the duty cycle δ are subsequently converted into the input voltages of the PWM generator, which consists of the VCO and capacitor-coupled Energies 2021, 14, 3656 4 of 25 difference amplifier to form a variable-frequency PWM module. The VFPWM module

generates a switching signal vS to the gate driver. In Figure 1, 𝐺 is the zero-order hold

transfer function matrix that converts the switching frequency fo and the duty cycle δ into cycle δ the WPT being based on empirical data or equations that can yield the optimal the corresponding voltages VF and Vδ, which is described in detail in the following sections power transfer efﬁciency. with respect to different VFPWM topologies.

Class-E Amplifier Frequency and Duty xCCDA VFPWM (Section 2) Cycle Tuning (Sec- (Section 3) (Section 4) and Wireless tion 2) Power Transfer (Section 5) (a)

DS fo: Switching Frequency v δ : Duty cycle iD i1 i2 VFPWM C2 Minimum CDS L2 f M1 Power o VF L1

Input δ Vδ VCO + Gate Gz vS vGS VDD RL Control xCCDA Drive vL [25] Impedance load side Switching power supply side

(b)

Figure 1. Implementation of the WPT system: (a) high-level block diagram and (b) class-E ampliﬁer as the power Figure 1. Implementation of the WPT system: (a) high-level block diagram and (b) class-E amplifier as the power trans- transmissionmission unit. unit.

TableTable 1. 1.Parameters Parameters used used in in the the class-E class-E ampliﬁer amplifier model model and and charge charge pump pump gate gate drive. drive.

SymbolSymbol ParameterParameter ValueValue UnitUnit

RRLL Equivalent Loading Loading 5 5 kΩ kΩ CC22 EquivalentEquivalent Coupling Capacitance Capacitance on on PRU PRU 75 75 pF pF L Equivalent Inductance of the PRU 8 µH L22 Equivalent Inductance of the PRU 8 µH L1 Inductance of the PTU 47 µH L1 Inductance of the PTU 47 µH CDS Parasitic Capacitance of GaN HEMT 75 pF DS CRG,p ParasiticTurn-on Capacitance Gate Resistance of GaN HEMT 12 75 Ω pF RRG,pG,n Turn-onTurn-off Gate Gate Resistance Resistance 30 12 Ω Ω RCG,nC ChargeTurn-off Pump Gate Capacitance Resistance 5 30 nF Ω CGS Parasitic Capacitance of GaN HEMT 140 pF CC Charge Pump Capacitance 5 nF IR Diode Reverse Saturation Current 50 µA CGS Parasitic Capacitance of GaN HEMT 140 pF IR Diode Reverse Saturation Current 50 µA The switching frequency fo and the duty cycle δ are subsequently converted into the input voltages of the PWM generator, which consists of the VCO and capacitor-coupled difference ampliﬁer to form a variable-frequency PWM module. The VFPWM module

generates a switching signal vS to the gate driver. In Figure1, Gz is the zero-order hold transfer function matrix that converts the switching frequency fo and the duty cycle δ into the corresponding voltages VF and Vδ, which is described in detail in the following sections with respect to different VFPWM topologies. Energies 2021, 14, 3656 5 of 25 Energies 2021, 14, 3656 5 of 25

Antenna (behind the painting)

Power receiving

Class-E amplifier –power units (PRU) transmitting unit (PTU)

5V, 12V PTU PTU vs VFPWM Low- Class-E Inductance VDD Amplifier Power Supply Resistor as

Figure 2. Experimental layout. Figure 2. Experimental layout. 2.1. Charge Pump Gate Drive 2.1. Charge Pump Gate Drive The charge pump gate drive presented by Okamoto [26] is useful in class-E amplifiers. The previousThe charge disadvantage pump gate of drive charge presented pump circuits—the by Okamoto leakage [26] is useful of current in class-E through amplifi- the diodeers. reverseThe previous saturation disadvantage current—is of not charge a problem pump because circuits—the of the high-frequencyleakage of current switching. through the diode reverse saturation current—is not a problem because of the high-frequency However, the class-E amplifier still suffers the effect of CGD linking to the high voltage switching. However, the class-E amplifier still suffers the effect of 𝐶 linking to the high switching of vDS. As illustrated in Figure3, we first assume that vDS floating. The correspondingvoltage switching gate driveof 𝑣 design. As illustrated parameters in areFigure presented 3, we first in Table assume1. that 𝑣 is floating. TheAs corresponding shown in Figure gate3 ,drive the gate design drive parameters receives theare PWMpresented signal in fromTable a1. PWM circuit. This PWMAs shown circuit in is Figure capable 3, ofthe operating gate drive at receives an adjustable the PWM frequency signal from around a PWM 6.78 MHz,circuit. andThis the PWM duty circuit cycle isis adjustablecapable of fromoperating 20% toat 50%,an adjustable meaning frequency that the gate around drive 6.78 can MHz, be successfullyand the duty switched cycle is toadjustable perform from the WPT 20% to task. 50%, High-frequency meaning that the PWM gate ICs drive such can as be the suc- TIcessfully SLUS489 switched with the maximumto perform frequency the WPT oftask. 2 MHz High-frequency cannot meet PWM the required ICs such frequency as the TI ofSLUS489 6.78 MHz. with The the other maximum commercially frequency PWM of 2 IC,MH thez cannot AD9560, meet is the a high-speed, required frequency digitally of programmable6.78 MHz. The pulse other width commercially modulator PWM with anIC, output the AD9560, pulse width is a high-speed, proportional digitally to an 8-bit pro- datagrammable input value. pulse The width pulse modulator width can bewith changed an output every pulse clock width cycle byproportional up to 50 MHz. to an The 8-bit drawbacksdata input of value. this IC The include pulse the width requirement can be chan of aged high-speed every clock digital cycle processor by up to such50 MHz. as the The ESP8266drawbacks Wi-Fi of module this IC toinclude fulfill the 6.78-MHzrequirement control, of a high-speed which means digital that itprocessor cannot be such used as in the low-costESP8266 applications, Wi-Fi module and to that fulfil thel the 8-bit 6.78-MHz resolution control, for the which output me pulseans widththat it iscannot insufficient be used forin resonant low-cost tuning applications, in 6.78-MHz and that resonant the 8-bit WPT resolution applications for the in output practice. pulse The width purpose is insuf- of thisficient paper for is resonant to construct tuning a low-cost, in 6.78-MHz PWM, resonant high-frequency-resolution WPT applications in circuit practice. feasible The forpur- 6.78-MHzpose of this resonant paper WPTis to construct applications. a low-co A VCOst, PWM, or voltage-to-frequency high-frequency-resolution converter circuit may be fea- usefulsible forfor the6.78-MHz frequency resonant control WPT needed applications. for resonant A VCO WPT; or however,voltage-to-frequency the ICs are usuallyconverter designedmay be foruseful a 50% for duty the frequency cycle. To achieve control WPT needed with for a transmissionresonant WPT; of 100however, cm and the greater, ICs are

Energies 2021, 14, 3656 6 of 25

usually designed for a 50% duty cycle. To achieve WPT with a transmission of 100 cm and greater, such as that shown in Figure 2, adjustments to both the frequency and duty cycle such as that shown in Figure2, adjustments to both the frequency and duty cycle are are required. We require a circuit that converts the VCO signal into the variable-frequency required. We require a circuit that converts the VCO signal into the variable-frequency pulsepulse width width modulation modulation (VFPWM) (VFPWM) wave form.form. InIn thethe following following sections, sections, we we ﬁrst first introduce intro- ducethe differencethe difference ampliﬁer amplifier coupled coupled with with capacitors capacitors that canthat convert can convert a 50% a duty50% cycleduty squarecycle squarewave wave into a into PWM a PWM signal. signal.

VGH vDS Charge pump reservoir CGD

UVLO RG,p

vG M1 vS iG

CC CGS Cj0

RG,n

VGL VSS

Figure 3. Gate drive design. Figure 3. Gate drive design. 2.2. The Minimum Power Input Control Strategy 2.2. TheBy Minimum controlling Power the Input duty ratioControlδ and Strategy the switching frequency simultaneously, minimum powerBy controlling input control the [25duty], which ratio δ trades and the off switching the PDL (Power frequency Delivered simultaneously, to Load) formini- the mumswitching power loss input of thecontrol GaN [25], HEMT, which can trades be used off to the obtain PDL the (Power optimal Delivered PTE (Power to Load) Transfer for theEfﬁciency). switching The loss minimum of the GaN power HEMT, input can controlbe used strategy, to obtain which the optimal concerns PTE the (Power feedback Trans- from ferPRU Efficiency). (Power ReceivingThe minimum Unit), power consists input of the control following strategy, steps. which concerns the feedback from PRUStep (Power 1. According Receiving to Unit), the PRU consists feedback of the regarding following the steps. distance between the PTU (PowerStep Transmitting1. According Unit) to the and PRU PRU feedback and the regarding power transfer the distance requirement between from the the PTU PRU, (Powerwe determine Transmitting the input Unit) voltage and PRUVDD and. The the input power voltage, transfer according requirement to the from experimental the PRU, Energies 2021, 14, 3656 7 of 25 wedata determine [24], as shownthe input in Figure voltage4, shouldVDD. The be tuned input to voltage, a low voltage according for short-rangeto the experimental WPT and dataa high [24], voltage as shown for in long-range Figure 4, WPT.should be tuned to a low voltage for short-range WPT and a high voltage for long-range WPT. 30

25 LowV is prefered DD 110V 60V

15 High VDD is prefered

5 Power Delivered to LoadPower Delivered (PDL; W)

0 0 20406080100 Distance (cm)

FigureFigure 4. 4.PDLPDL vs. vs. distance distance and and input input voltage voltage VDD.VDD .

Step 2. The input power of the PTU is determined from the feedback power requirement from all PRUs. Consequently, the duty cycle δ (or duty ratio %) is determined from the input power and the given input voltage VDD from Step 1. As shown in Figure 5, which is interpolated in [25], it is observed that the duty ratio δ% increases monotonically, in general, with increasing PTU input power.

0-10–1 1-21–2 2-32–3 3-43–4 4-54–5 5-65–6 6

2 1 Power Input Power Input (W) 0

22 DD 73.8 24.52 V 27.04 29.56 32.08 34.6 36 37.12 39.64 Duty ratio δ (%)

Figure 5. Power input vs. duty ratio % and Input voltage VDD.

Step 3. From the given input voltage VDD and the duty ratio δ% calculated in step 2, we determine the switching frequency f0 according to the empirical function shown in Figure 6, which is interpolated in [25].

Energies 2021, 14, 3656 7 of 25

25 LowV is prefered DD 110V 60V

15 High VDD is prefered

5 Power Delivered to LoadPower Delivered (PDL; W)

0 0 20406080100 Distance (cm) Energies 2021, 14, 3656 7 of 25 Figure 4. PDL vs. distance and input voltage VDD.

Step 2. The input power of the PTU is determined from the feedback power requirement fromStep all 2. PRUs. The input Cons powerequently, of the the PTU duty is cycle determined δ (or duty from ratio the %) feedback is determined power require-from δ thement input from power all PRUs.and the Consequently, given input thevoltage duty VDD cycle from(or dutyStep 1. ratio As %)shown is determined in Figure from5, whichthe inputis interpolated power and in the [25], given it is inputobserved voltage thatV theDD dutyfrom ratio Step δ 1.% As increases shown inmonotonically, Figure5, which δ in general,is interpolated with increasing in [25], it PTU is observed input power. that the duty ratio % increases monotonically, in general, with increasing PTU input power.

0-10–1 1-21–2 2-32–3 3-43–4 4-54–5 5-65–6 6

2 1 Power Input Power Input (W) 0

22 DD 73.8 24.52 V 27.04 29.56 32.08 34.6 36 37.12 39.64 Duty ratio δ (%)

Figure 5. Power input vs. duty ratio % and Input voltage VDD. Figure 5. Power input vs. duty ratio % and Input voltage VDD. Energies 2021, 14, 3656 Step 3. From the given input voltage VDD and the duty ratio δ% calculated8 inof step25

2,Step we determine 3. From the the given switching input frequencyvoltage VDDfo according and the duty to the ratio empirical δ% calculated function in shownstep 2, in weFigure determine6, which the isswitching interpolated frequency in [25]. f0 according to the empirical function shown in Figure 6, which is interpolated in [25]. 3.8-3.853.8–3.85 3.85-3.93.85–3.9 3.9-3.953.9–3.95 3.95-43.95–4.0

4.15 (MHz)

0 4.1 4.05 4 3.95 3.9

3.85 Switching Frequency f 3.8 DD

22 V 73.8 24.52 27.04 29.56 32.08 36 34.6 37.12 Duty ratio δ (%) 39.64

Figure 6. Desired switching frequency vs. duty ratio δ% and input voltage VDD. Figure 6. Desired switching frequency vs. duty ratio δ% and input voltage VDD. The goal of the minimum power input control strategy is to optimize the power efﬁciency of the WPT system when multiple PTUs and multiple PRUs are interacting. The The goal of the minimum power input control strategy is to optimize the power effi- control strategy will calculate the best switching frequency f and duty ratio δ% for each ciency of the WPT system when multiple PTUs and multiple oPRUs are interacting. The individual PTU. control strategy will calculate the best switching frequency 𝑓 and duty ratio 𝛿% for each individual2.3. Parameters PTU. of the Class-E Ampliﬁer and WPT System Two arrangements of PTU/PRU inductor settings are used in the experiments. The 2.3. Parameters of the Class-E Amplifier and WPT System data were reported in [24] and are reproduced in Table2. The distance between the PTU andTwo the PRU,arrangements as well as of the PTU/PRU orientation inductor of the settings PRU toward are used the in PTU, the affectsexperiments. the coupling The data were reported in [24] and are reproduced in Table 2. The distance between the PTU and the PRU, as well as the orientation of the PRU toward the PTU, affects the coupling coefficient in the wireless power transfer. The tuning of both switching frequency fo and the duty ratio δ must respond to the coupling coefficient change dynamically in order to achieve the impedance matching condition. The nominal input/output parameters of the class-E amplifier and WPT system in this research are shown in Table 3. The nominal values are only reference values for typical 10 W and 40 cm distance resonant WPT applications.

Table 2. Coil specifications used in the WPT experiments in this paper [24].

Inductance Capacitance Resistor SRF Inductor ID Q Factor (uH) (pF) (Ohm) (MHz) Tx1 8.87 28.54 0.128 4.364 10.00 Tx2 8.88 28.53 0.128 4.342 9.99 Rx1 9.03 27.7 0.081 7.06 10.06 Rx2 9.05 27.9 0.074 7.66 10.02

Table 3. The nominal input/output parameters of the class-E amplifier and WPT system.

Symbol Unit Nominal Value Min. Value Max. Value VDD Volt 108 36 300 fo MHz 4.1 3.8 4.4 δ (%) 30 20 40 PDL * Watt 5 0.1 20 vDS volt 400 100 800 iD Ampere 0.05 0.01 0.2

Energies 2021, 14, 3656 8 of 25

coefficient in the wireless power transfer. The tuning of both switching frequency fo and the duty ratio δ must respond to the coupling coefficient change dynamically in order to achieve the impedance matching condition. The nominal input/output parameters of the class-E amplifier and WPT system in this research are shown in Table3. The nominal values are only reference values for typical 10 W and 40 cm distance resonant WPT applications.

Energies 2021, 14, 3656 9 of 25 Table 2. Coil speciﬁcations used in the WPT experiments in this paper [24].

Inductance Capacitance Resistor SRF Inductor ID Q Factor PDL (Power Delivered to Load)(uH) *: based on(pF) a single PTU to(Ohm) multiple PRUs and calculated from(MHz) summationTx1 on all the individual 8.87 power received 28.54 by the PRUs. 0.128 4.364 10.00 Tx2 8.88 28.53 0.128 4.342 9.99 3. CCDAsRx1 9.03 27.7 0.081 7.06 10.06 TwoRx2 types of CCDA, 9.05 common mode 27.9 and difference 0.074 mode, are discus 7.66sed in detail 10.02 in this section. Table 3. The nominal input/output parameters of the class-E ampliﬁer and WPT system. 3.1. Difference-Mode CCDA Symbol Unit Nominal Value Min. Value Max. Value The difference-mode CCDA (dCCDA), illustrated in Figure 7, consists of the standard V Volt 108 36 300 arrangementDD of a difference amplifier and a capacitor inserted between the noninverting fo MHz 4.1 3.8 4.4 and invertingδ (%) terminals. The capacitor is referred 30 to as a differential-mode 20 capacitor. 40 AssumingPDL * an operational Watt amplifier of zero 5offset voltage, an 0.1 output resistance 20that is v volt 400 100 800 negligibly small,DS and an input resistance that is much larger than 𝑅, we obtain iD Ampere 0.05 0.01 0.2 PDL (Power Delivered to Load) *: based on a single PTU to multiple PRUs and calculated from summation on all (1 + 𝛼)𝑣(𝑠) − 𝛼𝑣(𝑠) the individual power received by the𝑖 PRUs.= (1) 𝛼𝑅 3. CCDAs The difference voltage is Two types of CCDA, common mode and difference mode, are discussed in detail in this section. 𝑖 𝛼𝑣(𝑠) − (1 + 𝛼)𝑣 (𝑠) 𝑣(𝑠) = − = (2) 𝑠𝐶 𝛼𝑅𝐶𝑠 3.1. Difference-Mode CCDA or The difference-mode CCDA (dCCDA), illustrated in Figure7, consists of the standard arrangement of a difference ampliﬁer𝛼𝑣 and(𝑠) a capacitor − 𝛼𝑅𝐶𝑠𝑣 inserted(𝑠) between the noninverting 𝑣(𝑠) = (3) and inverting terminals. The capacitor is referred1+𝛼 to as a differential-mode capacitor.

𝛼𝑅

𝑖 𝑣 𝑅 𝑉 𝑣

𝑖 𝑣 𝐶 𝑣 𝐴 𝑣 𝑖~0 𝑣 𝑅

𝛼𝑅

FigureFigure 7. The 7. ThedCCDA dCCDA circuit. circuit.

The output voltage is

𝑚𝑖𝑛(𝑉, 𝐴𝑣(𝑡)) if 𝑣 (𝑡) > 0 𝑣(𝑡) = 0if 𝑣(𝑡) ≤ 0 The voltage on the inverting terminal of the operational amplifier is then derived as

𝑣(𝑠) = 𝑣 (𝑠) − 𝑣 (𝑠)

Additionally, when 𝑣(𝑡) > 0, we have

𝛼𝑣(𝑠) + 𝑣 (𝑠) − (1 + 𝛼)𝑣 (𝑠) 𝑖 = (4) 𝛼𝑅

If 𝑣(𝑡) ≤ ,0 we have

Energies 2021, 14, 3656 9 of 25

Assuming an operational ampliﬁer of zero offset voltage, an output resistance that is negligibly small, and an input resistance that is much larger than R, we obtain

(1 + α)vp(s) − αv2(s) i = (1) dm αR The difference voltage is

idm αv2(s) − (1 + α)vp(s) vd(s) = − = (2) sCdm αRCdms or αv (s) − αRC sv (s) v (s) = 2 dm d (3) p 1 + α The output voltage is min(VPS, Admvd(t)) if vd(t) > 0 vo(t) = 0 if vd(t) ≤ 0

The voltage on the inverting terminal of the operational ampliﬁer is then derived as

vn(s) = vp(s) − vd(s)

Additionally, when vd(t) > 0, we have

αv (s) + v (s) − (1 + α)v (s) i = 1 o n (4) dm αR

If vd(t) ≤ 0, we have

αV (s) − (1 + α)V (s) i = 1 n dm αR

Substituting Equation (1) into (4)—that is, when vd(t) > 0 and vo(t) = Admvd(t) are assumed—we have

2(1 + α)vp(s) − αv1(s) − αv2(s) = (Adm + 1 + α)vd(s) (5)

Let Tdm = αRCdm; Equation (5) can then be expressed as

(2(1 + α)Tdms + (Adm + 1 + α)(1 + α))vp(s) = αTdmsv1(s) + ((Adm + 1 + α)α + αTdms)v2(s) 0 Assuming that Adm (1 + α), and letting Tdm = Tdm/Adm, the above equation is simpliﬁed to

0 0 α Tdms 1 + Tdms vp(s) = 0 v1(s) + 0 v2(s) 1 + α 1 + 2Tdms 1 + 2Tdms Equation (2) yields v2(s) − v1(s) vd(s) = α 0 (6) Adm 1 + 2Tdms

Substituting Equation (1) into (5) and then Equation (3) for vd(t) ≤ 0, we have

v2(s) − v1(s) vd(s) = α (7) (1 + α) + 2Tdms Energies 2021, 14, 3656 10 of 25

Let v2(s) = VZ/s be a square-wave pulse train, VZ range from 0 to VPS, and v1(s) = Vre f /s, where 0 < Vre f < VPS; the difference voltage response for vd(t) > 0 is then obtained as

 −t α 2T0 1 − e dm VZ − Vre f + vd(0) if vd(t) > 0  Adm v (t) = d  −(1+α)t (8)  2T α 1 − e dm VZ − Vre f + vd(0) else

The corresponding output of the operational ampliﬁer is

 −t 2T0 min VPS, α 1 − e dm VZ − Vre f + vo(0) if vd(t) > 0 vo(t) =  (9) 0 else

Figure8 illustrates the response of vo and vd when the resistance R is large. In other applications with a low R, the difference ampliﬁer is governed by the ampliﬁer equation as follows: Energies 2021, 14, 3656 11 of 25 vo(t) = min VPS, α VZ − Vre f (10)

𝑇

𝛿𝑇 𝛼(𝑉 −𝑉)

𝑉 𝑣

𝑣

𝑣, 𝑒𝑞.(6) 𝛼(𝑉 −𝑉)

𝐴 0

𝑣,𝑒𝑞.(9)

−𝑉

FigureFigure 8. 8. ResponseResponse of of a adCCDA dCCDA with with large large resistance. resistance.

3.2. Common-ModeThe amplification CCDA is Adm if vd(t) > 0; the amplification is unity if vd(t) ≤ 0. The time constant in the case of v (t) ≤ 0 is A /(1 + α) times larger than that when v (t) > 0. The The common-moded CCDA (cCCDA),dm illustrated in Figure 9, consists ofd a standard analytical results are depicted in Figure8. arrangement of a difference amplifier and two capacitors added to the terminals. The ca- pacitors3.2. Common-Mode are referred CCDA to as common-mode capacitors. Assuming the operational amplifier has zero offset voltage, the output resistance is negligibly small, and the input resistance The common-mode CCDA (cCCDA), illustrated in Figure9, consists of a standard is much larger than 𝑅, we obtain arrangement of a difference amplifier and two capacitors added to the terminals. The capacitors are referred to as common-mode capacitors.𝑇𝑠 𝑣 Assuming(𝑠) the operational amplifier 𝑖, = (11) has zero offset voltage, the output resistance(1 + 𝛼 is negligibly + 𝑇 𝑠) 𝑅 small, and the input resistance is much larger than R, we obtain where 𝑇 =𝛼𝑅𝐶Tcms v2(s) icm,p = (11) (1 + α + Tcms) R

where: 𝛼𝑅 Tcm = αRCcm

𝑖 𝑣 𝑅 𝑉 𝑣 𝑖 , 𝑣

𝐶 𝑣 𝐴 𝑣 𝑖~0 𝑣 𝑖 𝑅 ,

𝐶 𝛼𝑅

Figure 9. The cCCDA circuit.

From the inverting terminal, the following is obtained:

𝑇𝑠 𝑣(𝑠) 𝑇𝑠 𝑣(𝑠) 𝑖, = + (12) (1 + 𝛼 + 𝑇 𝑠) 𝑅 (1 + 𝛼 + 𝑇 𝑠) 𝛼𝑅

Energies 2021, 14, 3656 11 of 25

𝑇

𝛿𝑇 𝛼(𝑉 −𝑉)

𝑉 𝑣 𝑣

𝑣, 𝑒𝑞.(6) 𝛼(𝑉 −𝑉)

𝐴 0

𝑣,𝑒𝑞.(9)

−𝑉

Figure 8. Response of a dCCDA with large resistance.

3.2. Common-Mode CCDA The common-mode CCDA (cCCDA), illustrated in Figure 9, consists of a standard arrangement of a difference amplifier and two capacitors added to the terminals. The capacitors are referred to as common-mode capacitors. Assuming the operational amplifier has zero offset voltage, the output resistance is negligibly small, and the input resistance is much larger than 𝑅, we obtain

𝑇𝑠 𝑣(𝑠) 𝑖, = (11) (1 + 𝛼 + 𝑇 𝑠) 𝑅 where

Energies 2021, 14, 3656 𝑇 =𝛼𝑅𝐶 11 of 25

𝛼𝑅

𝑖 𝑣 𝑅 𝑉 𝑣 𝑖 , 𝑣

𝐶 𝑣 𝐴 𝑣 𝑖~0 𝑣 𝑖 𝑅 ,

𝐶 𝛼𝑅

FigureFigure 9. 9. The cCCDA cCCDA circuit. circuit. From the inverting terminal, the following is obtained: From the inverting terminal, the following is obtained: Tcms v1(s) Tcms vo(s) icm,n = + (12) 𝑇𝑠 (𝑣1+(𝑠)α + Tcms) R𝑇𝑠 (1 + α +𝑣T(𝑠)cms) αR 𝑖, = + (12) The(1 difference + 𝛼 + voltage 𝑇 𝑠) is𝑅 (1 + 𝛼 + 𝑇 𝑠) 𝛼𝑅

αv2(s) vo(s) vd = − (1 + α + Tcms) (1 + α + Tcms)

or  α(v2(s)−v1(s)) if vd(t) > 0 (1+α+Adm+Tcms) vd(s) =  ( ( )− ( )) (13) α v2 s v1 s else (1+α+Tcms)

After the substitution of v2(t) = VZ and v1(t) = Vre f for vd(t) ≤ 0, the common-mode capacitor starts to charge to a positive voltage from time t = 0 in a steady state, such that

−(1+α)t vd(t) = 1 − e Tcm VZ − Vre f + vd(0) (14)

When vd(t) > 0, that is, after time t ≥ βT, the voltage of the common-mode capacitor rises for Adm 1 + α such that

−(1+α)(t−βT) α T0 vd(t) = 1 − e cm VZ − Vre f (15) Adm

Because δ + β = 0.5, after the time t ≥ T/2, we have v2(t) = 0, and the voltage of the common-mode capacitor decreases.

−(1+α)(t−T/2) vd(t) = 1 − e Tcm 0 − Vre f + vd(T/2) (16) Energies 2021, 14, 3656 12 of 25

Consequently, the minimum voltage on the common-mode capacitor is

vd(0) = vd(T) < 0 (17)

Assuming that vd is negligibly small during the time T/2 ≥ t ≥ βT, Equations (14)–(17) yield

−(1+α)βT −(1+α)βT −(1+α)T/2 − e Tcm VZ + e Tcm + e Tcm Vre f + VZ − 2Vre f = 0

−(1+α)T/2 −(1+α)βT Assuming that e Tcm e Tcm , we obtain ! T VZ − 2Vre f β = − cm ln (18) (1 + α)T VZ − Vre f

and ! 1 1 T VZ − 2Vre f δ = − β = + cm ln (19) 2 2 (1 + α)T VZ − Vre f

From Equations (16) and (19), the constraint for Vre f is 0 < Vre f < VZ/2. The smaller the Vre f , the higher the duty cycle δ. From Equation (19), it is conﬁrmed that δmax = 0.5, which is identical to the VCO output when Vre f = 0 V. The sensitivity of δ with respect to Vre f is derived as follows:

∂δ −6T V = cm Z (20) ∂V re f (1 + α) VZ − 2Vre f VZ − Vre f T

Equation (20) shows that we must reduce either R or Ccm and let α = 1 to ensure small sensitivity of Vre f to the duty cycle δ. When δ = 0 and α = 1, the higher bound for Vre f is obtained as follows: 1 − e−T/Tcm Vre f |δ=0 = VZ 2 − e−T/Tcm

For example, if T = 1/(4·MHz), Tcm = 10 kΩ·15 pF, and VZ = 5 V, the higher bound is calculated to be 2.24 V. Let V2(s) = VZ/s be a square-wave pulse train, VZ range from 0 to VPS, and 0 < Vre f < VPS; consequently, the corresponding output is

 −(1+α)t T0 min VPS, α 1 − e cm VZ − Vre f + vo(0) if vd(t) > 0 vo(t) =  0 else

The analytical results are depicted in Figure 10. It is difficult to compare Figures8 and 10, because they have two similar characteristics: fast charging of the coupled capacitor when the operational amplifier is functioning as a voltage amplifier, and slow charging of the capacitor when the operational amplifier is outputting zero voltage. However, they are different with respect to their time constant during slow charging. Energies 2021, 14, 3656 13 of 25

1−𝑒/ 𝑉| = 𝑉 2−𝑒/

For example, if 𝑇=1/(4∙MHz), 𝑇 = 10 kΩ ∙ 15 pF , and 𝑉 =5 V, the higher bound is calculated to be 2.24 V. Let 𝑉(𝑠) = 𝑉 /𝑠 be a square-wave pulse train, 𝑉 range from 0 to 𝑉 , and 0< 𝑉 < 𝑉; consequently, the corresponding output is () 𝑣(𝑡) =𝑚𝑖𝑛(𝑉 ,𝛼(1−𝑒 )(𝑉 −𝑉)+𝑣(0)) 𝑖𝑓 𝑣 (𝑡) > 0 0𝑒𝑙𝑠𝑒 The analytical results are depicted in Figure 10. It is difficult to compare Figure 8 and Figure 10, because they have two similar characteristics: fast charging of the coupled ca- Energies 2021, 14, 3656 pacitor when the operational amplifier is functioning as a voltage amplifier, and 13slow of 25 charging of the capacitor when the operational amplifier is outputting zero voltage. How- ever, they are different with respect to their time constant during slow charging.

𝑇

𝛽𝑇 𝛿𝑇 𝛼(𝑉 −𝑉)

𝑉 𝑣

𝑣 𝑣, 𝑒𝑞.(14) 𝑉 −𝑉

𝐴 0

𝑣, 𝑒𝑞. (15) −𝑉

FigureFigure 10. 10. ResponseResponse of of a cCCDA a cCCDA with with large large resistance. resistance.

4.4. CCDA CCDA Application Application ToTo validate validate the the applicability applicability of of the the CCDAs, CCDAs, in in this this section, section, two two designs designs are are illustrated, illustrated, analyzed, and applied using the cCCDA and dCCDA. analyzed, and applied using the cCCDA and dCCDA. Energies 2021, 14, 3656 4.1. VCO to VFPWM Using Low-Resistance dCCDA Feedback 14 of 25 4.1. VCO to VFPWM Using Low-Resistance dCCDA Feedback The block diagram of the dCCDA is shown in Figure 11. The transfer function of a low-resistanceThe block diagram dCCDA of typically the dCCDA yields is a shown difference in Figure ampliﬁer 11. unityThe transfer gain when functionα = 1. of a low-resistance dCCDA typically yields a difference amplifier unity gain when 𝛼=1.

𝑉 𝑣 0 0 𝑑𝐶𝐶𝐷𝐴 𝑣 𝑉 𝑣, 𝑓 𝑣

Figure 11. Block diagram of the dCCDA.

The function of a practical VCO, such as the IC-SN54LS628, as shown in Figure 12 as Figurean example, 11. Block can diagram be simpliﬁed of the into dCCDA. the following expression: fo = GZ0 VI( f req) − g VI(rng) (21) The function of a practical VCO, such as the IC-SN54LS628, as shown in Figure 12 as an example, can be simplified into the following expression: The nonlinear function g VI(rng) increases monotonically with increasing VI(rng), i.e., the voltage input to control the frequency𝑓 =𝐺 range(𝑉() of the−𝑔(𝑉 SN54LS628())) VCO. When the (21) voltage V ( ) increases, the feedback signal g V ( ) increases and the frequency fo The nonlinearI rng function 𝑔(V ) increasesI rng monotonically with increasing 𝑉 , decreases simultaneously. To be consistent() with our WPT application shown in Figure1, () i.e., the voltage input to control the frequency range of the SN54LS628 VCO. When the we deﬁned VF ≡ VI( f req) − g VI(rng) and GZ0 as the gain of the switching frequency to voltagevoltage 𝑉 transfer() function.increases, the feedback signal 𝑔(𝑉()) increases and the frequency 𝑓 decreases simultaneously. To be consistent with our WPT application shown in Figure 1, we defined 𝑉 ≡𝑉() −𝑔(𝑉()) and 𝐺 as the gain of the switching frequency to voltage transfer function.

Figure 12. Output frequency versus frequency-control input voltage of the SN54LS628 (courtesy of Texas Instruments Inc., Dallas, Texas).

The output 𝑣 of the dCCDA with low resistance and 𝛼=1 is presented as a simple difference amplifier as follows: 𝑉 −𝑉 𝑖𝑓 𝑉 >𝑉 𝑉 =𝑣 = () 0𝑒𝑙𝑠𝑒 The dCCDA can be derived from the intrinsic parasitic capacitance of the operational amplifier. As shown in Figure 13, when 𝑉() =0, the output of the VCO has a frequency of 𝐺𝑉 . When 𝑉() =𝑉 −𝑉 , the output of the VCO is in the frequency range 𝐺(𝑉() −𝑔(𝑉 −𝑉)). The sampling time for 𝑣 of the dCCDA is then written as follows: 2+𝑔(𝑉 −𝑉)/𝑉() 𝑇=𝐺 (22) 𝑉() −𝑔(𝑉 −𝑉)

The duty cycle of 𝑣 of the dCCDA can expressed as

Energies 2021, 14, 3656 14 of 25

𝑉 𝑣 0 0 𝑑𝐶𝐶𝐷𝐴 𝑣 𝑉 𝑣, 𝑓 𝑣

Figure 11. Block diagram of the dCCDA.

The function of a practical VCO, such as the IC-SN54LS628, as shown in Figure 12 as an example, can be simplified into the following expression:

𝑓 =𝐺(𝑉() −𝑔(𝑉())) (21)

The nonlinear function 𝑔(V()) increases monotonically with increasing 𝑉(), i.e., the voltage input to control the frequency range of the SN54LS628 VCO. When the voltage 𝑉() increases, the feedback signal 𝑔(𝑉()) increases and the frequency 𝑓 Energies 2021, 14, 3656 decreases simultaneously. To be consistent with our WPT application shown in Figure14 1, of 25 we defined 𝑉 ≡𝑉() −𝑔(𝑉()) and 𝐺 as the gain of the switching frequency to voltage transfer function.

FigureFigure 12. 12.OutputOutput frequency frequency versus versus frequency-control frequency-control inpu inputt voltage voltage of the of the SN54LS628 SN54LS628 (courtesy (courtesy of of TexasTexas Instruments Instruments Inc., Inc., Dallas, Dallas, Texas). Texas).

The output vo of the dCCDA with low resistance and α = 1 is presented as a simple The output 𝑣 of the dCCDA with low resistance and 𝛼=1 is presented as a simple differencedifference amplifier ampliﬁer as asfollows: follows: 𝑉VPS−𝑉−Vre f 𝑖𝑓if V 𝑉 PS>𝑉> Vre f V𝑉()==𝑣v == I(rng) o 0𝑒𝑙𝑠𝑒0 else Energies 2021, 14, 3656 The dCCDA can be derived from the intrinsic parasitic capacitance of the operational15 of 25 The dCCDA can be derived from the intrinsic parasitic capacitance of the operational amplifier. As shown in Figure 13, when 𝑉() =0, the output of the VCO has a frequency ampliﬁer. As shown in Figure 13, when VI(rng) = 0, the output of the VCO has a frequency of 𝐺𝑉 . When 𝑉() =𝑉 −𝑉 , the output of the VCO is in the frequency range of GZ0VF. When VI(rng) = VPS − Vre f , the output of the VCO is in the frequency range 𝐺(𝑉() −𝑔(𝑉−𝑉)). The sampling time𝑔(𝑉 for 𝑣−𝑉 of the) dCCDA is then written as GZ0 VI( f req) − g VPS − Vre f . The𝛿= sampling time for v2 of the dCCDA is then written(23) follows: 2𝑉() +𝑔(𝑉 −𝑉) as follows: 2+𝑔(𝑉 −𝑉)/𝑉() 𝑇=𝐺 The switching frequency 𝑓 is 2+ g V − V /V (22) 𝑉()PS −𝑔(𝑉re f −𝑉I( f req)) T = GZ0 (22) 𝑣 1 𝑉() −𝑔(𝑉 −𝑉) The duty cycle of of the dCCDAV can expressed− g VPS −asV 𝑓 = I( f req) re f (24) 𝐺 2+𝑔(𝑉 −𝑉)/𝑉()

SN54LS628 VCO

V () 0 𝑣, 𝑓 𝑉 ideal 𝑉𝐶𝑂

𝑔(V())

𝑣 0 dCCDA 𝑣 V () 𝑣 𝑉

Figure 13. VFPWM with a low-resistance dCCDA feedback to a VCO. Figure 13. VFPWM with a low-resistance dCCDA feedback to a VCO. The duty cycle of v of the dCCDA can expressed as The VFPWM has a slew2 rate limit on the voltage output of the dCCDA; however, the slew rate limit due to the need to charge the difference-mode capacitor does not harm the g V − V VCO’s digital output. By contrast, the slew ratePS limitre f can prevent high-frequency noise in δ = (23) the feedback loop to the VCO. In practice,2VI( f req ad) +dingg V somePS − Vmorere f difference-mode capacitance 𝐶 to the dCCDA is preferable in order to improve the stability of the VFPWM. The corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of 1.0 MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V before feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%.

Energies 2021, 14, x FOR PEER REVIEW 15 of 26

𝑔(𝑉 −𝑉) 𝛿= (34) 2𝑉() +𝑔(𝑉 −𝑉)

The switching frequency 𝑓 is

1 𝑉() −𝑔(𝑉 −𝑉) 𝑓 = (35) 𝐺 2+𝑔(𝑉 −𝑉)/𝑉()

SN54LS628 VCO

V () 0 𝑣, 𝑓 𝑉 ideal 𝑉𝐶𝑂

Energies 2021, 14, 3656 15 of 25

𝑔(V())

𝑣 0 The switching frequency fo is dCCDA 𝑣 V () 𝑣 𝑉 1 VI( f req) − g VPS − Vre f fo = (24) GZ0 2 + g V − V /V Figure 13. VFPWM with a low-resistance dCCDAPS feedbackre f to aI VCO.( f req) The VFPWM has a slew rate limit on the voltage output of the dCCDA; however, the The VFPWM has a slew rate limit on the voltage output of the dCCDA; however, the slew rate limit due to the need to charge the difference-mode capacitor does not harm the slew rate limit due to the need to charge the difference-mode capacitor does not harm the VCO’s digital output. By contrast, the slew rate limit can prevent high-frequency noise in VCO’s digital output. By contrast, the slew rate limit can prevent high-frequency noise in the feedback loop to the VCO. In practice, adding some more difference-mode capacitance the feedback loop to the VCO. In practice, adding some more difference-mode capacitance C to the dCCDA is preferable in order to improve the stability of the VFPWM. The 𝐶 dm to the dCCDA is preferable in order to improve the stability of the VFPWM. The corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of 1.0 1.0 MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V before before feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%. feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%.

Energies 2021, 14, x FOR PEER REVIEW 16 of 26

7 vE1,out (V) vd,OPAMP (V) 5

−1 9.5 9.6 9.7 9.8 9.9 10 Time (μs)

FigureFigure 14.14.SPICE SPICE analysisanalysis ofof VFPWMVFPWM usingusing dCCDAdCCDA feedback.feedback. 4.2. VCO to VFPWM by Using High-Resistance cCCDA 4.2. VCO to VFPWM by Using High-Resistance cCCDA By having a VCO in series with a cCCDA that converts the 50% duty cycle square By having a VCO in series with a cCCDA that converts the 50% duty cycle square wave into PWM, the circuit achieves frequency control by simply adjusting V , and the duty wave into PWM, the circuit achieves frequency control by simply adjustingF 𝑉 , and the ratio is controlled by V = V . Compared with Equations (22) and (23), the frequency and duty ratio is controlledre f by 𝑉δ =𝑉. Compared with Equations (35) and (34), the fre- duty cycle of the VFPWM using the low-resistance dCCDA are coupled, which increases thequency complexity and duty of the cycle WPT of control, the VFPWM whereas usin VFPWMg the usinglow-resistance the high-resistance dCCDA are cCCDA coupled, can controlwhich theincreases frequency the complexity and duty cycle of the separately, WPT control, resulting whereas in less VFPWM complex circuitusing the calibration. high-re- Thesistance block cCCDA diagram can of control a VCO the to VFPWMfrequency using and duty the high-resistance cycle separately, cCCDA resulting is depicted in less com- in Figureplex circuit 15. SPICE calibration. analysis The demonstrates block diagram the of VFPWM a VCO to result, VFPWM and using the ﬁndings the high-resistance are shown incCCDA Figure is 16 depicted. In the in SPICE Figure circuit 15. SPICE model, analys a VCOis demonstrates is used with the the VFPWM same settings result, and as forthe Figurefindings 14 .are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same settings as for Figure 14.

SN54LS628 VCO 𝑉 V() 𝑣 𝑖𝑑𝑒𝑎𝑙 𝑉𝐶𝑂

𝑣, 𝑓

𝑣 cCCDA 𝑉 𝑣 V()) 𝑣

Figure 15. High-resistance cCCDA in series with a VCO.

Energies 2021, 14, x FOR PEER REVIEW 16 of 26

7 vE1,out (V) vd,OPAMP (V) 5

−1 9.5 9.6 9.7 9.8 9.9 10 Energies 2021, 14, 3656 16 of 25 Time (μs)

Figure 14. SPICE analysis of VFPWM using dCCDA feedback. Figure 14. SPICE analysis of VFPWM using dCCDA feedback. 4.2. VCO to VFPWM by Using High-Resistance cCCDA 4.2. VCO to VFPWM by Using High-Resistance cCCDA By having a VCO in series with a cCCDA that converts the 50% duty cycle square By having a VCO in series with a cCCDA that converts the 50% duty cycle square wave into PWM, the circuit achieves frequency control by simply adjusting 𝑉, and the wave into PWM, the circuit achieves frequency control by simply adjusting 𝑉, and the duty ratio is controlled by 𝑉 =𝑉. Compared with Equations (35) and (34), the fre- duty ratio is controlled by 𝑉 =𝑉. Compared with Equations (22) and (23), the frequency and duty cycle of the VFPWM using the low-resistance dCCDA are coupled, quency and duty cycle of the VFPWM using the low-resistance dCCDA are coupled, which increases the complexity of the WPT control, whereas VFPWM using the high-re- which increases the complexity of the WPT control, whereas VFPWM using the high-resistance cCCDA can control the frequency and duty cycle separately, resulting in less com- sistance cCCDA can control the frequency and duty cycle separately, resulting in less complex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance plex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same Energies 2021, 14, 3656 findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same16 of 25 settings as for Figure 14. settings as for Figure 14.

SN54LS628 VCO SN54LS628 VCO V 𝑉 () 𝑉 𝑣 V() 𝑖𝑑𝑒𝑎𝑙 𝑉𝐶𝑂 𝑣 𝑖𝑑𝑒𝑎𝑙 𝑉𝐶𝑂

𝑣, 𝑓 𝑣, 𝑓 𝑣 𝑣 cCCDA 𝑣 𝑉 cCCDA 𝑉 𝑣 V()) 𝑣 V()) 𝑣

Figure 15. High-resistance cCCDA in series with a VCO. Figure 15. High-resistance cCCDA in series with a VCO.

Energies 2021, 14, x FOR PEER REVIEW 17 of 26

6 VR6 (V) vE1,out (V) vd,OPAMP (V)

0 Figure 16. SPICE analysis of VFPWM using a high-resistance cCCDA in series with a VCO. −2

99.5 99.6 99.7 99.8 99.9 100 Time (μs)

FigureFigure 16. 16.SPICE SPICE analysis analysis of of VFPWM VFPWM using using a a high-resistance high-resistance cCCDA cCCDA in in series series with with a VCO.a VCO.

5.5. Experimental Experimental Results Results AA high high gain gain bandwidth bandwidth product product operational operational amplifier amplifier is is used, used, namely namely the the MAX4265 MAX4265 400-MHz operational amplifier, which yields gain of nearly 100, that is Adm = 100 with a 400-MHz◦ operational amplifier, which◦ yields gain of nearly 100, that is 𝐴 = 100 with nearly 60 phase lag, i.e., θdm = 50 , at the operation frequency around 4 MHz. Examples a nearly 60° phase lag, i.e., 𝜃 =50 , at the operation frequency around 4 MHz. Exam- of the VFPWM output from a VCO versus vd and the output in a dCCDA experiment are ples of the VFPWM output from a VCO versus 𝑣 and the output in a dCCDA experi- shown in Figure 17a. The circuit topology is presented in Figure7. The circuit parameters ment are shown in Figure 17a. The circuit topology is presented in Figure 7. The circuit are similar to those listed in Table4. The operation voltage, V , in this dCCDA configura- parameters are similar to those listed in Table 4. The operationre f voltage, 𝑉 , in this tion is 1.0 V, and the duty ratio, δ, is 22%. The phase lag of v versus the output from the dCCDA configuration is 1.0 V, and the duty ratio, δ, is 22%d . The phase lag of 𝑣 versus VCO is approximately 50◦, which matches the phase lag of the opamp. the output from the VCO is approximately 50°, which matches the phase lag of the opamp. The experimental results of the VFPWM using a high-resistance cCCDA in series with a VCO, with circuit parameters as shown in Table 4, are illustrated in Figure 17b. The VCO generates nearly 50% duty ratio output when the output of the low-resistance cCCDA is of the duty ratio δ = 30%. The phase lag of 𝑣 versus the output from the VCO is also approximately 50°.

Table 4. Parameters for the cCCDA and dCCDA designs.

Parameter Unit cCCDA dCCDA 𝑇 ns 250 250 𝑅 Ω 10k 100

𝐶 pF 15 𝐶 pF 15 𝑇 ns 100 100 𝐴 100 100 𝜃@4MHz degree 50 50 ′ ns 1.0 1.0 𝑇 𝛼 3 1

Energies 2021, 14, 3656 17 of 25 Energies 2021, 14, x FOR PEER REVIEW 18 of 26

vo vd 5

4 𝛿𝑇 T 3

T𝑣 gate driver turn-on voltage line 2 VOLTAGE (V) VOLTAGE 𝜃 1

-1 0.0 0.1 0.2 0.3 time (μs)

(a)

5 VCO Output Vd

𝛿T 3 𝑇

2 0.5T

𝜃

VOLTAGE (V) VOLTAGE 1

−1 0 0.1 0.2 0.3 0.4 0.5 time (μs)

(b)

Figure 17. Figure(a) VFPWM 17. (a) output VFPWM and outputvd from and a low-resistance𝑣 from a low-resistance dCCDA. (b )dCCDA. VFPWM ( outputb) VFPWM (=vs )output versus (= the vs) VCO output 𝑣 𝑣 (=vVCO) andversusvd of the the VCO VCO output in series (= with the) and high-resistance of the VCO cCCDA. in series with the high-resistance cCCDA. The experimental results of the VFPWM using a high-resistance cCCDA in series with To understand the influence of capacitance in this cCCDA configuration, we measure a VCO, with circuit parameters as shown in Table4, are illustrated in Figure 17b. The VCO the duty ratio δ and tuning results versus operation voltage 𝑉 and compare them with generates nearly 50% duty ratio output when the output of the low-resistance cCCDA is the theoretical result obtained using Equation (27). The parameters 𝑅 and α in Table 4 of the duty ratio δ = 30%. The phase lag of vd versus the output from the VCO is also are set to 20 kΩ and 1, respectively.◦ The parameter 𝐶 in Table 4 is set to two capaci- approximately 50 . tances, 𝐶 and 𝐶, respectively, according to the two ± terminals of the amplifier in Figure 9. The selection of 𝐶 and 𝐶 could be many combinations. Figure 18 shows the results for 𝐶 = 15𝑝𝐹, and 𝐶 varies from 9 to 23 pF when R = 20 kΩ and α=1.

Energies 2021, 14, 3656 18 of 25

Table 4. Parameters for the cCCDA and dCCDA designs.

Parameter Unit cCCDA dCCDA T ns 250 250 R Ω 10k 100 Ccm pF 15 Cdm pF 15 Tdm ns 100 100 Adm 100 100 θdm@4MHz degree 50 50 0 Tdm ns 1.0 1.0 α 3 1

To understand the influence of capacitance in this cCCDA configuration, we measure the duty ratio δ and tuning results versus operation voltage Vre f and compare them with the theoretical result obtained using Equation (19). The parameters R and α in Table4 are set to 20 kΩ and 1, respectively. The parameter Ccm in Table4 is set to two capacitances, + − Ccm and Ccm, respectively, according to the two ± terminals of the amplifier in Figure9. Energies 2021, 14, x FOR PEER REVIEW + − 19 of 26 The selection of Ccm and Ccm could be many combinations. Figure 18 shows the results for − + Ccm = 15pF, and Ccm varies from 9 to 23 pF when R = 20 kΩ and α = 1.

6 Time Vref Vvco 4 Vout09p Vd09p Vout11p 2 Vd11p Vout13p Vd13p Vout15p 0 Vd15p Vout17p Vd17p −2 Vout19p Vd19p Vout23p Vd23p −4

FigureFigure 18. 18. InfluenceInfluence of of the the capacitance capacitance 𝐶Ccm on the VFPWM output.output. + − Then, only three combinations of (C , C ), that is, (15 pF, 15 pF), (15 pF, 10 pF), and Then, only three combinations of (𝐶cm,𝐶cm), that is, (15 pF, 15 pF), (15 pF, 10 pF), and(10 pF(10, 15 pFpF, 15), arepF), implemented are implemented in the in experiments, the experiment and as, comparisonand a comparison of the measurements of the meas- urementswith the experimentalwith the experimental results of results Equation of (19)Equation is presented (27) is presented in Figure 19in. Figure The duty 19. ratioThe responses of the three capacitance combinations match the theoretical response; however, duty ratio responses of the three capacitance combinations+ match− the theoretical response; the combination with identical capacitances, namely (Ccm, Ccm) = (15pF , 15pF), is closest however, the combination with identical capacitances, namely (𝐶,𝐶) = (15pF, 15pF), isto closest the theoretical to the theoretical response. response. Thus, the Th VFPWMus, the designVFPWM of design the cCCDA of the configuration cCCDA configura- is well balanced in practice. tion is well balanced in practice. Figure 20 illustrates the influence of resistance on the relationship between the duty ratio and operation voltage Vre f in the cCCDA configuration. The δmax values are all close 15p-15p 15p-10p 10p-15p Eq. (19) to 50% when Vre f = 0, but they decrease slightly when the resistance in Table4 increases from 8.250.00to 20 kΩ. The limitation values of Vre f , when the duty ratios are diminished, = move away45.00 from the cutoff operation voltage at Vre f 2.5 V when the resistances are increased from 8.2 to 20 kΩ. The intersection of the duty ratio curves in Figure 20 is located 40.00 at approximately Vre f = 1.2 V, probably because we set a threshold of V = 1.2 V when analyzing35.00 the experimental results.

(%) 30.00 δ 25.00 20.00

duty ratio 15.00 10.00 5.00 0.00 0.00 0.40 0.80 1.20 1.60 2.00 2.40

Vref = Vδ (Volts)

Figure 19. Influence of the capacitance 𝐶 on the duty ratio vs. control voltage (𝑉) in cCCDA letting α=1 and 𝑅 = 20 kΩ in Table 2.

Figure 20 illustrates the influence of resistance on the relationship between the duty ratio and operation voltage 𝑉 in the cCCDA configuration. The 𝛿 values are all close to 50% when 𝑉 =0, but they decrease slightly when the resistance in Table 4 increases from 8.2 to 20 kΩ. The limitation values of 𝑉, when the duty ratios are diminished, move away from the cutoff operation voltage at 𝑉 =2.5 V when the re-

Energies 2021, 14, 3656 19 of 25

is closest to the theoretical response. Thus, the VFPWM design of the cCCDA configuration is well balanced in practice.

15p-15p 15p-10p 10p-15p Eq. (19) 50.00

Energies 2021, 14, 3656 45.00 19 of 25

40.00

Energies 2021, 14, 3656 35.00 19 of 25 is closest to(%) 30.00 the theoretical response. Thus, the VFPWM design of the cCCDA configuration is wellδ balanced in practice. 25.00

20.00 15p-15p 15p-10p 10p-15p Eq. (19) duty ratio 15.00 50.00 10.00 45.00 5.00 40.00 0.00 35.00 0.00 0.40 0.80 1.20 1.60 2.00 2.40 (%) 30.00 δ Vref = Vδ (Volts) 25.00

Figure20.00 19. Influence of the capacitance 𝐶 on the duty ratio vs. control voltage (𝑉) in cCCDA

lettingduty ratio α=1 and 𝑅 = 20 kΩ in Table 2. 15.00 10.00Figure 20 illustrates the influence of resistance on the relationship between the duty ratio5.00 and operation voltage 𝑉 in the cCCDA configuration. The 𝛿 values are all close0.00 to 50% when 𝑉 =0, but they decrease slightly when the resistance in Table 4 increases0.00 from 8.2 0.40to 20 kΩ. The 0.80 limitation 1.20 values of 1.60 𝑉, when 2.00 the duty ratios 2.40 are diminished, move away from the cutoff operation voltage at 𝑉 =2.5 V when the re- Vref = Vδ (Volts) sistances are increased from 8.2 to 20 kΩ. The intersection of the duty ratio curves in Fig- Figureure 20 19. is Inﬂuencelocated at of approximately the capacitance C𝑉on=1.2 the V duty, probably ratio vs. because control voltagewe set (aV threshold) in cCCDA of Figure 19. Influence of the capacitance 𝐶 oncm the duty ratio vs. control voltage (𝑉) inδ cCCDA lettingletting𝑉=1.2 α=1α = and 1V when and 𝑅R analyzing = 20 kkΩ Ω in inTable the Table experimental2.2 . results.

Figure 20 illustrates the influence of resistance on the relationship between the duty 8.2k 10k 12k 15k 20k ratio and operation50.00 voltage 𝑉 in the cCCDA configuration. The 𝛿 values are all close to 50% when 𝑉 =0, but they decrease slightly when the resistance in Table 4 45.00 increases from 8.2 to 20 kΩ. The limitation values of 𝑉, when the duty ratios are di- 40.00 minished, move away from the cutoff operation voltage at 𝑉 =2.5 V when the resistances are35.00 increased from 8.2 to 20 kΩ. The intersection of the duty ratio curves in Fig-

ure 20 is (%) located at approximately 𝑉 =1.2 V, probably because we set a threshold of

δ 30.00 𝑉=1.2 V when analyzing the experimental results. 25.00 20.00 8.2k 10k 12k 15k 20k Duty ratio 50.0015.00 45.0010.00 40.00 5.00 35.00 0.00 00.511.522.5 (%)

δ 30.00 Vref = Vδ (Volts) 25.00

Figure20.00 20. Influence of the resistance on the duty ratio vs. control voltage (𝑉) in cCCDA letting Figure 20. Inﬂuence of the resistance on the duty ratio vs. control voltage (Vδ) in cCCDA letting (𝐶Duty ratio +,𝐶−) be (15 pF,15 pF). (Ccm15.00, Ccm) be (15 pF,15 pF). 10.00 The results in Figures 19 and 20 provide the transfer function between duty ratio δ (%) 5.00 and the control voltage of Vδ for the VFPWM circuit associated with the high-resistance

cCCDA.0.00 The switching control depicted in Figure1 consisting of the transfer matrix could be formulated00.511.522.5 into the following equation.

Vref = Vδ (Volts) Gzo 0 Gz = (25) 0 Gz1 Figure 20. Influence of the resistance on the duty ratio vs. control voltage (𝑉) in cCCDA letting (𝐶,𝐶) be (15 pF,15 pF). The gain Gz1 from δ to Vδ are piecewise linear functions interpolated from + − Figures 19 and 20 according to the selection of (Ccm, Ccm) and R. The VFPWM driving circuit PCB was fabricated according to Figure 15, as shown in Figure 21. The VFPWM was integrated into a WPT device, as shown in Figure 22. It

EnergiesEnergies 2021 2021, ,14 14, ,3656 3656 2020 ofof 2525

TheThe results results in in Figures Figures 19 19 and and 20 20 provide provide th thee transfer transfer function function between between duty duty ratio ratio δδ

(%)(%) andand thethe controlcontrol voltagevoltage ofof 𝑉𝑉 forfor thethe VFPWMVFPWM circuitcircuit associatedassociated withwith thethe high-re-high-re- sistancesistance cCCDA. cCCDA. The The switching switching control control depicted depicted in in Figure Figure 1 1 consisting consisting of of the the transfer transfer ma- ma- trixtrix could could be be formulated formulated into into the the following following equation. equation.

𝐺𝐺 00 𝑮𝑮𝒛𝒛== (25)(25) 0𝐺0𝐺

The gain 𝐺𝐺 from 𝛿𝛿 to 𝑉𝑉 are piecewise linear functions interpolated from Figures Energies 2021, 14, 3656 The gain from to are piecewise linear functions interpolated from Figures20 of 25 1919 and and 20 20 according according to to the the selection selection of of ( (𝐶𝐶,𝐶,𝐶)) and and 𝑅𝑅. . TheThe VFPWM VFPWM driving driving circuit circuit PCB PCB was was fabricated fabricated according according to to Figure Figure 15, 15, as as shown shown in in FigureFigure 21. 21. The The VFPWM VFPWM was was integrated integrated into into a a WPT WPT device, device, as as shown shown in in Figure Figure 22. 22. It It illus- illus- tratesillustratestrates the the validity thevalidity validity of of the the of cCCDA thecCCDA cCCDA of of the the of VFPWM theVFPWM VFPWM in in the the in WPT theWPT WPT system system system application; application; application; the the dis- thedis- tancedistancetance of of the ofthe the wireless wireless wireless transfer transfer transfer was was was more more more than than than 100 100 100 cm. cm. cm. In In In the the the photo photo in in Figure Figure 23, 2323,, it itit can can bebe seenseen that that all all output output connectorsconnectors of of the the functionfunc functiontion generator generator are are disconnected.disconnected. disconnected. The The cCCDA cCCDA is is usedused insteadinstead ofof of thethe the functionfunction function generatorgenerator generator to to to provide prov provideide the the the switching switching switching signal signal signal to to theto the the gate gate gate driver driver driver of oftheof the the PTU. PTU. PTU. In In addition,In addition, addition, there there there are are are multiple multiple multiple PTUs PTUs PTUs powering powering powering multiple multiple multiple PRUs. PRUs. PRUs.

CouplingCoupling OPAMPOPAMP capacitorcapacitor VCOVCO ConnectorConnector toto antenna antenna

FigureFigure 21. 21. A A cCCDA cCCDA driving driving circuit circuit boardboard 6.5 6.5 cm cm wide wide and and 11 11 cm cm long. long.

OutputOutput connectors connectors of of FunctionFunction Generator Generator

PRUPRU 5 5 PTU2PTU2

PTUPTU 1 1 PRUPRU 2, 2, 3, 3, 4 4

PRUPRU 1 1

FigureFigure 22. 22. Integration Integration of of the the VFPWM VFPWM of of the the cCCDA cCCDA scheme scheme applied applied to to WPT. WPT.

The power transfer efﬁciency was reported in [24]. The maximum distance for 1 W power delivery can be as far as 140 cm when vDS is ≥ 700 V and the corresponding input voltage VDD is around 300 V. We achieved the same result as before. In addition, we surpassed the previous achievement by enabling MIMO (multiple input and multiple output) applications, because the function generator can only control a maximum of two PTUs at a time. Nevertheless, the VFPWM is much less inexpensive than the function generator, and it is very handy and small. In [25], we derived a theory called the minimum power input control, which trades off PDL (Power Delivered to Load) for the switching loss of the GaN HEMT in order to yield the optimal PTE (Power Transfer Efﬁciency). However, the MIMO control was not shown in [25], because the function generator Tektronix AFG 31054, which is a dual channel output equipment, does not allow easy management of the phase difference required for the operation of different PTUs in different arrangements. On the other hand, we were able to easily adjust the individual VFPWM boards in this paper Energies 2021, 14, 3656 21 of 25

Energies 2021, 14, 3656 to obtain the required phase difference among the PTUs and achieve the best power21 of output 25

for multiple PRUs.

Energies 2021, 14, x FOR PEER REVIEW 22 of 26

: PTU input : PRU output

voltage VDD is around 300 V. We achieved the same result as before. In addition, we sur- PRU3: passed the previous achievementPTU1: 20W by enabling MIMO (multiplePTU2: 25W input and multiple output) applications, because the function generator0.46W can only control a maximum of two PTUs at a time. Nevertheless, the VFPWM PRU2:is much less inexpensivePRU4: than the function generator, andPRU1: it is very 1.9W handy and small. In 1.7W[25], we derived2.1W a theory calledPTU5: the 3.12W minimum power input control, which trades off PDL (Power Delivered to Load) for the switching loss of the GaN HEMT in order to yield the optimal PTE (Power Transfer Efficiency). However, the MIMO control was not shown in [25], because the function generator Tektronix AFG 31054, which is a dual channel output equipment, does not allow easy management of the phase difference required for the operation of different PTUs in different arrangements. 140 80 50 30 10 0 −20 On the other hand, we were able to easily adjust the individual VFPWM boards in this Position (cm) paper to obtain the required phase difference among the PTUs and achieve the best power FigureoutputFigure 23. for 23. PDL multiplePDL of ofMIMO MIMO PRUs. applications. applications. The experiment of a MIMO WPT demo is depicted in Figure 23, which uses the VFPWMTheThe shownpower experiment transferin Figure of efficiency 21 a MIMOto control was WPT class-E reported demo amplifier in is depicted[24]. switching. The maximum in Figure In this 23distance experiment,, which for uses 1 weW the powersetVFPWM 𝐶 delivery=𝐶 shown = can 15pF in be Figure, as𝑅=20 far 21as to140kΩand control cm 𝛼=1when class-E vforDS is amplifierthe ≥ 700cCCDA. V and switching. Onethe correspondingof Inthe this VCO experiment, inputs input + = − = = = voltageVwe() set is VC setDDcm isto around C5V.cm The 30015 measuredpF V., RWe achieved20 resultskΩ and showtheα same a1 totalfor result the power cCCDA.as before. output One In from addition, of thefive VCO PRUs we sur- inputs of passed9.26VI( rngW )whentheis previous set the to total 5 V.achievement power The measured input by from enabling results two PTUs MIMO show is a(multiple45 total W. The power input input outputand signals multiple from to the fiveoutput) charge PRUs applications,pumpof 9.26 gate W drive when because and the thethe total drain-sourcefunction power generator input voltage from can of two theonly PTUsclass-E control is amplifier 45 a maximum W. The are input shown of two signals in PTUs Figure to at the a24. chargetime. The Nevertheless,control pump gatevoltages drive the of VFPWM and the theVFPWM drain-source is much are showless voltageinexpensiven in Table of the 5. thanCompared class-E the amplifierfunction to the theoreticalgenerator, are shown in andresults,Figure it is the 24very .estimated The handy control andvalue voltagessmall. of the In switching of[25], the we VFPWM derivedfrequency are a theoryclosely shown called matches in Table the 5the .minimum Compared data read power from to the inputFiguretheoretical control, 12. There results, which is some thetrades estimated difference, off PDLvalue (Powerwithin of Delivered20%, the switching between to Load) the frequency estimatedfor the closelyswitching duty matchesratio loss δ of% the thefromdata GaN the read measurementHEMT from in Figure order and 12to . theyield There theoretical the is optimal some duty difference, PTE ratio (Power δ% within interpolated Transfer 20%, Efficiency). between from Figure the However, estimated20. The thedifferencesduty MIMO ratio controlareδ% froma result was the notof measurement theshown input in impedance[25], and be thecause theoretical of the the function charge duty pumpgenerator ratio δgate% interpolatedTektronix drive and AFG the from 31054,inputFigure impedance which 20. The is a differencesdualof the channel GaN HEMT are output a result transistor, equipment, of the wh input ichdoes can impedance not be allow eliminated easy of the management by charge the closed pump of loop the gate phasecontroldrive difference andin the the WPT input required system impedance forusing the the ofoperation theminimum GaN of HEMT differentpower transistor, input PTUs control in which different [25]. can arrangements. be eliminated by Onthe the closed other loop hand, control we were in the able WPT to systemeasily adjust using the the individual minimum powerVFPWM input boards control in this [25 ]. paper to obtain the required phase difference among the PTUs and achieve the best power output for multiple PRUs. 272.7 ns 𝑣 The experiment of a MIMO WPT demo is depicted in Figure 23, which uses the 120 V PTU1: 20 W VFPWM shown in Figure 21 to control class-E amplifier switching. In this experiment, we VDD = 50 V set 𝐶 =𝐶 = 15pF, 𝑅=20 kΩand 𝛼=1 for the cCCDA. One of the VCO inputs V() is set to 5V. The measured results show a total power output from five PRUs of 𝑓 = =3.673 MHz 9.26 W0 V when the total power input from two PTUs is 45 W. The input. signals to the charge pump−7 Vgate drive and the drain-source voltage of the class-E amplifier are shown in Figure 𝑣 63 ns 24.− The12 V control voltages of the VFPWM are shown in Table 5. 𝛿%Compared = to the= 23%theoretical 272.7 ns results, the estimated 63nsvalue of the switching frequency closely matches the data read from Figure 12. There is some difference, within 20%, between the estimated duty ratio δ% 269.2 ns 𝑣 from180 theV measurement and the theoretical duty ratio δ% interpolated from Figure 20. The differences are a result of the input impedance of the chargePTU2: pump 25 gate W drive and the input impedance of the GaN HEMT transistor, which can be eliminatedVDD = 80 by V the closed loop

control in the WPT system using the minimum power input control [25]. 𝑓 = =3.717 MHz . 0 V −7 V 57.2 ns 𝛿% = = 21.2% −12 V 𝑣 269.2 ns 57.2 ns

Figure 24. The wave form of the input signal v and output signal v of class-E Ampliﬁer. Figure 24. The wave form of the input signal 𝑣 GS and output signal 𝑣DS of class-E Amplifier.

Table 5. Control voltage inputs of the individual PTUs in Figure 23.

Corresponding Estimated Theoretical Unit Value Symbol Unit Control Voltage Value Value

Energies 2021, 14, 3656 22 of 25

Table 5. Control voltage inputs of the individual PTUs in Figure 23.

Corresponding Estimated Theoretical Control Unit Value Symbol Unit Value Value Voltage

V V 1.92 fo MHz 3.673 3.65 * PTU1 I( f req) Vδ V 1.76 δ (%) 23 19 ** V V 2.02 fo MHz 3.717 3.77 * PTU2 I( f req) Vδ V 1.86 δ (%) 21.2 17 ** * corresponds to Figure 12 and ** corresponds to Figure 20. 6. Discussion The existing, and widely popular, inductive power transfer (IPT) cannot achieve long-distance power delivery, in theory. Resonant wireless power transfer allows electrical power to be delivered over long distances with acceptable efficiency, which is usually higher than 80%. Inductive power transfer through a metal object is also a major obstacle due to the generation of eddy currents, leading to substantial device heating. The resonant WPT system with a frequency of 6.78 MHz is capable of transferring power into metal- encapsulated mobile devices without considering the eddy current effect. However, many technologies and tests for resonant WPT systems are still under investigation. Namely, the class-E amplifier, the control of which still needs to be validated with respect to installation costs and radio regulations. The power efficiency for the WPT is also one of the major concerns in real-life scenarios; WPT will never be as efficient as wired power transfer, but how close could the efficiency be? In addition to low cost, low environmental contamina- tion, and high efficiency, the maximum power that can be transferred in a desired distance between the power transfer unit (PTU) and the power receiving unit (PRU) is also a factor that affects the decision to use resonant WPT systems. In this paper, we focused on the critical aspect of the gate driving the physical control of the class-E amplifier. The control of class-E amplifiers takes the optimal tuning of switching frequency and duty cycle as the inputs and generates the corresponding pulse train to switch the transistor on or off. Considering the multiple-input–multiple-output (MIMO) applications of WPT, the control hardware should be small in size, such that the PTU can be placed easily. It is recommended that the size of the PTUs be made so small that they can be placed directly into the socket on the wall or into a power extension cord, just like chargers for mobile devices. In this paper, the VFPWM consists of only a VCO and an OP-amp, and can be miniaturized into a system in packaging (SiP), while the class-E amplifier can also be reduced to the size of a cigarette box. The antenna of the PTU can also be made into the stickers that go on different faces of the PTU box. The minimum power input control [25] can also be implemented in the microprocessor or FPGA. The VFPWM proposed in this paper is a low-cost and high-reliability solution for the control of class-E amplifiers. Nevertheless, the duty cycle control, which is independent from the frequency control, can be adjusted via the analog voltage input, as shown in Figures 19 and 20, with the circuit topology as shown in Figures 15 and 16. The live demo photo shown in Figure 22 displays the possibility of multiple PRUs being charged simultaneously since PRUs can be distanced from one another.

7. Conclusions Two VFPWM circuitries derived from a VCO and CCDAs, classiﬁed as the dCCDA and cCCDA, are proposed in this paper. The dCCDA with low resistance reduces the noise in the feedback loop to the VCO. The cCCDA with high resistance can be used in series with the VCO to meet the VFPWM requirements. Compared with dCCDA, the cCCDA circuit enables independent control of the frequency, and the duty cycle is deemed to be better in 6.78-MHz resonant WPT applications. The circuit was fabricated and used in a ﬁeld test, yielding power transfer to 100 cm away for multiple power receiving units. The output power of the corresponding single power transmission unit was more than 10 W. Energies 2021, 14, 3656 23 of 25

The corresponding control can be either digital or analog for different WPT applications and market segments. With the VFPWM design introduced in this paper, the challenge of electromagnetic interference (EMI) from the antenna to the power supplies remains to be addressed in future studies. Currently, we can integrate multiple power transmission units to form a multiple-input–multiple-output system for WPT applications. In the future, we will devote more attention to high-power delivery, providing that the environmental safety issues are simultaneously addressed. High power delivery to load (PDL) can be achieved by using either multiple PTUs to the load or multiple PRU antennas on the load, depending on the load characteristics. The use of this resonant WPT technology will be seen in the future in electrical vehicle (EV) charging applications.

Author Contributions: Conceptualization, E.-Y.C. and W.-H.C.; methodology, L.-C.T.; software, S.-L.J.; validation, S.-L.J. and W.-H.C.; formal analysis, L.-C.T.; resources, E.-Y.C.; writing—original draft preparation, W.-H.C.; writing—review and editing, S.-L.J.; visualization, E.-Y.C.; experiments, L.-C.T.; supervision, E.-Y.C.; project administration, E.-Y.C.; funding acquisition, W.-H.C. All authors have read and agreed to the published version of the manuscript. Funding: This research was funded by Ministry of Science and Technology, R.O.C., grant number MOST 109-2218-E-008-003. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Data Availability Statement: Data sharing not applicable. Acknowledgments: This work was supported by the Ministry of Science and Technology, R.O.C. The authors also thank You-Chen Weng of the CSD Lab for fabricating the D-Mode MIS-HEMT chips and IMLab graduate students Rohit Roy for their help in the experimental setup and editing. This manuscript was edited by Wallace Academic Editing. Conﬂicts of Interest: The authors have no conﬂicts of interest to declare.

Nomenclature

fo (Hz) switching frequency in wireless power transfer δ duty cycle of the switching control L1 inductance on the switching power supply side of the PTU C1 resonant capacitance on the switching power supply side of the PTU L2 equivalent inductance including the load inductance on the PTU side C2 equivalent capacitance including the load capacitance on the PTU side RL equivalent resistance of PRU on the PTU side vs switching control signal of PTU VF control voltage corresponding to the frequency fo to the VFPWM; Vδ control voltage corresponding to the duty ratio δ to the VFPWM VDD input voltage of the PTU Gz zero-order hold transfer function matrix GZ0 gain of the switching frequency to voltage transfer function GZ1 gain of the duty ratio to voltage transfer function Adm differential mode gain of the OPAMP θdm differential mode phase lag of the OPAMP @ 4MHz vd Difference voltage of the OPAMP VPS power supply voltage of the OPAMP Cdm differential mode capacitance added to the difference ampliﬁer Ccm common mode capacitance added to the difference ampliﬁer Energies 2021, 14, 3656 24 of 25

α feedback gain of the difference ampliﬁer R Base resistance of the resistors of the difference ampliﬁer Tdm time constant for charging the difference mode capacitor Tcm time constant for charging the common mode capacitor VI( f req) voltage input to control the center frequency of the SN54LS628 VCO VI(rng) voltage input to control the frequency range of the SN54LS628 VCO

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