Dniio 82C822 PCIB VESA local Bus to PCI Bridge Inter-face
1.0 Features Fully compliant to the PCI V2.0 Specification Burst mode PCI accesses to local memory support Up to four PCI masters Combine host CPU sequential writes into PCI burst write cycles Supports system operational speeds of25, 33, 40, and 50MHz Interfaces with all OPTi's VL chipset solutions Provides central arbiter to arbitrate the bus requests Single 208-pin PQFP (Plastic Quad Flat Pack) between: - host CPU - PCI masters Note: The text in this document applies to Mask - DMAJISA masters #1285, Revision 1 Silicon of the 82C822. This - Refresh document supersedes all other 82C822 data Offers programmable priority scheme for both the central sheets. arbiter and DMA channels: - Fixed - Rotating - FixedIRotating combination
Figure 1-1 82C822-Based System Block Diagram
Multiplexed ~ Addr AddrJData 1-0-----1
VESA Data OPTi Command P Local 82C822 C I Bus VESA to PCI Bridge Command S I o t s HBE4# I I IR05 NMI IRO[12:91 CPU BOFF# IRO[15:141
MASTER#
AEN#
ISA RFSH#
ATCLK
LDEV# (VESA)
NMIIN
And! 1 nClJ. OPTi, Inc. ' 2525 Walsh Avenue' Santa Clara, CA 95051 . (408) 980-8178 82C822 PCID
2.0 Overview OPTi's 82C822 VESA local bus to PCI Bridge (PCIB) chip is a The PCIB works seamlessly with the motherboard chipset bus high integration 208-pin PQFP device designed to work with arbiter to handle all requests of the host CPU and PCI bus mas VESA VL bus compatible core logic chipsets. The 82C822 ters, DMA masters, I/O relocation and refresh. Extensive regis PCIB provides interface to the high perfonnance PCI bus and ter and timer support are designed into the 82C822 to is fully compliant to the PCI Version 2.0 specification. The implement the PCI specification. 82C822 requires no glue logic to implement the PCI bus inter The 82C822 is a true VESA to PCl bridge. It has the highest face and hence it allows designers to have a highly integrated priority on CPU accesses after cache and system memory. It motherboard with both VESA local bus and PCI local bus sup generates LDEV# automatically and then compares the port. The PCIB chip offers premium perfonnance and flexibil addresses with its internal registers to detennine whether the ity for VESA VL-based desktop systems running up to current cycle is a PCI cycle. When a cycle is identified as PCI 50MHz. The 82C822 PCIB can be used with OPTi's 82C802G cycle, the 82C822 will take over the cycle and then return core logic and 82C602 buffer chipsets to build a low cost and RDY# to the CPU. Ifnot, the 82C822 will give up the cycle to power efficient 486-based desktop solution. It also works with the local device or, in the case of an ISA slave, generate a OPTi 82C546/547 chipset to build a high perfonnance PCIIVL BOFF# cycle to the CPU. This action will abort the cycle and solution based on the Intel P54C processor. allow the CPU to rerun the cycle. The 82C822 PCIB provides all of the control, address and data The 82C822 includes registers to detennine shadow memory paths to access the PCI bus from the VESA Local bus (VL space, hole locations and sizes to allow the 82C822 to deter bus). The 82C822 provides a complete solution including data mine which memory space should be local and which is buffering, latching, steering, arbitration, DMA and master located on the ISA bus. Upon access to memory, the 82C822 functions between the 32-bit VL bus and the 32-bit PCI bus. can detennine whether or not the cycle is a PCI access by com paring the cycle with its internal registers.
Figure 2-1 82C822 Block Diagram
RESET AD[31:0] LCLK 1 - C/BE[3:0]# PAR ADR[31:2] 1 -- ADS# 1 CLK MIO# -- PCICLKIN WR# 1 -- PCICLK[3:1] DC# VESA 1 BE[3:0]# PCI FRAME# Local - IRDY# BLAST# 1 Bus Bus - TRDY# DAT[31:0] 1 - STOP# LRDY# 1 -- LOCK# BRDY# --- DEVSEL# RDYRTN# OPTi PERR# LDEVO# 82C822 -- SERR# WBACK# LDEVI# VESA to PCI Bridge REQ[4:1] LREQ# GNT[4:1]# LGNT# 1 INTD[4:1]# INTC[4:1]# 1 INTB[4:1]# 1 INTA[4:11# ---- -1- -- -- NMIIN . NMI ATCLK 1 - BOFF# MASTER# Misc. Misc. IRQ[15:14] AEN Input 1 Output IRQ[12:91 RFSH# Signals Signals IRQ5 HBE4# 1 ROMCS# LMEM# 1 NVMCS#
Page 2 DS-01-82C822-09 82C822 PCIB 82C822 PCIB
3.0 Signal Definitions
Figure 3-1 82C822 Pin Diagram
S~~;:S::;:~~~~~~ ADR2 104 NMIIN ADR3 103 NC ADR4 102 NC ADR5 101 NC ADR6 100 NC ADR7 99 DAT7 ADR8 98 DAT6 GND 97 VCC VCC 96 GND ADR9 95 OATS ADR10 94 DAT4 ADRll 93 DAT3 ADR12 92 DAT2 ADR13 91 DATl ADR14 90 DATO ADR15 89 PCIClKIN ADR16 82C822 88 PCIClKl ADR17 87 IR05 ADR18 86 PCIClK2 ADR19 85 PCIClK3 GND 84 IR09 ADR20 83 IR010 ADR21 PCIB 82 lClK ADR22 81 GND ADR23 80 ClK ADR24 79 IROll ADR25 78 IR012 ADR26 77 IR014 ADR27 76 IR015 ADR28 75 lMEM# ADR29 74 ATClK ADR30 73 MASTER# ADR31 72 AEN GND 71 RFSH# NC 70 NC NVMCS# 69 NC ROMCS# 68 NC INTD2# 67 INTD4# INTC2# 66 INTC4# INTB2# 65 INTB4# INTA2# 84 INTA4# INTD1# 63 INTD3# INTC1# 62 INTC3# GND 61 VCC VCC 60 GND INTB1# 59 INTB3# INTA1# 68 INTA3# GNT2# 57 GNT4# RE02# 56 RE04# GNT1# 55 GNT3# RE01# 54 RE03# GND 53 GND 82C822 PCIB
Table 3-1 82C822 Numerical Pin Cross-Reference List Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name I ADO 53 GND 105 GND 157 ADR2 2 ADl 54 REQ3# 106 DAT8 158 ADR3 3 AD2 55 GNT3# 107 DAT9 159 ADR4 4 AD3 56 REQ4# 108 DATI 0 160 ADR5 5 AD4 57 GNT4# 109 DATIl 161 ADR6 6 AD5 58 lNTA3# 110 DATI2 162 ADR7 7 AD6 59 lNTB3# 111 DATI 3 163 ADR8 8 AD7 60 GND 112 DATI 4 164 GND 9 CIBEO# 61 VCC 113 DATI 5 165 VCC 10 VCC 62 lNTC3# 114 VCC 166 ADR9 11 ADI6 63 lNTD3# 115 LGNT# 167 ADRIO 12 AD17 64 lNTA4# 116 LREQ# 168 ADRII 13 ADl8 65 lNTB4# 117 NMI 169 ADR12 14 AD19 66 lNTC4# 118 WBACK# 170 ADRI3 15 GND 67 lNTD4# 119 GND 171 ADR14 16 AD20 68 NC 120 DC# 172 ADR15 17 AD21 69 NC 121 MlO# 173 ADR16 18 AD22 70 NC 122 WR# 174 ADR17 19 AD23 71 RFSH# 123 BOFF# 175 ADR18 20 CIBE2# 72 AEN 124 LDEVI# 176 ADR19 21 PAR 73 MASTER# 125 LRDY# 177 GND 22 SERR# 74 ATCLK 126 RDYRTN# 178 ADR20 23 PERR# 75 LMEM# 127 LDEVO# 179 ADR21 24 LOCK# 76 IRQI5 128 BLAST# 180 ADR22 25 STOP# 77 IRQI4 129 ADS# 181 ADR23 26 VCC 78 IRQI2 130 GND 182 ADR24 27 GND 79 IRQ I I 131 BRDY# 183 ADR25 28 DEVSEL# 80 CLK 132 HBE4# 184 ADR26 29 TRDY# 81 GND 133 BE3# 185 ADR27 30 IRDY# 82 LCLK 134 BE2# 186 ADR28 31 FRAME# 83 IRQ 10 135 BEl# 187 ADR29 32 CIBE3# 84 IRQ9 136 BEO# 188 ADR30 33 AD31 85 PCICLK3 137 DATI 6 189 ADR31 34 AD30 86 PCICLK2 138 DATI 7 190 GND 35 AD29 87 IRQ5 139 DATI 8 191 NC 36 AD28 88 PCICLKI 140 DATI 9 192 NVMCS# 37 AD27 89 PCICLKlN 141 DAT20 193 ROMCS# 38 GND 90 DATO 142 GND 194 lNTD2# 39 AD26 91 DATI 143 DAT21 195 lNTC2# 40 AD25 92 DAT2 144 DAT22 196 lNTB2# 41 AD24 93 DAT3 145 DAT23 197 lNTA2# 42 CIBEI# 94 DAT4 146 DAT24 198 lNTDl# 43 VCC 95 DAT5 147 VCC 199 lNTCl# 44 ADl5 96 GND 148 DAT25 200 GND 45 ADI4 97 VCC 149 DAT26 201 VCC 46 AD 13 98 DAT6 150 DAT27 202 lNTBI# 47 ADI2 99 DAT7 lSI DAT28 203 lNTAI# 48 ADlI 100 NC 152 DAT29 204 GNT2# 49 AD 10 101 NC 153 DAT30 205 REQ2# 50 AD9 102 NC 154 DAT31 206 GNTI# 51 AD8 103 NC 155 RESET# 207 REQI# 52 GND 104 NMIlN 156 GND 208 GND
Page 4 05-01-82C822-0.9 82C822 PCIB
Table 3-2 82C822 Alphabetical Pin Cross-Reference List
Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. ADO I ADR22 180 DAT27 150 IRQ12 78 ADI 2 ADR23 181 DAT28 151 IRQ14 77 AD2 3 ADR24 182 DATI9 152 IRQ15 76 AD3 4 ADR25 183 DAT30 153 LCLK 82 AD4 5 ADR26 184 DAT31 154 LDEVO# 127 ADS 6 ADR27 185 DC# 120 LDEVI# 124 AD6 7 ADR28 186 DEVSEL# 28 LGNT# 115 AD7 8 ADR29 187 FRAME# 31 LMEM# 75 AD8 51 ADR30 188 GND IS LOCK# 24 AD9 50 ADR31 189 GND 27 LRDY# 125 ADI0 49 ADS# 129 GND 38 LREQ# 116 AD 11 48 AEN 72 GND 52 MASTER# 73 AD12 47 ATCLK 74 GND 53 MIO# 121 AD13 46 BEO# 136 GND 60 NC 68 AD14 45 BE1# 135 GND 81 NC 69 AD15 44 BE2# 134 GND 96 NC 70 AD16 II BE3# 133 GND 105 NC 100 AD17 12 BLAST# 128 GND 119 NC 101 AD18 13 BOFF# 123 GND 130 NC 102 AD19 14 BRDY# 131 GND 142 NC 103 AD20 16 CIBEO# 9 GND 156 NC 191 AD2l 17 CIBEI# 42 GND 164 NMI 117 AD22 18 C/BE2# 20 GND 177 NMIIN 104 AD23 19 CIBE3# 32 GND 190 NVMCS# 192 AD24 41 CLK 80 GND 200 PAR 21 AD25 40 DATO 90 GND 208 PCICLKI 88 AD26 39 DATI 91 GNTl# 206 PCICLK2 86 AD27 37 DATI 92 GNTI# 204 PCICLK3 85 AD28 36 DAT3 93 GNT3# 55 PCICLKIN 89 ·AD29 35 DAT4 94 GNT4# 57 PERR# 23 AD30 34 DAT5 95 HBE4# 132 RDYRTN# 126 AD31 33 DAT6 98 INTAl# 203 REFRESH# 71 ADR2 157 DAT7 99 INTA2# 197 REQl# 207 ADR3 158 DAT8 106 INTA3# 58 REQ2# 205 ADR4 159 DAT9 107 INTA4# 64 REQ3# 54 ADRS 160 DATI 0 108 INTBl# 202 REQ4# 56 ADR6 161 DATIl 109 INTB2# 196 RESET# 155 ADR7 162 DATI 2 110 INTB3# 59 ROMCS# 193 ADR8 163 DATI3 III INTB4# 65 SERR# 22 ADR9 166 DATI 4 112 INTC1# 199 STOP# 25 ADR10 167 DATI 5 113 INTC2# 195 TRDY# 29 ADRII 168 DATI 6 137 INTC3# 62 VCC 10 ADR12 169 DATI 7 138 INTC4# 66 VCC 26 ADR13 170 DATI 8 139 INTDl# 198 VCC 43 ADR14 171 DATI 9 140 INTD2# 194 VCC 61 ADR15 172 DAT20 141 INTD3# 63 VCC 97 ADR16 173 DATIl 143 INTD4# 67 VCC 114 ADR17 174 DAT22 144 IRDY 30 VCC 147 ADR18 175 DATI3 145 IRQ5 87 VCC 165 ADR19 176 DAT24 146 IR9 84 VCC 201 ADR20 178 DAT25 148 IRQI0 83 WBACK# llS ADR21 179 DATI6 149 IRQ 11 79 WR# 122 82C822 PCIB
3.1 Signal Descriptions Pin Signal Signal Name No. Type Signal Description
3.1.1 VESA Local Bus Interrace Signals RESET# 155 I Active low Reset Input LCLK 82 I VESA Local Bus Clock ADS# 129 I/O Address Data Strobe: Normally an input, this signal is only driven during PCI bus master cycles. ADS# is tristated when WBACK# is sampled active. This signal needs to be reasserted after WBACK# is released in order to restart the cycle. MIO# 121 1/0 Memory or I/O Status: Normally an input, this signal is an output during PCI bus master cycles. This signal is tristated when WBACK# is sampled active. WR# 122 I/O Write or Read Status: Normally an input, this signal is an output during PCI bus master cycles. This signal is tristated when WBACK# is sampled active. DC# 120 I/O Data or Code Status: Normally an input, this signal is an output during PCI bus mas- ter cycles. This signal is tristated when WBACK# is sampled active.
BE[3:0]# 133:136 I/O Byte Enables bits 3 through 0: Normally inputs, these signals are outputs during PCI bus master cycles. They are tristated when WBACK# is sampled active. BLAST# 128 1/0 Burst Last: Normally an input, this signal is an output during PCI bus master cycles. This signal is tristated when WBACK# is sampled active. DAT[31:0] 154: 148, 1/0 Data Lines bits 31 through 0: Normally inputs, these pins are outputs during CPUI 146: 143, VESAIDMAIISA master reads from PCl bus slaves (this includes reading the con- 141:137, figuration registers of the 82C822) or during PCI bus master write cycles. These pins 113:106, are tristated when WBACK# is sampled active. 99:98, 95:90 ADR[31:2] 189:178, I/O Address Lines bits 31 through 2: Normally inputs, these signals are outputs during 176:166, PCI bus master cycles. They are tristated when WBACK# is sampled active. 163:157
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Signal Descriptions (Cont.)
Pin Signal Signal Name No. Type Signal Description
LDEVO# 127 110 Local Device Output: this signal is usually connected to the LDEV# input pin of the OPTi VL chipset. When used as an output, LDEVO# is normally asserted in the next clock after ADS#, except during a restarted cycle due to BOFF# being asserted in the previous cycle. During DMAIISA bus master cycles, the assertion of LDEVO# is dependent on LMEM#, LDEVI#, the enable bit of the DMAIISA bus master to PCI slave access, and general purpose decoding blocks specified in the configuration register. The assertion of LDEVO# for DMAIISA bus master cycles is as follows: LMEM# LDEVI# LDEVO# o 1 1 1 o o 1 1 o (if enable bit = 1 or 0 and the access address is falling into the region specified in the general purpose decoding blocks) 1 (if enable bit = 0 and the access address is not falling into the region specified in the general purpose decoding blocks) As an input, it is latched at the trailing edge of the reset time and used to determine the sampling point ofLMEM# and LDEVI#. If sampled high during reset, the end of the first T2 is used as the sampling point, otherwise the end of the second T2 is used as the sampling point. LRDY# 125 o Local Ready: This signal is asserted when: 1) A CPUNESAIDMAIISA master accesses a PCI bus slave. 2) A CPUNESAlPCI bus master accesses an ISA slave (LRDY# is returned to ter minate the back-off cycle). 3) A PCI bus master accesses a PCI bus slave (in this case, LRDY# is asserted to terminate the cycle on the host bus).
BRDY# 131 110 Burst Ready: Normally an input, this signal is asserted when a CPUNESA master accesses a PCI bus slave and the cycle is burst-able. RDYRTN# 126 Ready Return: This signal is used by the 82C822 as a handshake to acknowledge the completion of the current cycle ..
WBACK# 118 Write-back: When WBACK# is active, the 82C822 floats all the address, data, and control signals which are driven onto the host bus during a PCI bus master cycle. The 82C822 needs to resume the back-off cycle when WBACK# becomes inactive again. LREQ# 116 o Local Bus Request: This signal, in conjunction with LGNT#, is used to gain control of the host bus. LREQ# goes active when anyone of the PCI bus masters asserts the REQn# to request the host bus. -82C822 PCIB Signal Descriptions (Cont.)
Pin Signal Signal Name No. Type Signal Description
LGNT# 115 I Local Bus Grant: This signal, in conjunction with LREQ#, is used to gain control of the host bus. Upon receiving LGNT#, the 82C822 grants the bus request by asserting GNTn# to one of the PCI bus masters. The active PCI bus master can be preempted by removing this signal. 3.1.2 PCI Interface Signals CLK 80 I Clock: This signal is used to provide timing for all transactions on the PCI bus. The clock source for this input can be the same input as LCLK for the synchronized mode, or the feedback ofPCICLK or the external oscillator. PCICLKIN 89 I PCI Clock Input: This clock input is used to generate the PCICLK[3:1] signals. PCICLK[3:1] 85,86,88 0 PCI Clock [3: 1]: In the asynchronous mode, these signals are used as the clock inputs to the PCI slots and should be fedback to the CLK input (pin 80). AD[31:0] 33:37, I/O Multiplexed Address and Data Lines, bits 31 through 0: These pins are the multi- 39:41, plexed PCI address and data lines. During the address phase, these pins are inputs 19:16, for PCI bus master cycles; otherwise they are outputs. During the data phase, these 14:11, pins are inputs during PCI bus master write cycles or during CPUNESAIDMAIISA 44:51,8:1 reads from a PCI bus slave; otherwise they are outputs. C/BE[3:0]# 32,20,42, I/O Bus Command and Byte Enables, bits 3 through 0: These pins are the multiplexed 9 PCI command and byte enable lines. Normally outputs, these pins are inputs during PCI bus master cycles. PAR 21 I/O Parity: This signal is an input either during PCI bus master cycles for address and write data phases or during PCI bus slave cycles for read data phases; otherwise it is an output. FRAME# 31 I/O Cycle Frame: This pin is driven by PCI bus masters to indicate the beginning and duration of an access. Normally an input, FRAME# is driven during CPUNESAI DMAIISA master accesses to PCI bus slaves. IRDY# 30 I/O Initiator Ready: This signal is asserted by PCI bus masters to indicate the ability to complete the current data phase of the transaction. Normally an input, this pin is driven during CPUNESAIDMAIISA master accesses to PCI bus slaves. TRDY# 29 I/O Target Ready: This pin is asserted by the target to indicate the ability to complete the current data phase of the transaction. Normally an input, this pin is driven during PCI bus master accesses to local memory, VESAIISA slaves, and the configuration register inside the 82C822. STOP# 25 I/O Stop: This signal is used by the target to request the master to stop the current trans- action. Normally an input, this signal is driven during PCI bus master accesses to local memory and VESAIISA slaves. LOCK# 24 I Lock: This signal is used to indicate an atomic operation that may require multiple transactions to complete. Since the 82C822 will never assert this signal, it is always an input.
[Ilill Page 8 DS-Ol-82C822-09 82C822 PCIB 82C822 PCIB
Signal Descriptions (Cont.)
Pin Signal Signal Name No. Type Signal Description
DEVSEL# 28 110 Device Select: This pin is an output when the 82C822 decodes its address as the tar- get of the current access via either positive or negative decoding; otherwise it is an input. INTD[4:1]#, 67,63, I PCI Interrupt Lines D-A for Slots 4-1: These signals are used to generate synchro-
INTC[4: 1]# I 194, 198, nous interrupt requests to the CPU via the programmable interrupt controllers. INTB[4:1]#, 66,62, INTA[4:1]# 195, 199, 65,59, 196,202, 64,58, 197,203 PERR# 23 I/O Parity Error: This pin is used to report data parity errors during all PCI transactions except during a Special Cycle. Normally an input, PERR# is driven when data parity errors occur either during a PCI bus master write cycle or during a CPUIVESAI DMAIISA master read from a PCI slave. SERR# 22 OD System Error: This signal is used to report address parity errors, or data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. This pin is an open drain. REQ[4:1]# 56,54, I Request Lines, bits 4 through 1: These signals are used by PCI bus masters to 205,207 request use of the PCI bus. GNT[4:1]# 57,55, 0 Grant Lines, bits 4 through 1: These signals are used to indicate to a PCI bus master 204,206 that the access to the bus has been granted. 3.1.3 Miscellaneous Interface Signals LDEVI# 124 I Local Device Input: This input is an ANDed signal of all LDEV# signals from VESA bus slaves; it is used to indicate to the 82C822 whether the current access is to VESA slave. NMI 117 0 Non-Maskable Interrupt: This output is asserted in response to an active PERR# or SERR# if the enable bit of the NMI generation for an active PERR# or SERR is set. NMI will not be asserted if bit 7 of Port 70 is set to 1. If the NMIIN input pin is con- nected to the NMI of the other chipset, then this output will go active in response to an active NMIIN also.
NMIIN 104 I Non-Maskable Interrupt Input: This input is the non-maskable interrupt input signal generated from the other chipset. The 82C822 will combine this input with its inter- nal NMI signal and generate a new NMI to the CPU. In the case where this pin is not used, an external pull-down resistor is recommended. BOFF# 123 0 Back-Off: This output is asserted when the assumed destination of the access for the current cycle turns out to be wrong and the cycle needs to be restarted in order to access the right target; it is asserted during a CPU or VESA bus master cycle to abort the cycle if the current access is to an ISA slave. LDEVO# is asserted as welL ATCLK 74 I ISA AT clock: The 8MHz ISA AT clock.
DS·01-82C822-09 Pal!e 9 82C822 PCIB
Signal Descriptions (Cont.)
Pin Signal Signal Name No. Type Signal Description
MASTER# 73 I ISA Master Cycle: This input is used to indicate to the 82C822 the current cycle is an ISA bus master cycle. AEN 72 I ISA Address Enable: This input is used to indicate to the 82C822 that the current cycle is either a DMA or refresh cycle. RFSH# 71 I ISA Refresh: An input signal used to indicate to the 82C822 that the current cycle is a refresh cycle.
HBE4# 132 I CPU Byte Enable 4: This signal is used only with Pentium chipsets. LMEM# 75 I Local Memory: When the enable bit at the top of the local memory decoding is dis- abled, this input is used to indicate to the 82C822 if the current access is to local memory. When the enable bit at the top of the local memory decoding is enabled, then internal decoding result for LMEM# is used and this input pin is ignored. IRQ[15:14], 76:79,83, aD PIC Interrupt Request Lines, bits 15, 14, 12 through 9, and 5: These outputs are con- IRQ[12:9], 84,87 nected to the PC-compatible programmable interrupt controllers (PIC) to generate IRQ5 asynchronous interrupts to the CPU in response to INTD[4:1]#, INTC[4:1]#, INTB[4: 1]#, and INTA[4: 1]#. The routing of each PCI interrupt line to the PC-com- patible interrupts is controlled by four bits specified in the configuration register. ROMCS# 193 a PCI ROM BIOS Chip Select: Used to select the BIOS ROM used to configure the chipset. NVMCS# 192 a Non-Volatile Memory Chip Select: This output signal is used to select the non-vola- tile memory in which the system information is stored; the memory address space for the non-volatile memory is always a 16KB chuck and between C8000h and DFFFFh. It is used to select any ROM located in the memory address space from EOOOOh to EFFFFh. 3.1.4 Power, Ground, and Reserved Pins VCC 10,26,43, PWR Power Connection 61,97, 114, 147, 165,201 GND 15,27,38, GND Ground Connection 52,53,60, 81,96, 105, 119, 130,142, 156, 164, 177, 190, 200,208 NC 68:70, No Connection: These pins are reserved. 100:103, 191
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4.0 Functional Description The following sub-sections will explain the various cycle oper The OPTi VL chipset will then return BRDY# after the data is ations the 82C822 PCIB perfonns to detennine which memory transferred. The 82C822 also detennines that the cycle is a space should be local and which is located on the ISA bus. local memory cycle and takes no action other than to deassert LDEVO# after the last BRDY#. 4.1 CPU Cycles VESA Slave Accesses The VL bus master begins the cycle. The 82C822 asserts CachelDRAM Accesses LDEVO# on the next clock. It then samples LDEVI# and, The CPU begins the cycle. The 82C822 asserts LDEVO# on determining that the cycle is a VESA cycle, takes no further the next clock in response to LADS# (VESA local bus ADS#). action. The VESA slave will then return LRDY#ILBRDY# In the OPTi Pentium chipsets, LADS# will not be generated after the data is transferred. RDYRTN# will be generated by for a local memory cycle and therefore, LDEVO# will not be the OPTi VL chipset. The 82C822 deasserts LDEVO# after the generated by the 82C822. In the OPTi 486 chipsets, the CPU last LBRDY#. will generate LADS# (LADS# and CPU ADS# are the same in PCI slave accesses the 486 implementation). The 82C822 will generate LDEVO#, The VL bus master begins the cycle. The 82C822 asserts but this will be ignored by the OPTi 486 chipsets during a local LDEVO# on the next clock. It then detennines that the cycle is memory cycle. In this case, the 82C822 will de assert LDEVO# a PCI slave cycle and starts the PCI cycle after synchroniza after the last BRDY#. tion. Data is latched into the 82C822 for read cycles. The VESA Slave Accesses 82C822 returns LRDY# to the OPTi VL chipset and de asserts The CPU begins the cycle. The 82C822 asserts LDEVO# on LDEVO#. the next clock in response to ADS#. The VESA slave willgen ISA Slave Accesses erate LDEVI# to the 82C822 at the end of the first T2 or sec The VL bus master begins the cycle. The 82C822 asserts ond T2 (depending on the VL speed). At this po in, the 82C822 LDEVO# on the next clock. It then detennines that the cycle is will keep asserting LDEVO# until the VESA slave returns not a local memory or VESA slave cycle and starts the PCI LRDY#ILBRDY#. cycle after synchronization. The 82C822 receives a master PCI Slave Accesses abort termination and asserts LRDY# and BOFF# at the same The CPU begins the cycle. The 82C822 asserts LDEVO# on time after synchronization. The 82C822 returns LRDY# and the next clock. It then detennines that the cycle is a PCI slave deasserts LDEVO# on the next clock. The CPU restarts the cycle and starts the PCI cycle after synchronization. Data is aborted cycle. The 82C822 ignores the restarted cycle by keep latched into the 82C822 for read cycles. The 82C822 com ing LDEVO# inactive. The OPTi VL chipset returns RDY# to pletes the cycle, returns LRDY#, and deasserts LDEVO#. the CPU at the end of the AT cycle. ISA slave accesses The CPU begins the cycle. The 82C822 asserts LDEVO# on 4.3 PCI Master Cycles the next clock. It then detennines that the cycle is not a local CachelDRAM Accesses memory or VESA slave cycle and starts the PCI cycle after The PCI master begins the cycle by asserting PCI REQ# to the synchronization. The 82C822 receives master-abort tennina 82C822. The 82C822 asserts LREQ# to the OPTi VL chipset tion and asserts LRDY# and BOFF# at the same time after syn after arbitration of the bus requests from the PCI bus masters. chronization. The 82C822 returns LRDY# and deasserts The 82C822 receives LGNT# from the OPTi VL chipset and LDEVO# on the next clock. The CPU restarts the aborted generates the appropriate VL bus signals according to the PCI cycle. The 82C822 ignores the restarted cycle by keeping command, address, and status lines. The 82C822 asserts LDEVO# inactive. The OPTi VL chipset returns RDY# to the LDEVO# on the next clock. The OPTi VL chipset detennines CPU at the end of the AT cycle. that the cycle is a local memory cycle. The 82C822 also deter mines that the cycle is a local memory cycle and asserts 4.2 VESA Master Cycles DEVSEL# to claim the cycle. Data is latched into the 82C822 for read cycles. The OPTi VL chipset returns RDY# to the CachelDRAM Accesses 82C822 and the 82C822 deasserts LDEVO#. The 82C822 The VL bus master begins the cycle. The 82C822 asserts returns TRDY# to the PCI bus master after synchronization. LDEVO# on the next clock. The OPTi VL chipset detennines The 82C822 deasserts DEVSEL# after the last transfer. that the cycle is a local memory cycle and ignores LDEVO#. m:am 82C822 pelB
VESA Slave Accesses 4.4 DMAIISA Master Cycles The PCl master begins the cycle by asserting PCl REQ# to the CachelDRAM Accesses 82C822. The 82C822 asserts LREQ# to the OPTi VL chipset The OPTi VL chipset determines that the DMA/ISA master after arbitration of the bus requests from the PCl bus masters. cycle is accessing local memory once the command is asserted. The 82C822 receives LGNT# from the OPTi VL chipset and The OPTi VL chipset asserts MEMCS16#. LADS# will not be generates the appropriate VL bus signals according to the PCl generated by the OPTi VL chipset. No action is taken by the command, address, and status lines. The 82C822 asserts 82C822. LDEVO# on the next clock. It then determines that the cycle is a VESA slave cycle and asserts DEVSEL# to claim the cycle. VESA Slave Accesses Data is latched into the 82C822 for read cycles. The OPTi VL The OPTi VL chipset determines that the DMA/ISA master chipset returns RDY# to the 82C822 and the PCIB deasserts cycle is a not a local memory cycle once the command is LDEVO#. The 82C822 returns TRDY# to the PCl bus master asserted. The OPTi VL chipset will generate the VESA local after synchronization. The 82C822 deasserts DEVSEL# after bus command lines. In response to LADS#, the 82C822 will the last transfer. assert LDEVO#. The 82C822 will receive LDEVI# by the next or subsequent clock. The OPTi chipset pulls IOCHRDY PCI Slave Accesses low to stall the command. The OPTi VL chipset samples The PCI master begins the cycle by asserting PCI REQ# to the LDEVO# active. If the cycle is a read cycle, the OPTi VL 82C822. The 82C822 asserts LREQ# to the OPTi VL chipset chipset will start driving the SD bus. LRDY# is asserted by the after arbitration of the bus requests from the PCl bus masters. VESA slave. The OPTi VL chipset releases IOCHRDY and The 82C822 receives LGNT# from the OPTi VL chipset and asserts RDY# at the end of the command after synchronization. generates the appropriate VL bus signals according to the PCI The 82C822 takes no action other than to deassert LDEVO# as command, address, and status lines. The 82C822 asserts soon as LDEVI# goes inactive. The OPTi VL chipset deas LDEVO# on the next clock. It then determines that the cycle is serts MEMCS16# when LDEVO# goes inactive. a PCI slave cycle and waits for DEVSEL# from the PCI slave. On receiving DEVSEL#, the 82C822 generates LRDY# to the PCI Slave Accesses OPTi VL chipset. The 82C822 deasserts LDEVO# after The OPTi VL chipset determines that the DMA/ISA master RDY#. Any data latched by the 82C822 for read cycles is cycle is a not a local memory cycle once the command is ignored. asserted. The OPTi VL chipset will generate the VESA local bus command lines. In response to LADS#, the 82C822 will ISA Slave Accesses assert LDEVO#. The OPTi VL chipset pulls IOCHRDY low The PCI master begins the cycle by asserting PCI REQ# to the to stall the command. The OPTi VL chipset samples LDEVO# 82C822. The 82C822 asserts LREQ# to the OPTi VL chipset active and pulls MEMCS16# low if the command is not an I/O after arbitration of the bus requests from the PCl bus masters. cycle. The 82C822 starts the PCI cycle after synchronization. The 82C822 receives LGNT# from the OPTi VL chipset and Data is latched into the 82C822 for read cycles when both generates the appropriate VL bus signals according to the PCI TRDY# and IRDY# are active. The 82C822 asserts LRDY# command, address, and status lines. The 82C822 asserts after synchronization. The OPTi VL chipset releases LDEVO# on the next clock. It then determines that the cycle is IOCHRDY and asserts RDY# at the end of the command after a not a local memory or VESA slave cycle and, detecting no synchronization. The 82C822 deasserts LDEVO# at the end of DEVSEL# from the PCI slave, realizes the cycle is an ISA the bus cycle. The OPTi chipset de asserts MEMCS16# when slave cycle. The 82C822 then asserts LRDY# to the 802G and LDEVO# goes inactive. generates an internal BOFF# signal after synchronization. RDY# is returned to the 82C822 when LRDY# is generated. ISA Slave Accesses The 82C822 deasserts LDEVO# the next clock after RDY#. The OPTi VL chipset determines that the DMAIISA master The 82C822 restarts the aborted cycle by asserting the VL bus cycle is a not a local memory cycle once the command is address and command signals, keeping LDEVO# high for the asserted. The OPTi VL chipset will generate the VESA local restarted cycle. The OPTi VL chipset forwards the restarted bus command lines. In response to LADS#, the 82C822 will cycle to the AT bus. The OPTi VL chipset returns LRDY# to assert LDEVO#. The OPTi VL chipset pulls 10CHRDY low the 82C822 at the end of the AT cycle. The data is latched into to stall the command. The OPTi VL chipset samples LDEVO# the 82C822 for the read cycle when it returns RDY# to the active and pulls MEMCS16# low if the command is not an 1/0 OPTi VL chipset. The 82C822 returns TRDY# to the PCI mas cycle. The 82C822 starts the PCl cycle after synchronization. ter after synchronization. The 82C822 deasserts DEVSEL# The PCI bridge will receive the master-abort termination. after the data is transferred.
WQiil Page 12 DS-Ol-82C822-09 82C822 PCIB 82C822 PCIB
LRDY# is asserted and LDEVO# is deasserted at the same the 82C822 to translate that CONFIG_ADDRESS value to the time by the 82C822 after synchronization. The OPTi VL requested configuration cycle on the PCI bus. chipset releases 10CHRDY and remains tristated on the SD Below is an example to read the address offset OOh of the bus. The OPTi VL chipset asserts RDY# at the end of the com 82C822 configuration space: mand after synchronization. MOV EAX,80008000h ;specifies device, function, register number 4.5 Guidelines to Program the 82C822 MOV DX,OCF8h ;CONFIG_ADDRESS The following briefly describes how to access the 82C822 and OUT EDX,EAX the PCI devices on the slots. The 82C822 uses the PCI Config MOV DX,OCFCh uration Mechanism #1 to access the configuration spaces. Two IN EAX,EDX double-word I/O locations are used in this mechanism. The The content of the CONFIG_ADDRESS showing above pos first double-word location (CF8h) references a read/write reg sesses the following meanings (device number IOOOOb means ister that is name CONFIG_ADDRESS. The second double OPTi 82C822 chose AD16 as the IDSEL) as shown in Table 4- word address (CFCh) references a register name 1. CONFIG_DATA. The general mechanism for accessing the configuration space is to write a value into In the OPTi 82C802G/82C822 demo design, we chose AD 17, CONFIG_ADDRESS that specifies the PCI bus, the device on AD18, and AD19 as the IDSEL line for the three PCI slots. that bus, and the configuration register in that device being Tables 4-2 through 4-4 show the address to access the PCI slots accessed. A read or write to CONFIG_DATA will then cause number I, 2, and 3, accordingly.
Table 4-1 CONFIG_ADDRESS Example
31 30 24 23 ." 16 15 11 10 8 7 2 1 0 1 Reserved Bus Number Device Number Function Number Register Number 0 0 1 0000000 00000000 10000 000 000000 0 0 80h OOh 80h OOh
Table 4-2 PCI Slot 1 Example
31 30 24 23 16 15 11 10 8 7 2 1 0 1 Reserved Bus Number Device Number Function Number Register Number 0 0 1 0000000 00000000 10001 OOO/xxx xxxxxx 0 0 80h OOh 88h18xh xxh
Table 4-3 PCI Slot 2 Example 31 30 24 23 16 15 11 10 8 7 2 1 0 1 Reserved Bus Number Device Number Function Number Register Number 0 0 1 0000000 00000000 10010 OOO/xxx xxxxxx 0 0 80h OOh 90hl9xh xxh
Table 4-4 PCI Slot 3 Example
31 30 24 23 16 15 11 10 8 7 2 1 0 1 Reserved Bus Number Device Number Function Number Register Number 0 0 1 0000000 00000000 10011 OOO/xxx xxxxxx 0 0 80h OOh 98h19xh xxh
82C822 PCIB 05-01-82C822-09 Page 13 82C822 PCIB
4.6 Asynchronous and Synchronous Modes of Operation The 82C822 supports both synchronous and asynchronous The synchronous mode of operation is recommended when the modes of operation. In the synchronous mode, the PCI bus VL bus is operating below 33MHz. The clock circuitry should interfaces runs at the same speed as the VL bus. In the asyn follow the block diagram in Figure 4-1 for synchronous mode chronous mode, the PCI bus can run at a different speed than of operation. the VL bus. This facilitates the VL bus to run at 50MHz with The asynchronous mode of opeation is recommended when the the PCI running at 33MHz. The recommended clock circuitry VL bus is running at 50MHz or to implement PCI interface in for both asynchronous and synchronous modes are shown in the riser card. The clock circuitry should follow the block dia Figure 4-1. gram given in Figure 4-2 of the asynchronous mode of opera-
Figure 4-1 Synchronous Mode
Vl Chipset
VL Bus 82C822
I 82 Clock lClK I 1 80 I ClK PCI Slot Clocks
Clock Buffer Note: Skew between clock buffer outputs should be less than 2ns.
Figure 4-2 Asynchronous Mode
r-- 82C822 PCI Slot Clocks 82 85 lClK V l 86 B u ~ ClK 88 s V
'--- 89 I OSC I
(I]ill DS-01-82C822-09 82C822 PCIB 82C822 PCIB .. ~ 19
5.0 Configuration Registers
5.1 PCI Configuration Register Space Note: In the address offsets given below, the most significant bit (MSB) corresponds to the upper address offset. The default values for the address offsets are given on the top right of the tables.
Table 5-1 Address Offset OOh-01h 1045h Bit(s) Type Default Function 15:0 RO 1045h Vendor Identification Register
Table 5-2 Address Offset 02h-03h C822h Bit(s) Type Default Function 15:0 RO C822h Device Identification Register
Table 5-3 Address Offset 04h-05h: Command Register 0007h Bit(s) Type Default Function 15:10 RO 000000 Reserved Bits 9 RO 0 Enable Fast Back-to-Back: Must always = 0 otherwise the 82C822 will never generate fast back-to-back transactions to different PCI bus slaves. 8 R1W 0 SERR# Enable: O=Disable 1 = Enable 7 RO 0 Wait Cycle Control: Must always = 0 always. No programmable wait states are supported by the 82C822. 6 R1W 0 Enable Parity Error Response: o = Disable 1 = Enable 5 RO 0 Reserved Bit 4 RO 0 Enable Memory Write and Invalidate Cycle Generation: Must always = O. No memory write and invalidate cycles will be generated by the 82C822. 3 RO 0 Enable Special Cycles: Must always = O. The 82C822 does not respond to the PCI special cycle. 2 RO 1 Enable Bus Master Operations: Must always = 1. The allows the 82C822 to perform bus master operations all the time. 1 RO 1 Enable Memory Access: Must always = I. The 82C822 allows a PCI bus master access to main memory all the time. 0 RO 1 Enable I/O Access: Must always = 1. The 82C822 allows a PCI bus master access to the PCI I/O all the time.
Page 14 82C822 PCIB
Table 5-4 Address Offset 06h-07h: Status Register 0280h Bit(s) Type Default Function 15 RlW 0 Detected Parity Error: o= No parity error I = Parity error occurred 14 RO 0 SERR# Status: o= No system error 1 = System error occurred 13 RJW 0 Master-Abort Status: 0= No master abort 1 = Master abort occurred 12 RO 0 Received Target-Abort Status: o= No target abort 1 = Target abort occurred 11 RlW 0 Signaled Target-Abort Status: 0= No target abort 1 = Target abort generated 10:9 RO 01 DEVSEL# Timing Status: These bits must always = 01. Medium timing is selected. The 82C822 asserts the DEVSEL# based on medium timing. 8 RJW 0 Data Parity Detected: o = No data parity detected I = Data parity has detected 7 RJW I Fast Back-to-Back Capable: I = Capable o= Not Capable Note: Can be set to 0 only when bit 2 of register at offset 52h is set to 0; for debugging purposes only. 6:0 RO 0000000 Reserved Bits
Table 5-5 Address Offset 08h Olh Bit(s) Type Default Function 7:0 RO OIh Revision Identification Register
Table 5-6 Address Offset 09h-OBh 060000h Bit(s) Type Default Function 23:0 RO 060000h Revision Identification Register
Table 5-7 Address Offset oeh OOh Bit(s) Type Default Function 7:0 RO OOh Reserved Bits
Table 5-8 Address Offset ODh 20h Bit(s) Type Default Function 7:0 RlW 20h Master Latency Timer Register [']lIlI 82C822 PCIB DS-01-82C822-09 Page 15 82C822 pelB
Table 5-9 Address Offset OEh OOh
Bit(s) Type Default Function
7:0 RO OOh Header Type
Table 5-10 Address Offset OFh OOh
Bit(s) Type Default Function
7:0 RO OOh BIST
Table 5-11 Address Offset 10h-3Fh OOh
Bit(s) Type Default Function
7:0 RO OOh Reserved Bits
Table 5-12 Address Offset 40h-41h OCOlh
Bit(s) Type Default Function
15 RIW 0 82C822 PCI Bridge Enable: o= Disable 1 = Enable 14 R/W 0 CPU Type Select: 0= Ll Write-through CPU I = L I Write-back CPU 13:12 RO 00 Reserved Bits 11:10 R/W IX The delay ofLRDY# after the assertion ofBOFF#: 11 10 Delay 0 0 No Delay 0 I 1 LCLKDelay 1 x 2 LCLKDelay 9 R/W 0 Disable LDEVO# Assertion during Local Memory Cycle: o = Enable 1 = Disable 8 RIW 0 Disable BOFF# Assertion: 0= No retry error 1 = Retry error occurred 7 R/W 0 Enable NM:IIN Input: 0= Disable 1 = Enable 6 R/W 0 Enable Back-to-Back CFC read/write without CF8 write: 0= Disable I = Enable 5:3 RO 000 Reserved Bits 2 RO 0 NMI Output Enable (via Port 70h) Status: o= NMI Output Disable 1 = NMI Output Enable I RO 0 Master Retry Status: o = No retry error I = Retry error has occurred 0 RO 1 LMEM#ILDEVI# Sampling Point Select: I = End of the first T2 o= End of the second T2
Page 16 DS-01-fl2C822-09 820322 PCIB 82C822 pelB
Table 5-13 Address Offset 42h-43h OOOOh
Bit(s) Type Default Function
15:4 RJW 20h A[31 :20] for the Top of Local Memory Decoding. 3 RJW OOh Enable Top of Local Memory Decoding: 0= Disable 1 = Enable Note: If bit 3 is enabled, then the LMEM# input pin is ignored; otherwise an external LMEM# is used to decide if the access for the current cycle is to local memory Bits Top of Bits Top of 15:4 Memory 15:4 Memory OOOh 1MB 03Fh 64MB 001h 2MB : 002h 3MB 07Fh 128MB 003h 4MB OFFh 256MB OOFh 16MB : : : lOOh Reserved OIFh 32MB FFFh Reserved 2:0 RO 000 Reserved Bits
Table 5-14 Address Offset 44h OOh
Bit(s) Type Default Function
7:6 RJW 00 Master Retry Timer: 7 6 Operation 0 0 Retries unmasked after 8 PCICLKs 0 1 Retries unmasked after 16 PCrCLKs 1 0 Retries unmasked after 32 PCrCLKs 1 1 Retries unmasked after 64 PCrCLKs 5:4 RO 00 Reserved Bits 3 RJW 0 LMEM#ILDEV# sampling point select for pcr master cycle: o = I pcr clock after FRAME# 1 = 2 pcr clocks after FRAME# 2 RO 0 Reserved Bit 1 RJW 0 Enable Read Shadowed RAM for FOOOOh-FFFFFh Block: O=Disable 1 = Enable 0 RJW 0 Enable Write Shadowed RAM for FOOOOh-FFFFFh Block: 0= Disable 1 = Enable
82C822 PCIB DS-01-82C822-09 Page 17 82C822 pels
Table 5-15 Address Offset 45h OOh
Bit(s) Type Default Function
7 R/W 0 Enable Read Shadowed RAM for ECOOOh-EFFFFh Block: 0= Disable I = Enable 6 RJW 0 Enable Read Shadowed RAM for ESOOOh-EBFFFh Block: 0= Disable I = Enable 5 R/W 0 Enable Read Shadowed RAM for E4000h-E7FFFh Block: o = Disable I = Enable 4 R/W 0 Enable Read Shadowed RAM for EOOOOh-E3FFFh Block: 0= Disable 1 = Enable 3 R/W 0 Enable Write Shadowed RAM for ECOOOh-EFFFFh Block: 0= Disable 1 = Enable 2 R/W 0 Enable Write Shadowed RAM for ESOOOh-EBFFFh Block: 0= Disable 1 = Enable I R/W 0 Enable Write Shadowed RAM for E4000h-E7FFFh Block: 0= Disable I = Enable 0 R/W 0 Enable Write Shadowed RAM for EOOOOh-E3FFFh Block: 0= Disable 1 = Enable
Table 5-16 Address Offset 46h OOh
Bit(s) Type Default Function
7 R/W 0 Enable Read Shadowed RAM for DCOOOh-DFFFFh Block: 0= Disable 1 = Enable 6 R/W 0 Enable Read Shadowed RAM for DSOOOh-DBFFFh Block: 0= Disable 1 = Enable 5 RlW 0 Enable Read Shadowed RAM for D4000h-D7FFFh Block: 0= Disable I = Enable 4 RlW 0 Enable Read Shadowed RAM for DOOOOh-D3FFFh Block: 0= Disable 1 = Enable 3 RlW 0 Enable Write Shadowed RAM for DCOOOh-DFFFFh Block: 0= Disable 1 = Enable 2 R/W 0 Enable Write Shadowed RAM for DSOOOh-DBFFFh Block: 0= Disable 1 = Enable I RlW 0 Enable Write Shadowed RAM for D4000h-D7FFFh Block: O=Disable I = Enable 0 RlW 0 Enable Write Shadowed RAM for DOOOOh-D3FFFh Block: 0= Disable 1 = Enable
Page 18 05-01-82C822-0.9 82C822 PCIB 82C822 PCIB
Table 5-17 Address Offset 47h OOh
Bit(s) Type Default Function
7 RJW 0 Enable Read Shadowed RAM for CCOOOh-CFFFFh Block: O=Disable I = Enable 6 RJW 0 Enable Read Shadowed RAM for C8000h-CBFFFh Block: 0= Disable I = Enable 5 RJW 0 Enable Read Shadowed RAM for C4000h-C7FFFh Block: o= Disable I = Enable 4 RJW 0 Enable Read Shadowed RAM for COOOOh-C3FFFh Block: O=Disable I = Enable 3 RJW 0 Enable Write Shadowed RAM for CCOOOh-CFFFFh Block: o = Disable I = Enable 2 RJW 0 Enable Write Shadowed RAM for C8000h-CBFFFh Block: o = Disable I = Enable I RJW 0 Enable Write Shadowed RAM for C4000h-C7FFFh Block: 0= Disable I = Enable 0 RJW 0 Enable Write Shadowed RAM for COOOOh-C3FFFh Block: O=Disable 1 = Enable
Note: Address offsets 48h-SIh are meant for setting the local memory holes 0-3.
Table 5-18 Address Offset 48h OOh
Bit(s) Type Default Function
7 RJW 0 Enable Memory Hole 3: 0= Disable I = Enable 6:4 RJW 000 Block Size for Memory Hole 3 3 RJW 0 Enable Memory Hole 2: O=Disable I = Enable 2:0 RJW 000 Block Size for Memory Hole 2
82C822 PCIB DS-Ol-82C822-09 Page 19 82C822 PCIB
Table 5-19 Address Offset 49h OOh Bit(s) Type Default Function
7 R/W 0 Enable Memory Hole 1: 0= Disable 1 = Enable 6:4 RJW 00 Block Size for Memory Hole 1 3 R/W 0 Enable Memory Hole 0: 0= Disable 1 = Enable 2:0 RJW 0 Block Size for Memory Hole 0: Block Size Definition 2 1 0 Size 0 0 0 64KB 0 0 1 128KB 0 1 0 256KB 0 1 1 512KB I 0 0 1MB 1 0 1 2MB I I 0 4MB 1 1 1 8MB
Table 5-20 Address Offset 4Ah-4Bh OOOOh
Bit(s) Type Default Function
15:0 R/W OOOOh A[31: 16] for Starting Address of Memory Hole 3
Table 5-21 Address Offset 4Ch-4Dh OOOOh
Bit(s) Type Default Function 15:0 R/W OOOOh A[31:16] for Starting Address of Memory Hole 2
Table 5-22 Address Offset 4Eh-4Fh OOOOh
Bit(s) Type Default Function 15:0 R/W OOOOh A[31:16] for Starting Address of Memory Hole I
Table 5-23 Address Offset 50h-51h OOOOh
Bit(s) Type Default Function
15:0 RJW OOOOh A[31: 16] for Starting Address of Memory Hole 0
Page 20 05-01-82C822-09 82C822 pelB ------~------Table 5-24 Address Offset 52h 06h
Bit(s) Type Default Function
7 RlW 0 DMAIISA Bus Master to PCI Bus Slave Access Enable: O=Disable 1 = Enable 6 RlW 0 Enable Write Buffers from Host Bus to PCI Bus: 0= Disable 1 = Enable 5 RlW 0 Enable Write Buffers from PCI Bus to Host Bus: 0= Disable 1 = Enable 4 RlW 0 Disable NMI Generation Globally: o = Disable 1 = Enable 3 RlW 0 Enable SERR# Generation for Target Abort: O=Disable 1 = Enable 2 RIW 1 Fast Back-to-Back Capable: 1 = Enable O=Disable Note: The change on this bit will reflect on bit 7 of the register in address offset 06h. 1:0 RIW 10 Subtractive Decoding Sample Point: 1 0 Operation 0 0 Fast sample point 0 1 Typical sample point 1 0 Slow sample point
Table 5-25 Address Offset 53h 90h
Bit(s) Type Default Function
7 RlW I PCI Bus Clock Synchronous to System Clock Enable: 1 = Asynchronous Clock o= Synchronous Clock 6 RlW 0 Host-to-PCI Bus FIFO Wait State: o =No Wait 1 =One Wait 5 RIW 0 Conversion of PERR# to SERR# Enable: o = Disable 1 = Enable 4 RIW 1 Enable Address Parity Checking: 1 = Enable o= Disable 3 RlW 0 Enable Conversion of PC I Shared Interrupts to ISA Edge Triggered Interrupts: 0= Disable 1 = Enable 2 RlW 0 Expansion Bus Selection: O=ISA bus 1 = EISA 1 RlW 0 PCI Bus Burst Cycle Enable: 0= Disable 1 = Enable 0 RlW 0 Host Bus to PCI Bus Post Write Enable: 0= Disable 1 = Enable
CI1QI:it1 82C822 PCIS DS-Ol-82C822-09 Page 21 82C822 pelB
Table 5-26 Address Offset 54h-57h OOOOOOOOh
Bit(s) Type Default Function
31:8 RlW OOOOOOh A[31 :8] for Starting Address of General Purpose decode Block 3 for PCI Address Space 7:2 RlW 000000 A[7:2] for Starting Address of General Purpose decode Block 3 for PCI Address Space I RlW 0 Enable Block 3 Decoding Function: O=Disable I = Enable 0 RIW 0 Memory or I/O Space Indicator for Block 3: o = Memory Space I = I/O Space Note: lfbit 0 = 0, then A[3:2] are ignored on decoding.
Table 5-27 Address Offset 58h-5Bh OOOOOOOOh
Bit(s) Type Default Function
31:8 RIW OOOOOOh A[31 :8] for Ending Address of General Purpose decode Block 3 for PCI Address Space 7:2 RIW 000000 A[7:2] for Ending Address of General Purpose decode Block 3 for PCI Address Space 1:0 RO 00 Reserved Bits
Table 5-28 Address Offset 5Ch-5Fh OOOOOOOOh
Bit(s) Type Default Function
31:8 RIW OOOOOOh A[31 :8] for Starting Address of General Purpose decode Block 2 for PCI Address Space 7:2 RlW . 000000 A[7 :2] for Starting Address of General Purpose decode Block 2 for PCI Address Space I RlW 0 Enable Block 2 Decoding Function: 0= Disable I = Enable 0 RIW 0 Memory or I/O Space Indicator for Block 2: o = Memory Space I = I/O Space Note: lfbit 0 = 0, then A[3:2] are ignored on decoding.
Table 5-29 Address Offset 60h-63h OOOOOOOOh
Bit(s) Type Default Function
31:8 RlW OOOOOOh A[31 :8] for Ending Address of General Purpose decode Block 2 for PCI Address Space 7:2 RIW 000000 A[7 :2] for Ending Address of General Purpose decode Block 2 for PCI Address Space 1:0 RO 00 Reserved Bits
Page 22 DS-01-82C822-09 82cn-"~ PCIB 82C822 PCIB
Table 5-30 Address Offset 64h-67h OOOOOOOOh
Bit(s) Type Default Function
31:8 RfW OOOOOOh A[31 :8] for Starting Address of General Purpose decode Block 1 for PCI Address Space 7:2 RfW 000000 A[7:2] for Starting Address of General Purpose decode Block 1 for PCI Address Space 1 RfW 0 Enable Block 1 Decoding Function: o= Disable I = Enable 0 RfW 0 Memory or I/O Space Indicator for Block 1: o= Memory Space 1 = 1/0 Space Note: Ifbit 0 = 0, then A[3:2J are ignored on decoding.
Table 5-31 Address Offset 68h-6Bh OOOOOOOOh
Bit(s) Type Default Function
31:8 RfW OOOOOOh A[31 :8J for Ending Address of General Purpose decode Block 1 for PCI Address Space 7:2 RfW 000000 A[7:2J for Ending Address of General Purpose decode Block 1 for PCI Address Space 1:0 RO 00 Reserved Bits
Table 5-32 Address Offset 6Ch-6Fh OOOOOOOOh
Bit(s) Type Default Function
31 :8 RfW OOOOOOh A[31 :8] for Starting Address of General Purpose decode Block 0 for PCI Address Space 7:2 RJW 000000 A[7:2] for Starting Address of General Purpose decode Block 0 for PCI Address Space 1 RlW 0 Enable Block 0 Decoding Function: o = Disable I = Enable 0 RlW 0 Memory or 1/0 Space Indicator for Block 0: o = Memory Space 1 = I/O Space Note: If bit 0 = 0, then A[3:2] are ignored on decoding.
Table 5-33 Address Offset 70h-73h OOOOOOOOh
Bit(s) Type Default Function
31 :8 RJW OOOOOOh A[31 :8] for Ending Address of General Purpose decode Block 0 for PCI Address Space 7:2 RJW 000000 A[7:2J for Ending Address of General Purpose decode Block 0 for PCI Address Space 1:0 RO 00 Reserved Bits
82C822 PCIS DS-01-82C822-09 Page 23 82C822 pels inr',
Table 5-34 Address Offset 74h OOh
Bit(s) Type Default Function
7 R/W 0 PCI Bus Master to Host Memory Burst Cycle Enable: 0= Disable 1 = Enable 6 R/W 0 Enable I/O Port 3F7h Write at ISA Bus: 0= Disable I = Enable 5 RJW 0 Enable I/O Port 3F7h Read at ISA Bus: 0= Disable 1 = Enable 4 R/W 0 Enable I/O Port 377h Write at ISA Bus: O=Disable 1 = Enable 3 R/W 0 Enable I/O Port 377h Read at ISA Bus: 0= Disable 1 = Enable 2:0 RO 000 Reserved Bits
Table 5-35 Address Offset 75h OOh
Bit(s) Type Default Function
7 R/W 0 Enable ESOOOh-EFFFFh Memory Block for ROMCS#: o= Disable 1 = Enable 6 R/W 0 Enable EOOOOh-E7FFFh Memory Block for ROMCS#: 0= Disable 1 = Enable 5 R/W 0 Enable DCOOOh-DFFFFh Memory Block for NVMCS#: O=Disable 1 = Enable 4 R/W 0 Enable DSOOOh-DBFFFh Memory Block for NVMCS#: o= Disable 1 = Enable 3 R/W 0 Enable D4000h-D7FFFh Memory Block for NVMCS#: 0= Disable 1 = Enable 2 R/W 0 Enable DOOOOh-D3FFFh Memory Block for NVMCS#. O=Disable 1 = Enable 1 RJW 0 Enable CCOOOh-CFFFFh Memory Block for NVMCS#. 0= Disable 1 = Enable 0 R/W 0 Enable CSOOOh-CBFFFh Memory Block for NVMCS#. 0= Disable 1 = Enable
Page 24 05-01-82C822-09 82C82~ PCIB 82C822 PCIS
Table 5-36 Address Offset 76h OOh
Bit(s) Type Default Function
7 RJW 0 Enable Serial Port 1 at ISA Bus (Address Decoded 3F8h-3FFh): O=Disable I = Enable 6 RJW 0 Enable Serial Port 2 at ISA Bus (Address Decoded 2F8h-2FFh): O=Disable 1 = Enable 5 R/W 0 Enable Parallel Port I at ISAISA Bus (Address Decoded 3BCh-3BFh): O=Disable 1 = Enable 4 R/W 0 Enable Parallel Port 2 at ISA Bus (Address Decoded 378h-37Fh): 0= Disable 1 = Enable 3 R/W 0 Enable Parallel Port 3 at ISA Bus (Address Decoded 278h-27Fh): 0= Disable I = Enable 2 RJW 0 Enable Primary Floppy Disk at ISA Bus (Address Decoded 3FOh-3F5h): 0= Disable I = Enable I R/W 0 Enable Secondary Floppy Disk at ISA Bus (Address Decoded 370h-375h): o = Disable 1 = Enable 0 R/W 0 Enable VGA Palette Snooping at ISA Bus (Address Decoded 3C6h-3C9h Write Cycle): 0= Disable 1 = Enable
Table 5-37 Address Offset 77h OOh
Bit(s) Type Default Function
7 R/W 0 Enable Primary IDE at ISA Bus (Address Decoded IFOh-IF7h, 3F6h): 0= Disable 1 = Enable 6 R/W 0 Enable Secondary IDE at ISA Bus (Address Decoded 170h-177h, 376h): 0= Disable 1 = Enable 5 RJW 0 Enable VGA at ISA Bus (Address Decoded 3COh-3CFh, 3B4h-3B5h, 3BAh, 3D4h-3D5h and 3DAh): 0= Disable 1 = Enable 4:3 R/W 00 Reserved Bits 2 RJW 0 Enable System Board Controllers and liD Address Range for EISA System (Address Decoded 0400h- 04FFh, OSOOh-OSFFh, excluding OCOOh-OCFFh due to the overlap with CFSh and CFCh in PCI configura- tion read/write): O=Disable 1 = Enable 1 RJW 0 Enable System Board liD Address Range for ISAIEISA System (Address Decoded OOOh-OFFh): o= Disable I = Enable 0 RJW 0 Enable FOOOOh to FFFFFh Memory Block at ISA Bus: 0= Disable 1 = Enable
82C822 PCIS 05-01-82C822-09 Page 25 82C822 pelB
Table 5-38 Address Offset 78h OOh
Bit(s) Type Default Function
7 RJW 0 Enable ECOOOh-EFFFFh Memory Block at ISA Bus: 0= Disable 1 = Enable 6 RJW 0 Enable ESOOOh-EBFFFh Memory Block at ISA Bus: o = Disable 1 = Enable 5 RJW 0 Enable E4000h-E7FFFh Memory Block at ISA Bus: 0= Disable I = Enable 4 RJW 00 Enable EOOOOh-E3FFFh Memory Block at ISA Bus: o = Disable I = Enable 3 RJW 00 Enable DCOOOh-DFFFFh Memory Block at ISA Bus: 0= Disable 1 = Enable 2 RJW 0 Enable DSOOOh-DBFFFh Memory Block at ISA Bus: 0= Disable 1 = Enable I RJW 0 Enable D4000h-D7FFFh Memory Block at ISA Bus: o = Disable I = Enable 0 RJW 0 Enable DOOOOh-D3FFFh Memory Block at ISA Bus: O=Disable I = Enable
Table 5-39 Address Offset 79h OOh
Bit(s) Type Default Function
7 RJW 0 Enable CCOOOh-CFFFFh Memory Block at ISA Bus: o = Disable I = Enable 6 RJW 0 Enable CSOOOh-CBFFFh Memory Block at ISA Bus: 0= Disable 1 = Enable 5 RJW 0 Enable C4000h-C7FFFh Memory Block at ISA Bus: 0= Disable 1 = Enable 4 RJW 00 Enable COOOOh-C3FFFh Memory Block at ISA Bus: 0= Disable I = Enable 3 RJW 00 Enable AOOOOh-AFFFFh Memory Block at ISA Bus: 0= Disable I = Enable 2 RJW 0 Enable BOOOOh-BFFFFh Memory Block at ISA Bus: 0= Disable I = Enable 1:0 RO 00 Reserved Bits
Page 26 DS-Ol-82C822-09 82C822 PCIB 82C822 pelB
Note: Offsets 7Ah-87h are for positive decode blocks of ISA bus memory and va.
Table 5-40 Address Offset 7Ah OOh
Bit(s) Type Default Function
7 RIW 0 Enable Memory Space 1 at ISA Bus: o = Disable 1 = Enable 6:4 RlW 00 Block Size for Memory Space I 3 RIW 0 Enable Memory Space 2 at ISA Bus: 0= Disable 1 = Enable 2:0 RIW 0 Block Size for Memory Space 2: Block Size Definition 2 1 0 Size 0 0 0 64KB 0 0 1 128KB 0 1 0 256KB 0 1 1 512KB 1 0 0 1MB 1 0 1 2MB 1 1 0 4MB 1 1 1 8MB
Table 5-41 Address Offset 7Bh-7Ch OOh
Bit(s) Type Default Function
15:0 RlW OOh A[31 :8J for Starting Address of Memory Space 1
Table 5-42 Address Offset 7Dh-7Eh OOh
Bit(s) Type Default Function
15:0 RlW OOh A[31 :8] for Starting Address of Memory Space 2
Table 5-43 Address Offset 7Fh OOh
Bit(s) Type Default Function
7:2 RO 000000 Reserved Bits 1 RlW 0 Enable I/O Space 1 at ISA Bus: O=Disable 1 = Enable 0 RIW 0 Enable I/O Space 2 at ISA Bus: 0= Disable 1 = Enable
82C822 PCIS DS-01-82C822-0.9 Page 27 82C822 pels
Table 5-44 Address Offset 80h-8th OOh
Bit(s) Type Default Function
15:0 RJW OOOOh A[15:0] for Comparison ofI/O Space 1
Table 5-45 Address Offset 82h-83h OOh
Bit(s) Type Default Function
15:8 RO 0000 Reserved Bits 0000 7:0 RlW 0000 A[7:0] for Masking ofIlO Space 1 0000
Table 5-46 Address Offset 84h-85h OOh
Bit(s) Type Default Function
15:0 RJW OOOOh A[15:0] for Comparison ofI/O Space 2
Table 5-47 Address Offset 86h-87h OOh
Bit(s) Type Default Function
15:8 RO 0000 Reserved Bits 0000 7:0 RlW 0000 A[7:0] for Masking of I10 Space 2 0000 Note: Offsets 88h-8Fh are for PCI interrupt to ISA interrupt mapping.
Table 5-48 Address Offset 88h-8Bh OOOOOOOOh
Bit(s) Type Default Function
31:28 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request A2 has been triggered. 27:24 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request B2 has been triggered. 23:20 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request C2 has been triggered. 19:16 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request D2 has been triggered. 15:12 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request Al has been triggered. 11 :8 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request B 1 has been triggered. 7:4 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request Cl has been triggered. 3:0 RlW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request Dl has been triggered.
Page 28 D5-01-82C822-0.9 82C822 PCIB 82C822 PCIB -am
Table 5-49 Address Offset SCh-SFh OOOOOOOOh
Bit(s) Type Default Function
31:28 R/W 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request A4 has been triggered. 27:24 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request B4 has been triggered. 23:20 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request C4 has been triggered. 19:16 R/W 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request D4 has been triggered. 15:12 R/W 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request A3 has been triggered. 11:8 R/W 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request B3 has been triggered. 7:4 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request C3 has been triggered. 3:0 RJW 0000 Selects which IRQ signal is to be generated when PCI Interrupt Request D3 has been triggered. Routing Definition: Routing Definition 0000 Disabled 0001 IRQ5:flow through mode 0010 IRQ9:flow through mode a a 1 I IRQ 1O:flow through mode 0100 IRQ 11 :flow through mode a 1 a 1 IRQ I 2:flow through mode a I I a IRQ14:flow through mode a I I I IRQ15:flow through mode 1000 Disabled 100 1 IRQ5:level 101 0 IRQ9:level I a 1 I IRQIO:level I 100 IRQll:level 1 1 a I IRQ12:level I I 1 a IRQ14:level I 1 1 1 IRQ15:level
Table 5-50 Address Offset 90h-FFh OOh
Bit(s) Type Default Function
7:0 R/W OOh Reserved Bits
5.2 Non-Configuration Register Space
Table 5-51 1/0 Port Address 70h lXXXXXXXb
Bit(s) Type Default Function
7 WO I EnableNMI: I = Disable O=Enable 6:0 RO 0000 000 Reserved Bits mB 82C822 PClS 05-01-82C822-09 Page 29 82C822 PCIB
0'
6.0 AC Timing Waveforms
NOTE A15_0 are the CPU address pins 15-0.
NOTE 031_0 are the CPU data pins 31-0.
Figure 6-1 822 back off ISA Cycle
U : U • . u u
I· u
NOTE LOEV_ 0 is the LOEV# pin of the 822.
Figure 6-2 o ClK Delay of lRDY# after the assertion of BUFF#
~b~~LK 8~O · ~~~=o • n cJ i : I i BRO V LJ • r---lil...------i BOFFRDVI= _ I. ' Ii AHOLO all ! LDEV- 1 ,.,L- ______~.-~r------;, i ~gT~= ' · I FRAME- LJ ; IRDV- , , · , TROV- .· ,I ! , I CB3_0 all , Ii · A15_0 all if , · , , , , III II , 03~~~~L- LO all ~~~~~'"' ~g~~~~~~~3~~5~~';' : i 1111
NOTE ROY_ is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV _1 is the LOEVO# pin of the 822. LOEV_0 is the LOEV# pin of the local bus.
Page 30 DS-01-82C822-09 82C822 PCIB 82C822 PCIS
Figure 6-3 1CLK Delay of LRDY# after the assertion of BUFF#
R :: I : I L-.J I I -w I I I L-JI I I ! I 1 I I I I ,I ! I I [ b..! ~ I I l I I I I I I I I I I I I I I Iii Ii ;;; : i II "11'" II
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_O is the LDEV# pin of the local bus.
Figure 6-4 2 CLK Delay of LRDY# after the assertion of BUFF#
n :. n n I:I 1 I ~ I W I ~ I I IL-J I I I I 1 I I I I I , I I I [
I I W I I I I I I I I I I I I I I I 1 I I 1 III fI ;:01 I i II 1111 II "
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LOEV_O is the LOEV# pin of the local bus.
82C822 PCIS DS-01-82C822-09 Page 31 82C822 PCIB
Figure 6-5 PCI Configuration Write Cycle
CPUCLK. AOS-. B~3_0 011 :! M 0 In:·; O. .. HR I . I ROV- ~ L...... J BROL ~2~~t:------~~~------~------~------fROV-
~~~~2- I A 15_0 011 II 03 LO 011 II CB3_0 011 =====~==i:==c==J~~===:E:=====±======
NOTE ROY_is the ROYRTN# pin of the local bus.
Figure 6-6 PCI Configuration Read Cycle
~ . I
NOTE ROY_is the ROYRTN# pi n of the Icoal bus.
Page 32 DS-01-82C822-09 82C822 PCIB 82C822 pelB
Figure 6-7 DMA Write to PCI Slave
I I U ! I !..! I
I I LJ-- '-----.J W I I I bl I I I I I i
I I I
I I
I I
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LDEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PCIB D5·01·82C822·09 Page 33 82C822 PCIB
Figure 6-8 DMA Read from PCI Slave
~b~~LK c ,,~~§~~~~~~~~~~~~~~~~~~~~~~~u b- ~E~~T_ RDV-r- u L...... ~8[D- HLDA AHOLD STOP_ HITM_ LDEV-LQEV- o=-======~:::::::::::::::::::::£======::1
~RARt:-f~8~: -======W~=-=-=-:-=-=-=-=-=-=-=-=-""l-J--;'-=-=-=I W..------=-=-=-=-=-=-=-=-=-=-=-=-=-= IDSEL- CB3_0 oIl DSEL-A15_0 oIl ~~~g~~~~~I~~~~~ D31_0COE_ 0110 ______" 111111' _ COE_ 1 ______E~~- ~------RAS_TAH~______CAS3 __ 01l ______e~~(L LGNT_ IOR_ A~~iL ======~I------~r-I r_ ~a~~v
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LOEVO# pin of the 822. LOEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 34 DS-Ol-82C822-0.9 82C822 PCIB 82C822 pelB
Figure 6-9 DMA Read from DRAM CPUCLK ~~~- • ! ~5~=O oil ~~~~~~~~~~~::::::::::~~~~~~~~ ~b~~i- HOLD~otr= HLDA AHOLD STOP_ HITM_
hLB~~:S16_ ~------~------FRAME IRDV TRDV- ~5~~L- ~~s:83LO oil;;;;;gil ~~~~~~~~~~3===c=====:i= " ~ 8§:H~_ O----~======~======______-r ______
1 ~~~E-~AS3--D~~3-- °2 ==~~~~~~~~~~~~~~~~~~;;;;~~~~;~~~~~~;E~~~~~~~~~~~~~~~~~~______-..... ______LREQ_ ------~------lB~~- IOH M~MiL ~O~~v
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LDEV_O is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LCNT_ is the LCNT# pin from the VL chip set to the 822.
82C822 PCIB DS-Ol-82C822-09 Page 35 82C822 PCIB • 1 I I
I I
1 1 1 I I I 1
I I I I I I
-----, I
I I
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV _0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 36 05-01-82C822-09 82C822 PCIB 82C822 PCIB
Figure 6-11 DMA Write to Cache with Write-Back
: · I ·. I . I I · I ----, ·, 1 ·, I I I I ·,I I
NOTE ROY_is the ROYRTN# pin of the local bus. ROYL is the LROY# pin of the local bus.
NOTE LOEV_, is the LDEVO# pin of the 822. LDEV_O is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PCIB DS-01-82C822-09 Page 37 82C822 pels
Figure 6-12 DMA Read from Cache with Write-Back
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 38 DS-01-82C822-09 82C822 PCIB 82C822 PCIS
Figure 6-13 ISA Master Write to PCI Slave
1 I I I I 6.! ! I u ~ I I U I I U l-
I I I I I W 1...1 L...-.J L-...J L.J W L.....I L...J I 1 I D I I ~ 1 1 I I
I I I I c:
I I I I r- J I I I I I I I I
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LCNT_ is the LCNT# pin from the VL chip set to the 822.
82C822 PCIB 05-01-82C822-09 Page 39 82C822 PCIB
Figure 6-14 ISA Mastger Read from PCI Slave
, ~~~~LK , ~~~=o alI I ~ BRDY i u ~ U - BLA~T_ RDY~- u---L.-.J U-- ~8[D- HLDA AHOLD STOP_ H~TM_ [~~: 01 I I I r-- F AME IRDY- ~ , ~ , u u I I T~~~~: : I B3j-al1 I 0 15_0 a1 I , I , : 3LO aJ 1 51, III , , II , i, o01_ _ 01 , ~ H _ 0 , , T~HE_ 1 , , 0 , R~~:L8AS3_ 2 , 8 HE_ , LREQ_ LGNT_ , , IOR_ , IOH_ , MEMR_ I ,.--, , ~B~~v I I , I r- M16_ , I I I r-
NOTE ROY_is the ROYRTN# pin of the local bus. ROY'_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LOEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT _ is the LGNT# pin from the VL chip set to the 822.
Page 40 DS-01-82C822-09 82C822 PCIB 82C822 PCIB
Figure 6-15 ISA Master Write to DRAM
• I ~~~~LK 0 I i B 3_0 011 I I R V- .L--J L_ B2 OV ~b~~!- I-I ~8~o- eO STOP_~~ H~TM_ L ~v-v- I F AME- ° fROV- R~V- ~S L- CBO~Eb- _ 011 I ~~T~2 g~ I I 1III II H~_ 0 AHHE~ _ I RAS_ CAS3_0 2 ~ CAr-ODH _ 0 S?'.---, .---, r=or-- ~~N~:DR_ OlL MEMR_ i I ° r--l r--l I ; r- M16_~a~~v
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_, is the LDEVO# pin of the 822. LOEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PCIB DS-01-82CB22-09 Page 41 82C822 PCIS
Figure 6-16 ISA Master Write to Cache with Write-Back Jl.I1
I L.. 1 II I I I I -, I I I i I t: ! u-u-u-ub l.J"'Wl....Jl I ~ I I ! 0 I r- i I C ~ I I: I I : u-u-u-u ~ I I I I I I 1 I 1 tI 11III I 1 II I I II ! I II II III i L LJ ! U U U U 1 I W I -r--l I I I I --J I L--...J L--J I I , ~ I I l.J'"L.rLf'W! I I I I I I --r---l .---, I I I : I I I
NOTE RDY_ is the RDYRTN# pin of the local bus. RDY'_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 42 D5-01-82C822-09 82C822 PCIS 82C822 PCIB
Figure 6-1 7 ISA Master Read from Cache with Write-Back
I I I I IS §OJ I I; d §OJ , ~ [II .....J L-.J I ! LJ ! I !iL.J I I I I: ! I 1 : l.r"'tr"'UIJ I I I
I I II I I 1=4' r---J , 1 "i I I , 1._ U U U U , -, r---J ! ! , I I : L...J""'W""LJ"W I I I I I -, r---J r---J : r---J I I I .I
NOTE ROY_is the RDYRTN# pi n of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LOEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PCIB DS-01-82C822-09 Page 43 82C822 pelB
Figure 6-18 VESA Master Write to PCI Slave
I I I I I 11 I U : LJ U u !J I I n r-, r'1 0 ~ ! Lr I.J Lr !oJ u : u !..! U U I I I I I I I I ~ I I I n n n n w u u I I I~ '~ r29 \ ~I I I I I I ~ 111 I 0 bI IJL.. 11 6l I I ~ I I I i 11 II I ! I I 0 I I 1 I 0 I 1 I I I I 11 I I I I I I I I I I I I I I
NOTE RDY_ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_O is the LDEV# pin ofthe local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 44 05-01-82C822-0.9 82C822 PCIB 82C822 pelB
Figure 6-19 DMA Write to ISA Slave
1 I I I t
I I [
1
1 I 1-0 I 1
I !
I I
I I --, I
NOTE ROY_is the ROYRTN# pin of the local bus. ROYL is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT _ is the LGNT# pin from the VL chip set to the 822.
mmH 82C822 PCIS DS-01-82C822-09 Page 45 82C822 PCIB - Figure 6-20 DMA Read from ISA Slave
~b~~LK ~~:_o on : : ~ ~~2~T _ ! u::lC 68~~= ~eb2 ~~~~~ ~5EO= o------~------ ~DEV-I~~~~- 1 ======~======:J...,=_..... TR~V- ~5 ~L-
01 0 u II! , , ~~~5::_~ ~ol1111_---,______~------i-!------! Hi- o------~------JHI~ 1 ______~------~~ S~ ~:8 ~ BBt t~N~: i OR - M~~iL I .• ~b~~v I I M16_
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_ 0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 46 05-01-82C822-0.9 82C822 PCIS 82C822 pelB
Figure 6-21 ISA Master Read from ISA Slave
·j 1 I I :: §S ·. ~ i5 • I l I I I I I ·. · ·. ·I ·. ·. I 1 I I I I 1 I I ·I i 1 .· · · 1 · ·. · I · r---l r---1 r---l I ·I I I I I I L...... - 1 ·
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_O is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PClB D5-01-82C822-09 Page 47 82C822 pels
Figure 6-22 ISA Master Write to ISA Slave · · Jl I ;r===C:J 0 D , ,'IL.-J L.J L.J , , , , , , , , I · ·I ·, I I Jl ·I I I I I 11 I I I 11 , , 1 , 1 · ·., I 1 I :w--1 rl D . ·I .I L....:.-....rl D I I r1=L:J I I
NOTE ROY_is the ROYRTN# pin of the local bus. ROY'_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 48 DS-01-82C822-0.9 82C822 PCIB 82C822 pelB
Figure 6-23 DMA Write to VESA Slave
1 I : r=::u i ! ! : I r==u · I I .· I ·• I ·I I , I I ! · , ·.I · 1 I 1 ;;oJ II , , i 1 ! ! , ·.I · ·I 1 . I • t I ; I I .• I • I I · L...... J
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the lROY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. lOEV_O is the lOEV# pin of the local bus.
82C822 PCIB DS-01-82C822-09 Page 49 82C822 PCIB
Figure 6-24 DMA Read from VESA Slave I~~~K
~~~=o 011 ~~§§§51~~~::::tui::::~~~~§§2~ ~E~~i_ !.... RDVF'- u ~8[D- HLDA IL AHOLD STOP_ HITM_ ~~~X~- ~ ======3:II:======r-~ IRDV- TRDY- . D5E~- ~~~-b8-gn~~~~~~~:l;~~~~~~~~~~!:~~ ~ 81~ o~:: :I w" 5 A~~_~~- ~:--==--==--==--==--==--==--==--==--==--==~'=--==--=______~------=--==--==--==--==--==--==--==--==--==--==--==--==--==--=::-- c~~~_OOll------~------ ~H~- 18H- MEMiL MEMH_ IORDY M16_ ------7------~~r----
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LDEVO# pin of the 822. LOEV _0 is the LOEV# pin ofthe local bus.
Page 50 DS-01-82C822-09 82C822 PCIS 82C822 pelB
Figure 6-25 ISA Master Read from VESA Slave
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_, is the LOEVO# pin of the 822. LDEV_O is the LOEV# pin of the local bus.
82C822 PCIB DS-Ol-82C822-09 Page 51 82C822 PCIB
Figure 6-26 VESA Master Write to VESA Slave
I I I I I I I I 11 I I bI ~ u U U !.! t:4 ra l Il Il r-, Jl bI !..I \.I 1,,1 bI tf. ! I I I I I I I I I
I I I I I I ~ I!i I : I I I I I I I I I , : I 11 I 11 t I I I I I 11 I I : I! 0 I I I ¢ I 1 I I I L-J I 1 I L-....J I I I I I I I L--J ; ! I I I I i I
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 52 DS-01-82C822-09 82C822 PCIB 82C822 PCIS
Figure 6-27 VESA Master Read from VESA Slave
I I I I 1 I U !..I ~ u iJ iJ iJ r-, r-, r-, IJ u 'i LC 0 ~ ~ 2S I I I I I I I I , I , I 1 rI'I U I L...... I I I ,:I 1 0 , 1 I ! I I I 1 11111. 1'1 I III I 10 I 0' "5 6 ~ b ~ I I I I I 1 I I I I , I I I I. I ! I I I
NOTE RDY _ is the RDYRTN# pin of the local bus, RDY'_ is the LRDY# pin of the local bus,
NOTE LDEV_1 is the LDEVO# pin of the 822, LDEV_O is the LDEV# pin of the local bus,
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set LGNT_ is the LGNT# pin from the VL chip set to the 822,
82C822 PCIS 05-01-82C822-09 Page 53 82C822 pels
Figure 6-28 VESA Master Read from DRAM
1 LJ LJ LJ n n n LJO Wo WCJ W--n....
1 rl n rl rl rl rl rL.
1 1 I I I I I I I 1 II L-J L...J L...J ! r 1 L-J LJ I I LJ LJ LJ 1 L-J ---, w W 2T W & W J L I ~ I I ~ I !:
NOTE ROY_is the ROYRTN# pin of the local bus. ROY 1_ is the LROY# pin of the local bus.
NOTE LDEV _1 is the LDEVO# pin of the 822. LOEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 54 05-01-82C822-0.9 82(822 PCIS 82C822 PCIB
Figure 6-29 VESA Master Write to DRAM
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LOEVO# pin of the 822. LOEV_ 0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PClB DS-01-82C822-0.9 Page 55 82C822 PCIS
;} I I I I I 1 I
r-1 ~ I I I I I I I I I I i,.. In 1 I DCJCJ-n Cl I I I i I 1 I 1 II : I I I I I I 1 II I If I 1 I LJ !....l LJ I 1 LJ:I LJ W I I I I , ! I I ! I I I
NOTE RDY_ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_, is the LDEVO# pin of the 822. LDEV_ 0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 56 DS-01-82C822-0.9 82C822 PCIB 82C822 PCIS
Figure 6-31 VESA Master Write to Cache
CPUCLK ADS- 1~11~ O ---, I BeHR BE3_0 1311 RDV L.J BRDV_ BLAST_ '---, .r-L~ RDVI L.J BOFF_ I I HOLD "L-J HLDA I I AHOLD STOP_ HITM_
LDEV- °.~ LDEV- 1 ----fL.~ .rt_ CSI6_ FRAME W IRDV I I TRDV DSEL IDSEL CB3_0 131 1 CJ A15_0 131 1 I II II I I I I D3LO 131 1 II 11111 I COE_ ~ L-.J L--...J COE_ °1 L-....J L-.J L- CHE_ °1 TAHE_ RAS_ CAS3_0al 1 E~~GL I LGNT_ IOR_ J I IOH_ MEMR_ MEMH_ IORDV M16_
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LOEVO# pin of the 822. LOEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
82C822 PCIB DS-01-82C822-09 Page 57 82C822 PCIB
Figure 6-32 VESA Master Write to ISA Slave
I I 1 I I I 1 I I 1 1 U U : !.I 1 1 I rJ I U hi I ~ ! I U : U 1 : I I I I 1 I I I I 1 I I I 1 I I 1 I 1 U I I I 1 L-J I I I 1 I 1 I I : 1 n 1 1 I I II I ; 1 1 0 1 i I I 1 I 1 1 I I 1 I ,I 1 , 1 1 , 1 , I I I 1 I , 1 1 1_ J I rI I I ! I 1 : I . I
NOTe RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus. NOTe LDEV_1 is the LDEVO# pin of the 822. LDEV_ 0 is the LDEV# pin of the local bus.
NOTe LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
Page 58 DS-01-82C822-09 82C822 PCIB 82C822 PCIS
Figure 6-33 VESA Master Read from ISA Slave
I I I
: I I 1 I !,j ~ u I l I 11 I U I W- I ---, I I : I I I I I I I I I I I I I I I I I 1 I I -U I L.....J : ! I I I I n I 1 I J i I I I tp ! 1 '~ i I I I I I I 1 I I I I I I 1 I I I I I I : ! I I I I 1 11 I :t : I I I I I I I I I I , I
NOTe ROY_is the ROYRTN# pin of the local bus, ROYI_ is the LROY# pin of the local bus,
NOTe LOEV_1 is the LOEVO# pin of the 822, LDEV_0 is the LOEV# pin of the local bus, NOTe LREQ_ is the LREQ# pin from the 822 to the VL chip set LCNT_ is the LCNT# pin from the VL chip set to the 822,
82C822 PCIB D5-01-82C822-09 Page 59 82C822 PCIS • Figure 6-34 VESA Master Read from PCI Slave
CPUCLKI. ADS- U I U W- I I B~O I I WR I BE3_0 I a 11 I RDV U I U U- BRDV_ I BLAST_ r-l I n rL RDVI U I U U- BOFF_ I EADS_ I HOLD HLDA I AHOLD STOP_ HITM_ LOEV- 0 LOEV 1 I n rL FRAME U LJ IROV I I I TRDY DSEL I I IDSEL I I I~ 2il== CB3_0 a1 1 0 I A 15_0 a1 1 I II I I II I I 031-0 a1 1 II I II II I : 1C:J1~1I11 I COE_ I " COE_ °1 LJ I L I CWE_ ° I CWE_ 1 I TAWE_ I RAS_ I I CAS3_0a1 1 I DWE_ I LREQ_ I LGNT_ I I IOR_ I I IOW_ I MEMR_ I I MEMW_ I I IORDY I M16_ I
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set LGNT_ is the LGNT# pin from the VL chip setto the 822.
Page 60 05-01-82C822-0.9 82C822 PCIB 82C822 PCIS
Figure 6-35 PCI Master Write to ISA Slave
I u== I I I I I I I I I I :I I I
1 I I I I I I I I I I I I I r I i I i I I r---, l ------IL______i- __ L-I, ______~r
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_0 is the LOEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
NOTE PLREQ_ is the PC! REQ# from the PCI bus master. PLGNT is the PC! GNT# from the 822.
82C822 PCIS 05-01-82C822-09 Page 61 82C822 PCIS ------_\~-.------Figure 6-36 PCI Master Read from ISA Slave
CPUCLKI. ADS W W MIO I U-- DC LJ U-- WR I I BE3_0 81 1 0 I RDV --U U BRDV_ BLAST_ RDVI --U U BOFF_ EADS_ HOLD I L HLDA I AHOLD STOP_ W-- HITM_ LDEV- 0 LDEV- 1 --1 FRAME I r-- IRDV I TRDV .-- DSEL I WI I IDSEL !l.-.-J - . ,-_ .. rL CB3_0 81 1 CJ CJu A 15_0 81 1 I I I I I I I I I I I c:: D31-0 81 1 I WI II I I rcnr:: COE_ 0 • UL..J COE_ 1 UL..J CHE_ 0 CHE_ 1 TAHE_ RAS_ CAS3 __ 81 1 DHE_ LREQ_ -----, r LGNT_ I r PLREQ_ ~ rL- PLGNT_ I r- IOR_ IOH_ MEMR_ I r-l I L MEm-L IORDV I I I I M16_ I f1-.
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV _1 is the LDEVO# pin of the 822. LDEV _0 is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT _ is the LGNT# pin from the VL chip set to the 822.
NOTE PLREQ_ is the PCI REQ# from the PCI bus master. PLGNT is the PCI GNT# from the 822.
Page 62 05-01-82C822-0.9 82C822 PClB 82C822 pelB
Figure 6-37 PCI Master Read from Cache
~b~£LK MDCIO I : U ,LJ J HR ~: III: I, J BE3_0 a 11 q c==J' CJ RDV- ..=u::.. ____--I --_--. 'u BRDV_ I U ' BLAST_ ' I: I RDVI- .!:O"U:!.. ____--t l______'-, --. U ,..--______BOFF _ I , L-...J EADS_ ------~I---.wr------~,-~~~--~ur----- HOLD -.-J: L.J I HLDA I I I I I
PLGNTPLREQ_ _ ~~~~~~:jI:::::::::::ro~~~~~1I : I ' ~~~r::::::::::::::1 I AHOLD I I STOP_ : U I LI HITM_ ' LDEV- O------~I------r,------
LDEV-FRAME - 1 I I I U I I r IRD V- ~~~~;!I~~~~~~II I ~j'~~1 L.W ~~~~~I 0 TRDV- ,U I U- DSEL- Ii I IDSEL - I I I; I
COE_@~~:8 gll=:::~,~,.~,~,~1?~i'~,o_= ______~~ ~~~~~~I! __ ~t:J~ _____~I ~~~~,~IL~o~I~,~: u~ __;- ~~~~li?~.ill~,~,~~,I~,~,~1______~ CHE_COE_ O1 ______;:~I------'~------~~~--- ______'~ ______CHE_TAHE_ 1 ------tl~------~'------: :
CAS3_0aJJRAS______~I------~'------+i ______~:~ ______DHE_ I IOR_ : IOH_ , MEMR_ i MEMH_ I IORDV : M16_ ,
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LDEVO# pin of the 822. LOEV_O is the LOEV# pin of the local bus.
NOTE PLREQ_ is the PCI REQ# from the PCI bus master. PLGNT is the PCI GNT# from the 822.
[milD 82C822 PCIS DS-01-82C822-09 Page 63 82C822 PCIS
Figure 6-38 PCI Master Write to Cache with CPU Write-Back Cycle
CPUCLK ADS , MID L.J , U DC I I trI HR I , BE3_0 al1 Cl I ~ I RDY U ,IU I IJ" BRDY_ , ~ I BLAST_ I :...rL..rL...fL. I I RDYI U ,l..J I L[ BOFF_ L--...J , I l- EADS_ U U I I I HOLD I W HLDA I 'wI I I I r- PLREQ_ , h I PLGNT_ I I I I AHOLD I I I STOP_ LJ HITM_ I I I I LDEV- I LDEV- °1 I I r FRAME U I I ; U IRDY ~ I I ~ TRDV U I DSEL I , IDSEL I I I CB3_0 al1 0 0 A15_0 el 1 I I I I I i5 I , I 031-0 al1 I II lIT i I ~I COE_ I COE_ °1 . I I , ~ U CHE_ ° I I CHE_ 1 , U U I TAHE_ , I I RAS_ I CAS3_0al1 , I I I DHE_ ~ I LREQ_ ,I , n I LGNT_ I I I L PLREQ_ ,I PLGNT_ I I f? IDR_ , I rOIL I . MEMR_ , I I I MEMH_ I I IORDV I I I M16_ I
NOTE RDY _ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV _1 is the LDEVO# pin of the 822. LDEV_O is the LDEV# pin of the local bus.
NOTE LREQ_ is the LREQ# pin from the 822 to the VL chip set. LGNT_ is the LGNT# pin from the VL chip set to the 822.
NOTE PLREQ_ is the PCI REQ# from the PCI bus master. PLGNT is the PCI GNT# from the 822.
Page 64 DS-01-82C822-09 82C822 PCIS 82C822 PCIS
Figure 6-39 PCI Master Write to DRAM
CPUCLK. ADS- ___---, I U U I .--_=U___ _ MID W I U I W DC I : III I II HR H U.=J: ;.-., BE3_0 all==~r===~=;~======~~======~====~~~~======~ RDY---U__-= ___ -'1 ___ -, I U BRDY_ I ur-----~,--~------BLAST_ I! I RDYI- --U I I U BOFF _ I I L--..J EADS_ ------~I--,ur------~,--====~----~ur--- HOLD : L.J HLDA I I I PLREQ_ I n PLGNT_ I: AHOLD ! STOP_ I LJ I ~B~O= O------':------~:------
~S~XE-IRD Y-:1~~~~~,;f!~~~~~,~~~,~Wcj:~~~'~~,~~~~~~ II I I.....I....J I TRDV- ! L.! I DSEL- II I I I IDSEL- II I, I ~~~-8 gll~~~~~Cl~il~~~~,~,:6(~:,~~D~;I~~~~j]~~~~~~ E5J:O a~;______!i~,, ______lb I ! : II COE_ 1 : W I CHE_ O ______~i------~:------CHE_ 1 ______~I------~I------TAHE_ : I RAS_ ::::::::::~I==:JI==rr======~I======d~:: CAS3_0all I L.J : ~ DHE_ I I I I L- IDR_ : I
MEMR_IOW_ ---lr-----~!------~'------i : ~ ~8~~v : M16_ :
NOTE ROY_is the ROYRTN# pi n of the local bus. ROYL is the LROY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LOEV_O is the LOEV# pin ofthe local bus.
NOTE PLREQ_ is the PCI REQ# from the PCI bus master. PLGNT is the PCI GNT# from the 822.
82C822 PCIB DS-01-82C822-0.9 Page 65 82C822 pelB
Figure 6-40 PCI Master Read from DRAM
______~====~======~LJr-~'------I • I n
LJ L
, ,I 0 , I , , , , , , , , , , , , , , ,
NOTE RDY_ is the RDYRTN# pin of the local bus. RDYI_ is the LRDY# pin of the local bus.
NOTE LDEV_, is the LDEVO# pin of the 822. LDEV_0 is the LDEV# pin of the local bus.
NOTE PLREQ_ is the PC! REQ# from the PCI bus master. PLGNT is the PC! GNT# from the 822.
Page 66 DS-01-82C822-09 82C822 PCIB 82C822 pelB
Figure 6-41 PCI Master Read from VESA Slave
LJ
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LRDY# pin of the local bus.
NOTE LDEV_1 is the LDEVO# pin of the 822. LDEV_O is the LDEV# pin of the local bus.
NOTE PLREQ_ is the PCI REQ# from the PCI bus master. PLGNT is the PC! GNT# from the 822.
82C822 PCIB DS-01-82C822-09 Page 67 82C822 pelB
dQSWI
Figure 6-42 PCI Master Write to VESA Slave
u u, ------~~--~~,------.~,------~,------~~----==~------~~------,~,--~,------
~ ____~~ ______~r--, I ': I
, ,
III IlEI . I ., , , , , , , , , , , ,
NOTE ROY_is the ROYRTN# pin of the local bus. ROYI_ is the LROY# pin of the local bus.
NOTE LOEV_1 is the LOEVO# pin of the 822. LOEV_ 0 is the lDEV# pin of the local bus.
NOTE PLREQ_ is the PC! REQ# from the PCI bus master. PlGNT is the PCI GNT# from the 822.
Page 68 DS-01-82C822-09 82C822 PCIS 82C822 PCID
Figure 6-43 ISA Master Write to VESA Slave
MCP~~LK.
i:~~~~1 bJ t:I L U 28~~!- U _I U I~ U L ~O[D- HLDA AHOLD STOP_
FRAME-~gl~: 0 ===311~======f~8~:
~~~:o gn ~~§~L-31'j 011 ~~g~~~~~~~~~~~~~~~~~~ O~_ 0 _---;:----______~o _ 1 ______~------~ - ~------~------
CAR~HIE- 3'_00 11 ------~------:======~======::: DH!8H: r----l r==J r M~MiL [ ~os~v M16_
NOTe ROY_is the ROYRTN# pin of the local bus. ROY'_ is the LROY# pin of the local bus.
NOTe LOEV_1 is the LDEVO# pin of the 822. LDEV_O is the LOEV# pin of the local bus.
82C822 PCIB D5-01-82C822-09 Page 69 82C822 PCIB th
7.0 Mechanical Package Outline
Figure 7-1 208-Pin Plastic Quad Flat Package (PQFP)
He
E A2 A1
Millimeter Inch
Symbol Min Nom Max Min Nom Max A1 0.05 0.25 0.50 0.002 0.010 0.020 A2 3.17 3.32 3.47 0.125 0.131 0.137 b 0.10 0.20 0.30 0.004 0.008 0.012 c 0.10 0.15 0.20 0.004 0.006 0.008 0 27.90 28.00 28.10 1.098 1.102 1.106 E 27.90 28.00 28.10 1.098 1.102 1.106 e 0.50 0.020 Hd 30.35 30.60 30.85 1.195 1.205 1.215 He 30.35 30.60 30.85 1.195 1.205 1.215 L 0.35 0.50 0.65 0.014 0.020 0.026 L1 1.30 0.051 y 0.08 0.003 9 0 10 0 10
82C822 PCIB ASE-64-06-AOOO-343ffi Page 70 Headquarters: Sales Offices: OPTi Inc. OPTi Inc. 2525 Walsh Avenue 9F, No 303, Sec 4, Hsin Yih Road Santa Clara, CA 95051 Taipei, Taiwan, ROC tel: 408-980-8178 x216 tel: + 886-2-325-8520 fax: 408-980-8860 fax: + 886-2-325-6520 Sales Representatives: United States Michigan Texas Hong Kong ArizonaINew Mexico Jay Marketing CJ Sales, Inc. Dynax Electronics, Ltd. 763 WingSt. 3737 Executive Center Dr., Ste. #255 Unit I, 211F Star Centre Excel USA Plymouth, MI 48170 Austin, TX 78731 443-451 Castle Peak Road ISIS W. University Dr., Ste. #103 tel: 313-459-1200 tel: 512-338-1333 Kwai Chung, N.T. Hong Kong Tempe, AZ 8S281 fax: 313-459-1697 fax: 512-338-9185 tel: + 85 (2) 481-0223 tel: 602-829-8820 tel: + 85 (2) 796-5913 fax: 602-967-2658 Minnesota C3 Sales, Inc. fax: + 85 (2) 481-0826 AlabamalMississippi Stan Clothier Company 20333 S.H. 249, Ste. #480 9600 W. 76th St., Ste. A Houston, TX 77070 Italy Concord Component Reps Eden Prairie, MN 55344 tel: 713-379-5411 Consystem Sri 190 Line Quarry Rd., Ste. # I 02 tel: 612-944-3456 fax: 713-379-5727 Viale Lorn bardia 20 Madison, AL 35758 fax: 612-944-6904 Cusano Milanino, (MI) tel: 205-772-8883 C3 Sales, Inc. Italy, 20095 fax: 205-772-8262 Missouri 16990 Dallas Pkwy, Ste. #224 Dallas, TX 75248 tel: + 39-2-66-400153 Stan Clothier Company California tel: 214-733-0306 fax: + 39-2-66-400339 3910 Old Highway 94 South, Ste. #1\6 Brooks Technical Group fax: 214-733-0307 St. Charles, MO 63304 Japan 883 N. Shoreline Blvd. tel: 314-928-8078 Dia Semicon Systems, Inc. Mountain View, CA 94043 Virginia fax: 314-447-5214 Flowerhill-Shinmachi, tel: 415-960-3880 S-J Associates, Inc. 1-23-9 Hsinmachi Setagaya-Ku fax: 415-960-3615 New Jersey 900 S. Washington St., Ste. #307 Falls Church, VA 22046 Tokyo 154, Japan S-J Associates, Inc. Excel USA tel: 703-533-2233 tel: + 81-3-3439-2700 131-0 Gaither Dr. 9980 Huennekens St. fax: 703-533-2236 fax: + 81-3-3439-2701 San Diego, CA 92121 Mt. Laurel, NJ 08054 Micro Summit tel: 619-587-0545 tel: 609-866-1234 Washington/Canada (B.C.) Premier Kl, Bldg 4F, fax: 619-587-1380 fax: 609-866-8627 Electronic Component Sales I Kanda, Mikura-Cho, Chiyoda-Ku 931\ S.E. 36th St. Jones & McGeoy Sales New York Tokyo 101, Japan Mercer Island, W A 98040-3795 SIOO Campus Dr., Ste. #300 S-J Associates, Inc. tel: + 81-3-3258-5531 tel: 206-232-930 I Newport Beach, CA 92660 265 Sunrise Highway fax: + 81-3-3258-0433 fax: 206-232-1095 tel: 714-724-8080 Rockville Centre, NY 11570 fax: 714-724-8090 tel: 516-536-4242 Wisconsin Korea FMKorea fax: 516-536-9638 Micro-Tex, Inc. Colorado/Utah 3rd Fl, Elim Bldg, 203-13 22660 Broadway, Ste. #4A Excel USA North & South Carolina Yangjae-dong, Seocho-ku, Waukesha, WI 53186 384 Inverness Dr. South, Ste. #105 Concord Component Reps Seoul, Korea. Post # 137-130 tel: 414-542-5352 Englewood, CO 80112 10608 Dunhill Terrace tel: 822-575-9720 fax: 414-542-7934 + tel: 303-649-1800 Raleigh, NC 27615 fax: + 822-575-9732 fax: 303-649-1818 tel: 919-846-3441 International Singapore Florida fax: 919-846-3401 Australia Westech Electronics Pte. Ltd. EIR, Inc. OhiolW, Pennsylvania 12 Lorong Bakar Batu, #05-07, Braemac Ply. Ltd. 1057 Mainland Center Commons Lyons Corp. Kolam Ayer Industrial Park Unit 6, III Moore St., Leichhardt Maitland, FL 32794-5057 4812 Fredrick Rd., Ste. #101 Singapore, 1334 Sydney, 2040 Australia tel: 407-660-9600 Dayton,OH 45414 tel: + 65-743-6355 tel: + 61-2-564-121\ fax: 407-660-9091 tel: 513-278-0714 fax: + 65-746-1396 fax: + 61-2-564-2789 Georgia fax: 513-278-3609 Canada (Eastern) & Europe South America Concord Component Reps Lyons Corp. Uniao Digital OPTilnc. 6048 Tracy Valley Drive 4615 W. Streetsboro Rua Georgia, 69-Brooldin Novo 2525 Walsh Avenue Norcross, GA 30093 Richfield, OH 44286 04559-010-Sao Paulo-Brazil Santa Clara, CA 95051 tel: 404-416-9597 tel: 216-659-9224 tel: + 55-11-533-4121 tel: 408-980-8178 fax: 404-441-0790 fax: 216-659-9227 fax: + 55-11-533-6780 fax: 408-980-8860 Illinois Lyons Corp. Taiwan 248 N. State St. France Micro-Tex, Inc. ASEC International Corp. Westerville,OH 43081 Tekelec Airtronic, France 2400 W. Central Rd. 7F No. 344-1, Min-Sheng E. Road . tel: 614-895-1447 5 Rue Carle Vernet, BP.2 Hoffinan Estates, IL 60196 Taipei, Taiwan ROC fax: Same 9213 5 Sevres, Cedex, France tel: 708-765-3000 tel: + 886-2-505-7025 tel: + 33 (I) 4-623-2407 fax: 708-765-3010 Oregon fax: + 33 (I) 4-507-2191 4/94 Kansas Electronic Component Sales 3879 South West Hall Blvd. Stan Clothier Company Beaverton, OR 97075 13000 W. 87th St. Pkwy., Ste. #105 tel: 503-245-2342 Lenexa, KS 66215 fax: 503-520-0767 tel: 913-492-2124 fax: 913-492-1855
The infonnation contained within this document is subject to change without notice. In no event will OPTi Inc. be liable for any damages, direct, indirect, incidental or conse quential resulting from any error, defect, or omission in this specification. OPTi Inc. reserves the right to make changes in this manual at any time as well as in the products it describes, at any time without notice or obligation. Copyright C 1994 by OPTi Inc. All rights reserved. OPTi Inc. assumes no responsibility for any errors contained within. OPTi is a trademark of OPTi Incorporated. All other brand and product names are trade marks or copyrights of their respective owners.
OPTi Inc•. 2525 Walsh Avenue' Santa Clara, CA 95051 . (408) 980-8178