DOCSLIB.ORG

SYCL for Hihat

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
SYCL for Hihat SYCL for HiHat Gordon Brown – Staff Software Engineer, SYCL Ruyman Reyes - Principal Software Eng., Programming Models Michael Wong – VP of R&D, SYCL Chair, Chair of ISO C++ TM/Low Latency Andrew Richards – CEO Codeplay HiHat 2017 Acknowledgement Disclaimer Numerous people internal and external to the original C++/Khronos group, in industry and academia, have made contributions, influenced ideas, written part of this presentations, and offered feedbacks to form part of this talk. I even lifted this acknowledgement and disclaimer from some of them. But I claim all credit for errors, and stupid mistakes. These are mine, all mine! 2 © 2016 Codeplay Software Ltd. Legal Disclaimer This work represents the view of the author and does not necessarily represent the view of Codeplay. Other company, product, and service names may be trademarks or service marks of others. 3 © 2016 Codeplay Software Ltd. Codeplay - Connecting AI to Silicon Products Addressable Markets Automotive (ISO 26262) C++ platform via the SYCL™ open standard, IoT, Smartphones & Tablets enabling vision & machine learning e.g. High Performance Compute (HPC) TensorFlow™ Medical & Industrial Technologies: Vision Processing Machine Learning The heart of Codeplay's compute technology Artificial Intelligence enabling OpenCL™, SPIR™, HSA™ and Vulkan™ Big Data Compute Company Customers High-performance software solutions for custom heterogeneous systems Enabling the toughest processor systems with tools and middleware based on open standards Established 2002 in Scotland Partners ~70 employees © 2017 Codeplay Software Ltd. Agenda • SYCL • SYCL Example • SYCL for HiHat • Distributed & Heterogeneous Programming in C/C++ (DHPCC++) • BoF at SC17 5 © 2016 Codeplay Software Ltd. Codeplay Goals ● To gauge whether it is worth doing ComputeSuite/SYCL stack HiHat-compatible ● To collaborate with the HiHat community in the overall research direction ● To evaluate if possible to be a “provider” for HiHat community (e.g, custom work on request or deployment of stack for HiHat community) ● To consolidate efforts of HiHat with C++ standardization ● To evaluate HiHat as a suitable safety-critical layer ● To integrate SYCL into ISO C++ along with other Modern C++ Heterogeneous/distributed frameworks 6 © 2016 Codeplay Software Ltd. SYCL: A New Approach to Heterogeneous Programming in C++ 7 © 2016 Codeplay Software Ltd. SYCL for OpenCL ➢ Cross-platform, single-source, high-level, C++ programming layer ➢ Built on top of OpenCL and based on standard C++14 8 © 2016 Codeplay Software Ltd. The SYCL Ecosystem C++ Application C++ Template Library C++ Template Library C++ Template Library SYCL for OpenCL OpenCL CPU GPU APU Accelerator FPGA DSP 9 © 2016 Codeplay Software Ltd. How does SYCL improve heterogeneous offload and performance portability? ➢ SYCL is entirely standard C++ ➢ SYCL compiles to SPIR ➢ SYCL supports a multi compilation single source model 10 © 2016 Codeplay Software Ltd. Single Compilation Model CPU CPU x86 C++ Compile Object CPU Source r x86 ISA File (Embedded Devic Linker Device e Device Object) Sourc Device Compile GPU e Object r 11 © 2016 Codeplay Software Ltd. Single Compilation Model x86 C++ CPU Source x86 ISA File (Embedded Devic Single Source Host & Device Compiler Device e Object) Sourc GPU e Tied to a single compiler chain 12 © 2016 Codeplay Software Ltd. Single Compilation Model C++ 3 different language 3 different compilers 3 different executables Source extensions File C++ x86 ISA x86 AMP AMD C++ AMP Compiler (Embedded Sourc CPU AMD ISA) GPU e CUDA x86 ISA X86 Sourc CUDA Compiler (Embedded NVidia CPU e NVidia ISA) GPU Open MP x86 ISA X86 Sourc OpenMP Compiler (Embedded SIMD CPU e x86) CPU 13 © 2016 Codeplay Software Ltd. SYCL is Entirely Standard C++ __global__ vec_add(float *a, float *b, float *c) { return c[i] = a[i] + b[i]; vector<float> a, b, c; } #pragma parallel_for float *a, *b, *c; for(int i = 0; i < a.size(); i++) { vec_add<<<range>>>(a,array_view<float> b, c); a, b, c; c[i] = a[i] + b[i]; extent<2> e(64, 64); } parallel_for_each(e, [=](index<2> idx) restrict(amp) { c[idx] = a[idx] + b[idx]; }); cgh.parallel_for<class vec_add>(range, [=](cl::sycl::id<2> idx) { c[idx] = a[idx] + c[idx]; })); 14 © 2016 Codeplay Software Ltd. SYCL Targets a Wide Range of Devices when using SPIR or SPIRV CPU GPU APU Accelerator FPGA DSP 15 © 2016 Codeplay Software Ltd. Multi Compilation Model CPU CPU x86 ISA x86 C++ Compile (Embedded Object CPU Source r SPIR) File Linker Devic e SYCL Online Code Compile SPIR Finalize GPU r r SYCL device compiler Generating SPIR 16 © 2016 Codeplay Software Ltd. Multi Compilation Model GCC, Clang, VisualC++, Intel C++ CPU CPU x86 ISA x86 C++ Compile (Embedded Object CPU Source r SPIR) File Linker Devic e SYCL Online Code Compile SPIR Finalize GPU r r 17 © 2016 Codeplay Software Ltd. Multi Compilation Model CPU CPU x86 ISA x86 C++ Compile (Embedded Object CPU Source r SPIR) File Linker Devic e SYCL Online Code Compile SPIR Finalize GPU r r 18 © 2016 Codeplay Software Ltd. Multi Compilation Model CPU CPU x86 ISA x86 C++ Compile (Embedded Object CPU Source r SPIR) File Linker SIMD Devic CPU e SYCL Code Compile SPIR GPU r OpenC L Standard IR allows Online APU for better Finalize performance r FPGA SYCL does not mandate portability SPIR Device can be DSP selected at runtime 19 © 2016 Codeplay Software Ltd. Multi Compilation Model CPU CPU x86 ISA x86 Compile (Embedded Object CPU r SPIR) C++ Linker SIMD Source CPU File SYCL Compile SPIR GPU r OpenC Devic L e Online APU Code SYCL Finalize Compile PTX r FPGA r DSP 20 © 2016 Codeplay Software Ltd. Multi Compilation Model CPU CPU x86 ISA x86 Compile (Embedded Object CPU r SPIR) C++ SIMD Source CPU File SYCL Compile SPIR Linker GPU r OpenC Devic L e Online APU Code SYCL Finalize Compile PTX r FPGA r PTX binary can be selected for NVidia DSP GPUs at runtime 21 © 2016 Codeplay Software Ltd. How does SYCL support different ways of representing parallelism? ➢ SYCL is an explicit parallelism model ➢ SYCL is a queue execution model ➢ SYCL supports both task and data parallelism 22 © 2016 Codeplay Software Ltd. Representing Parallelism cgh.single_task([=](){ /* task parallel task executed once*/ }); cgh.parallel_for(range<2>(64, 64), [=](id<2> idx){ /* data parallel task executed across a range */ }); 23 © 2016 Codeplay Software Ltd. How does SYCL make data movement more efficient? ➢ SYCL separates the storage and access of data ➢ SYCL can specify where data should be stored/allocated ➢ SYCL creates automatic data dependency graphs 24 © 2016 Codeplay Software Ltd. Separating Storage & Access Buffers managed Accessors are used data across host to describe access CPU and one or more devices Accessor CPU Buffer Accessor GPU Buffers and accessors type safe access across host and device 25 © 2016 Codeplay Software Ltd. Storing/Allocating Memory in Different Regions Memory stored in Global global memory region Accessor Buffer Memory stored in Constant read-only memory Kernel Accessor region Local Memory allocated in group memory region Accessor 26 © 2016 Codeplay Software Ltd. Data Dependency Task Graphs Buffer A Read Accessor Kernel A Write Accessor Kernel Kernel A B Buffer B Read Accessor Kernel B Write Accessor Buffer C Read Accessor Kernel C Read Accessor Kernel C Buffer D Write Accessor 27 © 2016 Codeplay Software Ltd. Benefits of Data Dependency Graphs •Allows you to describe your problems in terms of relationships • Don’t need to en-queue explicit copies •Removes the need for complex event handling • Dependencies between kernels are automatically constructed •Allows the runtime to make data movement optimizations • Pre-emptively copy data to a device before kernels • Avoid unnecessarily copying data back to the host after execution on a device • Avoid copies of data that you don’t need 28 © 2016 Codeplay Software Ltd. Agenda • SYCL • SYCL Example • SYCL for HiHat • Distributed & Heterogeneous Programming in C/C++ (DHPCC++) • BoF at SC17 29 © 2016 Codeplay Software Ltd. So what does SYCL look like? ➢ Here is a simple example SYCL application; a vector add 30 © 2016 Codeplay Software Ltd. Example: Vector Add 31 © 2016 Codeplay Software Ltd. Example: Vector Add #include <CL/sycl.hpp> template <typename T> void parallel_add(std::vector<T> inA, std::vector<T> inB, std::vector<T> out) { } 32 © 2016 Codeplay Software Ltd. Example: Vector Add #include <CL/sycl.hpp> template <typename T> void parallel_add(std::vector<T> inA, std::vector<T> inB, std::vector<T> out) { cl::sycl::buffer<T, 1> inputABuf(inA.data(), out.size()); cl::sycl::buffer<T, 1> inputBBuf(inB.data(), out.size()); cl::sycl::buffer<T, 1> outputBuf(out.data(), out.size()); The buffers synchronise upon destruction } 33 © 2016 Codeplay Software Ltd. Example: Vector Add #include <CL/sycl.hpp> template <typename T> void parallel_add(std::vector<T> inA, std::vector<T> inB, std::vector<T> out) { cl::sycl::buffer<T, 1> inputABuf(inA.data(), out.size()); cl::sycl::buffer<T, 1> inputBBuf(inB.data(), out.size()); cl::sycl::buffer<T, 1> outputBuf(out.data(), out.size()); cl::sycl::queue defaultQueue; } 34 © 2016 Codeplay Software Ltd. Example: Vector Add #include <CL/sycl.hpp> template <typename T> void parallel_add(std::vector<T> inA, std::vector<T> inB, std::vector<T> out) { cl::sycl::buffer<T, 1> inputABuf(inA.data(), out.size()); cl::sycl::buffer<T, 1> inputBBuf(inB.data(), out.size()); cl::sycl::buffer<T, 1> outputBuf(out.data(), out.size()); cl::sycl::queue defaultQueue; Create a command group to defaultQueue.submit([&] (cl::sycl::handler &cgh) { define an asynchronous task }); } 35 © 2016 Codeplay Software Ltd. Example: Vector Add #include <CL/sycl.hpp> template <typename T> void parallel_add(std::vector<T> inA, std::vector<T> inB, std::vector<T> out) { cl::sycl::buffer<T, 1> inputABuf(inA.data(), out.size()); cl::sycl::buffer<T, 1> inputBBuf(inB.data(), out.size()); cl::sycl::buffer<T, 1> outputBuf(out.data(), out.size()); cl::sycl::queue defaultQueue; defaultQueue.submit([&] (cl::sycl::handler &cgh) { auto inputAPtr = inputABuf.get_access<cl::sycl::access::read>(cgh); auto inputBPtr = inputBBuf.get_access<cl::sycl::access::read>(cgh); auto outputPtr = outputBuf.get_access<cl::sycl::access::write>(cgh); }); } 36 © 2016 Codeplay Software Ltd.
Load more

Recommended publications
  • The Importance of Data
    The landscape of Parallel Programing Models Part 2: The importance of Data Michael Wong and Rod Burns Codeplay Software Ltd. Distiguished Engineer, Vice President of Ecosystem IXPUG 2020 2 © 2020 Codeplay Software Ltd. Distinguished Engineer Michael Wong ● Chair of SYCL Heterogeneous Programming Language ● C++ Directions Group ● ISOCPP.org Director, VP http://isocpp.org/wiki/faq/wg21#michael-wong ● [email protected] ● [email protected] Ported ● Head of Delegation for C++ Standard for Canada Build LLVM- TensorFlow to based ● Chair of Programming Languages for Standards open compilers for Council of Canada standards accelerators Chair of WG21 SG19 Machine Learning using SYCL Chair of WG21 SG14 Games Dev/Low Latency/Financial Trading/Embedded Implement Releasing open- ● Editor: C++ SG5 Transactional Memory Technical source, open- OpenCL and Specification standards based AI SYCL for acceleration tools: ● Editor: C++ SG1 Concurrency Technical Specification SYCL-BLAS, SYCL-ML, accelerator ● MISRA C++ and AUTOSAR VisionCpp processors ● Chair of Standards Council Canada TC22/SC32 Electrical and electronic components (SOTIF) ● Chair of UL4600 Object Tracking ● http://wongmichael.com/about We build GPU compilers for semiconductor companies ● C++11 book in Chinese: Now working to make AI/ML heterogeneous acceleration safe for https://www.amazon.cn/dp/B00ETOV2OQ autonomous vehicle 3 © 2020 Codeplay Software Ltd. Acknowledgement and Disclaimer Numerous people internal and external to the original C++/Khronos group, in industry and academia, have made contributions, influenced ideas, written part of this presentations, and offered feedbacks to form part of this talk. But I claim all credit for errors, and stupid mistakes. These are mine, all mine! You can’t have them.
    [Show full text]
  • (CITIUS) Phd DISSERTATION
    UNIVERSITY OF SANTIAGO DE COMPOSTELA DEPARTMENT OF ELECTRONICS AND COMPUTER SCIENCE CENTRO DE INVESTIGACION´ EN TECNOLOX´IAS DA INFORMACION´ (CITIUS) PhD DISSERTATION PERFORMANCE COUNTER-BASED STRATEGIES TO IMPROVE DATA LOCALITY ON MULTIPROCESSOR SYSTEMS: REORDERING AND PAGE MIGRATION TECHNIQUES Author: Juan Angel´ Lorenzo del Castillo PhD supervisors: Prof. Francisco Fernandez´ Rivera Dr. Juan Carlos Pichel Campos Santiago de Compostela, October 2011 Prof. Francisco Fernandez´ Rivera, professor at the Computer Architecture Group of the University of Santiago de Compostela Dr. Juan Carlos Pichel Campos, researcher at the Computer Architecture Group of the University of Santiago de Compostela HEREBY CERTIFY: That the dissertation entitled Performance Counter-based Strategies to Improve Data Locality on Multiprocessor Systems: Reordering and Page Migration Techniques has been developed by Juan Angel´ Lorenzo del Castillo under our direction at the Department of Electronics and Computer Science of the University of Santiago de Compostela in fulfillment of the requirements for the Degree of Doctor of Philosophy. Santiago de Compostela, October 2011 Francisco Fernandez´ Rivera, Profesor Catedratico´ de Universidad del Area´ de Arquitectura de Computadores de la Universidad de Santiago de Compostela Juan Carlos Pichel Campos, Profesor Doctor del Area´ de Arquitectura de Computadores de la Universidad de Santiago de Compostela HACEN CONSTAR: Que la memoria titulada Performance Counter-based Strategies to Improve Data Locality on Mul- tiprocessor Systems: Reordering and Page Migration Techniques ha sido realizada por D. Juan Angel´ Lorenzo del Castillo bajo nuestra direccion´ en el Departamento de Electronica´ y Computacion´ de la Universidad de Santiago de Compostela, y constituye la Tesis que presenta para optar al t´ıtulo de Doctor por la Universidad de Santiago de Compostela.
    [Show full text]
  • Intel® Oneapi Programming Guide
    Intel® oneAPI Programming Guide Intel Corporation www.intel.com Notices and Disclaimers Contents Notices and Disclaimers....................................................................... 5 Chapter 1: Introduction oneAPI Programming Model Overview ..........................................................7 Data Parallel C++ (DPC++)................................................................8 oneAPI Toolkit Distribution..................................................................9 About This Guide.......................................................................................9 Related Documentation ..............................................................................9 Chapter 2: oneAPI Programming Model Sample Program ..................................................................................... 10 Platform Model........................................................................................ 14 Execution Model ...................................................................................... 15 Memory Model ........................................................................................ 17 Memory Objects.............................................................................. 19 Accessors....................................................................................... 19 Synchronization .............................................................................. 20 Unified Shared Memory.................................................................... 20 Kernel Programming
    [Show full text]
  • Executable Modelling for Highly Parallel Accelerators
    Executable Modelling for Highly Parallel Accelerators Lorenzo Addazi, Federico Ciccozzi, Bjorn¨ Lisper School of Innovation, Design, and Engineering Malardalen¨ University -Vaster¨ as,˚ Sweden florenzo.addazi, federico.ciccozzi, [email protected] Abstract—High-performance embedded computing is develop- development are lagging behind. Programming accelerators ing rapidly since applications in most domains require a large and needs device-specific expertise in computer architecture and increasing amount of computing power. On the hardware side, low-level parallel programming for the accelerator at hand. this requirement is met by the introduction of heterogeneous systems, with highly parallel accelerators that are designed to Programming is error-prone and debugging can be very dif- take care of the computation-heavy parts of an application. There ficult due to potential race conditions: this is particularly is today a plethora of accelerator architectures, including GPUs, disturbing as many embedded applications, like autonomous many-cores, FPGAs, and domain-specific architectures such as AI vehicles, are safety-critical, meaning that failures may have accelerators. They all have their own programming models, which lethal consequences. Furthermore software becomes hard to are typically complex, low-level, and involve explicit parallelism. This yields error-prone software that puts the functional safety at port between different kinds of accelerators. risk, unacceptable for safety-critical embedded applications. In A convenient solution is to adopt a model-driven approach, this position paper we argue that high-level executable modelling where the computation-intense parts of the application are languages tailored for parallel computing can help in the software expressed in a high-level, accelerator-agnostic executable mod- design for high performance embedded applications.
    [Show full text]
  • Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
    [3B2-14] mmi2010030003.3d 11/5/010 16:48 Page 2 .......................................................................................................................................................................................................................... PROGRAMMING MULTICORES: DO APPLICATIONS PROGRAMMERS NEED TO WRITE EXPLICITLY PARALLEL PROGRAMS? .......................................................................................................................................................................................................................... IN THIS PANEL DISCUSSION FROM THE 2009 WORKSHOP ON COMPUTER ARCHITECTURE Arvind RESEARCH DIRECTIONS,DAVID AUGUST AND KESHAV PINGALI DEBATE WHETHER EXPLICITLY Massachusetts Institute PARALLEL PROGRAMMING IS A NECESSARY EVIL FOR APPLICATIONS PROGRAMMERS, of Technology ASSESS THE CURRENT STATE OF PARALLEL PROGRAMMING MODELS, AND DISCUSS David August POSSIBLE ROUTES TOWARD FINDING THE PROGRAMMING MODEL FOR THE MULTICORE ERA. Princeton University Keshav Pingali Moderator’s introduction: Arvind in the 1970s and 1980s, when two main Do applications programmers need to write approaches were developed. Derek Chiou explicitly parallel programs? Most people be- The first approach required that the com- lieve that the current method of parallel pro- pilers do all the work in finding the parallel- University of Texas gramming is impeding the exploitation of ism. This was often referred to as the ‘‘dusty multicores. In other words, the number of decks’’ problem—that is, how to
    [Show full text]
  • An Outlook of High Performance Computing Infrastructures for Scientific Computing
    An Outlook of High Performance Computing Infrastructures for Scientific Computing [This draft has mainly been extracted from the PhD Thesis of Amjad Ali at Center for Advanced Studies in Pure and Applied Mathematics (CASPAM), Bahauddin Zakariya University, Multan, Pakitsan 60800. ([email protected])] In natural sciences, two conventional ways of carrying out studies and reserach are: theoretical and experimental.Thefirstapproachisabouttheoraticaltreatmment possibly dealing with the mathematical models of the concerning physical phenomena and analytical solutions. The other approach is to perform physical experiments to carry out studies. This approach is directly favourable for developing the products in engineering. The theoretical branch, although very rich in concepts, has been able to develop only a few analytical methods applicable to rather simple problems. On the other hand the experimental branch involves heavy costs and specific arrangements. These shortcomings with the two approaches motivated the scientists to look around for a third or complementary choice, i.e., the use of numerical simulations in science and engineering. The numerical solution of scientific problems, by its very nature, requires high computational power. As the world has been continuously en- joying substantial growth in computer technologies during the past three decades, the numerical approach appeared to be more and more pragmatic. This constituted acompletenewbranchineachfieldofscience,oftentermedasComputational Science,thatisaboutusingnumericalmethodsforsolvingthemathematicalformu- lations of the science problems. Developments in computational sciences constituted anewdiscipline,namelytheScientific Computing,thathasemergedwiththe spirit of obtaining qualitative predictions through simulations in ‘virtual labora- tories’ (i.e., the computers) for all areas of science and engineering. The scientific computing, due to its nature, exists at the overlapping region of the three disciplines, mathematical modeling, numerical mathematics and computer science,asshownin Fig.
    [Show full text]
  • Performance Tuning Workshop
    Performance Tuning Workshop Samuel Khuvis Scientifc Applications Engineer, OSC February 18, 2021 1/103 Workshop Set up I Workshop – set up account at my.osc.edu I If you already have an OSC account, sign in to my.osc.edu I Go to Project I Project access request I PROJECT CODE = PZS1010 I Reset your password I Slides are the workshop website: https://www.osc.edu/~skhuvis/opt21_spring 2/103 Outline I Introduction I Debugging I Hardware overview I Performance measurement and analysis I Help from the compiler I Code tuning/optimization I Parallel computing 3/103 Introduction 4/103 Workshop Philosophy I Aim for “reasonably good” performance I Discuss performance tuning techniques common to most HPC architectures I Compiler options I Code modifcation I Focus on serial performance I Reduce time spent accessing memory I Parallel processing I Multithreading I MPI 5/103 Hands-on Code During this workshop, we will be using a code based on the HPCCG miniapp from Mantevo. I Performs Conjugate Gradient (CG) method on a 3D chimney domain. I CG is an iterative algorithm to numerically approximate the solution to a system of linear equations. I Run code with srun -n <numprocs> ./test_HPCCG nx ny nz, where nx, ny, and nz are the number of nodes in the x, y, and z dimension on each processor. I Download with: wget go . osu .edu/perftuning21 t a r x f perftuning21 I Make sure that the following modules are loaded: intel/19.0.5 mvapich2/2.3.3 6/103 More important than Performance! I Correctness of results I Code readability/maintainability I Portability -
    [Show full text]
  • Regent: a High-Productivity Programming Language for Implicit Parallelism with Logical Regions
    REGENT: A HIGH-PRODUCTIVITY PROGRAMMING LANGUAGE FOR IMPLICIT PARALLELISM WITH LOGICAL REGIONS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF COMPUTER SCIENCE AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Elliott Slaughter August 2017 © 2017 by Elliott David Slaughter. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/mw768zz0480 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Alex Aiken, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Levis I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Oyekunle Olukotun Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost for Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii Abstract Modern supercomputers are dominated by distributed-memory machines. State of the art high-performance scientific applications targeting these machines are typically written in low-level, explicitly parallel programming models that enable maximal performance but expose the user to programming hazards such as data races and deadlocks.
    [Show full text]
  • Introduction to Parallel Processing
    IntroductionIntroduction toto ParallelParallel ProcessingProcessing • Parallel Computer Architecture: Definition & Broad issues involved – A Generic Parallel ComputerComputer Architecture • The Need And Feasibility of Parallel Computing Why? – Scientific Supercomputing Trends – CPU Performance and Technology Trends, Parallelism in Microprocessor Generations – Computer System Peak FLOP Rating History/Near Future • The Goal of Parallel Processing • Elements of Parallel Computing • Factors Affecting Parallel System Performance • Parallel Architectures History – Parallel Programming Models – Flynn’s 1972 Classification of Computer Architecture • Current Trends In Parallel Architectures – Modern Parallel Architecture Layered Framework • Shared Address Space Parallel Architectures • Message-Passing Multicomputers: Message-Passing Programming Tools • Data Parallel Systems • Dataflow Architectures • Systolic Architectures: Matrix Multiplication Systolic Array Example PCA Chapter 1.1, 1.2 EECC756 - Shaaban #1 lec # 1 Spring 2012 3-13-2012 ParallelParallel ComputerComputer ArchitectureArchitecture A parallel computer (or multiple processor system) is a collection of communicating processing elements (processors) that cooperate to solve large computational problems fast by dividing such problems into parallel tasks, exploiting Thread-Level Parallelism (TLP). i.e Parallel Processing • Broad issues involved: Task = Computation done on one processor – The concurrency and communication characteristics of parallel algorithms for a given computational
    [Show full text]
  • CIS 501 Computer Architecture This Unit: Shared Memory
    This Unit: Shared Memory Multiprocessors App App App • Thread-level parallelism (TLP) System software • Shared memory model • Multiplexed uniprocessor CIS 501 Mem CPUCPU I/O CPUCPU • Hardware multihreading CPUCPU Computer Architecture • Multiprocessing • Synchronization • Lock implementation Unit 9: Multicore • Locking gotchas (Shared Memory Multiprocessors) • Cache coherence Slides originally developed by Amir Roth with contributions by Milo Martin • Bus-based protocols at University of Pennsylvania with sources that included University of • Directory protocols Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood. • Memory consistency models CIS 501 (Martin): Multicore 1 CIS 501 (Martin): Multicore 2 Readings Beyond Implicit Parallelism • Textbook (MA:FSPTCM) • Consider “daxpy”: • Sections 7.0, 7.1.3, 7.2-7.4 daxpy(double *x, double *y, double *z, double a): for (i = 0; i < SIZE; i++) • Section 8.2 Z[i] = a*x[i] + y[i]; • Lots of instruction-level parallelism (ILP) • Great! • But how much can we really exploit? 4 wide? 8 wide? • Limits to (efficient) super-scalar execution • But, if SIZE is 10,000, the loop has 10,000-way parallelism! • How do we exploit it? CIS 501 (Martin): Multicore 3 CIS 501 (Martin): Multicore 4 Explicit Parallelism Multiplying Performance • Consider “daxpy”: • A single processor can only be so fast daxpy(double *x, double *y, double *z, double a): • Limited clock frequency for (i = 0; i < SIZE; i++) • Limited instruction-level parallelism Z[i] = a*x[i] + y[i]; • Limited cache hierarchy • Break it
    [Show full text]
  • Comparing SYCL with HPX, Kokkos, Raja and C++ Executors the Future of ISO C++ Heterogeneous Computing
    Comparing SYCL with HPX, Kokkos, Raja and C++ Executors The future of ISO C++ Heterogeneous Computing Michael Wong (Codeplay Software, VP of Research and Development), Andrew Richards, CEO ISOCPP.org Director, VP http://isocpp.org/wiki/faq/wg21#michael-wong Head of Delegation for C++ Standard for Canada Vice Chair of Programming Languages for Standards Council of Canada Chair of WG21 SG5 Transactional Memory Chair of WG21 SG14 Games Dev/Low Latency/Financial Trading/Embedded Editor: C++ SG5 Transactional Memory Technical Specification Editor: C++ SG1 Concurrency Technical Specification http:://wongmichael.com/about SC2016 Agenda • Heterogensous Computing for ISO C++ • SYCL • HPX (slides thanks to Hartmut Kaiser) • Kokkos (slides thanks to Carter Edwards, Christian Trott) • Raja (Slides thanks to David Beckingsale) • State of C++ Concurrency and Parallelism • C++ Executors coming in C++20 • C++ simd/vector coming in C++20 2 © 2016 Codeplay Software Ltd. The goal for C++ •Great support for cpu latency computations through concurrency TS- •Great support for cpu throughput through parallelism TS •Great support for Heterogeneous throughput computation in future 3 © 2016 Codeplay Software Ltd. Many alternatives for Massive dispatch/heterogeneous • Programming Languages Usage experience • OpenGL • DirectX • OpenMP/OpenACC • CUDA • HPC • OpenCL • SYCL • OpenMP • OpenCL • OpenACC • CUDA • C++ AMP • HPX • HSA • SYCL • Vulkan 4 © 2016 Codeplay Software Ltd. Not that far away from a Grand Unified Theory •GUT is achievable •What we have is only missing 20% of where we want to be •It is just not designed with an integrated view in mind ... Yet •Need more focus direction on each proposal for GUT, whatever that is, and add a few elements 5 © 2016 Codeplay Software Ltd.
    [Show full text]
  • The Cascade High Productivity Programming Language
    The Cascade High Productivity Programming Language Hans P. Zima University of Vienna, Austria and JPL, California Institute of Technology, Pasadena, CA ECMWF Workshop on the Use of High Performance Computing in Meteorology Reading, UK, October 25, 2004 Contents 1 IntroductionIntroduction 2 ProgrammingProgramming ModelsModels forfor HighHigh ProductivityProductivity ComputingComputing SystemsSystems 3 CascadeCascade andand thethe ChapelChapel LanguageLanguage DesignDesign 4 ProgrammingProgramming EnvironmentsEnvironments 5 ConclusionConclusion Abstraction in Programming Programming models and languages bridge the gap between ““reality”reality” and hardware – at differentdifferent levels ofof abstractionabstraction - e.g., assembly languages general-purpose procedural languages functional languages very high-level domain-specific languages Abstraction implies loss of information – gain in simplicity, clarity, verifiability, portability versus potential performance degradation The Emergence of High-Level Sequential Languages The designers of the very first highhigh level programming langulanguageage were aware that their successsuccess dependeddepended onon acceptableacceptable performance of the generated target programs: John Backus (1957): “… It was our belief that if FORTRAN … were to translate any reasonable scientific source program into an object program only half as fast as its hand-coded counterpart, then acceptance of our system would be in serious danger …” High-level algorithmic languages became generally accepted standards for
    [Show full text]