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Building Hardware Components for Memory Protection of Applications on a Tiny Processor Hyunyoung Oh, Yongje Lee, Junmo Park, Myonghoon Yang and Yunheung Paek Seoul National University {hyoh,yjlee,jmpark,mhyang}@sor.snu.ac.kr,[email protected] ABSTRACT the OS can exercise access control over every page in its memory As we move towards the IoT era, it is clear that many tiny proces- system by specifying security properties for memory protection sors will surround us, constantly communicating and transferring (i.e., memory access permissions and memory region attributes) valuable information with others. Although it is obvious that such in memory-mapped tables known as translation tables [2]. From processors will become appealing targets to attackers, they often the perspective of security, a key benefit of virtualizing address lack sophisticated hardware memory protection mechanism, such space is that it empowers the OS to protect sensitive data from as virtual memory. To enhance memory protection of tiny proces- unauthorized code by selectively binding the data with the code in sors, several studies have tried to design new hardware protection the virtual address space. That is, in the virtual memory system, if mechanisms at low cost. Those mechanisms, however, demand in- any application wants to access data at runtime, its code and the vasive modifications to the CPU internal architecture, and these data must be mapped (or bound) to the same virtual address space. modifications require significant cost and time for CPU redesign Therefore, in order to authorize only a trusted application to access and verification. In this paper, we present the design of hardware sensitive data, the OS simply configures translation tables in a way components for realizing an isolation of critical information on a to map the physical address of the data onto the virtual address tiny processor. Unlike other previous work, in our approach, several space of the authorized application code. hardware components are integrated together to build a system Despite its powerful security capability through code-data bind- with enhanced memory protection. To check the feasibility of our ing, virtual memory is rarely adopted by tiny embedded processors idea, we implement an early prototype where a RISC-V processor today in the market [3], but instead, deployed mostly in more capa- is connected with the proposed hardware components. Empirical ble processors targeting desktop PCs or other computing devices results show that ours achieves the goal with virtually no perfor- with ample resources. One major reason is that maintaining virtual mance and low area overhead. memory inherently requires a considerable amount of computation which is more than what a resource-stringent tiny processor could 1 INTRODUCTION afford. To satisfy the resource constraints, many vendors ofsuch low-end processors have implemented in hardware memory protec- As we move to the Internet of Things (IoT) era, more and more ex- tion mechanisms without virtualization. For this, these processors tremely small embedded devices like implanted medical devices are usually have a hardware memory management module, called the expected to use tiny embedded processors. Moreover, these devices memory protection unit (MPU), that assists the OS to enforce basic mostly would likely be connected to the IoT network and carry access rules for memory protection on the device without virtual sensitive user information like user profiles or credentials, and ac- memory support. MPU assumes that the system has a single physi- cordingly they are becoming attractive targets for cybercriminals. cal memory space regardless of the number of processes running on Therefore, for the proliferation of small devices in the IoT era, it the device. The memory space is divided into a number of regions, seems clear that we must properly address the security challenge and each process is assigned a set of regions associated with specific that is to protect security-critical information on these devices from access permissions given by the OS. At runtime, MPU enforces the various attacks. To enforce the protection of the critical informa- access rules by constantly checking if every process makes data tion, a conventional method is to implement a memory protection accesses complying with their permissions. mechanism that can isolate trusted applications processing critical Being free from the virtualization overhead, MPU can control information from other untrusted ones. data accesses of a process on memory regions with more efficiency. To efficiently support memory protection, the hardware typi- To maximize the efficiency, the access control mechanism ofMPU cally provides a special module for memory management, called the in existing tiny processors has been simplified in a way that each memory management unit (MMU). A main task of MMU is perform- region in the main memory is given the identical access permission ing virtual-to-physical mappings to realize virtual memory so that for every process trying to access it. However, from the perspective Permission to make digital or hard copies of all or part of this work for personal or of security, such efficiency exposes the system to a potential security classroom use is granted without fee provided that copies are not made or distributed breach that even when sensitive data must be processed by a trusted for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM application, the region containing the data can be accessed not only must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, by the trusted code but also by others (possibly from adversaries). to post on servers or to redistribute to lists, requires prior specific permission and/or a For this reason, when users want to set different access permissions fee. Request permissions from [email protected]. CARRV’17, Oct 2017, Boston, MA USA individually for each process, the OS should set different MPU © 2017 Association for Computing Machinery. configurations whenever the context switch occurs. However, this ACM ISBN 978-x-xxxx-xxxx-x/YY/MM...$15.00 OS-dependent approach is reportedly no longer secure because https://doi.org/10.1145/nnnnnnn.nnnnnnn many recent cases have reported that even an OS kernel can be patterns of the host. To check the feasibility of our idea, we make a compromised by the high-level attack such as rootkits. In those prototype where the slightly modified RISC-V Rocket is integrated cases, the memory isolation based on MPU is no longer guaranteed. with other hardware components. To overcome the limitation of the OS-dependent memory protec- The rest of the paper is organized as follows. Section 2 describes tion, recent studies [4, 7] endeavor to extend the protection features our assumption and the threat model. After Section 3 shows the by providing a hardware-enforced isolation of software modules overall system architecture for the memory protection, Section 4 targeting tiny embedded processors. In SMART [4], they presented explains the detailed implementation of our hardware modules. a new processor architecture which includes an attestation Read- Then, Section 5 discusses the experimental setup and results. In Only Memory (ROM) and a special storage in which the sensitive Section 6, we cover the previous studies related to ours. data are stored. Also, its MCU access control logic is changed to en- sure that only the specified code in the attestation ROM can access 2 ASSUMPTION AND THREAT MODEL the sensitive data in the special storage. In [7], they tried to en- In this work, we target embedded systems employing tiny pro- hance the protection mechanism of the original MPU architecture cessors available in today's market, which cannot afford MMUs by augmenting hardware logic to link code regions to data regions, for sophisticated virtual memory managements. We assume that thus making the permission check execution-aware. Although they the target system comes in the form of an SoC and therefore any have successfully enhanced the security of tiny processors, all these external hardware can be attached during implementation. previous solutions cannot be applied directly to the devices with As for our adversaries, we assume that untrusted software mod- existing processors because they require intrusive modifications ules can be installed in the target devices. These untrusted modules to the internal architecture of an existing processor including the can lead to compromising an entire program when (1) the modules pipeline registers and datapaths. have vulnerabilities which can be exploited by an attacker or (2) the A line of research [6, 8] has focused on implemental issues such modules themselves are malicious. This is due to the fact that, with- as how security hardware logics can be implemented with keep- out address protection between modules, a software module would ing the underlying CPU intact. Both studies commonly have used be able to corrupt the data used by another module. Additionally, we the hardware debugging interface of the processor to extract the assume that the adversary has full control over the communication branch target addresses for the control flow integrity enforcement. interface with the target system and can deliberately manipulate or By verifying branch target addresses at runtime, they have success- eavesdrop on the messages sent over the interface. We also assume fully detected the illegal control flow with incurring virtually no that the target system is exposed to physical attacks such as on-chip overhead on the host CPU. Motivated by their work, in this paper, bus probing or reverse engineering but these are out of the scope we present the design of hardware components which enable the of this paper. enhanced memory protection features for a tiny embedded proces- sor. Our solution is basically exerting the strategy similar to that of 3 OVERALL SYSTEM ARCHITECTURE earlier work [7].

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