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A Noniterative Radix-8 CORDIC Algorithm with Low Latency and High Efficiency

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electronics Article A Noniterative Radix-8 CORDIC Algorithm with Low Latency and High Efficiency Wenming Tang * and Feng Xu The Key Laboratory for Information Science of Electromagnetic Waves, School of Information Science and Technology, Fudan University, Shanghai 200433, China; [email protected] * Correspondence: [email protected] Received: 6 August 2020; Accepted: 1 September 2020; Published: 17 September 2020 Abstract: An efficient, noniterative Radix-8 (NR-8) coordinate rotation digital computer (CORDIC) algorithm is proposed for low-latency and high-efficiency computation of the functions of sine, cosine, or the phase shift, with which the values of the functions are precisely computed by only using the angle in a narrow range of [0, π/12] rather than in a wide angle range of [0, π/2]. This algorithm is expressed by a formula that simplifies the traditional iterative processes by using a complex multiplier. The results obtained from the simulation and the experiment on an FPGA show that the NR-8 CORDIC algorithm operates well, with which the 16-bit precision output is extremely precise, with only 0.012% of the absolute error for computing the sine or cosine function with a step of 0.001◦. Compared with the best conventional CORDIC algorithm, the clock latency of this algorithm significantly decreases down to less than 50%, only needs half of the logic resources and consumes half of the power. This algorithm also takes advantages over other newly improved CORDIC algorithms and requires less than half of the clock latency, even for a 23-bit precision output. Therefore, this algorithm could provide a potential application in real-time systems such as radar digital beamforming. Keywords: CORDIC; sine and cosine; phase shift; FPGA; digital beamforming 1. Introduction As one of the most common transcendental functions, the sine or cosine function has been widely used in real-time digital signal processing systems, such as radar, ultrasound, robotics, communication and so on [1–7]. The accuracy and efficiency of the computation of the functions are two key requirements for evaluating the performance of these systems. For this purpose, many methods to calculating the sine or cosine function have been developed, such as the lookup table, Taylor series, polynomial approximation and so on [8–10]. However, these methods have the disadvantage of either high complexity or high latency, and thus an efficient method is extremely required to meet the accurate and efficient computation for real-time systems. Fortunately, the coordinate rotation digital computer (CORDIC) algorithm [11] can provide accurate and efficient computations by employing an iterative way and decomposing the calculation into a series of addition, subtraction and shift operations, which enables it to be widely used in digital circuits to implement the computations of trigonometric and exponential functions, and so forth [12]. However, as an iterative algorithm, the accuracy of the CORDIC algorithm strongly relies on the number of iterations, so the increase of the iteration number leads to the increase of the clock latency, thus lowering the efficiency for the computations. To further enhance the efficiency, more progress has been made by improving the architecture of the CORDIC algorithm to achieve a more efficient algorithm, such as the Scaling-Free (SF) CORDIC, Radix-4 CORDIC, Radix-8 CORDIC and low-latency Hybrid (LLH) CORDIC algorithms [13–17]. Electronics 2020, 9, 1521; doi:10.3390/electronics9091521 www.mdpi.com/journal/electronics Electronics 2020, 12, x FOR PEER REVIEW 2 of 18 Electronics 2020, 9, 1521 2 of 17 [13–17]. Some of the improved CORDIC algorithms have been widely used in radar digital beamforming (DBF) systems. For instance, Lee et al. developed a CORDIC-based algorithm to be Some of the improved CORDIC algorithms have been widely used in radar digital beamforming (DBF) used in Multi-Gbps MIMO systems, which is implemented by a Virtex-6 FPGA using 49,752 slices, systems. For instance, Lee et al. developed a CORDIC-based algorithm to be used in Multi-Gbps and the algorithm needs 260 ns (250 MHz, 65 clock periods) of latency due to the many iterations MIMO systems, which is implemented by a Virtex-6 FPGA using 49,752 slices, and the algorithm needs required for computations [4]. Similarly, Jun et al. described look-ahead, pipelined CORDIC-based 260 ns (250 MHz, 65 clock periods) of latency due to the many iterations required for computations [4]. adaptive filters and their application to adaptive beamforming [5], and the pipeline level m depends Similarly, Jun et al. described look-ahead, pipelined CORDIC-based adaptive filters and their on the m-bit precision. However, the CORDIC algorithm often requires many iterations to converge, application to adaptive beamforming [5], and the pipeline level m depends on the m-bit precision. which has become a major bottleneck for real-time applications. However, the CORDIC algorithm often requires many iterations to converge, which has become a In this work, a new noniterative Radix-8 (NR-8) CORDIC algorithm is proposed for low-latency major bottleneck for real-time applications. implementation on FPGAs. In the process of the development of an NR-8 CORDIC algorithm, three In this work, a new noniterative Radix-8 (NR-8) CORDIC algorithm is proposed for low-latency steps were taken: (1) The NR-8 CORDIC algorithm was derived from the conventional Radix-2 implementation on FPGAs. In the process of the development of an NR-8 CORDIC algorithm, CORDIC one. (2) The input angle θ was set to a narrow range by simultaneously transforming the three steps were taken: (1) The NR-8 CORDIC algorithm was derived from the conventional Radix-2 input variables x and y . (3) A formula was deduced and optimized. These steps can narrow the CORDIC one. (2)0 The input0 angle θ was set to a narrow range by simultaneously transforming the selectinputed variables range ofx 0theand iterationy0. (3) Aangle formula and wasrealize deduced a noniterative and optimized. formula Theseof the stepsCORDIC can narrowalgorithm the; bselectedesides, the range algorithm of the iterationcan be accelerated angle and by realize the multiplier a noniterative module formula readily of available the CORDIC in FPGAs algorithm; [18]. Asbesides, a result, the algorithmthe algorithm can becan accelerated reduce 7– by17 theclock multiplier latencies module of the readilyconventional available CORDIC in FPGAs (16 [-18bit]. precision)As a result, alg theorithm algorithm to a canthree reduce-clock 7–17 latency clock, needs latencies less of logic the conventional resources and CORDIC consume (16-bits less precision) power. Comparedalgorithm towith a three-clock the LLH algorithm latency, needs [16], less it has logic great resources advantages and consumes in terms lessof time power. and Comparedresources. withFor thethe structure LLH algorithm of this [ 16paper,], it has following great advantages the introduction in terms is of Section time and 2, resources.in which the For derivation the structure from of the this conventionalpaper, following CORDIC the introduction algorithm is Sectionis presented.2, in which In Section the derivation 3, the from proposed the conventional NR-8 CORDIC CORDIC is introduced.algorithm is Section presented. 4 presents In Section its3 ,FPGA the proposed implementation NR-8 CORDIC and isanalysis introduced.. Section Section 5 introduces4 presents the its applicationFPGA implementation of the NR-8 andCORDIC analysis. in radar Section DBF.5 introduces Finally, a the conclusion application is made of the according NR-8 CORDIC to the in results radar obtainedDBF. Finally, from a the conclusion above sections is made. according to the results obtained from the above sections. 2.2. C Conventionalonventional CORDIC CORDIC Rotator Rotator Algorithm Algorithm TheThe CORDIC algorithmalgorithm usually usually operates operates in in rotation rotation mode mode or vector or vector mode mode [11,12 [1],1 following,12], following linear, linear,circular circular or hyperbolic or hyperbolic coordinate coordin trajectories.ate trajectories. In this In paper, this paper we focus, we focus on the on rotation the rotation mode mode using usingcircular circular trajectory. trajectory. * TheThe rotation rotation mode mode is is depicted depicted in in Fig Figureure 1,1, where where θθ isis the the angle angle between between the the VV00(,)( xx 00, yy 00) andand * * * Vdd(,)( xx dd, yy dd) vectors.vectors. AsAs thethe vector vectorV 0Vrotates0 rotates counterclockwise counterclockwise to the to vectorthe vectorVd, the V coordinate,d , the coordinate,(xd, yd) , can be described as in Equation (1): (,)xydd, can be described as in Equation (1): " # " #" # " #" # xd cos θsinθ x 0 1 1 tan θ x0 = xd cosθ sinθ x00= tanθ x − =coscosθθ − (1) yd sin θcos θ y0 tan θ 1 y0 (1) yd sinθ cosθ y00 tanθ 1 y y V1 (x1,y1) (x ,y ) Vd d d (x ,y ) V2 2 2 . (x ,y ) V0 0 0 2nd rotation θ1 1st rotation θ θ 0 O x FigureFigure 1. 1. TThehe CORDIC CORDIC vector vector rotation rotation model. model. If the initial vector (x , y ) is set to x = 1, y = 0, Equation (1) can be used to compute cos θ and If the initial vector (,)0xy0 is set to0 xy=1, 0 0 , Equation (1) can be used to compute cosθ sin θ. 00 00 and sinθ . is decomposed into a series of micro angles, each of which corresponds to one step rotation as shown in Figure 1 and described as in Equation (2): Electronics 2020, 9, 1521 3 of 17 θ is decomposed into a series of micro angles, each of which corresponds to one step rotation as shown in Figure1 and described as in Equation (2): Xn 1 (i+1) θ = θi, θi = tan− (σiR− ) (2) i=0 where n denotes the number of rotations, R denotes the radix, R = 2l, l N, θ denotes micro angles 2 i and σ is the selection factors defined as all integers within the interval σ [ R/2, R/2].
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  • A Highly Optimized Arithmetic Software Library and Hardware Co

    A Highly Optimized Arithmetic Software Library and Hardware Co

    TETRACOM: Technology Transfer in Computing Systems FP7 Coordination and support action to fund 50 technology transfer projects (TTP) in computing systems. FP7 Coordination and Support Action to fund 50 technology transfer projects (TTP) in computing systems. This project has received funding from the European Union’s Seventh Framework Programme for research, This project has received funding from the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement n⁰ 609491. technological development and demonstration under grant agreement n⁰ 609491. A Highly Optimized Arithmetic Software Library and Hardware Co-processor IP for Fixed-Point VLIW-SIMD Processor Architectures Lukas Gerlach, Stephan Nolting, Holger Blume and Guillermo Payá Vayá, Leibniz Universität Hannover, Germany Hans‐Joachim Stolberg and Carsten Reuter, videantis GmbH, Hannover, Germany TTP Problem Performance requirements are pushing the limits of Area and energy efficiency is restricted for embedded multimedia systems: embedded multimedia systems: Often used non-linear complex Area and energy optimized computation by mathematical functions require a lot of using specific arithmetic evaluation computational power. software libraries or hardware accelerators. sin() atan() ln() div() cos() sqrt() exp() pow() TTP Solution Software-based solution: Hardware-based solution: Mathematic software CORDIC (Coordinate CORDIC processing element config x,y,z start Rotation Digital Computer) library (LibARITH) N optional Scalable co-processor Pre-processing stage architecture: Optimized for VLIW-SIMD processors: scale . M CORDIC modules in . Exploiting data and instruction level parallelism series are incorporated to Register Register Register Iteration controller process M CORDIC Advantages: D S iterations per clock cycle CORDIC Scale factor M table . High flexibility Angle P P table P .