Under~~g Wide-b~dMOS

Fine-line MOS are now fast enough to compete with bipolar detectors and , but quantitative understanding of MOS device speed has not kept pace.

through the use of fT for MOS transis- tors, the use of fr in the prediction of bandwidth, and a wider famil- iarity among designers with practical examples of MOS wide-band amplifiers. igh-- Figuring merit frequency analog MOSH circuits that am- When a new MOS process is developed, plify and detect signals well above audio the first test circuit is almost always a frequencies have appeared in the last ring-oscillator chain. This is appropri- few years [l,2,3]. These circuits demon- ate because digital circuits drive MOS strate that fine-line MOS transistors are process development, and ring oscilla- now sufficiently fast to perform in what tors give a quick indication of the mini- has been the bipolar ’s domain. mum gate delay for a process. Inferring But a quantitative understanding of analog performance from ring-oscillator MOS-transistor speed has been slow to speed is not so straightforward because emerge. For example, given a particular information about the ring’s topology CMOS process with a minimum chan- and operating point are usually not nel length of 2 pm, what amplifier available. bandwidth can we achieve? A useful stand-alone figure of merit This lack of understanding stems from for transistors in the unity-gain current the absence a commonly-agreed-upon frequency (fT). This figure of merit figure of merit for MOS-transistor speed makes intuitive sense for current- and a lack of familiarity among design- controlled bipolar device, but is it a use- ers with MOS-amplifier topologies. ful measure of an MOS transistor’s These problems can be addressed capabilities? In fact, it is. Although a

by John M. Steininger

26 Circuits and Devices MOSFET’s gate draws no current at DC, the displacement current through the gate-to-source capacitance becomes the primary limitation to the transistor’s response at high frequency. We can bet- ter understand how the fT of an MOS transistor can be calculated and mea- sured by viewing the transistor as a (a)Hybrid-r Model (b) fT Model two-port device (Fig. 1). This two-port’s I small-signal, linear response can be char- 2. Small-signal MOS transistor models. acterized by any complete set of two- port parameters, such as h-parameters. in a low-gain, wide-bandwidth configu- cal amplifier in which the gain is still C,, The fT of a two-port is defined as the ration where the Miller-multiplied set by the ratio of device geometries frequency where the magnitude of hZ1is can be neglected. (Fig. 4). Here, the bias current is set by unity-where liout/ii,l = 1. We can also current source M3 and the output is ca- calculate thefr of an MOS transistor us- What bandwidths are possible? pable of a wider swing. We can calcu- ing the equivalent circuit elements of Wide-band amplifier configurations in late the achievable bandwidth of this the hybrid-.rr model (Fig. 2a), which MOS have a different look than the re- yields: sistively loaded gain stages found in bipolar amplifier designs. The MOS versions are often resistorless because where C, = C,, + c,d resistors, although available in most modern CMOS technologies, have been Typically, an n-channel MOS transis- + neglected by process developers. This tor fabricated in a 2p CMOS process $ neglectful attitude has been shared by with WIL = 30012, V,, = 3 V, and analog MOS designers, who have sought to deviate as little as possible from all- transistor, “digital-like” circuit struc- tures. The simplest “all-transistor’’ realization of a wide-band MOS ampli- Vi n fier is the enhancement-mode inverter (Fig. 3). Here the two active devices are 3. Enhancement-mode inverter. I biased in the region where both are ac- port 1 port 2 tive, so Kn = V,,,. This amplifier’s gain is the ratio of the transconductance of 1. An equivalent circuit of an MOS the two transistors. Since the current transistor as a two-port device. through the two devices is identical, the gain is set by the ratio of the device ~3 +bias ID = 3 mA will have an fT of 2 GHz. sizes: Since OJT = g,,,/C,, we can express the gate capacitance of an MOS transistor as c, = &/WT. And this allows us to put forth a simple fT model for an MOS Unfortunately, the current through this transistor (Fig. 2b). amplifier is not well controlled and the This fTmodel is useful if the drain-to- output swing can go no higher than I I bulk capacitance, Cdb, is small com- &d - Khn. pared to C,, and if the transistor is used It is possible to design a more practi- 4. Simplepractical CMOS amplifier.

May 1990 27 tinue to exhibit square-law behavior. Second, in a given technology, devices + + made with the minimum channel length and biased with the largest V,, will have in v out the greatest fT, regardless of W. We can see from the above equations I- I I I I that fT is an unbounded increasing func- tion of both V, and ID(Fig. 6). This dif- 1 fers from the situation in a bipolar 5. A small-signal equivalent circuit of the amplifier shown in Fig. 4 based on the fT transistor, where fr peaks at some opti- transistor model. mum collector current (Fig. 7). This roll-off in bipolar fr at high currents is due to an increase in rFcaused by high- simple gain stage by using the fr transis- V,, = v,, - I/;h tor model to analyze the small-signal level injection and the Kirk effect, the From these two equations we can write equivalent circuit (Fig. 5). same mechanisms that cause PF to drop a simple expression for fT: If we neglect the capacitance loading off [4]. of M3 and assume the circuit is loaded It is natural to compare the fT of by an identical following stage, the stage bipolar transistors at their optimum col- gain is A" = -gml/gm2. The 3 db band- lector current. But no such fr peak oc- width is: This simple expression has two im- curs in MOS, so at what point should portant implications. First, fr is pro- MOS transistors from different tech- portional to I/L'. Since process nologies be compared? That point technologies tend to scale down by a should be some practical value of V,, ur ur factor of l/dper generation, each new that is held constant across technolo- technology should have twice the fr of gies. A value of V,, that is commonly andfp/fr = MAO+ 1). the old, provided that the devices con- used to measure the drive-current capa- To obtain an amplifier with the bility of MOS transistors for digital highest possible bandwidth, we would applications (I/upply- vh)is not appro- like to cascade stages of low gain. (See priate for analog design because it is not sidebar 1.) For a stage gain of A,, = 3, a practical biasing point. we can calculate that the maximum at- In a 5-V technology, the upper limit tainable bandwidth of an amplifier of a practical bias is approximately made in a 2p CMOS technology with fT V,, = 2.25 V, and this is the point at fT = 2 GHz ishdhmax= 500 MHz. which we have plotted measurements of fr vs. Lefffor 3 CMOS technologies ID Scaled MOS andfT 1. (Fig. 8). Also plotted are the calculated We can increase the fr of an MOS fT)s of these processes using the simple device by making the g, larger or the C, fT theory and normalized to the 3pm smaller, or both. A simple, first-order CMOS measurement. The measured f+s theory that relates fT to device proper- do not follow the simple theory in which ties can be developed if we approximate fr is proportional to 1/L2. Instead, the the gate capacitance of a MOS transis- increase in fr with decreasing gate tor in a way that neglects the gate-to- length is shown to be much less dra- drain overlap capacitance. If we assume "0" matic, and there are two reasons for that C, is only the parallel plate capaci- this. First, short-channel transistors op- tance between the -gate and channel, we '. fr ''. Kn and ID. erated at practical bias voltages do not can then say that C, = C,,WL. We behave as square-law devices. Their know that: short channel lengths and correspond- Iingly thin gate dielectrics (<500 A) f T produce high electric fields in the channel, both in the longitudinal and transverse directions. These high fields n degrade the drift velocity of the channel carriers-often called velocity satura- tion-which produces a smaller-than- expected transconductance for these devices [5,7]. W 7. fT of a bipolar transistor vs Second, the simple theory neglects = peffCox~V,,,where log Icc. the gate-to-drain overlap and assumes

28 Circuits and Devices that C, is only a parallel-plate capaci- tance even though small gate ge- *O ometries have fringing fields that 0.75 um contribute significantly to C,. These - Von= Vgs-Vth= 2.25 field lines to not terminate on charge in the channel and therefore do not con- o simple theory 12 - tribute to the transconductance of the fT U measured data device. [Ghzl These two factors produce a mea- sured fT for scaled MOS technologies that is lower than that predicted by first-order theory. Still, on a absolute scale, the speed of these transistors is quite respectable, and CMOS circuits 0, -1 1 with wide bandwidth are possible. 0 0.4 0.8 1.2 1.6 IF1 Wide-band CMOS amplifiers 8. fT VS. L,, for various CMOS technologies. Although the simple-wide-band CMOS amplifier shown in Fig. 4 is practical, its application is limited by its single-ended nature. Differential wide-band amplifiers are more versatile, due to their floating common-mode input range, increased output swing, and the first-order can- cellation of nonlinearities in their dif- ferential outputs. Another advantage of

It+ differential circuits is their potential for increased power-supply rejection. This is particularly important at high fre- quencies where active power-supply re- jection is not possible. A differential amplifier where gain is again set by the ratio of g,’s is shown in Fig. 9. Here, current mirrors are used to provide additional current gain. The 9. Simple differential wideband amplifier. voltage gain of this amplifier is:

G= gm1(WLIM6(WL)M9 gm11 (W/L)M3(W/L)M7 A limitation of this scheme is that dc bias I bias current, as well as signal current, is Mb4 amplified by the current mirrors. This can be overcome by using interstage dc subtractors [l]. If this and other limita- R L+ R L- tions-the inherent non-linearity of the single-ended outputs and the limited output swing-can be tolerated, the cir- cuit can provide very wide bandwidth. out+- -out- For applications where wide output swing and good single-ended linearity are most important, being able to incor- porate resistors in the design would be helpful. But combining resistors and in amplifiers is problematic, primarily because of the g, of MOSFET transistors. To understand this, consider a bipolar and a MOS transistor biased at the same current and dimensioned so 10. Resistively loaded MOS amplifier with g, cancellation. that they have the same fr. The g, of

May 1990 29 Optimum Stage Gain the MOS transistor, even in a fine-line Derivation of the Bias Current for Maximum technology, will typically be an order of that Produces gm= l/Rb Cascaded Bandwidth magnitude less than the g, of the bipo- lar transistor. If we construct a simple The bias circuit shown in Fig. 12 one-transistor amplifier, using RL as the produces a current that will set the It is possible to show that there is load resistor and Rs as the degeneration gm of a matched transistor equal to an optimum stage gain for a resistor in series with the source or 1/Rb. Referring to Fig. 12, if we sum cascade of identical amplifiers that emitter, the gain will be: the voltages around the loop formed maximizes the overall bandwidth. by MB2, MB1, and Rb,we get: Consider a cascade of several amplifiers with an equivalent circuit vgsz = vgsl IbRb like that of Fig. 5. The frequency Since: transfer function of this circuit will be: In the bipolar case, the gain of this amplifier can be made independent of g, by choosing R, * l/gm.To meet this same criterion in the MOS case, RL and where A. and "p are the gain and Rs must be at least an order of magni- Then: 3db bandwidth of an individual tude larger. This becomes a problem if stage. We can solve Equation all for bias current passes through these resis- h, the 3db frequency of the overall tors because their voltage drop can cascade, such that quickly exceed the power supply's avail- Solving for /b yields: 1 1 able head room. This suggests that MOS lb=---= amplifier designs that include resistors 4KRE &ett C,(W/L) Rb" should ensure that bias current does not The g, of a device with dimensions flow through the gain-setting resistors. (W/L) and biased at lb is: This yields: Large-valued resistors take up area

Oh = wpm(a1.2) and have correspondingly large para- sitic capacitances that limit amplifier We know that: bandwidth. It would be more conve- We desire to find the maxima of this grn2 gm2 U1 nient if we could use smaller resistors in function To do so, we can take the w P- - Ctotac & + e AO + 1 our amplifier designs and still have a derivative of the natural logarithm of both sides-maximizing the Or OT gain that is independent of g,. In fact, we can design a circuit that has its gain logarithm will maximize the The total cascaded gain will be the set by a ratio of resistors and removes expression-and set equal it equal product of each of the individual to zero gains, A = Aon. Substituting these the effect of the MOSFET's g, on the into Equation a1.2 gives: circuit gain by using a cancellation "(in:) = 7In A - 1 = 0 scheme (Fig. 10). dn This cancellation is accomplished by Now, solving for the stage gain gives cross coupling the drains of M2 and M3 the very simple final result: Equation a1.3 has a maxima that is to the sources of M1 and M4. This in- independent of A. We can find that sures that V,, + V,, = V,, + GT4.If we A. = A& maxima analytically if we make a apply a small differential voltage vd Thus, the maximum overall couple of assumptions. First, for across the input terminals, it appears di- bandwidth can be achieved with large n (n > 4), we can say that: rectly across the resistor, 2Rs. The re- cascaded stages of very low gain. sulting current, Vd/2Rs,is added or This relation is exact only for the subtracted from the circuit's bias cur- amplifier configuration specified. A rent and mirrored into the load resis- plot of a1.3 and a1.5 vs. stage gain to a good approximation. Second, tors. The gain of this circuit, provided for a fixed A (A = 50) is shown in assume that the capacitance of the that Ib1,4e Ib2,3,is then: Fig. A,. load conductance can be neglected, Notice that the plot of a1.3, which that is gml/"T %- gm2/"T.Then: represents the fr equivalent circuit, has a broad maxima. Typically, the more complicated the gain stage, the It is even possible to build resistively smaller the achievable bandwidth Combining this with Equation a1.4 loaded MOS amplifiers with no source and the broader the peak. The actual gives a new expression for a1.3: degeneration at all and still have the choice of stage gain becomes a gain set by a ratio of resistors (Fig. 11). trade-off between power This differential amplifier uses a tapped consumption and ultimate resistive load and a simple output bandwidth. common-mode setting network. By cen-

30 Circuits and Devices ter tapping the load resistor and level- tuting MOS transistors produces a band designs. Although the speed of shifting through source follower M7, current Ib = 1/(4KRt) where K = these fine-line devices does not scale up the output common-mode voltage is set (pC,/2) (W/L).(See sidebar 2) as rapidly as simple theory would pre- at V,, + T&. With no source degenera- If the devices are sized such that dict, MOSFETs with gate dimensions tion resistor Rs, the gain of this ampli- (w/L)B2 = (W/L),= 2(W/L)1,2 and on the order of 1 pm have fT)s approach- fier is simply G = gm1,,RL. (W/L)B~,~= W/Lh = (W/Lh, then a ing 5 GHz. Thefr figure of merit can be The cleverness that makes this circuit current will bias the input pair M1 and used to predict the performance of useful is in the bias circuit, which biases M2 such that gm1,2= l/Rb. Therefore, simple amplifiers, a1 t houg h practical M9 to produce a current that sets the G = g,1,2R~ = (4KIB)“’RL = RL/Rb, amplifiers typically have less band- g,’s of M1 and M2 proportional to RL and the gain has been made indepen- width. Practical differential amplifiers (Fig. 12). This circuit is an MOS ver- dent of the MOSFET’s g, and propor- that have gains set by ratios of transis- sion of a self-biasing Widlar current tional to a ratio of resistors. tors or resistors can be built, and the source [6]. In the bipolar version, a cur- As we’ve seen, scaled MOS technolo- exhibit gain-bandwidth products ap- rent Ib proportional to the thermal gies have native transistors with high proaching the predicted limit of fr. voltage V, = kT/q is produced. Substi- f;s that can be incorporated into wide-

References 1. D. M. Pietruszynski et al., “A 50 Mbit/s CMOS Monolithic Optical Receiver,” IEEE J. Solid-state Cir- cuits, Vol. SC-23, No. 6, pp. 1426-33 1 (Dec. 1988). 2. A. A. Abidi, “Gigahertz Transresis- R L- R L+ tance Amplifiers in Fine Line out--* I W.- out+ NMOS,” IEEE J. Solid-state Cir- M7 - cuits, Vol. SC-19, No. 6, pp. 986-94 M6 (Dec. 1984). j. 3. Jeff Scott et al., ‘A 16 Mbit/s Data Detector and Timing Recovery Cir- - cuit for Token LAN,” ISSCC Di- biasn I M8 gest of Technical Papers, Vol. 32, pp. 150-51 (Feb. 1989). 4. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, pp. 31, (Wiley, 1977). 11. A MOSFET amplifier with G = g,RL. 5. C. G. Sodini, P. K. KO and J. L. Moll, “The Effects of High Fields on MOS Device and Circuit Performance,” IEEE Tran. on Electron Devices, Vol. ED-31 (Oct. 1984). 6. P. R. Gray and R. G. Meyer, op. cit., biasp pp. 282-83. 7. K.Y. Toh, P. K. KO and R. G. Meyer, “An Engineering Model for Short- Channel Devices,” IEEE J. Solid- State Circuits, Vol. SC-23, No. 4, pp. 950-58 (August 1988). CD

Acknowledgements Thanks to Dave Pietruszynski, Jeff biasn Scott, and T.R. Viswanathan for their wide-band-amplifier-circuit contribu- tions. Special thanks to 0. G. Petersen for his editorial assistance.

Biography John M. Steininger is supervisor of an analog IC design group at AT&T Bell 12. Bias circuit for the amplifier of Figure I1 thatproduces g, = Rb Laboratories in Reading, Pennsylvania.

May 1990 31