Geforce FX Go5100 Graphics Processor Unit
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Data Sheet GeForce FX Go5100 Graphics Processor Unit CONFIDENTIAL INFORMATION RELEASED UNDER NDA ONLY 4/21/2003 GPU Da ta Shee t PROPRIETARY INFORMATION Document Change History Version Date Responsible R ea so n f or Cha nge 01 04/21/03 N Smith Initiial Relea se ii DS-00829-001_v01 NVIDIA CONFIDENTIAL 4/21/03 Chapter 1. Introduction ............................................................................................................. 1 Features and Functions ....................................................................................... 2 Chapter 2. Ball Map andFeature Signal SetDescriptions Overview .......................................................................................... .............................................................................9 5 BGA Device Pinout (Left View) ................................................................................. 10 BGA Device Pinout - (Right View) ............................................................................ 11 Signal Descriptions ................................................................................................. 12 Table of Contents Conventions ..................................................................................................... 12 Host Interface .................................................................................................. 13 SDRAM Memory Interface ................................................................................. 18 ROM Access Signals .......................................................................................... 20 VIP 1.1 Interface Port ....................................................................................... 21 Integrated Dual-Link LVDS/TMDS Transmitter Interface ....................................... 22 Integrated Single-Link LVDS/TMDS Transmitter Interface..................................... 23 Digital Video Output Interface ........................................................................... 24 I2C Interface C....................................................................................................onfidential Inf 25ormation Dual Video DAC and PLL Analog Signals ............................................................. 25 Power Supply .................................................................................................. 27 General Signals ............................................................................................... 28 Chapter 3. Functional DescriptionTest Signals...................................................................................................... ...........................................................................................29Released U 28nder NDA Functional Block Diagram ........................................................................................ 30 Frame Buffer Interface ............................................................................................ 31 Physical vs. Internal Banks of Memory ............................................................... 31 Frame Buffer Memory Accesses and Commands .................................................DO 33NOT COPY Host InterfaceProgrammable ........................................................................................................ Frame Buffer AC Timing Parameters ............................................ 35 34 General AGP Overview ...................................................................................... 35 AGP3.0PCI Interface Transactions .................................................................................................... on the AGP2.0 Bus .................................................................. 39 37 DS-00829-001_v01 4/21/03 NVIDIA CONFIDENTIAL iii GeForce FX Go5100 GPU Data Sheet PROPRIETARY INFORMATION AGP2.0 Interface .................................................................................................... 44 AGP2.0 Overview .............................................................................................. 45 AGP2.0 Bus Transactions ................................................................................... 45 AGP Sideband Transfers .................................................................................... 51 Display Interfaces ................................................................................................... 58 LVDS Mode ...................................................................................................... 58 DAC ................................................................................................................. 60 Pixel Formats Supported ................................................................................... 60 TV Encoder Interface .............................................................................................. 61 Features ..........................................................................................................on 61 Media Port for VIP 1.1 Interface ..............................................................................ti 62 Video Interface Port Features ............................................................................a 62 Connection Diagram .........................................................................................m 64 Chapter 4. r A Timing and Electrical Specifications.......................................................................65fo D Absolute Maximum Ratings ....................................................................................In N 65 Operating Conditions ..............................................................................................l er 66 Electrical Specifications ...........................................................................................ia d 67 Parameters Applying to AGP nInterfacet Pins .........................................................n Y 67 Parameters for 3.3 V LVTTL...............................................................................e U P 68 Parameters for 5 V Signalingid Environment Onlyd ..................................................O 68 Video DAC Characteristicsf .................................................................................e C 69 Frame Buffer SDRAMn Interface Timing ....................................................................s T 70 Host Interface Timingo .............................................................................................a O 71 AGP3.0 CTiming Specificationsl e............................................................................N 71 AGP2.0 Timing Specificationse ............................................................................ 74 PCI 2.3 Timing SpecificationsR ............................................................................O 79 Chapter 5. D Power Specifications ..............................................................................................83 PowerMizer Hardware Support ................................................................................. 83 Power and Current Configuration ............................................................................. 84 Chapter 6. Power-On Reset Configuration ..............................................................................85 Chapter 7. GeForce FX Go5100 Package Description ..............................................................89 Package Marking ................................................................................................... 89 Package Specification ............................................................................................. 90 Appendix A. Pin Listings.............................................................................................................95 Sorted by Signal Name ........................................................................................... 96 Sorted by Ball .......................................................................................................102 iv DS-00829-001_v01 NVIDIA CONFIDENTIAL 4/21/03 Appendix B. Display Options.................................................................................................... 109 Resolutions Supported ........................................................................................... 109 Hardware Cursor ................................................................................................... 112 Appendix C. XOR Tree Testing................................................................................................. 113 Enabling XOR Tree Test Mode ................................................................................PROPRIETARY INFORMATION 113 Description of XOR Tests ....................................................................................... 114 Parametric XOR Tree ....................................................................................... 114 Tri-State Pins .................................................................................................. 114 Output HIGH .................................................................................................. 114 RequiredOutput Pins LOW....................................................................................................... ................................................................................................... 115 115 XOR Tree Signal Lists ............................................................................................ 115 Index .................................................................................................................