Quad-Band GSM Phone Chip

1094 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005 A 0.25-"m CMOS Quad-Band GSM RF Transceiver Using an Efﬁcient LO Frequency Plan Eunseok Song, Yido Koo, Member, IEEE, Yeon-Jae Jung, Deok-Hee Lee, Sangyoung Chu, and Soo-Ik Chae, Member, IEEE

Abstract—This paper describes a single-chip CMOS quad-band a monolithic transceiver with low-cost CMOS technologies [1], (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS appli- [2]. cations. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In The Global Systems for Mobile communication (GSM) particular, reducing the number of voltage-controlled oscillators network spanning over 200 countries is a rapidly growing and (VCOs) required for local oscillator (LO) frequency generation is evolving mobile standard [3]. It is the first cellular system that very important because the VCO and phase-locked loop (PLL) cir- specifies digital modulation and network-level architectures cuits occupy a relatively large area. We propose a quad-band GSM and services [4]. There are several frequency bands where GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL terminals are or will shortly be operated. Therefore, a GSM to generate LO signals by using an efficient LO frequency plan. terminal that can support all of the GSM frequency bands listed In the receive path, four separate LNAs are used for each band, in Table I will be more useful for its global roaming [3], [5]. and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). Previously, there have been several works related to GSM A receiver baseband circuit is shared for all four bands because transceivers [6]–[11]. Early GSM transceivers [6]–[8] employed all of their channel spaces are the same. In the transmit path, the super-heterodyne architecture to integrate the receiver and most of the building blocks of the offset PLL, including a TX VCO transmitter in a single chip. However, they were implemented and IF filters, are integrated. The quad-band GSM transceiver with BJT technology and did not integrate all of the functions, that was implemented in 0.25- m CMOS technology has a size of 3.3 3.2 mmP, including its pad area. From the experimental requiring several external components, such as an IF filter. Al- results, we found that the receiver provides a maximum noise though the GSM transceivers [9], [10] developed later were figure of 2.9 dB and a minimum IIP3 of 13.2 dBm for the EGSM implemented with low-cost CMOS technology, they still re- 900 band. The transmitter shows an rms phase error of 1.4 quired several off-chip filters for image rejection and channel and meets the GSM spectral mask specification. The prototype selection [9] or deferred these tasks to their baseband digital chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively. signal processing (DSP) chip [10]. Moreover, they supported only single-band communication, that is, the GSM900 band in Index Terms—CMOS, dc offset, direct conversion, frequency di- [9] and the DCS1800 band in [10]. A GSM transceiver that sup- vider, GSM, LO frequency, offset phase-locked loop (PLL), quad- band, transceiver. ports the quad bands (850/900/1800/1900 MHz) [11] was implemented with BiCMOS technology. It employed a direct conversion receiver (DCR) and achieved a considerably high inte- I. INTRODUCTION gration level. However, the TX IF filters and loop filters were not HE wide use of portable communication systems has cre- integrated. Moreover, its frequency doubler and subharmonic T ated a great demand for low-cost, low-power, small form- mixers (SHMs), which consume a large bias current, are dif- factor transceivers. In the past, radio frequency (RF) front-end ficult to be implemented in CMOS technology due to the rela- circuits have been implemented with GaAs or bipolar junction tively small transconductance of the MOS transistors. transistor (BJT) technologies while the low-frequency baseband In order to overcome these problems, we have proposed a circuits have used CMOS technologies. Such implementations single-chip CMOS RF transceiver architecture for the four GSM using the technologies of different kinds, however, are not suit- bands (850/900/1800/1900 MHz). The proposed transceiver able as a low-cost solution for RF transceivers. In modern-day architecture employs a direct-conversion receiver and an offset implementations, high-frequency CMOS circuits are becoming PLL transmitter. The rest of this paper is organized as follows. more feasible due to the aggressive scale-down in CMOS tech- In Section II, we explain the proposed architecture of the GSM nologies. Thus, the recent research trends have been to develop quad-band transceivers in CMOS technology. Moreover, we also describe how we obtained an efficient LO frequency plan that is suitable for area reduction, low-power consumption, and Manuscript received June 25, 2004; revised October 22, 2004. E. Song and S.-I. Chae are with the ISRC, School of Electrical Engineering, precise generation in the proposed architecture. The major Seoul National University, Seoul 151-742, Korea (e-mail: dooly@sd- circuit blocks of the transceiver are described in Section III. group.snu.ac.kr). The experimental results of the prototype GSM transceiver Y. Koo, Y.-J. Jung, D.-H. Lee, and S. Chu are with GCT Semiconductor, Inc., San Jose, CA 95131 USA. are presented in Section IV. Finally, the conclusion is given in Digital Object Identifier 10.1109/JSSC.2005.845990 Section V.

TABLE I GSM FREQUENCY BANDS

II. QUAD-BAND TRANSCEIVER ARCHITECTURE AND ITS LO FREQUENCY PLAN In this section, we propose the architecture for the GSM quad- band transceiver that employs a direct-conversion receiver and an offset PLL transmitter. Therefore, we can share the baseband filters among the four frequency bands and image rejection filters are not required in the receiver, which reduces the area of the transceiver. We employ an offset PLL transmitter in the proposed transceiver architecture because it has lower noise and less spurious emission. The LO frequency planning is the key to designing the multiband GSM transceivers because it strongly influences the performance of the transceiver as well as its area and power consumption [12]. What we must consider in the LO frequency planning includes the number of VCOs/PLLs required, the VCO tuning range, precise generation, and RF-LO interference. To reduce the die size of a GSM quad-band transceiver, min- Fig. 1. Waveforms of input and sa signals generated with frequency imizing the number of VCOs and PLLs is the most important dividers. (a) With a divide-by-2 circuit. (b) With a divide-by-4 circuit. factor because they occupy relatively large areas in the transceiver ICs. In this section, we will also describe how we ob- signal depends on the duty cycle of the input signal. On the other tained an efficient frequency plan using direct down conversion hand, in the frequency-divide-by-4 method shown in Fig. 1(b), for the receiver and offset PLL for the transmitter. Then, we will both and are rising-edge triggered. Therefore, the explain the detailed architecture of the quad-band transceiver phase accuracy is not affected by the duty cycle of the input based on the proposed frequency plan. signal. Although the divide-by- methods require a higher fre- Most RF communication systems today employ accurate quency signal, which can be a disadvantage in a frequency plan, signals for the complex domain signal processing. Thus, gener- they consume a relatively small current and provide good phase ating the precise signals is a key to making a successful accuracy against the process and frequency variations. We de- frequency plan, in order to meet the phase error specification cided to use the divide-by-4 or divide-by-8 circuits to generate for the GSM transceivers. the precise signals in the frequency plan in order to meet the phase-error specification for the GSM transceivers. A. Precise Generation In integrated circuits, there are two common methods for gen- B. How to Obtain an Efficient Frequency Plan erating signals: using an RC–CR phase shifter or using a In finding an efficient LO frequency plan, we put some con- divider circuit. The RC–CR phase shifters are more suitable to straints that are required to develop a low-power low-cost small the frequency planning of the transceivers because they do not form-factor GSM transceiver based on the proposed architec- translate the frequency at all. However, it is difficult to achieve ture, as shown in Table II. First, it is very important to minimize good matching performance in the RC–CR phase shifters be- the number of VCOs/PLLs required in the transceiver. Note that cause the absolute values of R and C depend on the process the number of VCOs required depends on the tuning range of variations. Although the higher order phase shifters can reduce each VCO and that the typical tuning range of an on-chip L–C these mismatches substantially [10], they have larger signal at- VCO is less than 20% due to their design margin against the tenuation and consume more power. L and C variations. Although the VCOs using a ring oscillator Fig. 1 shows the other method of generating I/Q signals with have a wider tuning range, they are rarely used in the transceiver the divider circuits. In the frequency-divide-by-2 method shown IC due to their large phase noise. in Fig. 1(a), is rising-edge triggered and is falling- The constraint for is intended to loosen the VCO edge triggered. Therefore, the phase accuracy of the quadrature pulling and pushing effect by separating away from 1096 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

TABLE II CONSTRAINTS FOR THE LO FREQUENCY PLAN FOR THE GSM QUAD-BAND TRANSCEIVER ARCHITECTURE THAT EMPLOYS A DIRECT-CONVERSION RECEIVER AND AN OFFSET PLL TRANSMITTER

is suitable to the offset PLL transmitter for the quad-band transceiver, which can satisfy the requirement of separating away from in the direct conversion receiver. Note that we do not permit low-side mixing for high bands, to prevent the LO VCO frequency from being too high. For the frequency plan in Fig. 2(a), we can write the following equations:

(1)

(2) (3)

where is the low-band frequency and is the high-band frequency. Equation (3) is the necessary condition to support the quad-band GSM. From (1)–(3), we write

(4)

To solve (4), , and are assumed as follows:

or (5) (6) (7)

Equations (5)–(7) are the constraints for generation with the divide-by-4 or divide-by-8 circuits, thus limiting the VCO frequencies and making the task of implementing the dividers easier. By solving (4)–(7) together, we obtained six feasible solutions for , and , as shown in Table III. If , and are all fixed, we can calculate the VCO range and the TX IF range from the frequency band defined in the GSM specification. Among the six solutions, Plan3, in which the VCO and TX IF frequencies are the lowest, is the Fig. 2. LO frequency plans for the transceiver architecture that employs a most suitable to be implemented in integrated circuits because direct conversion receiver and an offset PLL transmitter. (a) A general frequency the on-chip L–C VCO has smaller phase noise if its oscillation plan. (b) Proposed frequency plan. frequency is low. In addition, its prescaler is easier to be designed and consumes less current for the lower LO frequencies. the RF frequency [6], [13], [14]. The constraint for the The TX IF range should not be too high so that the TX IF generation with the divide-by-4 or divide-by-8 circuits is added filters can be easily implemented in the integrated circuits. We to meet the tight phase error in the GSM specification because adopted the frequency Plan3 shown in Fig. 2(b), which satisfies they are more precise and insensitive than the phase shifters, as all the constraints in Table II. explained before. Now we explain how we obtained the efficient LO frequency C. Quad-Band Frequency Plan plans that satisfy the constraints in Table II. Fig. 2(a) shows a Based on the frequency Plan3 in Table III, we describe general frequency plan that employs only one LO VCO/PLL and the detailed frequency plan suitable to the GSM quad-band SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1097

TABLE III LO FREQUENCY PLANS THAT SATISFIES THE CONSTRAINTS IN TABLE II

the required range of the LO VCO that supports the quad band is from 1390 to 1592 MHz for the receiver. In the TX frequency plan shown in Fig. 4, we used the offset PLL architecture including a TX VCO to reduce the noise in the transmit signal. The TX VCO directly covers the high-band RF and its divide-by-2 signal covers for the low-band RF. Similar to the RX frequency plan, the LO VCO in the TX frequency plan runs at 8/5 of the transmit RF for the low-band RX (GSM850/EGSM900) and of the transmit RF for the high-band RX (DCS1800/PCS1900), as shown in Fig. 4. The quadrature LO2 signals that are generated by divide-by-4 or divide-by-8 circuits are applied to the offset UP mixers. Similarly, an LO VCO can be shared between the low and high bands. Thus, the required tuning range of an LO VCO that supports the quad-band TX is from 1318 to 1528 MHz, which is mostly overlapped with the tuning range of the LO VCO in the receiver. Therefore, we can share an LO VCO between the receiver and the transmitter. Table IV summarizes the tuning ranges of the TX and LO VCOs in the proposed GSM transceiver. Each VCO can be implemented with an on-chip L–C VCO because its tuning range is less than 20%. This frequency plan relaxes the VCO pulling/pushing problems because the LO VCO frequency is either 4/5 of the high- band frequency or 8/5 of the low-band frequency. However, it requires four different divider circuits. Because it uses the two different IF frequencies in the transmitter, the IF filters of the TX offset PLL should be designed to select their cut-off frequency Fig. 3. RX block diagram based on the proposed frequency plan. according to the target frequency band. (a) GSM850/EGSM900 bands. (b) DCS1800/PCS1900 bands. D. Quad-Band Transceiver Architecture transceiver. In the low-band RX (GSM850/EGSM900) fre- We propose an efficient architecture for the single-chip quency plan shown in Fig. 3(a), the LO VCO runs at of the GSM quad-band transceiver based on the detailed frequency RF frequency, and the LO signal for direct down conversion plans, which can be implemented with CMOS technology. As is generated by the high-sided mixing of the signals from shown in Fig. 5, the proposed architecture integrates most of the divide-by-2 with the divide-by-8 signals of the LO VCO the building blocks for the quad-band transceiver. The required frequency. Note that the signals are generated through external components are the RX band-select SAW filters, the the divide-by-8. For the high-band RX (DCS1800/PCS1900) matching circuits of the LNAs, and the TX power amplifiers. frequency plan in Fig. 3(b), the LO VCO runs at 4/5 of the In the receiver, four separate LNAs are employed to im- RF frequency and the signals are generated through the prove the blocking performance for each band. In addition, divide-by-4 of the LO VCO frequency. Note that a single LO two separate down-conversion mixers are used: one for the VCO in the receiver supports the quad bands by being shared low bands (850/900 MHz) and the other for the high bands between the low-band and high-band receivers. Consequently, (1800/1900 MHz). The baseband circuits are shared for all four 1098 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

Fig. 4. TX block diagram based on the proposed frequency plan. (a) GSM850/EGSM900 bands. (b) DCS1800/PCS1900 bands.

TABLE IV VCO TUNING RANGES REQUIRED FOR THE GSM QUAD-BAND TRANSCEIVER BASED ON THE PROPOSED FREQUENCY PLAN

bands because their channel spaces are equal to 200 kHz. In it transmits the VCO signal directly for the high bands and the transmitter, the offset PLL is employed to meet the tight through the divide-by-2 circuit for the low bands. We used GSM spectral mask specifications. The offset PLL transmitter the - fractional- synthesizer for the LO PLL, and all the includes the offset UP/DN mixers, IF filters, TX VCO, loop operating modes and options of the transceiver can be set by a filter, and preamplifiers. Because it employs a single TX VCO, 3-wire serial peripheral interface (SPI). SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1099

Fig. 5. Block diagram of the quad-band GSM transceiver based on the proposed frequency plan.

III. CIRCUIT DESCRIPTIONS band frequency, to achieve maximum LNA gain. We designed A. LNA to be to prevent out-of-band blockers from being mixed-down with the third harmonics of the LO signal. For each LNA, we used a single-stage differential LNA, as Fig. 7 shows the simulation result for the PCS1900 LNA. Its shown in Fig. 6(a), to improve its linearity. The differential LNA power gain is 21 dB at 1960 MHz and its rejection at the third was employed to achieve a good IIP2 characteristic, although harmonic band (5880 MHz) is about 56 dB. Although this LNA it requires a large area and consumes more current. We used has a better blocking performance, it occupies an area of about down-bond wires as series feedback inductors to lower both the 0.3 0.3 mm due to the additional on-chip spiral inductor . noise figure and the input voltage standing wave ratio (VSWR). The load of the LNA is composed of a resonant circuit using B. RX Down-Conversion Mixer spiral inductors, which attenuates the out-of-band blockers. The The down-conversion mixer, which is a key building block impedance of the half circuit of its load, shown in Fig. 6(b), can of the RF receiver, has a large influence on the noise figure and be written as follows: linearity of the receiver. The down-conversion mixer we used is shown in Fig. 8, where the NMOS current, , is 3 mA. Each PMOS current source, , reduces the bias current of its corresponding LO switch, which is the main source of the noise (8) in Gilbert-type mixers [15]. However, reducing the current of the switches too much will result in a severe degradation of con- From (8), we can write and as follows: version gain and linearity. In the mixers with a switch current less than the bias current, a small variation in the bias current can result in a large change in the output voltage. Thus, the output common-mode voltage is very sensitive to device mismatches and process variations. Instead of using the ac couplers, which have a long settling time and occupy a large area, we employed a common-mode feedback circuit with an operational amplifier At the frequency of , the load impedance has its min- to overcome these problems [16], as shown in Fig. 8. imum value, and, at the frequency of , it is at its max- The simulation results for the down-conversion mixer are imum value. should be designed to be , the receive shown in Fig. 9. The rms output noise voltage in Fig. 9(b) is 1100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

Fig. 8. Down-conversion mixer with common-mode feedback (CMFB).

Fig. 6. LNA. (a) Schematic. (b) Equivalent circuit for a half circuit of the load.

Fig. 7. Simulation result for the PCS1900 LNA. calculated over the frequency range 1–100 kHz. If the of the PMOS load is sufﬁciently large, the output load impedance is R . Thus, the load impedance is almost indepen- dent of the switch and load current. As a result, the conversion gain of the mixer can be maintained even though the switch Fig. 9. Simulation results for the down-conversion mixer. (a) Gain and IIP3 current is reduced to a certain level. versus s . (b) RMS output noise versus s . SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1101

Fig. 10. RX baseband block diagram.

However, the conversion gain and IIP3 in Fig. 9(a) are se- verely degraded as the PMOS current increases more than 2 mA. There is a tradeoff between noise and linearity, and, therefore, the PMOS current is selected to be 2 mA, which is near the point where reducing the output noise by increasing the PMOS current more has no further advantage.

C. RX Baseband Circuits The block diagram of the RX baseband is shown in Fig. 10. It consists of a PreAGC, four PostAGCs, and three low-pass filters. The overall dynamic range of the RX baseband circuit is 75 dB. In order to loosen the linearity requirement of the baseband circuits, the LNA is designed to have about a 27-dB gain con- trol range. Thus, the total dynamic range of the receiver is about 102 dB. The output of the RX down-conversion mixer is applied to the input of the PreAGC, as in Fig. 10. We allocated a larger area and more current to the PreAGC than the other baseband circuits, in order to allow both high linearity and low noise performance. Three low-pass filters reject the in-band interferers, Fig. 11. VGA with DCC. (a) Schematic. (b) Its frequency response. which are implemented by third-order active-RC Butterworth filters. The transfer function of (10) is drawn in Fig. 11(b). The corner In the direct-conversion receivers, the dc-offset cancellation frequency of the high-pass filter can be adjusted by changing the is very important. Although the ac couplers are a simple solu- resistance in the dc extractor. tion, they require a large area and a long settling time. We used the active dc-offset cancellation circuits (DCCs), which are con- D. TX Offset UP/DN Mixers nected to each AGC, as shown in Fig. 10. An AGC cell with the The nonlinear terms of the offset UP mixer will cause spu- DCC is shown in Fig. 11, where we used MOS capacitors to re- rious emission in the transmit signal. Among them, the spurious duce the area. A dc extractor integrates the offset voltage of the tones from the baseband third harmonics are hard to remove be- AGC output and the integrated offset voltage is subtracted from cause they appear very close to the transmit frequency. Fig. 12 the AGC input through a feedback connection. For the AGC cir- shows the offset UP mixer used in this work, which improves cuit in Fig. 11(a), the AGC output can be written as follows: linearity substantially using a gain-boosting operational amplifier. is a degeneration resistor and the transistors, M1 and M2, operate as source followers. If the gain-boosting circuits are not added to M1 and M2, harmonic terms can appear when the (9) current of varies due to the insufficient transconductance of M1 and M2. From (9), the transfer function of the AGC can be written as If the gain of the operational amplifier is sufficiently large, follows: the differential current of M1 and M2 can be written as follows:

Because the signal bandwidth of the IN/INB is less than 100 kHz, it is not difﬁcult to design an operational ampliﬁer (10) with a bandwidth wider than 100 kHz. From the simulation 1102 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

Fig. 14. Simulation result for TX offset PLL: rms phase error and phase noise at 20-MHz offset versus loop bandwidth.

Fig. 12. Offset UP mixer with improved linearity.

Fig. 15. Microphotograph of the quad-band GSM transceiver.

E. Offset PLL Loop Filter

The frequency of the Gaussian-ﬁltered minimum shift keying (GMSK) modulated signal is deviated within the range from kHz to kHz according to the conveyed digital data. Fig. 13. Offset DN mixer with cascode stage. Thus, the output of the offset UP mixer, which corresponds to the reference input of the PFD, will also be deviated from the result, the offset UP mixer provides an IIP3 of 12 dBV, which center IF frequency. If the bandwidth of the offset PLL is too shows an improvement of about 10 dB compared with the UP narrow, the output of the offset PLL cannot track the reference mixer without the gain boosting circuits. deviation, which can result in a large rms phase error of the The offset DN mixer translates the VCO frequency into the transmit signal. Fig. 14 shows the simulation result for the rms IF frequency, which is applied to the phase frequency detector phase error along with the phase noise at 20-MHz offset versus (PFD), as shown in Fig. 5. Because it is a relatively high fre- the loop bandwidth of the offset PLL. There exists a tradeoff quency circuit, the signal couplings should be taken into ac- between the rms phase error and the 20-MHz wideband noise count. Fig. 13 shows the offset DN mixer used in this work. [8], [17]. In order to achieve an rms phase error of less than The cascode transistors, M3 and M4, prevent the LO signals 0.6 and to minimize the wideband noise, we designed the loop from directly coupling to the VCO/VCOB. If the LO signals bandwidth of the offset PLL to be 933 kHz. In designing the are coupled to the VCO/VCOB, it will add spurious tones to loop parameters of the offset PLL, the division factor should the transmit signal. According to the simulation results, the cas- be calculated as 1. Because the VCO frequency is translated to code stack reduces the coupling from the LO to the VCO by the IF frequency by the offset DN mixer, the frequency deviation more than 20 dB. of the VCO output is not scaled down at all [18]. SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1103

Fig. 16. RX noise ﬁgure versus frequency. (a) EGSM900 band. (b) PCS1900 band.

Fig. 18. Constellations of the GMSK demodulated signal at the RX output. (a) For the RX input power of VT dBm. (b) For the RX input power of IHP dBm.

prototype chip occupies an area of 3.3 3.2 mm including its pads, which was assembled in a 40-pin quad ﬂat no-lead (QFN) package. The RX RF circuits, such as LNAs and down-conversion mixers, are placed in the upper left corner and the RX baseband circuits, such as PGAs and LPFs, in the lower left corner. We allotted a large area to the RX baseband blocks to reduce the noise. The TX offset PLL including the TX VCO is located in the upper right corner and the LO VCO with a - fractional- synthesizer is located in the lower right corner. Their loop ﬁlters are integrated using the MOS capacitors. The type of each VCO is an LC oscillator with an external inductor, and its size is about 0.7 0.7 mm . Each VCO consumes about 5 mA.

Fig. 17. RX IIP3 versus frequency. (a) EGSM900 band. (b) PCS1900 band. Fig. 16 shows a graph of noise figure versus frequency for the receiver. The measured chip noise figures (NFs) for the EGSM900 and PCS1900 bands are less than 2.9 and 3.4 dB, IV. EXPERIMENTAL RESULTS respectively. The NF variations in a band are related with the The quad-band GSM transceiver described in the previous SAW filter ripple, impedance matching, and so on. We mea- section was implemented in 0.25- m 1-poly 5-metal CMOS sured the NF with the inclusion of the external band-select SAW technology, and its microphotograph is shown in Fig. 15. The filter. From this, we compensated for the insertion loss of the 1104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

Fig. 19. Measured rms phase error at the TX output for the GMSK modulated signal.

SAW filter in order to calculate the chip NF. Although the insertion loss of the SAW filter at each channel (or frequency) must be strictly compensated for, we used a typical loss in a band for simplicity. Thus, the insertion loss variation of the SAW is included in the NF plot of Fig. 16. The SAW filters used in this work are the EPCOS B7701/B7706/B7716/B7717 components for GSM/EGSM/DCS/PCS, and their typical insertion losses are 2.3/2.6/3.0/2.6 dB, respectively. Fig. 17 shows a graph of IIP3 versus frequency for the receiver. The IIP3 values were measured by the two-tone test. The minimum receiver IIP3 is about dBm for the EGSM900 band and dBm for the PCS1900 band, which satisfies the specifications required for the GSM transceiver. The specifications shown in Fig. 17 were also calculated by assuming that the front-end loss is Fig. 20. GMSK modulated spectrums at the TX output. (a) EGSM900 band. 4 dB. Fig. 18 shows the constellations of a GMSK demodulated (b) PCS1900 band. signal at the RX output for the input of (a) dBm and (b) dBm. The measured rms phase errors are 2.9 and which is due to the nonlinearity of circuits, especially the third 4.6 , respectively, which are sufficiently less than the required harmonics of the offset UP mixer. Thus, the IIP3 of the offset rms error of 5 in the GSM specifications [5]. UP mixer should be improved in order to achieve better TX Fig. 19 shows the rms phase error at the TX output for mask performance. We used a - fractional- synthesizer the GMSK modulated signal. According to the experimental to meet the settling time requirement for the GPRS class 12. results, the rms phase errors for the PCS1900 and EGSM900 The measured RX and TX settling times are less than 200 and bands are 1.7 and 1.4 , respectively, which are also sufficiently 220 s, respectively. smaller than the required RMS phase error of 5 in the GSM Although the frequency plan used in this study has the ad- specification [5]. The GMSK modulated spectrums at the TX vantage of reduced area and smaller power consumption, the output are shown in Fig. 20, which also meet the GSM spectral undesirable mixing products from the LO generator affect the mask specifications [5]. The prototype chip consumes about out-of-band blocking performance of the receiver. The front-end 56 mA in the RX mode and 58 mA in the TX mode at 2.8 V. SAW filter on the receiver side should have enough selectivity to Specifically, the LO generation circuitry with the exception of suppress the input frequency bands corresponding to the mixing the synthesizer consumes about 10 mA. terms. In order to improve the blocking characteristics, an L–C Table V summarizes the performance of the quad-band GSM tuned amp for the LO buffer or a bandpass filter following the transceiver. The overall receiver dynamic range is 102 dB. The LO generation mixers should be added, which might increase maximum receiver gain is 107 dB and the minimum gain is 5 dB. the power consumption. Therefore, there is a tradeoff between For the high bands, the IIP2 performance is not sufficient to performance and power consumption. pass the AM suppression test. In order to improve the IIP2 at 1800/1900 MHz, we should reduce the mismatches between the differential signal paths, for example, the asymmetry of the PCB V. C ONCLUSION lines, the chip layout, and the pin assignment. The TX spectral In this paper, we proposed an efficient frequency plan that is mask performance at 400 kHz, as shown in Table V, is marginal. suitable for the GSM quad-band transceiver. We also presented a SONG et al.: 0.25- m CMOS QUAD-BAND GSM RF TRANSCEIVER USING AN EFFICIENT LO FREQUENCY PLAN 1105

TABLE V PERFORMANCE SUMMARY OF THE QUAD-BAND GSM TRANSCEIVER CHIP

single-chip 0.25- m CMOS RF transceiver using the proposed [3] [Online]. Available: http://www.gsmworld.com frequency plan. The GSM quad-band transceiver includes only [4] S. Tadjpour, “A 900 MHz dual conversion, low-IF CMOS GSM re- one LO VCO with a tuning range from 1318 to 1592 MHz. We ceiver,” Ph.D. dissertation, Univ. of California, Los Angeles, 2001. [5] V8.11.0: Digital Cellular Telecommunications System (Phase PC); used divide-by-4 and divide-by-8 circuits to generate all of the Radio Transmission and Reception, Aug. 2001. ETSI TS 100 910. signals, which consume less power and are less sensitive to [6] T. D. Stetzler, I. G. Post, J. H. Havens, and M. Koyama, “A 2.7–4.5 V the process and frequency variations, compared with the phase single chip GSM transceiver RF integrated circuit,” IEEE J. Solid-State shifters. Moreover, we selected the LO VCO frequencies to re- Circuits, vol. 30, no. 12, pp. 1421–1429, Dec. 1995. [7] C. Marshall et al., “A 2.7 V GSM transceiver IC’s with on-chip filtering,” duce the VCO pulling and pushing effects by separating them in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 148–149. away from the RF frequency. According to the measured re- [8] T. Yamawaki et al., “A 2.7-V GSM RF transceiver IC,” IEEE J. Solid- sults, the receiver provides the maximum noise figure of 2.9 dB State Circuits, vol. 32, no. 12, pp. 2089–2096, Dec. 1997. [9] P. Orsatti, F. Piazza, and Q. Huang, “A 20-mA-receive, 55-mA-transmit, and the minimum IIP3 of 13.2 dBm for the EGSM band. The single-chip GSM transceiver in 0.25-"m CMOS,” IEEE J. Solid-State transmitter presents an rms phase error of 1.4 , which meets Circuits, vol. 34, no. 12, pp. 1869–1880, Dec. 1999. the GSM spectral mask specification. The prototype chip con- [10] M. S. J. Steyaert, J. Janssens, B. De Muer, M. Borremans, and N. Itoh, “A sumes 56 mA in the RX mode and 58 mA in the TX mode at 2-V CMOS cellular transceiver front-end,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1895–1907, Dec. 2000. 2.8 V. Thus, we conclude that the proposed GSM transceiver is [11] R. Magoon, A. Molnar, J. Zachan, G. Hatcher, and W. Rhee, “A suitable for low-cost low-power small-form factor solutions. single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCO’s and fractional-N synthesizer,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1710–1720, ACKNOWLEDGMENT Dec. 2002. [12] J. Strange and S. Atkinson, “A direct conversion transceiver for The authors would like to thank S.-W. Lee and J. Park for multi-band GSM application,” in Proc. IEEE RFIC Symp., Jun. 2000, their discussion on the transceiver architecture, S. Hong for his pp. 25–28. helpful comments on the GSM standard, and Y. Ahn for his test [13] K. Lee et al., “A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion equipment setup. technique,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 800–809, May 2001. [14] A. Zolfaghari and B. Razavi, “A low-power 2.4-GHz transmitter/re- REFERENCES ceiver CMOS IC,” IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. [1] A. A. Abidi, “RF CMOS comes of age,” IEEE Microw. Mag., pp. 47–60, 176–183, Feb. 2003. Dec. 2003. [15] D. Manstretta, R. Castello, and F. Svelto, “Low Iaf noise CMOS ac- [2] B. Razavi, “RF CMOS transceivers for cellular telephony,” IEEE tive mixers for direct conversion,” IEEE Trans. Circuits Syst. II, Analog Commun. Mag., pp. 144–149, Aug. 2003. Digit. Signal Process., vol. 48, no. 9, pp. 846–850, Sep. 2001. 1106 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

[16] J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, and P. Deok-Hee Lee was born in Korea on May 6, 1977. R. Gray, “A 1.9-GHz wide-band IF double conversion CMOS receiver He received the B.S. and M.S. degrees in electrical for cordless telephone applications,” IEEE J. Solid-State Circuits, vol. engineering from Seoul National University, Seoul, 32, no. 12, pp. 2071–2088, Dec. 1997. Korea, in 2000 and 2002, respectively. [17] E. Hegazi and A. A. Abidi, “A 17-mW transmitter and frequency syn- He is currently with GCT Semiconductor, Inc., San thesizer for 900-MHz GSM fully integrated in 0.35-"m CMOS,” IEEE Jose, CA, where he works on the design and develop- J. Solid-State Circuits, vol. 38, no. 5, pp. 782–792, May 2003. ment of integrated CMOS transceivers for GSM and [18] J.-M. Hsu, “A 0.18-"m CMOS offset-PLL upconversion modulation wireless LAN. loop IC for DCS1800 transmitter,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 603–613, Apr. 2003.

Eunseok Song was born in Korea in 1971. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1996 and 1999, respectively, where he is currently working toward the Ph.D. degree. He has been working on CMOS analog circuit design, and his research interests include CMOS RF circuits and CMOS image sensors. Sangyoung Chu was born in Korea on August 11, 1973. He received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1998 and 2000, respectively. In 2000, he joined GCT Semiconductor, Inc., San Jose, CA, where he is currently a Principal Engineer Yido Koo (S’96–M’03) was born in Seoul, Korea. He leading the development of wireless communication received the B.S., M.S., and Ph.D. degrees in elec- systems. trical engineering and computer science from Seoul National University, Seoul, Korea, in 1996, 1998, and 2003, respectively. His doctoral dissertation includes the design of a fully integrated CMOS frequency synthesizer for CDMA applications. From 2000 to 2002, he developed the frequency synthesizer for CDMA and PHS wireless systems working with GCT Semiconductor, Inc., San Jose, CA, as a part-time Design Engineer. In 2003, after graduation, he joined the same company as a Manager of Analog Division, where he is now involved in the design and implementation of RF transceiver and building blocks for GSM and W-CDMA systems. He is the inventor of two Soo-Ik Chae (M’87) received the B.S. and M.S. de- and co-inventor of several U.S. patents. grees in electrical engineering from Seoul National Dr. Koo was the recipient of the 2003 IEEE Best Student Award of the IEEE University, Seoul, Korea, in 1976 and 1978, respec- Solid-State Circuits Society Seoul Chapter. tively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, in 1987. He was an Instructor with the Electronics Depart- ment, Air Force Academy of Korea, Seoul, from 1978 Yeon-Jae Jung was born in Korea in 1974. He re- to 1982. He also worked as a Manager of an ASIC ceived the B.S., M.S., and Ph.D. degrees in electrical Design Group, ZyMOS Corporation, Sunnyvale, CA, engineering and computer science from Seoul Na- from 1987 to 1988 and a General Manager at Daewoo tional University, Seoul, Korea, in 1997, 1999, and Telecom Company from 1988 to 1990. Since 1990, 2003, respectively. he has been with Seoul National University, where he is currently a Professor Currently, he is a Design Engineer with GCT in the School of Electrical Engineering and the Director of the Center of SoC Semiconductor, San Jose, CA. His main research Design Technology. He was the Director of the Inter-University Semiconductor interests are in RF and baseband CMOS circuits and Research Center (ISRC) from 2001 to 2003. His research interests include dig- system planning for wireless communications. ital system design, especially programmable DSP design for H.264 and three-di- mensional graphics and ultralow-power circuits.