AGENDA 08:30 View the latest 09:30 Registration and Designer Expo

09:30 agenda in the Opening Remark, Sherry Xu, Vice President, General Manager of China and Southeast Asia, Cadence 09:45 mobile app 09:45 10:15 K01 - Anirudh Devgan, President, Cadence

10:15 10:45 K02 - Shao-Jun Wei, Professor, Tsinghua University

10:45 11:15 K03 - Leo Zhu, CEO, YITU Tech

11:15 11:40 Best Presentation Award Ceremony

11:40 13:00 Lunch and Designer Expo

TRACK 1 TRACK 2 TRACK 3 TRACK 4 TRACK 5 TRACK 6 TRACK 7 TRACK 8 Digital Implementation Digital Front-End PCB Design, System Design and Custom IC Design Tensilica DSP Automotive Tensilica Audio DSP 3F, Shanghai Ballroom 2 and Signoff IC Packaging, and System Verification 3F, Shanghai Ballroom 1 Ecosystem Partners 3F, Function Room 2 New Applications 3F, Function Room 4 Analysis 3F, Function Room 1 3F, Function Room 3 3F, Function Room 2 3F, Shanghai Ballroom 3

SP01 - True 3D Analysis of SV01 - Optimizing Verification CUS01 - Analog/Mixed-Signal TIP01 - AI安全与影像应 AU01 - 汽车智能化演进为半 13:00 Large Geometries with Clarity Throughput for a Connected Technology Overview 用及趋势 导体行业带来的新动力 13:30 3D Solver World - Cadence, Zhong Fan - 旷视科技 Megvii, 沈瑄 产 - SemiDrive, Jason Zhang - Cadence, Michael Young 品市场总监 - Cadence, Jian Liu DI01 - Achieving Your Best DF01 - Genus iSpatial Flow for PPA with Cadence Digital and Best Predictability and PPA Signoff Solution SP02 - Allegro Pulse and What’s SV02 - Enhance LPDDR5 DRAM CUS02 - Meeting Quality and TIP02 - 整合AI产业链，促进 AU02 - Automotive – The - Cadence, Kam Kittrell - Cadence, Chin-Chi Teng New in Allegro 17.4 Release Controller Verification with Reliability Requirements for 算法高效落地 Changing Landscape 13:30 Cadence LPDDR VIP Advanced-Node and Mission- - Cadence, Simon Chang - Cadence, Julian Sun - 极视角 Extreme Vision, 14:00 - Mediatek, Mengru Si Critical Applications 刘若水 - Cadence, Rui Pan 战略合作总监

DI02 - TSMC-Cadence DF02 - Tempus Hierarchical SP03 - 2.5D Package Interposer SV03 - 基于硬件加速器的高 CUS03 - Analog Mixed-Signal TIP03 - 智能感知与边缘计算 AU03 - Power-Efficient AI Collaboration on Mobile and Techniques and Cloud Automatic Design Based on 性能芯片仿真与验证 UVM-Based Verification in - 臻识科技 Vision-Zenith, and Sensor Processers for 14:00 HPC Design Enablement Using Computing for STA Signoff Allegro Package Designer - IMECAS, Lei Wang Automotive Chip 白震东 Perception and Decision 14:30 5nm Technology and ECO - Analog Device, Steven Xu 高级副总裁 Making in Autonomous Vehicles - GLOBALFOUNDRIES, Cheng - TSMC, Henry Hsieh - Cadence, Marc Swinnen - Cadence, Thomas Wong Zhang

DI03 - A Comprehensive DF03 - Timing and Power SP04 - Overcoming SI/PI SV04 - Formal Practice in CUS04 - AMS Verification TIP04 - Deep Learning AU04 - Complete Electrical- Power Optimization Practice on Convergence on Mega Chip Simulation Challenges of LP4/ CPU Core Verification Using Method for NXP i.MX RT Optimization for Edge AI Device Thermal Co-Simulation for System 14:30 14nm Chips by Using Innovus Using TSO LP4X Interfaces on Mobile JasperGold Formal Verification Product - Skymizer, Samual Liu Designs 15:00 Power Recovery Engine - Avera Semiconductor, Wei Liu Applications Platform - NXP Semiconductor, Angela - Cadence, CT Kao - Avera Semiconductor, - UniSOC, Nikki Xie Liang - 天津飞腾信息技术有限公 Wenxing Jia 司, Hongbo Xue

AU05 - Addressing the State of Safety and Security in Today’s 15:00 Autonomous Vehicles System Tea Break and Designer Expo 15:15 Designs - Green Hills Software, Julia Tang A

15:15 DF04 - A True Signoff Solution DI04 - Interposer Design with CUS05 - Automatic Simulation TIP05 - 语音交互引领下的 Tea Break and Designer Expo 15:30 for Concurrent IR Drop and SP05 - 面对高速高密需求的 SV05 - Palladium and PCIe Innovus Implementation Method for Functional 新计算平台 Timing in Voltus and Tempus 软硬结合板的设计与仿真 Environment System Equivalence Check - 声智科技 SoundAI, Technologies - EDADOC, Bruce Wu/Yali Cui - Cadence, Allen Pan - ZTE/SANECHIPS, Leqi Li - YMTC, Lu Liao 李智勇 副总裁&合伙人 15:30 - Cadence, Jerry Zhao TA01 - AI-改变世界的力量, 15:45 The Power of AI

15:45 - 深聪智能 Smartic, 吴耿源 16:00 联合创始人 DI05 - Low Power Clock Tree SV06 - FSM Deadlock Hunt CUS06 - UMC 28HPC+ Analog/ TIP06 - XANC-芯云融合的新 Buffer and Inverter Reduction DF05 - 设计中电压降分 SP06 - IPI Simulation Efficiency Case Study with JasperGold Mixed-Signal Reference Flow— —代主动降噪技术 in Innovus Implementation 析与优化 Improvement Case Superlint App Cadence Schematic to GDS - 会听声学 HTAcoustics, 16:00 System - Verisilicon, Qing Wang - Ericsson, Xiaoli Zhang - GLOBALFOUNDRIES, - Cadence, Kevin Tsai 虞安波 16:15 - NXP, Glen Ge Jun Shen TA02 - 低功耗语音唤醒方案 - 瑞芯微 Rockchip, 简欢 软件总监

16:15 16:30 DF06 - A Robust Power DI06 - 基于innovus提升芯片 Distribution Design with Early CUS07 - Introducing the TIP07 - 智能音箱的音频信号 SP07 - SerDes Simulation Using SV07 - 浅谈Emulator在多媒 性能的物理实现方法 PSI Analysis in Voltus IP Power Virtuoso RF Solution for RF 后处理及系统优化 IBIS AMI Model 体芯片开发中的应用 Integrity Solution System Design 索那声美 16:30 - 天津飞腾信息技术有限公 - SONA Acoustic, - Teradyne, Gary Wu - Goke, Jiguo Zeng 李文烨 16:45 司, Shaoxian Bian - Avera Semiconductor, - Cadence, Huanyan Liu Hongwei Dai TA03 - Low Latency Audio Streaming and Multi Connection Solution - 欧思数码 Optek, 谷石林 副总裁 16:45 17:00 DI07 - Feedthrough of Very DF07 - InDesign Voltage- SV08 - Simplify PCIe RP SP08 - 高速并行信号过孔间 CUS08 - Using Virtuoso ADE TIP08 - 基于深度学习的新一 Large Scale Integrated Drop Aware Optimization Enumeration Verification 的串扰研究 Verifier in Project Management 代信号处理技术及其应用 Circuit Based on Innovus for Accelerating the Design Using VIP - NXP Semiconductor, Vector and Project Regression - 大象声科 Elevoc, 时晓宽 Implementation System Convergence - Avera Semiconductor, Cheng - Cadence, Bob Lv 产品总监 - ZTE SANECHIPS, Yuebin Xu - NVIDIA, Chuck Chu Fangheng Yu 17:00 17:15 TA04 - Tensilica HiFi DSP for TWS Solutions - Cadence, Jeffrey Xu 17:15 SP09 - Automatic Extraction, Lucky Draw 17:30 EDF08 - Electromigration SV09 - Real Number Modeling CUS09 - Fastest Design DI08 - 基于Innovus平台的 Verification, and Optimization Analysis of FinFET in Flash Memory Fullchip Closure with Accurate Parasitic 云端训练AI芯片设计 of 2D and 2.5D Packages Self-Heating Validation Extraction 17:30 - Enflame, Wade Lu - Avera Semiconductor, - Cambricon, Xiaojun Zhang - Cadence, Hitendra Divecha Lucky Draw 17:45 Tianhong Lan - YMTC, Lin Zhou

17:45 Lucky Draw Lucky Draw Lucky Draw Lucky Draw 18:00 DI09 - AI in P&R, Mixplacer Introduction 18:00 - Broadcom, Necle Zhao 18:15

18:15 Lucky Draw 18:30

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