CUPL TOTAL DESIGNER FPGA/PLD DESIGN SOFTWARE

CUPL is a complete Logic Design Environment. The main core is a language compiler similar to "C", VHDL or , optimised for PLD and FPGA designs. CUPL outputs file formats needed by device programmers to program the PLD or FPGA devices. In addition to the compiler section CUPL also includes synthesis, simulation, partitioning, technology mapping and design rule checking. CUPL is the "Universal Software Tool" used by design Engineers to create PLD and FPGA designs.

CUPL Total designer includes:

· Schematic / Logic Capture Design Entry (OnCUPL) · Graphical Truth Table · Graphical State Machine Design Entry · New 32-bit Compiler for faster and more powerful design entry · HDL editor with full syntax checking · Graphical Waveform Simulation input and output · Automatic Device Partitioning CUPL is generally used by digital design · Project navigator engineers to integrate glue · Optional VHDL Compiler logic in a programmable device. With · Direct EDIF, PLA, XNF, QDIF, PLD prices now below standard AHDL output formats logic for equivalent functionality it makes · Import Orcad, Viewlogic, Protel, economic sense to replace Accel, PADs etc schematic net lists most discrete logic with PLDs. CUPL is · Includes nine FREE fitters used by over 30,000 design engineers · Software provided on CD-ROM and today to aid with the design and comes complete with full manual set debugging of logic equations · Supports , AMD, , ICT, and the realisation of the design into , NATIONAL, PHILIPS and actual programmable devices. (FPGAs, PALs, GALs, FPLAs and PROMs)

WHY USE CUPL languages such as VHDL, Verilog, ABEL, PALASM, etc. This Most manufacturers of programmable ICs will allow you to get the best PLD/FPGA will offer some form of software optimisation by running your design design tool for their proprietary device through the industries most proven architecture. The software is often given programmable logic tool, CUPL free or at special prices as in incentive to design with their parts. For obvious EXPORT TO OTHER TOOLS reasons these tools are not fully compatible with other programmable CUPL outputs various design formats to logic devices made by their competitors. provide seamless integration with Often the customer realises this fact after other software tools such as technology heavy investment of source code using mappers, routers, simulators, and the proprietary tool. CUPL is a universal graphical entry tools, making CUPL a language and attempts to provide valuable general purpose logic design seamless migration to any manufacturer productivity tool. CUPL currently of PLD and FPGA exports PLA, QDIF, AHDL, EDIF, and without any time penalty. Using CUPL will soon include VHDL and Verilog will prevent you from getting with subsequent software releases. locked to a specific device manufacturer. EASY TO LEARN LANGUAGE! USE YOUR FAVORITE HAVE YOUR FIRST PLD DESIGN SCHEMATIC CAPTURE ON YOUR BOSSES DESK IN LESS SOFTWARE THAN 24 HOURS

Even though CUPL HDL is the best form CUPL is a powerful, yet simple of creating logic designs, language. It deals with PLD design in a sometimes it is more convenient to use very straightforward manner. graphical tools for creating glue Programming languages such as VHDL, logic designs. In this case CUPL can were created to model and simulate take the output from your schematic complex environments. VHDL has been capture software and automatically create used to model the forces in the Universe CUPL source code. to show the instability of our Solar System. The CUPL language is not that IMPORT FROM OTHER HDL broad, and therefore is easier to learn. TOOLS CUPL shields the user from specifying devices architectural details that is If your designs are already in a different otherwise required to specify by other HDL, CUPL can import from a variety of general purpose HDLs.

Support and Updates Other Logical Products Available via Kanda Systems: All Kanda System products come complete with: · Device Programmers · Free Telephone, Fax and Email Technical Support · 90 Days warranty after purchase · Extensive Documentation, including a step-by-step tutorial CUPL Requires: Contact Information:

PC: Minimum Pentium, with Windows 95 UK or Windows NT with at least 16MB Kanda Systems Ltd. memory (32 MB for Windows NT). Hard Unit 17, Glanyrafon Enterprise Park, disk 35 Meg and a CD-ROM reader. VGA Aberystwyth, graphics required. Ceredigion, SY23 3JQ.

Tel: (+44) (0)1970 621030 (sales) (+44) (0)1970 621041 (support)

Fax: (+44) (0)1970 621040

Email: [email protected] [email protected]

Website: www.kanda-systems.com

Other CUPL software packages:

Starter Kit PALexpert ST-CUPL PLDmaster Total CUPL/IST MacCUPL Designer Device 9 Basic PAL 75 popular 4 GAL Over 240 Over 275 Over 250 Over 240 PAL, devices16V8, PAL,GAL, PROM devices PAL,GAL, FPGA, PAL, FPGA, PAL, GAL, FPLA, 16R4/6/8, architectures 16V8, 20V8, PROM GAL, FPLA, GAL, FPLA, PROMs 20L10 22V10 PROM. PROM Hardware DOS/WIN DOS/WIN DOS DOS/WIN3.1/ DOS/ WIN3.1/ SUN SPARC MAC OS Platform WIN96 & WIN WIN95 & WIN stations based NT NT computers Output files JEDEC, JEDEC, HEX, JEDEC, JEDEC, HEX, JEDEC, HEX, JEDEC, HEX, JEDEC, HEX, document document HEX, HL, HL, PLA, HL, EDIF, HL, XNF, HL, PLA, PLA, PDIF, PDIF, EDIF, PDIF, OPENPLA, PDIF, EDIF, EDIF, PALASM, PALASM, PDIF, EDIF, PALASM, PALASM, document document PALSM, document document document Unit delay N o Yes Yes Yes Yes Yes Yes Simulation Complex PLD No No No No Altera, AMD, Altera, AMD, No Fitters Atmel, ICT, Atmel, Intel, National, National, Xilinx Philips, Xilinx (FPGA) Device No Yes Yes Yes Yes Yes Yes Independent Design FINDPLD No No Yes Yes Not Needed Not Needed No (single device (part of (part of fitter) PLDpartition) PLDpartition) PLPartition N/A Optional Included Optional Included Included N/A (Multiple PLD Design tool) Graphical Optional Optional Included Optional Included Included Included Entry Tools (ONCUPL & (ONCUPL & (ONCUPL & (ONCUPL for Schem- Schem-Quik, Schem-Quik, McCAD) Quik, other other ONCUPL other ONCUPL ONCUPL interfaces interfaces interfaces available) available) available)