Investigation of Architectures for Wireless Visual Sensor Nodes

Total Page:16

File Type:pdf, Size:1020Kb

Investigation of Architectures for Wireless Visual Sensor Nodes Thesis work for the degree of Licentiate of Technology Sundsvall 2011 Investigation of Architectures for Wireless Visual Sensor Nodes Muhammad Imran Supervisors: Professor Mattias O’Nils Professor Bengt Oelmann Dr. Najeem Lawal Electronics Design Division, in the Department of Information Technology and Media Mid Sweden University, SE-851 70 Sundsvall, Sweden ISSN 1652-8948 Mid Sweden University Licentiate Thesis 66 ISBN 978-91-86694-45-6 Akademisk avhandling som med tillstånd av Mittuniversitetet i Sundsvall framläggs till offentlig granskning för avläggande av teknologie Licentiate examen i elektronik onsdagen den 10 Juni 2011, klockan 10:30 i sal O102, Mittuniversitetet Sundsvall. Seminariet kommer att hållas på engelska. Investigation of Architectures for Wireless Visual Sensor Nodes Muhammad Imran © Muhammad Imran, 2011 Electronics Design Division, in the Department of Information Technology and Media Mid Sweden University, SE-851 70 Sundsvall Sweden Telephone: +46 (0)60 148561 Printed by Kopieringen Mittuniversitetet, Sundsvall, Sweden, 2011 ABSTRACT Wireless visual sensor network is an emerging field which has proved useful in many applications, including industrial control and monitoring, surveillance, environmental monitoring, personal care and the virtual world. Traditional imaging systems used a wired link, centralized network, high processing capabilities, unlimited storage and power source. In many applications, the wired solution results in high installation and maintenance costs. However, a wireless solution is the preferred choice as it offers less maintenance, infrastructure costs and greater scalability. The technological developments in image sensors, wireless communication and processing platforms have paved the way for smart camera networks usually referred to as Wireless Visual Sensor Networks (WVSNs). WVSNs consist of a number of Visual Sensor Nodes (VSNs) deployed over a large geographical area. The smart cameras can perform complex vision tasks using limited resources such as batteries or alternative energy sources, embedded platforms, a wireless link and a small memory. Current research in WVSNs is focused on reducing the energy consumption of the node so as to maximise the life of the VSN. To meet this challenge, different software and hardware solutions are presented in the literature for the implementation of VSNs. The focus in this thesis is on the exploration of energy efficient reconfigurable architectures for VSNs by partitioning vision tasks on software, hardware platforms and locality. For any application, some of the vision tasks can be performed on the sensor node after which data is sent over the wireless link to the server where the remaining vision tasks are performed. Similarly, at the VSN, vision tasks can be partitioned on software and the hardware platforms. In the thesis, all possible strategies are explored, by partitioning vision tasks on the sensor node and on the server. The energy consumption of the sensor node is evaluated for different strategies on software platform. It is observed that performing some of the vision tasks on the sensor node and sending compressed images to the server where the remaining vision tasks are performed, will have lower energy consumption. In order to achieve better performance and low power consumption, Field Programmable Gate Arrays (FPGAs) are introduced for the implementation of the sensor node. The strategies with reasonable design times and costs are implemented on hardware-software platform. Based on the implementation of the VSN on the FPGA together with micro-controller, the lifetime of the VSN is predicted using the measured energy values of the platforms for different processing strategies. The implementation results prove our analysis that a VSN with such characteristics will result in a longer life time. iii ACKNOWLEDGEMENTS First of all I am thankful to the Allah Almighty, the most merciful for giving me the strength and perseverance during this work and for blessing me with many great people who have been the greatest support in both my personal and professional life. I would, in particular, express my deepest regards and gratitude to my supervisor Prof. Mattias O’Nils for his guidance, support and encouragement throughout this work. Without his constant guidance and support this work would not have been possible. Every meeting with him gave me a new inspiration for work. I am thankful to Dr. Najeem Lawal for his support and motivation during this work. I would also like to thank Fanny Burman and Christine Grafström for the administrative support and Magnus Ödling for the IT support. Further, I am thankful to my friends and colleagues Khursheed Khursheed, Naeem Ahmad, Abdul Waheed Malik, Khurram Shahzad, Abdul Majid, Jawad Saleem, Dr. Benny Thörnberg, Suliman Abdalla, Mohammad Anzar Alam, Cheng Peng, Kotte Hari Babu, Radhika Ambatipudi, Muhammad Amir Yousaf, Mazhar Hussain, Xiaozhou Meng, Mikael Bylund, David Krapohl, Sebastian Bader and all the colleagues in the department for their discussions and cooperation. I would also like to express my gratitude to Mid Sweden University (miun), Higher Education Commission (HEC) Pakistan, Swedish Institute (SI) and Knowledge Foundation (KK) for their financial and administrative support. I am thankful to my sisters and brothers for all the blessing and prayers. Moreover, I humbly thank my parents and teachers for motivating me and giving me the inspiration for higher education. Finally, I am thankful to my wife Farri and my lovely daughter Aleena Imran who have been a constant source of support and strength during this work. Sundsvall, May 2011 Muhammad Imran v TABLE OF CONTENTS ABSTRACT..............................................................................................................III ACKNOWLEDGEMENTS.........................................................................................V TABLE OF CONTENTS .........................................................................................VII ABBREVIATIONS AND ACRONYMS ....................................................................XI LIST OF FIGURES ................................................................................................XIII LIST OF TABLES .................................................................................................. XV 1 INTRODUCTION ...............................................................................................1 1.1 APPLICATION OF WIRELESS VISION SENSOR NETWORKS ................................. 2 1.1.1 Industrial control and monitoring ....................................................... 2 1.1.2 Surveillance....................................................................................... 2 1.1.3 Environmental monitoring ................................................................. 3 1.1.4 Personal care .................................................................................... 3 1.1.5 Virtual Reality .................................................................................... 3 1.2 PROCESSING PLATFORMS............................................................................. 4 1.2.1 Hardware platforms........................................................................... 4 1.2.2 Software platforms ............................................................................ 5 1.2.3 Comparison of ASICs and Programmable Devices .......................... 6 1.3 PROBLEM DESCRIPTION................................................................................ 7 1.4 MAIN CONTRIBUTIONS.................................................................................. 8 1.5 THESIS OUTLINE .......................................................................................... 9 2 WIRELESS VISUAL SENSOR NETWORKS .................................................11 2.1 CHARACTERISTIC OF WIRELESS VISUAL SENSOR NETWORKS ........................ 12 2.1.1 Energy, bandwidth and processing requirements........................... 12 2.1.2 Data storage requirement ............................................................... 12 2.1.3 Delay requirement........................................................................... 13 2.1.4 Self-configuration ............................................................................ 13 2.1.5 Scalability ........................................................................................ 13 2.2 WIRELESS VISUAL SENSOR NODE............................................................... 13 2.3 TYPE OF WIRELESS VISUAL SENSOR NETWORKS .......................................... 14 2.3.1 Homogenous Visual sensor network............................................... 14 2.3.2 Heterogeneous visual sensor network ............................................ 14 2.4 PROCESSING IN THE WIRELESS VISUAL SENSOR NETWORK .......................... 16 2.4.1 Centralized smart camera network ................................................. 16 2.4.2 Distributed smart camera network .................................................. 17 3 ARCHITECTURES FOR VISUAL SENSOR NODES.....................................21 3.1 VISUAL SENSOR NODE ON SOFTWARE PLATFORM........................................ 21 3.1.1 Light-weight camera........................................................................ 21 vii 3.1.2 SensEye ..........................................................................................21 3.1.3 Stanford’s MeshEye ........................................................................22
Recommended publications
  • Energy Efficient and Programmable Architecture for Wireless Vision Sensor Node
    Thesis work for the degree of Doctor of Technology Sundsvall 2013 Energy Efficient and Programmable Architecture for Wireless Vision Sensor Node Muhammad Imran Supervisors: Prof. Mattias O’Nils Dr. Najeem Lawal Prof. Bengt Oelmann Faculty of Science, Technology and Media, Mid Sweden University, SE-851 70 Sundsvall, Sweden ISSN 1652-893X Mid Sweden University Doctoral Thesis 167 ISBN 978-91-87557-12-5 Akademisk avhandling som med tillstånd av Mittuniversitetet i Sundsvall framläggs till offentlig granskning för avläggande av teknologie doktors examen i elektronik tisdagden 22 October 2013, klockan 13:15 i sal M108, Mittuniversitetet Sundsvall. Seminariet kommer att hållas på engelska. Energy Efficient and Programmable Architecture for Wireless Vision Sensor Node Muhammad Imran © Muhammad Imran, 2013 Faculty of Science, Technology and Media Mid Sweden University, SE-851 70 Sundsvall Sweden Telephone: +46 (0)60 148561 Printed by Kopieringen Mittuniversitetet, Sundsvall, Sweden, 2013 ABSTRACT Wireless Vision Sensor Networks (WVSNs) is an emerging field which has attracted a number of potential applications because of smaller per node cost, ease of deployment, scalability and low power stand alone solutions. WVSNs consist of a number of wireless Vision Sensor Nodes (VSNs). VSN has limited resources such as embedded processing platform, power supply, wireless radio and memory. In the presence of these limited resources, a VSN is expected to perform complex vision tasks for a long duration of time without battery replacement/recharging. Currently, reduction of processing and communication energy consumptions have been major challenges for battery operated VSNs. Another challenge is to propose generic solutions for a VSN so as to make these solutions suitable for a number of applications.
    [Show full text]
  • VLSI Architectures for Digital Signal Processing on Energy-Constrained Systems-On-Chip
    VLSI Architectures for Digital Signal Processing on Energy-Constrained Systems-on-Chip A Dissertation Presented to the Faculty of the School of Engineering and Applied Science University of Virginia In Partial Fulfillment of the requirements for the Degree Doctor of Philosophy (Electrical and Computer Engineering) by Alicia Klinefelter August 2015 c 2015 Alicia Klinefelter Abstract The design of ultra-low power (ULP) integrated circuits for Systems-On-Chip (SoCs) requires consideration of both flexibility and robustness during low-energy operation. Due to their quadratic relationship, the strongest design knob for reducing energy on-chip is the supply voltage. By operating digital circuits in the subthreshold region, using a supply voltage that falls below the threshold of the device, designers can minimize energy per operation at the cost of a performance penalty. However, there are many applications with low throughput requirements that can benefit from these energy savings. For example, systems that process biomedical data such as ECG, EEG, and EMG require sampling and processing rates on the order of kHz, making subthreshold operation feasible. The result of these substantial energy improvements is an emerging application space for these ULP SoCs in batteryless sensor nodes capable of running on energy harvested from the surrounding environment alone. This work presents two versions of a highly integrated, flexible SoC platform targeted for Internet-of-Things (IoT) applications. These SoCs support multiple sensing modalities, extract information from data flexibly across applications, harvest and deliver power efficiently, and communicate wirelessly. The first version of the chip acquired ECG data, extracted the heart-rate, and transmitted the raw signal operating off of harvested energy while consuming 19µW.
    [Show full text]
  • (2009 A-SSCC).Indd
    7-2 IEEE Asian Solid-State Circuits Conference November 16-18, 2009 / Taipei, Taiwan CRISP-DS: Dual-Stream Coarse-grained Reconfigurable Image Stream Processor for HD Digital Camcorders and Digital Still Cameras Tsung-Huang Chen, Jason C. Chen, Teng-Yuan Cheng, and Shao-Yi Chien Media IC and System Lab Graduate Institute of Electronics Engineering and Department of Electrical Engineering National Taiwan University BL-421, 1, Sec. 4, Roosevelt Rd., Taipei 106, Taiwan Abstract— A 329mW 600M-Pixels/s dual-stream coarse- In this paper, a dual-stream coarse-grained reconfigurable grained reconfigurable image stream processor is implemented in image stream processor (CRISP-DS) is designed to support μm 2 TSMC 0.13 CMOS technology with a core size of 4.84mm . HD image processing with high power efficiency. It is charac- The reconfigurable pipelined processing element array architec- ture makes a good balance between computing performance and terized as follows. First, the reconfigurable pipelined process- flexibility with only 10Kb on-chip memory. Moreover, a new dual- ing element (PE) array architecture can provide a good balance stream architecture is proposed to improve the flexibility and between computing performance and flexibility with low on- hardware efficiency by processing two independent image streams chip memory cost. Second, the new concept of dual-stream with two-layer context switching, and an isolation technique is processing is introduced to improve both the performance and also proposed to improve the power consumption. Implementa- tion results show that it achieves 1.52 times power efficiency than flexibility. With PE isolation technique, CRISP-DS can achieve previous works and can meet the requirements of high-definition better power efficiency than previous works.
    [Show full text]
  • Energy-Efficient Foreground Object Detection on Embedded Smart
    University of Nebraska - Lincoln DigitalCommons@University of Nebraska - Lincoln Faculty Publications from the Department of Electrical & Computer Engineering, Department Electrical and Computer Engineering of 2011 Energy-efficientor F eground Object Detection on Embedded Smart Cameras by Hardware-level Operations Mauricio Casares University of Nebraska-Lincoln, [email protected] Paolo Santinelli University of Modena, [email protected] Senem Velipasalar University of Nebraska-Lincoln, [email protected] Andrea Prati University of Modena, [email protected] Rita Cucchiara University of Modena and Reggio Emilia Follow this and additional works at: https://digitalcommons.unl.edu/electricalengineeringfacpub Part of the Electrical and Computer Engineering Commons Casares, Mauricio; Santinelli, Paolo; Velipasalar, Senem; Prati, Andrea; and Cucchiara, Rita, "Energy- efficientor F eground Object Detection on Embedded Smart Cameras by Hardware-level Operations" (2011). Faculty Publications from the Department of Electrical and Computer Engineering. 202. https://digitalcommons.unl.edu/electricalengineeringfacpub/202 This Article is brought to you for free and open access by the Electrical & Computer Engineering, Department of at DigitalCommons@University of Nebraska - Lincoln. It has been accepted for inclusion in Faculty Publications from the Department of Electrical and Computer Engineering by an authorized administrator of DigitalCommons@University of Nebraska - Lincoln. IEEE Computer Society Conference on Computer
    [Show full text]
  • Design of an FPGA-Based Smart Camera and Its Application Towards Object Tracking
    Copyright is owned by the Author of the thesis. Permission is given for a copy to be downloaded by an individual for the purpose of research and private study only. The thesis may not be reproduced elsewhere without the permission of the Author. Design of an FPGA-Based Smart Camera and its Application Towards Object Tracking A thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Electronics and Computer Engineering at Massey University, Manawatu, New Zealand Miguel Contreras 2016 Abstract Smart cameras and hardware image processing are not new concepts, yet despite the fact both have existed several decades, not much literature has been presented on the design and development process of hardware based smart cameras. This thesis will examine and demonstrate the principles needed to develop a smart camera on hardware, based on the experiences from developing an FPGA-based smart camera. The smart camera is applied on a Terasic DE0 FPGA development board, using Terasic’s 5 megapixel GPIO camera. The algorithm operates at 120 frames per second at a resolution of 640x480 by utilising a modular streaming approach. Two case studies will be explored in order to demonstrate the development techniques established in this thesis. The first case study will develop the global vision system for a robot soccer implementation. The algorithm will identify and calculate the positions and orientations of each robot and the ball. Like many robot soccer implementations each robot has colour patches on top to identify each robot and aid finding its orientation. The ball is comprised of a single solid colour that is completely distinct from the colour patches.
    [Show full text]
  • CMOS-3D Smart Imager Architectures for Feature Detection M
    IEEE JETCAS-SPECIAL ISSUE ON HETEROGENEOUS NANO-CIRCUTS AND SYSTEMS 1 CMOS-3D Smart Imager Architectures for Feature Detection M. Suarez,´ V.M. Brea, J. Fernandez-Berni,´ R. Carmona-Galan,´ G. Lin˜an,´ D. Cabello and A. Rodr´ıguez-Vazquez´ Fellow, IEEE, Abstract—This paper reports a multi-layered smart image dominate the market of area imagers, with more than 90% of sensor architecture for feature extraction based on detection the total share [10]. of interest points. The architecture is conceived for 3D IC The most important asset of CISs is the incorporation of technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to intelligence on-chip [1]. Different levels of intelligence can be perform Gaussian filtering and generate Gaussian pyramids in contemplated. The lowest involves basically readout, control fully concurrent way. The circuitry in this tier operates in mixed- and error correction, and is the only one yet exploited by signal domain. It embeds in-pixel Correlated Double Sampling industry [11], [12]. Higher intelligence levels, as required to (CDS), a switched-capacitor network for Gaussian pyramid analyzing, extracting and interpreting the information con- generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split tained into images have been explored for years at academia into two for improved resolution; one containing the sensors and [13] - [25], but with scarce industrial impact [11]. From now another containing a capacitor per sensor plus the mixed-signal on we will refer to CISs with high-level intelligence attributes processing circuitry.
    [Show full text]