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Local Search for Final Placement in VLSI Design

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Local Search for Final Placement in VLSI Design Local Search for Final Placement in VLSI Design Oluf Faroe, David Pisinger, and Martin Zachariasen Dept. of Computer Science, University of Copenhagen, DK-2100 Copenhagen Ø, Denmark. oluf,pisinger,martinz ¡ @diku.dk Abstract the general nature of the method proposed in this paper makes it easy to incorporate additional or alternative objectives. A new heuristic is presented for the general cell placement We present a new iterative placement algorithm which is problem where the objective is to minimize total bounding box well-suited for solving the final (or detailed) placement prob- netlength. The heuristic is based on the Guided Local Search lem. The algorithm both takes the packing problem, i.e. plac- (GLS) metaheuristic. GLS modifies the objective function in a ing the modules disjointly, and the total bounding box (BB) constructive way to escape local minima. Previous attempts to netlength into account. The algorithm uses the Guided Local use local search on final (or detailed) placement problems have Search (GLS) metaheuristic [18, 19] for controlling the search. often failed as the neighborhood quickly becomes too exces- The neighborhood structure is simple: Flipping and/or moving sive for large circuits. Nevertheless, by combining GLS with a single module along one of the coordinate axes. This neigh- Fast Local Search it is possible to focus the search on appro- borhood has previously been used by [6, 10, 11, 12, 14, 21], in priate sub-neighborhoods, thus reducing the time complexity particular in conjunction with simulated annealing. The weak- considerably. ness of all these algorithms is the slow convergence towards Comprehensive computational experiments with the devel- good solutions — which is an inherent feature of simulated an- oped algorithm are reported on small, medium and large in- nealing. By combining GLS with the Fast Local Search (FLS) dustrial circuits, and for standard cell and general cell variants approach [18, 19], an algorithm that both finds good solutions of the problem. The experiments demonstrate that the devel- quickly and in the long run converges towards high-quality so- oped algorithm is able to improve the estimated routing length lutions is obtained. of large-sized general cell layouts with as much as 20 percent. In addition to its applicability as a final placement algo- The general nature of the proposed method makes it easy rithm, the new heuristic can be used in the following setting. to incorporate other goals, such as routability and timing con- Current layout algorithms use a feedback approach in which straints, into the objective function. Current layout algorithms a placement is evaluated by performing (partial) routing and use a feedback approach in which a placement is evaluated timing analysis; the output of this analysis is then used to con- by performing (partial) routing and timing analysis; the output struct an improved placement. This iterative nature of the de- of this analysis is then used to construct an improved place- sign process calls for placement algorithms that take an exist- ment. This iterative nature of the design process calls for ing placement and construct an improved placement that re- placement algorithms that take an existing placement and con- sembles the original one, but in which the information from struct an improved placement that resembles the original one, the routing/timing analysis is taken into account. but in which the information from the routing/timing analysis Finally, the new algorithm can be used to construct high- is taken into account. quality placements of small general cell circuits. This is known to be a very difficult problem in practice, and our ex- 1 Introduction perimental results show that the new algorithm on average pro- duces significantly better solutions than existing algorithms The placement problem in VLSI design is the first phase in from the literature. For some instances the total netlength is the process of designing the physical layout of a chip. This reduced by more than 20 percent when compared to the recent makes the placement problem of paramount importance, since results for the O-Tree algorithm [5]. the quality of the attainable routing is to a high degree de- The paper is organized as follows. In Section 2 we define termined by the placement. In the placement problem we are the placement problem. In Sections 3 and 4 we present the given a set of rectangular modules (or cells/circuits/macros) of details of applying GLS and FLS, respectively, to the place- different height and width that should be placed disjointly on ment problem. Extensive computational results are presented the chip surface. Every module has a number of connection in Section 5, and concluding remarks are given in Section 6. points, so-called pins, and the netlist is a partitioning of the pins into nets that should be interconnected. The problem is to place the modules such that an objec- 2 The Placement Problem tive function that reflects the quality of the placement is mini- mized. Most objective functions in placement add up the con- The placement problem asks to assign locations to the modules tribution from each net separately, with the overall objective of a circuit such that these are within the available placement of minimizing total wiring length after routing. Clearly, such area and do not overlap. We assume that modules may have an objective function has the weakness of not taking timing is- arbitrary rectangular dimensions, thus the considered layout sues explicitly into account, since minimizing total length may style is general cell layout. The objective of the problem is to leave critical nets having a significant signal delay. However, minimize the total length of the nets connecting the modules. d3¡ To be more formal, a circuit is defined by the tuple initial solution d ¡ ¥ © ¢¡¤£¦¥¨§ © § § where is the placement area, best best solution is the set of modules, is the set of pins, and is the while stopping condition not satisfied do hi£¦dc netlist defining which pins should be connected. We will as- dfgR¡ LOCALOPT sume that the placement area is defined as the integer grid if bc£¦dfgVjkbc£¦d best then g d ¡kd %'&(© ¥¡§§ ¨ §!§ "#$ For each module best the corresponding (integer) width is )+* and (integer) height is end if , , £¦-.*/§ 01*2 * . Moreover let denote the (integer) coordinates penalize and modify g d=¡9d of the lower left corner of the module in the placement area ¥ . % In order to not exceed ¥ the coordinates of module must end while , d * * * * - &34§!§576) 0 &84§!§ "96 satisfy and . return best For technical reasons, some of the modules may be fixed at a given position. In this case the module coordinates £¦-:*/§ 01*2 Figure 1: Outline of Guided Local Search (GLS). may not be changed. If some part of the circuit area ¥ is not available for the modules, this space may be represented by one or more fixed modules which do not have any pins. a solution dl& . The use of GLS for placement was moti- Depending on the restrictions from the layout style and the vated by recent results on packing problems in two and three fabrication technology, modules may be allowed to change ori- dimensions [3]. a entation. In the present definition we will allow modules to be [ & Given an initial solution d , local search vis- Z rotated in steps of 90 degrees and to be reflected around the [ § d §!§ dfm donT& its a sequence of solutions d such that - 0 - and -axis. This gives eight different orientations of each Z n¦q r¨¡ts1§vu$§§ w p£¦d for . When the series of solutions Z [ Z module. To make the following discussion simpler, we will [ § d §!§ dfm bc£¦d pxybc£¦d pxz!{x|bc£¦dcm1 d fulfills not mention the orientations explicitly, although they should the process is denoted local optimization. Local optimization be taken into account in all definitions and algorithms. stops when the current solution dfm is a local minimum, that is, Each pin ;<& has a relative position within its module dfm when e£¦dcm} contains no solution better than . Applying ; % % . This is denoted the offset of the pin in . The netlist local optimization to a solution using the objective function b is defined as a partitioning of the pins , such that every pin will be denoted by the operator LOCALOPT ~ . In the above ;=&> ?@&A is part of exactly one net . [ dfm2¡ £¦d case we have LOCALOPT ~ . B ? For a given placement we let CDFE denote the set of P GLS extends local search with the concept of features, i.e., £? pin coordinates corresponding to net ? &¨ , and BB be P a set of attributes which characterize a solution to the problem the bounding box netlength for the set ? . In order to make P in a natural way. GLS assumes that any solution can be de- it possible to differentiate between how much the individual a d{& scribed using a set of features, that is, a solution ei- nets should contribute to the objective function, a net weight ther has or does not have a particular feature r&#$s}§§ e . )/£?3 function )GHJILK+MN assigns some weight to each d r The indicator function n £¦df is 1 if has feature and 0 oth- net ?¢& . We can now formulate the min-sum placement erwise. Features should be defined such that the presence of problem as: a feature in a solution has a more or less direct contribution to the value of the objective function. This direct or indirect Placement Problem: For a given circuit find a placement contribution is reflected in the cost n of the feature. A feature O9PRQST)/£?3VU £? B which minimizes the objective BB P for with a high cost is not attractive and may be penalized.
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