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Single Bit Radar Systems for Digital Integration

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Single Bit Radar Systems for Digital Integration Single Bit Radar Systems for Digital Integration Øystein Bjørndal Department of Informatics University of Oslo (UiO) & Norwegian Defence Research Establishment (FFI) September 2013 – September 2017 Thesis submitted for the degree of Philosophiae Doctor 1Copyright ©2017 All content not marked otherwise is freely available under a Creative Commons Attribution 4.0 International License cb https://creativecommons.org/licenses/by/4.0/ Abstract Small, low cost, radar systems have exciting applications in monitoring and imaging for the industrial, healthcare and Internet of Things (IoT) sectors. We here explore, and show the feasibility of, several single bit square wave radar architectures; that benefits from the continuous improvement in dig- ital technologies for system-on-chip digital integration. By analysis, sim- ulation and measurements we explore novel and harmonic-rich continuous wave (CW), stepped-frequency CW (SFCW) and frequency-modulated CW (FMCW) architectures, where harmonics can not only be suppressed but even utilized for improvements in down-range resolution without increasing on air- bandwidth. In addition, due to the flexible digital CMOS implementation, the system is proved by measurement, to feasibly implement pseudo-random noise-sequence and pulsed radars, simply by swapping out the digital base- band processing. Single bit quantization is explored in detail, showing the benefits of simple implementation, the feasibility of continuous time design and only slightly degraded signal quality in noisy environments compared to an idealized analog system. Several iterations of a proof-of-concept 90 nm CMOS chip is developed, achieving a time resolution of 65 ps at nominal 1.2 V supply with a novel Digital-to-Time converter architecture. In pulsed mode, the chip features programmable pulses with a minimum width of 130 ps and a time step of 65 ps. In CW mode, we can transmit arbitrary signals up to 3.8 GHz all the way down to DC. With a continuous time single bit receiver, the backscat- tered signal can be mixed with the on-chip XOR gate and integrated with the on-chip counters, to provide a system-on-chip CW platform. iii Acknowledgments I am really grateful to everyone who has collaborated, motivated and sup- ported me throughout this work. In particular, my supervisors Svein-Erik Hamran from FFI and Tor Sverre Lande (Bassen) from UiO; whose insight not only in their respective fields but also cross-discipline, goes without say- ing, has been invaluable. Thank you to Svein-Erik for always having an open door, your motivation, guidance and realistic goals have helped me grow as a researcher. Thanks to Bassen for pushing boundaries and scrutinizing my suggestions, both the long and short conversations, in-person and by email; has not only been motivating but also enlightening. My colleagues both at FFI (Norwegian Defence Research Establishment) and at the Nanoelectronics group at UiO (University of Oslo) for your sup- port, insight and lunch breaks: Tor Berger, Sverre Brovoll, Leif Damsgård and Mats Jørgen Øyan from FFI and Philipp Häfliger, Yngvar Berg, Joar Martin Østby, Kristian Gjertsen Kjelgård, Olav Stanly Kyrvestad, Mathias Tømmer, Jon Håvard Eriksrød, Tohid Moradi Khanshan, Amir Hasanbegovic and Sohail Musa Mahmood from UiO. Especially Kristian and Olav, with- out whom this thesis would be purely theoretical, for your assistance and support with chip tapeout, circuit board design, fabrication, lab setup and debugging. I would like to acknowledge some of the previous PhD students work- ing on the swept threshold principle and implementation for pulsed radar: Håkon Andre Hjortland, Malihe Zarre Dooghabadi, Shanthi Sudalaiyandi and Nguyen Thanh Trung whose circuit blocks have all been vital for the chip prototype in this work. In particular, to Håkon, for paving the way with the swept threshold principle and for your invaluable and insightful comments. I am also grateful to Novelda for the comparator. Financial support from FFI from September 2013 through December 2016 and UiO from January 2017 through June 2017 is gratefully acknowledged. Lastly to the love of my life, Ine, thank you for your patience and under- standing and to my family for your support and encouragement. v Contents I Thesis 1 1 The first chapter 1 1.1 Introduction to the proposed radar . 4 1.1.1 Analog radar . 4 1.1.2 Digital transmitter . 6 1.1.3 Digital transmitter and receiver . 8 1.1.4 Proposed radar solution . 8 1.1.5 Beneficial harmonics . 11 1.1.6 Summary . 12 1.2 Applications . 13 2 Background 15 2.1 Radar architecture fundamentals . 15 2.1.1 Pulsed time-of-flight radar . 17 2.1.2 Continuous-Wave (CW) Radar . 18 2.1.3 Stepped-Frequency Continuous-Wave (SFCW) . 22 2.1.4 Frequency-Modulated Continuous-Wave (FMCW) . 26 2.1.5 Correlator based radar . 28 2.2 Swept threshold . 35 2.2.1 A single quantizer . 36 2.2.2 Multiple quantizers . 39 3 System perspective 51 3.1 Time resolution . 52 3.1.1 Continuous time . 54 3.1.2 Discrete time . 56 3.2 Thermal noise . 60 3.2.1 Intentional dithering . 62 vii CONTENTS 3.3 Moving targets . 65 3.3.1 Tracking . 65 3.3.2 Comparing frames in time . 67 3.3.3 Doppler shift . 70 3.3.4 Summarizing moving targets . 76 4 Implementation 79 4.1 System overview . 79 4.1.1 SPI configuration . 83 4.1.2 Transmitter . 83 4.1.3 Receiver . 88 4.2 Design flow . 92 4.2.1 Analog design . 93 4.2.2 Testbenches . 94 4.3 Concluding implementation . 97 5 Baseband 99 5.1 Analog filter and ADC baseband path. 99 5.1.1 Double swept threshold baseband . 103 5.2 Cascaded Integrator-Comb filters . 109 5.3 Fourier and Walsh transform of square wave signals . 112 5.3.1 Implementation, XOR as a multiplication circuit. 117 5.3.2 Utilizing Walsh in a square wave radar . 117 5.3.3 Walsh and m-sequence . 121 5.4 N-path filter bank . 121 5.4.1 Relationship to a superheterodyne receiver . 125 5.5 From autocorrelation to Fourier domain . 127 5.6 Concluding baseband . 131 6 The last chapter 133 6.1 Summary of thesis and published papers . 133 6.2 Discussion and limitations of this work . 136 6.3 Future work . 138 6.4 Conclusion . 139 viii CONTENTS II Publications included in the thesis 141 A Paper I 143 A.1 Introduction . 145 A.2 Quantization in amplitude and time . 147 A.3 Fabricted chip . 148 A.4 Measurement results . 152 A.5 System simulation . 154 A.6 Conclusion . 155 B Paper II 159 B.1 Introduction . 161 B.2 Dealing with harmonics . 163 B.2.1 Moving out of band . 163 B.2.2 Resolving in band ambiguity . 165 B.3 Post layout XOR simulation . 167 B.4 Stepped Frequency Continuous Wave (SFCW) . 167 B.5 Correlation based radar . 171 B.6 Conclusion . 172 C Paper III 175 C.1 Introduction . 177 C.2 Analytical mixing of frequency modulated waveforms . 180 C.2.1 Analytical FMCW . 181 C.2.2 Analytical CW/SFCW . 184 C.3 Dealing with harmonics . 186 C.3.1 Moving out of band . 186 C.3.2 Resolving in band ambiguity . 187 C.4 Stepped Frequency Continuous Wave (SFCW) . 191 C.5 Correlation based radar . 194 C.6 Unmodulated pulsed radar . 195 C.7 Measurements . 197 C.7.1 FMCW linearity correction . 199 C.7.2 XOR gate as a digital mixer . 200 C.7.3 Full system measurements . 200 C.8 Discussion . 203 C.9 Conclusion . 204 ix CONTENTS D Paper IV 209 D.1 Introduction . 211 D.2 WP as delay generator . 212 D.3 Implementing the MUX . 214 D.3.1 Choice of circuit . 214 D.3.2 Sizing for the critical transitions . 214 D.4 Characterization . 217 D.4.1 N/P ratio . 218 D.4.2 Supply sensitivity . 218 D.4.3 Back-gate tuning . 220 D.4.4 Comparison . 221 D.5 Conclusion . 221 III References 225 x Nomenclature ADC Analog-to-Digital Converter AWGN Additive white Gaussian noise BW Bandwidth CAD Computer-Aided Design CIC Cascaded Integrator-Comb CML Current Mode Logic CMOS Complementary metal-oxide-semiconductor COTS Commercial off-the-shelf CW Continuous-Wave DAC Digital-to-Analog Converter DCO Digitally Controlled Oscillator DDS Direct Digital Synthesizer DTC Digital-to-Time Converter ENOB Effective Number Of Bits FMCW Frequency-Modulated Continuous-Wave FPGA Field-Programmable Gate Array GPR Ground Penetrating Radar HDL Hardware Description Language xi CONTENTS LFM Linear Frequency-Modulated LFSR Linear Feedback Shift Register LNA Low Noise Amplifier mux multiplexer OSR OverSampling Rate PA Power amplifier PDM Pulse-Density Modulation PLL Phase Locked Loop PRF Pulse Repetition Frequency PSD Power Spectral Density PVT Process, Voltage and Temperature PW Pulse-Width RMS Root Mean Square SAR Synthetic Aperture Radar SerDes Serializer/Deserializer SFCW Stepped-Frequency Continuous-Wave SFDR Spurious Free Dynamic Range SNDR Signal to Noise and Distortion Ratio SNR Signal to Noise Ratio SPI Serial Peripheral Interface bus SQNR Signal to Quantization Noise Ratio SR Stochastic Resonance SSR Suprathreshold Stochastic Resonance xii CONTENTS TDC Time-to-Digital Converter VCO Voltage Controlled Oscillator WP Wave-Pipeline xiii Part I Thesis Chapter 1 The first chapter When interfacing with the real world, an ideal analog circuit can track the environment with infinite speed and infinite precision. The traditional chal- lenge is then to build an analog circuit that is as close to ideal as we need. This usually leads to a circuit that can handle a specific bandwidth (speed) at a specific input range and limited by a noise level. The analog circuit requirements are then traded off between cost (technology), power consump- tion (vs noise), size/portability, existing vs custom components and so on.
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