Riviera-PRO™ Advanced Verification

RivieraPRO™ Advanced Verication

Verication Platform System Interfaces

Verif ication Platform that grows with MATLAB®, SystemVue® RivieraPRO™ addresses verication needs of engineers your requirements. Debugging MixedLanguage crafting tomorrow’s cuttingedge FPGA and SoC devices. IDE, Code tracing, Waveform, Dataow RivieraPRO enables the ultimate testbench productivity, Metrics Coverage, Assertions Code & Functional Coverage, SVA/PSL/OVA reusability, and automation by combining the Test Automation TLM, RTL, GateLevel highperformance simulation engine, advanced debugging SystemVerilog, SystemC, UVM, C/C++ capabilities at dierent levels of abstraction, and support for Simulation MixedLanguage, MixedSignal, HW/SW the latest Language and Verication Library Standards. Verilog, VerilogAMS, VHDL

High Performance Simulation Top Benef its RivieraPRO incorporates industryleading simulation Standardsbased support for VHDL, SystemVerilog, optimization algorithms to achieve the highest performance in mixedlanguage simulations. Combined with the and SystemC to enable design and verication of the industryleading capacity, RivieraPRO enables high most sophisticated digital designs regression throughput for developing the most complex systems. Highperformance simulator with industryleading Advanced Debugging capacity and high regression throughput for Integrated multilanguage debug environment enables developing complex systems automating timeconsuming design analysis tasks and xing bugs quickly. It supports all standard languages and provides Integrated multilanguage debug environment to intuitive ways to visualize and analyze key objects in your automate timeconsuming design analysis tasks and design. Builtin debugging tools provide code tracing, waveform, dataow, coverage, assertion, and memory x bugs quickly visualization capabilities. Comprehensive assertionbased verication (SVA, Industry’s Best ROI PSL) for increased design observability and RivieraPRO enables Aldec customers to deliver innovative decreased debug time products at a lower cost in shorter time. Aldec’s proven design automation methods help customers to speed up the design and implementation of products for automotive, medical, Advanced code coverage capabilities and coverage aerospace, and military applications. In addition to EDA tool analysis tools for fast metricbased verication packages accompanied by the comprehensive trainings and closure support, Aldec invests in the partnerships and integrations necessary to build complete design and verication ows.

www.aldec.com R THE DESIGN VERIFICATION COMPANY FEATURES PRODUCT CONFIGURATIONS Supported Standards LV LVT LVTSV VHDL IEEE 1076 (1987, 1993, 2002 and 2008) • • • Verilog® HDL IEEE 1364 (1995, 2001 and 2005) • • • SystemVerilog IEEE 1800™2009 (Design) • • • SystemC™ 2.3 IEEE 1666™/TLM 2.0 Option • • Analog/Mixed Signal (SPICE, VerilogAMS 2.3.1) Option Option SystemVerilog IEEE 1800™2009 (Verication) • Verication Libraries (UVM/OVM and VMM) • Design Entry and Design Management HDL Editor with AutoComplete and Code Templates • • • Design and Library Managers, File Browser • • • Customizable GUI Perspectives • • • Task Management • • • Macro, Tcl/Tk, Perl script support • • • HDL Debug and Analysis Interactive Code Execution Tracing • • • Advanced Breakpoint Management • • • Accelerated Waveform Viewer (ASDB) • • • Hierarchical References to/from VHDL (Signal Agent) • • • PostSimulation Debug • • • Waveform Compare • • • Memory Viewer • • • Plot Window • • • Assertions in Waveform and Debugging Option • • Integrated C/SystemC Debugger • • XTrace Option • • Advanced Dataow Option • • Simulation/Verication Single or Mixed Language • • • Verilog Programming Language Interfaces (PLI/VPI) • • • VHDL Procedural Interface (VHPI) • • • SystemVerilog IEEE 1800™2005 DPI 2.0 • • • Value Change Dump (VCD and Extended VCD) Support • • • Incremental Compilation • • • MultiThreaded Compilation • • • 32/64Bit CrossCompatible Libraries • • • Simulation Model Protection/Library Encryption • • • VHDL 2008 and Verilog 2005 IEEE Encryption • • • Xilinx® SecureIP Support Option • • Altera® LanguageNeutral Libraries Option • • Simulation Performance Optimization (Verilog/SystemVerilog, VHDL) • • 64bit Simulation • • TransactionLevel Visual Debugging Option • Proler (Performance Metrics) Option • • SFM (Server Farm Manager) Option Option • HES™ Hardware Assisted Verication (Acceleration and Emulation) Option Option Option Assertions and Coverage Tools PSL, SystemVerilog, OpenVera Assertions and Functional Coverage (Assertion) Option • • Code and Toggle Coverage and UCIScompatible Aldec Coverage Database Option • • Functional Coverage (Covergroup) • External Simulation Interfaces Synopsys® SmartModels, SWIFT Interface and LMTV Option • • SpringSoft® Verdi™ FSDB Recording Option • • CoSimulation Interfaces Agilent SystemVue® • • • MathWorks Simulink® • • • MathWorks MATLAB® Option • • Design Rule Checking ALINT™ with Aldec Basic Rule Library Option • • DO254 VHDL or Verilog Rule Library Option Option Option STARC® VHDL or Verilog Rule Library Option Option Option Reuse Methodology Manual (RMM) Rule Library Option Option Option Supported Platforms Windows® 7/Vista/XP/2003 32/64 bit 32Bit Only • • Linux 32/64 bit 32Bit Only • •

Aldec, Inc. Europe Israel Japan Corporate N. America Ph. +972.072.2288316 Ph. +44.1295. 20.1240 Ph. +81.3.5312.1791 Ph +1.702.990.4400 sales[email protected] sales[email protected] sales[email protected] [email protected] China India Taiwan R Ph. +86.21.6875.2030 Ph. +91.80.3255.1030 Ph. +886.3.6587712 THE DESIGN VERIFICATION COMPANY Visit us at www.aldec.com [email protected] sales[email protected] sales[email protected]