Si CMOS for RF Power Applications

J. A. del Alamo MIT

Workshop on Advanced Technologies for Next Generation of RFIC 2005 RFIC Symposium June 12, 2005 Sponsors: DARPA, IBM, SRC RF power applications Power vs. frequency

GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT LDMOS CMOS 30

20 Output Power [dBm] Power Output 10

0 0.1 1 10 100 1000 Frequency [GHz] Compilation of research papers from IEEE Xplore by J. Scholvin Research activity by material and frequency

100 100 r SiC r above 27 GHz InP 3 to 27 GHz 75 GaN 75 GaAs below 3 GHz Silicon 50 50

25 25 Publications per Yea per Publications Publications per Yea per Publications 0 0

5 7 9 1 3 5 7 9 1 3 8 8 8 9 9 9 9 9 0 0 5 7 9 1 3 5 7 9 1 3 9 9 9 9 9 9 9 9 0 0 8 8 8 9 9 9 9 9 0 0 1 1 1 1 1 1 1 1 2 2 9 9 9 9 9 9 9 9 0 0 1 1 1 1 1 1 1 1 2 2 Year Year

Compilation of research papers from IEEE Xplore by J. Scholvin RF power technologies: 1993 vs. 2003

GaAs HBT 12% InP HEMT Ga As HEMT 12% 37% LDMOS 5%

Ga As MESFET 2003 34% InP HBT 3% GaN HEMT SiC InP HEMT 16% 3% Si BJT 3% LDMOS 3% 1993 5% GaAs HBT Silicon 16% SiGe HBT 34% CMOS 10% 16%

Ga As HEMT Ga As MESFET 22% 5%

Compilation of research papers from IEEE Xplore by J. Scholvin RF Power Figures of Merit

• PA specs:

– Frequency –Power –Gain – Linearity – Voltage PA – Reliability – Power efficiency –Cost Fundamental trade-off between voltage and frequency

scaling Key to power: supply voltage

100 GaAs & GaN HEMT 10 Wf InP HBT

1 Si BJT SiGe HBT GaAs MESFET 0.1 HEMT CMOS

0.01 LDMOS

Power Density [W/mm] 0.001

0.0001 0.1 1 10 100

Vdd [V]

Compilation of research papers from IEEE Xplore by J. Scholvin Key to frequency: efficiency

GaAs/InP HBT 100 InP HEMT GaAs HEMT GaAs MESFET 80 CMOS SiGe HBT LDMOS 60

20 Power Added Efficiency [%]

0 0.1 1 10 100 1000 Frequency [GHz]

Compilation of research papers from IEEE Xplore by J. Scholvin The benefits of scaling

All FETs 27 GHz < f < 50 GHz 40 scaling

Peak PAE [%] 20

0 0 0.2 0.4 0.6 0.8 1

Lg [µm]

Compilation of research papers from IEEE Xplore by J. Scholvin Gate length scaling in III-V FETs and CMOS

10 ]

0.1

Physical Gate Length [µm III-V's CMOS CMOS Roadmap 0.01 1970 1980 1990 2000 2010 Year Compilation of research papers from IEEE Xplore Si CMOS: a disruptive technology for RF power? by J. Scholvin Si MOSFETs for RF power

GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT LDMOS CMOS 30

20 Output Power [dBm] 10

0 0.1 1 10 100 1000 Frequency [GHz] 1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS 1. Extending LDMOS beyond 2 GHz

(PhD Thesis of J. Fiorenza)

Source LDMOSFET: Lightly-doped Drain MOSFET

Drain

Source Gate Drain Gate n+ nn-- nn++ P

• Two critical sources of RF Loss: – Gate resistance loss: reduces power gain – Substrate loss: reduces power efficiency Low-loss gate: Metal/Poly-Si damascene gate

Al 300 nm TiN 50 nm PolySi 50 nm Gate Oxide 20 or 30 nm n-

Advantages: – Implemented in the back end of process – Allows the use of Al or Cu: very low gate resistance – Self-aligned: no increase in overlap capacitance – Gate oxide undisturbed Achieved: 0.2 ohm/sqr (>10 for polySi, ~1 for silic’d gate) Metal/Poly-Si Damascene Gate

Source

Gate Drain

3 μm 200 μm

Lg = 0.6 μm ft ~ 15 GHz BVoff > 18 V Test chip

0.6 μm minimum Lg 10 mask levels 2 levels of metal Fabricated at MIT Benefit of low gate resistance: small signal

Source Drain Gate Source

Damascene gate increases fmax, enables wide gate fingers Benefit of low gate resistance: large signal

Source

Drain

Gate Source

High PAE with gate finger width up to 140 μm Low-loss substrates: SOI and high-resistivity Si

Source Gate Drain Source Gate DrainDrain n+ n-- n++ n+ n-- n++ n n P n n P Gate

Bulk Si Thin-film SOI

Substrate: Handle wafer: • Regular Si • Regular Si • High-resistivity Si • High-resistivity Si Impact of substrate

• SOI improves PAE • High-resistivity silicon improves PAE on bulk • High-resistivity silicon does not improve PAE on SOI Beyond 2 GHz

Low-loss substrate very important at high frequencies Analysis of substrate loss

Source Drain Pad

Gate

Drain Loss Pad Loss • Pad Loss: • SOI effective • HR effective on bulk Si and SOI • Drain Loss: • SOI somehow effective • HR very effective on bulk Si, only moderately on SOI Why is HRSOI Ineffective?

Source Drain Pad

Gate n+ p n+ ------Cbox HRSOI Rsurf Rsub

Surface inversion increases drain loss on HRSOI Effect of substrate inversion in HRSOI-LDMOS

60 Load-Pull Measurement 55 2.4 GHz

RFin RFout 50

45 HRSOI 40 Peak PAE [%] Peak

+ 35 4.8 GHz - V HS 30 -30 -20 -10 0 10 20 30

VHS [V]

• Eliminating substrate inversion improves PAE • Most prominent at high frequencies Impact of inversion layer elimination

60 f=1.9 GHz Enhancement due to 55 elimination of inversion layer

50 Peak PAE [%] Peak

45 Bulk HR Bulk SOI HR SOI Substrate Impact of inversion layer elimination

• Eliminating substrate surface effects improves performance: – Particularly prominent in LDMOS due to large drain area – Both linear and saturated performance – Most prominent at high frequencies

14 60 60 VHS=5.5 V 12 50 55 10 40 50 VHS = 5.5 V VHS=0 V 8 f = 4.8 GHz 30 45 6

36x40 µm PAE [%] V = 0 V Gain [dB] HS 20 PAE [%] peak 4 Vdd = 3.6 V 40 Id = 10 mA 2 10 35 0 0 30 -10-50 5 10152025 2345678 Output Power [dBm] Frequency [GHz] Si MOSFETs for RF power

GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT LDMOS CMOS 30

20 Output Power [dBm] 10

0 0.1 1 10 100 1000 Frequency [GHz] 1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS 2. RF power suitability of deeply scaled CMOS (PhD Thesis of J. Scholvin)

Attractiveness of CMOS: • System-on-Chip integration • Low cost • Low voltage • Good device models • Aggressive roadmap • Wide flavor of devices available

Suitable for: • High-volume, low cost consumer applications 90 nm CMOS • Moderate frequencies (2-10 GHz) • Medium power (<100 mW) • Current: WLAN, Bluetooth, Cell-phone PA driver, WiMax/802.16

Picture from: http://www.intel.com/research/silicon/micron.htm#silicon Issues of CMOS for RF power

• Concerns: CMOS scaling ⇒ Vdd ↓⇒Pout ↓

data for IEEE published CMOS PA devices and circuits

• Possible solutions:

–Raise Vdd ⇒ impact on reliability – Use I/O devices ⇒ not really scaling 90 nm CMOS: there is a lot more than 90 nm devices!

• Includes devices with longer gate lengths and thicker gate oxides for I/O drivers and high V operation

• Designed RF power devices in collaboration with IBM

Oxide thickness thin medium thick (14 A) (22 A) (51A) Nominal voltage [V] 1.0 1.2 2.5

Lg = 90 nm x

Lg = 130 nm x x

Lg = 250 nm x x x The benefits of scaling for RF

200 logic device

150

100 (GHz) max f

power device 0 90 nm 130 nm 250 nm Device type

• Logic devices at optimized bias point have very high bandwidth • But… power devices at class AB bias point have much less bandwidth RF power performance of standard 90 nm devices

70 1 cell 8 cells V = 1 V, I = 26 mA/mm 60 dd d f = 2.2 GHz 50 48x16 µm (1 cell) 8 x 48x16 (8 cell) 40

30 PAE

Gain [dB], PAE [%] [dB], Gain 20 Gain 10

0 -20 -10 0 10 20 30

Pout [dBm]

• 1 cell: Peak PAE = 66% at Pout = 12.5 dBm

• 8 cell: Peak PAE = 59% at Pout = 20.2 dBm Linear performance of 90 nm CMOS

70 0

60 PAE -20

50 -35 dBc -40 40 IM3 [dBc] 30 3 PAE [%] -60 IM

20 Vdd = 1 V Id = 26 mA/mm -80 10 freq = 2.2 GHz WCDMA PA driver spec 8x48x16 µm 0 -100 -20 -10 0 10 20 30

Pout [dBm]

• What is PAE at a given IM3 ?

– at IM3 = -35 dBc, PAE = 12% at Pout = 12 dBm • Exceeds WCDMA PA driver specs 90 nm vs. 250 nm devices at 8 GHz

70 Lg = 90nm, Thin Ox 30 Lg = 250nm, Thick Ox 60 25 PAE 50

40 20 Pout

30 15 [dBm mm] 1 at Peak PAE [%] Peak 20 10 Output Power Density 10 freq = 8 GHz Id = 26 mA/mm 0 5 0.1 1.0 10.0

Vdd [V]

•At Vdd = 1 V, 90 nm has best PAE and Pout

• 250 nm device offers highest power density at Vdd=2.5 V 90 nm vs. 250 nm

90 nm, thin oxide 250 nm, thick oxide Vgs = 1V Vgs = 2.4V 0.1V steps 0.2V steps

• 250 nm thick oxide device has higher Vds,sat

⇒ compresses earlier and softer ⇒ lower Pout and peak PAE

• As Vdd ↑ impact of Vds,sat decreases What about reliability?

5 For RF power, reliability related to ratio of: (V) 4 BVoff nom 3 •nominal Vdd , V off 2

• to breakdown voltage BV 1 Vnom 0 90 nm 130 nm 250 nm For RF power: Device type

• 90 nm device expected to be more reliable at Vdd=1 V than 250 nm device at 2.5 V Reliability: impact of output power

60 0 Vdd = 1.6 V

Id = 26 mA/mm ] f = 8 GHz -0.1 40 48x16 μm PAE -0.2 16.8 dBm

-0.3 17.2 dBm 20 Gain 17.4 dBm

Change in Gain [dB Gain in Change -0.4 Gain [dB], PAE [%] PAE [dB], Gain

Pout = 17.6 dBm 0 -0.5 -20 -10 0 10 0.01 0.1 1 10 100 1000 Input Power [dBm] Time [minutes]

• Run device under continuous RF power conditions • Measure drop in gain over time, define MTTF as 0.2 dB drop • Power compression has huge impact on degradation Reliability: impact of Vdd

1 Impedances and RF power set for peak PAE

250 nm Id = 26 mA/mm 0.1 90 nm thick oxide freq = 8 GHz thin oxide Mean Time to Failure [hours] Failure [hours] to Time Mean 0.01 110 Vdd [V]

•For same Vdd, thick oxide is more reliable – but thin oxide has better performance • For identical lifetime, how does performance compare? Reliability: impact of Vdd

10 PAE=58%, Pout=16.8 dBm PAE=56%, Pout=15.6 dBm

1 Impedances and RF power set for peak PAE

250 nm Id = 26 mA/mm 0.1 90 nm thick oxide freq = 8 GHz thin oxide Mean Time to Failure [hours] Failure [hours] to Time Mean 0.01 110 Vdd [V]

• 90 nm thin ox. outperforms 250 nm thick ox. for high MTTF

– Low Vdd performance of 90 nm device much better than 250 nm device Conclusions

• Metal-containing gates and low-loss substrates will project LDMOS to 5-6 GHz

• Deeply scaled CMOS suitable for RF power for: – Moderate power levels (~100 mW) – Very low operating voltage (~1 V and below)

• Scaling will project CMOS beyond 10 GHz

• Si-based RF power technologies will dominate many high-volume consumer applications: – WLANs, bluetooth, cellphone PA drivers, RF tags, etc MIT’s RF power measurement setup

– 1.8 - 18 GHz Maury ATS automatic load-pull system – 8-inch Cascade on-wafer probe station – Synthesized source with 10 W TWT-PA supplying up to 200 mW at DUT References

•LDMOS: – Bengtsson: MTT 2003 – Fiorenza: SOI Conf. 1999; MTT-S 2001; IEDM 2002, EDL 2001, 2003, 2005; TED 2002 – Scholvin: IEDM 2003 – Van der Heijden: MTT-S 2001

• 90 nm CMOS: – Ferndahl: MGWL 2003 – Scholvin: IEDM 2004