A Comparative Analysis of Copper and Carbon Nanotubes Based Global Interconnects

International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

A Comparative Analysis of Copper and Carbon NanoTubes Based Global Interconnects

Arti Joshi, Gaurav Soni

 the landscape of the integrated circuit. In the sub 100nm Abstract-Due to continuous advances in technology scaling, scaling regime, interconnect behavior limits the performance modern integrated circuits consist of billions of transistors. and correctness of VLSI systems. The wiring in today’s Interconnects between the gates in these transistors were integrated circuits forms a complex geometry that introduces considered as ideal conductors that propagated signals instantaneously. While device sizes were shrinking with each capacitive, resistive, and inductive parasitics. They can cause technology generation, multilevel metal structures rose higher an increase in propagation delay, impact on energy and higher above the surface of the silicon and soon began to dissipation and the power distribution and introduce extra dominate the landscape of the integrated circuit. In the sub noise sources, which affects the reliability of the circuit. As 100nm scaling regime, interconnect behavior limits the the device size scales down the impact of interconnect in the performance and correctness of VLSI systems. The wiring in VLSI circuits became even more significant. It controls all of today’s integrated circuits forms a complex geometry that introduces capacitive, resistive, and inductive parasitics. They these important electrical characteristics on the chip [29]. can cause an increase in propagation delay, impact on energy Also as the width of wires is decreased, the resistance dissipation and the power distribution and introduce extra noise increases. This increase in wire resistance causes RC delay to sources, which affects the reliability of the circuit. As the device increase. The spacing between wires has been decreasing to size scales down the impact of interconnect in the VLSI circuits the point where the coupling between wires is significant. The became even more significant. The performance of copper resulting capacitive coupling introduces additional delay and interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. noise effects. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current II. LIMITATIONS OF COPPER INTERCONNECTS carrying capacity and large electron mean free paths. Initially In the past copper wire replaced aluminum wires due to the we have analyzed the performances of a copper based CMOS low resistance of copper wires when compared with inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved aluminum wires and also the resistance to electromigration performance of CNT interconnects in terms of power and delay was much higher in copper when compared with aluminum, time in comparison to traditional copper based interconnects. now copper wires are going through similar problems due to This work suggests using Single Wall Carbon Nanotubes the increasing resistivity and as a result, wire delay is (SWCNT) as interconnects for global interconnects in VLSI becoming serious concern especially when the processing design as they consume less energy and gives more throughput technology approaching the sub nanometer regime. From the and bandwidth when compared with traditional Copper wires. report of International Technology Roadmap for Index Terms: Copper, SWCNT, Global Interconnects Semiconductors (ITRS) plotted below we find that copper resistivity for future technologies is increasing at a very fast I. INTRODUCTION rate [7]. Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were considered as ideal conductors that propagated signals instantaneously. Interconnects are used to connect components on a VLSI chip, connect chips on a multichip module and connect multichip modules on a system board. While device sizes were shrinking with each technology generation, multilevel metal structures rose higher and higher above the surface of the silicon and soon began to dominate

Manuscript received February 20, 2015. Arti Joshi, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: [email protected] ). Figure 1 : Increase in Cu Resistivity with Technology Scaling [7] Gaurav Soni, Department of Electronics & Communication, Poornima University, Jaipur, India, (e-mail: [email protected]). We find that the increase in resistivity is not much when we

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move from 90nm to 32nm technology node, but as we reduce conceptualized by wrapping a one-atom-thick layer of the feature size further from 32nm, we see a sharp resistivity graphite (or graphene) into a seamless cylinder. The way the increase due to scattering effects. graphene sheets wraps can be represented by a pair of indices Besides increasing resistivity, the wire width is also shrinking (n,m) called the chiral vector. The relationship between n and with newer technologies. That further increases the overall m defines three categories of CNTs viz: arm chair, zigzag and resistance, since resistance of a wire is inversely proportional chiral. to the wire width. Therefore, even though the wire length is MWCNTs consist of multiple layers of graphite rolled in on getting smaller, but decreasing cross section area and them to form a tube shape with an interlayer spacing of 3.4 Å. increasing resistivity resulting in higher interconnect delay, The outer diameter of MWCNTs may range from 1 to 50nm which is not a good sign as we always look to obtain higher while the inner diameter is usually of several nanometers. speed. Hence as we look deeper into the circuit level issues, we find B. . General Properties of Carbon Nanotubes that as we slowly move from deep sub-micron technology to nanotechnology, the traditional copper wires will not be able The electronic transport in metallic SWCNTs and MWCNTs to keep up, and we will need to look beyond conventional occur ballistically over long lengths owing to their nearly one materials for interconnect design. Consequently, alternative dimensional electronic structure. This enables nanotubes to solutions such as metallic carbon nanotube (CNT) carry high currents with negligible heating. It is reported that interconnects have been proposed in order to avoid the the MWCNTs can carry high current densities up to 109 to problems associated with global on-chip wires altogether. 1010 A/cm2. CNT’s are the strongest and stiffest materials yet discovered in terms of tensile strength and elastic modulus respectively. This strength results from the covalent sp2 bonds formed between the individual carbon atoms. Standard III. CARBON NANOTUBES single walled carbon nanotubes can withstand a pressure up to Carbon Nanotubes popularly called by the acronym CNT was 24GPa without deformation. Depending on the direction in discovered by Sumio Lijima in 1991. Nanotubes are which the carbon sheet is rolled up i.e. chirality they exhibit composed of sp2 bonds, similar to those observed in graphite metallic or semiconductor properties. Due to lack of chirality and they naturally align themselves into ropes held together any bundle of CNT consists of both metallic and by Vander Waals forces. These are allotropes of carbon with a semiconducting nanotubes. For a given (n,m) nanotube, if cylindrical nanostructure. n=m, the nanotube is metallic; if n-m is a multiple of 3, then the nanotube is semiconducting with a very small band gap, otherwise the nanotube is a moderate semiconductor. This work analyses the efficiency of using single-walled carbon nanotube bundle instead of copper as an interconnect material as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.

IV. CIRCUIT PARAMETERS MODELLING

To study the parasitic effects described above requires the introduction of electrical models that estimate and approximate the real behavior of the wire as a function of its parameters.

A. Modeling Parameters for Copper:

Figure 2 : Carbon NanoTube [29] Carbon Nanotubes (CNTs) are cylindrical carbon molecules with novel properties (outstanding mechanical, electrical, thermal and chemical properties: 100 times stronger than steel, best field emission emitters, can maintain current density of more than 1010 A/cm2)

Figure 3: RLC interconnect model [19]

A. Types of Carbon Nanotubes The resistance of a wire is: CNTs are of two types namely, single walled carbon nanotubes (SWCNTs) and multi walled carbon nanotubes (MWCNTs). SWCNTs were discovered in 1993 and most of Where, ρ is the resistivity of material (in Ω-m). these have a diameter close to 1 nm, with a tube length that may be many thousands of times larger and up to order of centimeters. The structure of a SWCNT can be

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The wire capacitance is modeled as follows This additional scattering resistance appears as distributed resistance per unit length in the equivalent circuit.

Where ε is the dielectric permittivity, s is the interwire spacing (assumed s = w), h is wire height and t is intermetal It is important to note that the mean free path of a CNT is layer spacing. proportional to diameter [4]. For global wires, we included inductance, as shown in the The total capacitance of a CNT consists of two components: following equation:

1. Electrostatic capacitance (CE) 2. Quantum capacitance (CQ)

B. Modeling Parameters for CNT Bundles: Electrostatic capacitance is the intrinsic plate capacitance of an isolated CNT whereas the quantum capacitance accounts for the electrostatic energy stored in the nanotube when it carries current[10].

Figure 4 : Equivalent RLC circuit model for an isolated SWCNT [35]

The various parameters are: Here ε is dielectric permittivity, d is CNT diameter, y is 1. RF is the fundamental (quantum) resistance, distance of CNT from ground plane and v is fermi velocity 5 F 2. LCNT is the total inductance, in graphite (8*10 m/s). 3. CQ is quantum capacitance, The total inductance of a CNT consists of two 4. CE is the electrostatic capacitance. components[10]:

The fundamental resistance RF, is equally divided between 1. Magnetic inductance (LM) the two contacts on either side of the nanotube. It can be 2. Kinetic inductance (LK) expressed as[10]: In presence of a ground plane, the magnetic inductance per unit length is given by:

The mean free path of electrons in CNT is typically 1µm [4]. If CNT length is less than mean free path (λCNT), electron Apart from magnetic inductance, another inductive transport within nanotube is ballistic and the fundamental component appears due to the kinetic energy of the electrons. resistance is independent of its length and is given by (h/4e2 The kinetic inductance per unit length can be expressed )=6.45kΩ. However, if the length is greater than the mean free as[10]: path, an additional ohmic resistance results due to scattering which increases with length as[10]:

V. CNT INTERCONNECT MODELS USED BY RESEARCHERS Here l is length of CNT. [Navin Srivastava and Kaustav Banerjee, 2005] analyses the applicability of carbon nanotube (CNT) bundles

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as interconnects for VLSI circuits, while taking into account they have concluded that MWCNT bundles show better the practical limitations in this technology. A model is performance over copper wire at all level of interconnects and developed to calculate equivalent circuit parameters for a technology nodes [15]. CNT-bundle interconnect based on interconnect geometry. Using this model, the performance of CNT-bundle [Kyung-Hoae Koo, et-al, 2008] present promising interconnects (at local, intermediate and global levels) is options for replacing the existing Cu-based global/semiglobal compared to copper wires of the future. It is shown that CNT and local wires. Authors quantify the performance of carbon bundles can outperform copper for long intermediate and nanotubes (CNTs) interconnects and compare it with global interconnects, and can be engineered to compete with Cu/low-κ wires for future high-performance integrated copper for local level interconnects. The technological circuits. For a local wire, a CNT bundle exhibits a smaller requirements necessary to make CNT bundles viable as future latency than Cu for a given geometry. In addition, for a future interconnects are also laid out. At the local interconnect level; technology node, authors compare the relationship between CNT-bundles with imperfect contacts do not give much bandwidth density, power density, and latency, thus alluding performance improvement. In the case of long intermediate to the latency and power penalty to achieve a given bandwidth and global interconnects, densely packed CNT bundle density. The power density comparison is highly switching interconnects show significant improvement in performance activity (SA) dependent. At lower bandwidth density and SA as compared to copper interconnects, in spite of imperfect lower than 20%, an improvement in mean free path and metal-nanotube contacts [35]. packing density of CNT can render it most energy efficient. In general, the CNT bundle shows lower latency than Cu. For [Hong Li, et-al, 2006] proposed an equivalent global wires, authors used proper R, L, C modeling to transmission line model for CNT interconnects & calculated compare latency, power density/energy efficiency, and the equivalent circuit parameters for CNT bundles. Also bandwidth density of Cu and CNTs. The first set of author has made performance comparisons between carbon comparisons entailed latency and energy per bit as a function nanotubes & copper interconnects at various interconnect of technology scaling. Bandwidth density was varied using levels using interconnects dimensions data envisioned by different implicit parameters: wire pitch for Cu and CNT. ITRS. Author examined several previous research works & Finally concluded that CNT wires exhibit the lowest latency desisted that conventional copper interconnect performance is whereas the power density comparison depends on SA. High degrading & is conflicting with the requirements of today’s SA yielded the best results, whereas at lower SA of 20%, there high performance systems. The capacitance extraction of is a critical bandwidth density below which CNTs have lower CNT bundle has been done using FEM method. After getting power density [16]. all the circuit parameters of CNT bundles and Cu wires, we can estimate the propagation delay of a CNT interconnect and [Naushad Alam, et-al, 2009] has discussed the prospects compare it with Cu interconnect. Author showed that the of mixed bundle of Carbon Nanotubes (CNT) as low-power delay of CNT bundle is smaller than Cu wire at either high-speed global interconnects for future VLSI applications. intermediate or global interconnect level. In particular at Author studied several previous research works which shows global level, the performance enhancement in delay reduction that as interconnect feature size shrinks, copper resistivity can be as large as 80% [14]. increases & the Cu wires becomes more vulnerable to electromigration. Author has examined the power dissipation [Kyung-Hoae Koo, et-al, 2007] has presented a and delay of CNT bundle interconnects & compared them comprehensive analysis of the performances of Copper wire with that of the Cu interconnects for power dissipation & and MWCNT (Multi-walled Carbon Nano Tube) bundles delay at the 32-nm technology node. Mixed bundle of CNTs across deep submicron technology nodes like 45nm, 32nm, and Cu interconnects are modeled as an equivalent 22nm and 16nm for the local, intermediate and global level of transmission line and the equivalent circuit parameters (R, L, interconnects. The authors have studied about both copper C) were extracted, using Carbon Nanotube Interconnect wire and CNTs (which are classified in SWCNTs and Analyzer (CNIA) and BPTM tools. To extract the circuit MWCNTs), they have found that Carbon Nano Tubes(CNTs) parameters of mixed CNT bundle interconnect a realistic have immense potential in dictating the future VLSI nanotube density of 5 x 1012 tubes/cm2 has been considered interconnect technology due to their great electrical, thermal & the power dissipation of interconnects were calculated & properties, high mechanical stability, current carrying analyzed using simulation runs with H-SPICE at a frequency capacity and later's electromigration concerns at high of 500MHz with Vdd = 0.9V. The delay analysis is done at a temperature. They are the most promising one to replace the frequency of 500MHz and voltage swing of 0.9V which existing Copper interconnect technology. The authors have shows that CNT bundle is faster than Cu interconnects done simulations at 45, 32, 22 and 16 nm technology nodes because of the smaller resistances and capacitances. Finally using Specter simulator of Cadence .The analytical delay concluded that power dissipation of local copper interconnect estimation was done in MATLAB which has computed on the is smaller than the corresponding CNT bundle but at basis of some analytical expressions. From some figures intermediate and global level, the CNT bundle consumes 1.5 authors have achieved 85% performance advantage of to 4 folds smaller power than Cu. So mixed bundle of CNTs MWCNT bundle over Copper wire. Finally authors have can replace Cu interconnects in future low-power high-speed observed, in 16nm technology node, the performance VLSI systems [2]. advantage numbers are 50%, 90% and 85% for 20µm long local interconnect, 200µm long intermediate interconnect and 10000µm long global interconnect respectively. Then finally

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[Sudeep Pasricha, et-al, 2010] presented a comparative the propagation delay reduces but power dissipation increases analysis of Carbon Nanotube (CNT) interconnects as an at global interconnect lengths. Thus SWCNTs with higher alternative to the conventional copper (Cu)-based global number of shells can be predicted as more appropriate interconnects. Since Cu based interconnects faced the candidate for future global VLSI interconnects [25]. problem of being susceptible to electromigration, rising crosstalk coupling noise, and parasitic resistivity, which reduces its reliability and performance. Author basically VI. CIRCUIT MODELS, PARAMETERS USED AND investigate the performance and energy impact of using RESULTS CNT-based global interconnect alternatives in place of Table 1: Circuit Models and parameters used by conventional Cu global interconnects at the system-level for Researchrs several CMP applications. Discussed previous work done & Interconnect concluded that a lot of work has been done in studying the Model Used Parameters Result properties of CNT’s but little work has done to analyze the impact of using CNT instead of Cu. First of all author TN=22nm presented an overview of RLC circuit models for 4 CNT Larger dcnt increases CNT resistance global interconnect candidates i.e. SWCNT, SWCNT dcnt=1nm Wire Bundle, MWCNT & Mixed SWCNT/MWCNT Bundles. For (MFP, PD) = length=1/10mm, Author compared the global wire delay of Cu and CNT (1.6µm,1/3), CNT has RLC Circuit [5] PMOS:NMOS=2:1 1.7% delay advantage interconnect alternatives across the 45–22 nm UDSM (W/L ratio) technology nodes & the results showed that other CNT MFP= For (MFP, PD) = alternatives have lower interconnect delays compared to Cu. 1.6µm/2.8µm (2.8µm,1), CNT has Also the MWCNT wire in particular has a much lower delay PD=1/3 /1 5% delay advantage due to its large concentric tubes. In order to analyze the TN=22nm CNT interconnects overall performance and energy impact of CNT global Wire length=10mm consumes less power interconnects author selected applications from the well RLC Wire Cu ρ= 1.9µΩ.cm than Cu interconnects known SPLASH-2 benchmark suite. Results showed that the model [4] MFP= 1.6µm Increasing MFP results applications now perform better with CNT global Vbias=4.7 V in decreasing Power interconnects because of their lower signal propagation SA=20% density. delays & Since CNTs have a marginally lower capacitance, a TN=22nm reduction in energy consumption (1%–11%) has been For MFP=0.9µm Contact CNT’s has1.6X observed. Finally author concluded that SWCNTs are not as resistance=1.2KΩ suitable for global interconnect buses due to their large ohmic improvement in latency MPF=2.8µm resistance and very high delays but global MWCNT buses can RLC Circuit [3] Scattering provide performance speedups of up to 1.98× for CMP coefficient=0.5 For MFP=2.8µm applications & a potential communication architecture energy Grain boundary CNT’s are 1.2X energy saving of as much as 30% can be achieved with the advances coefficient =0.5 efficient than Cu. in fabrication technology [32]. W/L ratio=2:1 Length =10µm For a metallic SWCNT [Manoj Kumar Majumder, et-al, 2012] has presented an density of one per 3 equivalent single conductor (ESC) model of SWCNT which nm2, the bandwidth potentially provides attractive solution in propagation delay Equivalent R= 0.198 kΩ density can potentially and power dissipation & solve the problems associated with circuit metallic increase by up to 40% SWCNT’s [2] the Al & Cu interconnects i.e. electromigration due to higher L= 0.952 & 0.010 While density of one current density. This model is accurate up to several tens of nH per 6 nm2 offers less GHz and any distance from ground plane & follows two fold C=30.36 fF than10% improvement. modeling approaches. Initially, a multi conductor TN=32nm CNT bundle consumes transmission line (TL) model is presented & then it is reduced Vdd=0.9 V at 700 1.5 to 2 folds smaller RLC Equivalent MHz to the ESC one by assuming that all the shells of SWCNTs are power connected in parallel at both ends. The author has compared Circuit model Length=200µm the propagation delay and power dissipation using a DIL [6] R=374.2 Ω CNT bundle are 1.4 to (Driver-Interconnect-Load) system for SWCNT structures L=317 Ph 3 times faster than Cu with different number of shells. A CMOS driver with1V C=36.283fF interconnect supply voltage is used for accurate estimation of delay and TN=22/32 nm CNT has an 80% Equivalent Length =10µm power dissipation. The ESC model of SWCNT structures performance transmission W=70n replaces interconnect line in the bus architecture & the enhancement in delay line model [10] interconnect line ranging from length 400µm to 2000µm is H=168nm reduction. terminated by a load capacitance CL of 10aF. Finally Cu ρ= 2.963µΩ.cm concluded that for increasing number of shells in SWCNTs, VII. PERFORMANCE COMPARISON Table 2: RLC Parametrs for Cu & CNT Interconnect

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Interconnect Parameters used to compare SWCNT bundle interconnect with that of Interconnect Interconnect L Length (μm) R (Ω) C (fF) copper interconnects. The simulation results obtained (pH) strengthened the fact that CNT technology is a possible and Cu 374.2 317 36.283 200 viable replacement for the present copper based technology. CNT 109.05 5270 28.3 Cu 1870.8 1907 181.42 1000 CNT 546.44 26700 142.0 ACKNOWLEDGMENTS Note: All values have been taken from the IEEE Paper [1] I would like to express my deep gratitude and thanks to Dr. Experimentation is done using HSPICE and waveform is Mahesh Bundele (Coordinator, Research), Poornima observed using CosmosScope. Power Simulation of a Cu University for giving me an opportunity to work under his based and CNT based interconnect is shown in Figure 5 and guidance for review of research papers and his consistent Figure 6 respectively. The input is taken in the form of a pulse motivation & direction in this regard. I would also express my and output power pulse is shown in figure above. The output sincere thanks to Mr. Gaurav Soni (Asst. Professor, ECE), waveform is simulated under the process of transient analysis. Poornima University for their guidance and support.

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38 www.alliedjournals.com International Journal of Engineering, Management & Sciences (IJEMS) ISSN-2348 –3733, Volume-2, Issue-5, May 2015

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