(IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 4, No. 12, 2013 Pre-Eminance of Open Source Eda Tools and Its Types in The Arena of Commercial Electronics

Geeta Yadav Neeraj Kr. Shukla VLSI Design Group VLSI Design Group Department of EECE, ITM University Department of EECE, ITM University Gurgaon (Haryana), India Gurgaon (Haryana), India

Abstract—Digital synthesis with a goal of chip designing in B. Platform the commercial electronics arena is packed into large EDA Linux serves as a open source platform for the various Software providers like, , Cadence, or MentorGraphics. EDA tools. It is very advantageous as compared to the other These commercial tools being expensive and having closed file operating systems as it is free to obtain, while Microsoft structures. It is also a financial constraint for the startup products are available for a hefty and sometimes recurring fee, companies sometimes who have their budget limitations. Any the security aspect of Linux is much stronger than that of bug-fixes or add features cannot be made with ease; in such scenario the company is forced to opt for an alternative cost Windows as free from virus, the power to control just about effective EDA software. This paper deals with the advantages of every aspect of the , flexibility, its use as a using open source EDA tools like Icarus , , firewall, a file server, or a backup server [4]. GTKwave viewer, GHDL VHDL simulator, gEDA, etc. that are C. Github available as a free source and focuses on the simulator tool. It can be seen as a big encouragement for startups It is a web based hosting service which is used for software in Semiconductor domain. Thereby, these open source EDA tools development projects using the Git version control system. Git make the design process more cost-effective, less time consuming is a software version control tool which is mainly used for and affordable as well. proper management of the various versions of a particular tool. It keeps track of the dates when the changes are being made to Keywords—Open source EDA; MentorGraphics; Cadence; the tool, what are those changes, and who has made those Icarus Verilog; GTKwave viewer; Verilator; GHDL VHDL changes. This way, we can easily follow the continuous simulator; gEDA; Linux; Github; VPI changes being made to the tool. For private repositories, Github provides paid plan whereas for open source projects it I. INTRODUCTION is free. The site provides social networking functionality such A. Open source EDA tools as feeds, followers and the social network graph to display how developers work on their versions of a repository. The open source plays a key role in the EDA tool development. A set of tools known as Digital synthesis flow is II. TYPES OF OPEN SOURCE EDA TOOLS used to turn a circuit design written in Verilog or VHDL a high-level behavioral language into a physical circuit, which A. Icarus Verilog Simulator can either serve to be configuration code for a or Icarus verilog is an open source synthesis and simulation chip, or a layout in a specific fabrication process technology tool. It works as a compiler and compiles the source code [1]. In the commercial electronics arena, digital synthesis with written in Verilog(IEEE-1364) into a format. The Icarus the application of a chip design is usually packaged into large Verilog compiler is written by Stephen Williams. He is still EDA software systems like MentorGraphics or Cadence or working on it. This tool supports a waveform viewer named Synopsys which are very expensive. So the designers need to GTKWave. This tool has various released versions; one of its maintain cutting-edge performance as these commercial tool latest released versions is version 0.9.6 [5]. chains get more and more expensive. Another disadvantage of working with the closed file structures is that it becomes Characteristics: difficult to add customized features to the tool. Also, for small  Simulation engine is efficient customers it becomes very difficult and time consuming for them to fix the bugs appearing in the tool. An alternate to this,  Portable compiler is to go for new software that is more user friendly and easier to deal with [2].  Challenge for commercial tools The oldest of these are probably VIS and SIS, two  Supported graphics tool like GTKwave software tools developed at Berkeley for Verilog parsing,  New compatibility with de facto standards such as logic verification, and mapping of logic onto a digital standard library formats and command files cell library. They perform the task of logic optimization and cell mapping admirably [3]. Significance:

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The addition of the functionality to the Icarus Verilog tool  The ability to target netlists to PCB was quickly built would lead to the effective and reduction in the design and into the gEDA Project's netlister, and plans to write a verification of the circuits through the Hardware Description new layout program from scratch were scrapped Languages. List of providers who offer commercial support for Icarus Verilog and/or related products are Dolly Software  The authors of other open source programs became Private Limited, Embecosm, OCLogic Limited [6]. affiliated with the gEDA website and mailing lists, and the collaborative gEDA Project was born The tool has various release versions like 0.9.2, 0.9.3, 0.9.4, and so on, latest being the version 0.9.6. The release E. GTKwave viewer notes of the tool lists the various bugs in that version which It is a GTK+ based wave viewer for Unix, Win32 etc. are then worked on. This can be fixed by any user as it is an GTK+ is basically a toolkit used for creating graphical user open source EDA detail. The fixation of these bugs leads to interfaces. It helps in viewing the VCD files. The Icarus making the verification of the tool more effective. Verilog tool uses the GTKwave tool for the graphical representation of the results. B. Verilator Verilator is a free Verilog HDL simulator. It compiles III. VERILOG PROCEDURAL INTERFACE synthesizable Verilog into an executable format and wraps it VPI stands for Verilog Procedural Interface. The use of into a SystemC model. Internally a two-stage model is used. VPI permits behavioral Verilog code to invoke C functions The resulting model executes about 10 times faster than and C functions to invoke standard Verilog system tasks. VPI standalone SystemC. Verilator has been used to simulate many is a part of the programming language interface standard IEEE very large multi-million gate designs with thousands of 1364. Users can access information contained in a Verilog modules. Therefore we have chosen this tool to be used in the design as well as provides facilities to interact dynamically verification environment for the Open RISC processor [7]. with a software product via the VPI interface routines. VPI Characteristics: interface provides applications such as annotators and  Verilator is the fastest connection of a Verilog simulator with other simulation tools and customize the debugging of tasks, delay calculators. The  It compiles synthesizable Verilog (not test-bench code), basic functions of the VPI interface can be categorized into plus some PSL, SystemVerilog and Synthesis two main areas: VPI callbacks usage for dynamic software assertions into C++ or SystemC code product interaction. Verilog HDL objects and simulation specific objects can be accessed.  Verilator has been used to simulate many very large multi-million gate designs with thousands of modules Callbacks in VPI can call a user-defined application by the use of Verilog HDL software product like logic simulator C. GHDL VHDL simulator when a specified activity occurs on request of the user. GHDL implements the VHDL87 (common name for IEEE Dynamic software product interaction is accomplished by 1076-1987) standard, the VHDL93 standard (aka IEEE 1076- registered callback mechanism. To understand this take an 1993) and the protected types of VHDL00 (aka IEEE 1076a or example like, when a particular net value changes the user can IEEE 1076-2000). The VHDL version can be selected with a request the calling of the user application my_monitor and can command line option [7]. call my_cleanup() routine when the execution of the product of the software completes. The detection of the changes in the Characteristics: occurrence of values, termination of simulation, time  It has been successfully employed for compiling and advancement, etc. can be detected by using VPI callback simulating the DLX processor and the LEON1 SPARC facilities which allows the dynamic interaction with software processor product. The callback feature allows applications of  It directly creates binaries or executable images, which integration with other simulation systems, specializing of the is the best form for testbenches timing checks, complexity of debugging features, etc. There are four basic reasons for callbacks as listed below [9]:  It can be used to pretty print or to generate cross references in HTML  Simulation event (e.g., change in the value on a net or a behavioral statement execution) D. gEDA The gEDA project was started by Ales Hvezda in an effort  Simulation time (e.g., the termination of a time queue to remedy the lack of EDA tools for Linux/Unix. or after certain amount of time) The first software was released on 1 April 1998, and included  Simulator action/feature (e.g., the end of compilation, a schematic capture program and a netlister. At that time, the end of simulation, restart, or enter interactive mode) gEDA project website and mailing lists were also set up.  User-defined system task or function execution Characteristics:  Originally, the project planned to also write a PCB Steps required writing a C function and interfacing it with layout program a Verilog simulator:  Write a function in C

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 Associate the C function with a new system task For the addition of this functionality changes need to be made in the source code. For this bug the scheduler.cc is the  Register a new system task part of the source code where changes are needed. An event  Invoke system tasks queue is used for scheduling the active, inactive, and non- blocking and monitors assignments. Hence for inertial delay a second event queue needs to be added providing input to the event loop in the scheduler.cc which will automatically keep a check on the inertial delay of the design. The adding of this functionality leads to the more efficient design verification as the inertial delay will also be encountered.

Fig. 1. Example showing use of VPI

IV. EVENT QUEUE STANDARD The Verilog HDL is defined in terms of a discrete event execution model. A design has a large number of threads Fig. 2. Example showing inertial delay support without VPI connections for execution or processes. Objects that can have state can be evaluated and respond to the changes in the The inertial delay support is present in the Icarus Verilog outputs with respect to the changes in the inputs are called version 0.9.6 without the use of VPI, whereas when the VPI is Processes. Modules, primitives, initial and always procedural used than the inertial delay is not supported by the tool. Hence blocks, continuous assignments, asynchronous tasks, and this is one of the bug present in the version 0.9.6. procedural assignment statements are all included in a process. VI. CONCLUSION Update event: Change in value of a every net or variable in the circuit being simulated and named event as well. The closed file structures are a real challenge for the startup companies as they are expensive and the bug-fixes as Evaluation event: Processes have sensitivity for update well as the adding of functionality is not possible, in such events. All the processes that are sensitive to that event are scenario the company needs to change the whole software. On evaluated in an arbitrary order when an update event is the other hand open source EDA tools are of great importance, executed. Process evaluation is also an event. it provides its source code for the users to make changes and use it. Simulation time: It is the time value maintained by the simulator for modeling the actual time it would take for the The availability of the source code leads to the faster circuit in simulation. development of the tool. Icarus Verilog is a very strong simulation tool; the synthesis part is being worked on. Icarus Scheduling an event: Events occur at different times slots, Veilog also has a graphical support in the form of GTKwave so in order to keep track of the events and to have a surety viewer. So, open source EDA tools are cost-effective, less that they are processed in the correct order, the events are time consuming, user friendly with a lot of fun learning as kept on an event queue, as ordered by simulation time. Putting well. an event on the queue is called scheduling an event. REFERENCES V. VPI FOR INERTIAL DELAY IN ICARUS VERILOG VERSION [1] URL: http://opencircuitdesign.com/qflow/welcome.html 0.9.6 [2] URL: http://blog.engineersimplicity.com/2008/11/open-source- This is one of the functional bugs in the 0.9.6 released eda.html version. VPI (Verilog Procedural Interface) is used to invoke [3] URL: http://opencircuitdesign.com/qflow/welcome.html the C functions from Verilog or vice-versa. Inertial delay is [4] URL:http://ubuntu-artists.deviantart.com/journal/8-Advantages-of- basically the gate delay associated with the design. Icarus using-Linux-overWindows-291681914 Version 0.9.6 does not provide the VPI support for inertial [5] URL: ]http://iverilog.icarus.com/ delays i.e. it does not consider the inertial delays associated [6] URL: https://sites.google.com/site/iverilog/support/support-providers with the design when interfacing with the other tools. [7] URL: http://opencores.org/opencores,tools

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