Communications Design Communications Hardware

Hybrids drive interfaces USB 3.0 and PCIe 3.0 are set to play an embedded role in mobile devices. By Roy Rubenstein.

new class of digital has been Fig 1: Adapting PCI express for use with MIPI M-PHY unveiled by and Samsung. Featuring Awireless technology and running the open Super speed interchip (SSIC) source Android operating system, the screens could be mistaken for smartphones. xHCI The development highlights how hybrid products are being created through wireless ics PCI express Other MIPI being embedded into existing consumer devices. USB SS protocol protocols Android cameras can transmit high resolution photos and video directly to social media sites without needing an intermediary pc or tablet. MIPI M-PHY Moreover, mobile devices are driving wired interface developments, including the Universal Serial Bus (USB) and PCI Express (PCIe), more commonly associated with moving heavy data PCIe supports single lanes, like USB, or x2, x4, around the mobile application processor, with payloads over computing backplanes. x8 or x16 lane configurations. While it can go to 32 several MIPI point to point interfaces defined. USB has long been embraced by mobile lanes, this is rarely needed. The next generation of These include the link between the mobile consumer devices for downloading music and the standard – PCIe v4.0 – will support 16Gbit/s application processor and the baseband video and for offloading content. Downloading lanes and will be available from 2016. processor, the link to the device’s camera sensor music and video onto the device remains a USB 3.0 and PCIe 3.0 are set to play an – the latest being CSI3, which supports 20Mpixel requirement but, with Wi-Fi and faster mobile data embedded role within mobile devices. The sensors – and the DSI-2 display interface. services, content is increasingly streamed to the SuperSpeed InterChip (SSIC) interface is based on In particular, two physical (PHY) devices – D- device. However, with 8Mpixel cameras now USB 3.0 and is the follow on to the High Speed PHY or the M-PHY – are used by MIPI. M-PHY is the commonplace on smartphones, the offload InterChip (HSIC) interface that connects ics within faster of the two (up to 5.8Gbit/s, compared to D- requirements of high resolution digital images mobile devices. HSIC, based on USB 2.0, operates PHY’s 1Gbit/s). M-PHY links the handset’s and video continue to grow. at 480Mbit/s. application processor to the radio, display and USB 3.0 will appear in handsets this year, While PCI-SIG is translating PCIe 3.0 for use camera sensor, as well as supporting the low supporting 5Gbit/s. USB 3.0 also handles more within mobile devices, it has no legacy within the latency interface (LLI) for memory. And it is the power; 4.5W, compared to the 2.5W of USB 2.0, sector, unlike USB. M-PHY on which the USB 3.0 based SSIC and PCIe enabling faster charging. PCIe 3.0, meanwhile, Handsets use the Mobile Industry Processor 3.0 protocols will run. runs at 8Gbit/s and is the standard I/O bus for Interface (MIPI) Alliance’s interfaces developed The motivation is to benefit from the huge servers, workstations, pcs and amount of software and applications developed laptops. “All those applications for USB and PCIe, while running them on M-PHY, need to connect to I/O media, which has a lower power consumption than the whether it is Ethernet, graphics, USB or PCIe PHYs. storage, communications or “There is tremendous [PCIe] software Infiniband,” said Al Yanes, developed over the last decade,”said Mark Fu, president of the PCI Special senior director marketing at Cypress Interest Group (PCI-SIG). Semiconductor. When PCIe was developed, care was taken that existing PCI software would work Nikon’s CoolPix S800c features wireless connectivity, allowing over the new standard. “The beauty of PCI and instant upload of images and videos. PCIe is that, at the software level, it is

www.newelectronics.co.uk 22 January 2013 29 Communications Design Communications Hardware

transparent,” said Fu. “Everything has been worked out at the physical layer.” The USB and PCIe groups, working with the MIPI-Alliance, seek the same goal. A Gear 1, single lane M-PHY consumes a quarter of the power of a USB 3.0 PHY, while offering a speed of 1.25 to 1.45Gbit/s. “You get power reduction and [die] area reduction, but still have plenty of throughput,” said Eric Huang, senior product marketing manager at Synopsys.

Gearing up Two faster M-PHY Gears were defined by the MIPI Alliance in 2012: Gear 2 is a single lane at 2.5 to 2.9Gbit/s, and Gear 3 is a single lane at up to 5.8Gbit/s. “This [Gear 3] is faster than USB 3.0, which is at 5Gbit/s,” said Huang. “This is good The camera blends an Android based mobile phone with a 16.3Mpixel camera because you don’t want to be the [speed] bottleneck, but you do want to provide the lower power PHY for mobile, but chose instead to The Wi-Fi chip will need a USB 3.0 PHY and a minimum power.” The power consumption for the port PCIe onto M-PHY. PCIe 3.0 PHY, whilst supporting SSIC and PCIe 3.0 5.8Gbit/s M-PHY is 70% less than that drawn by “The migration with PCIe will increase the over M-PHY. This will allow the chip maker to the USB 3.0 PHY. adoption of M-PHY and will allow expansion into target its product as add on after sales to tablets A PHY adaptor layer, known as the PIPE 3.0 to other areas, for instance [for] the display,” said and laptops as well as within embedded mobile M-PHY bridge, is needed for the SSIC standard to Bob Feng, senior technical marketing manager at designs. run on M-PHY. The bridge translates the USB 3.0 Xilinx. “There has been tons of software Ultimately, the work being undertaken by the protocol onto the M-PHY hardware. The same applications/drivers written for PCIe based display two groups and the MIPI Alliance will enable the strategy is being pursued by the PCI-SIG to run controllers. Having MIPI with mapping of PCIe will multiplexing of an M-PHY to support either the PCIe 3.0 protocol on M-PHY. Here, a logical PHY help those applications/drivers to be leveraged.” standard, thereby saving PHY hardware. – the equivalent of the bridge – translates Huang views the SSIC and PCIe developments Huang believes SSIC is at least a year ahead between PCIe 3.0 and M-PHY. for mobile as competing ventures. That said, a Wi- over PCIe 3.0 running over M-PHY. “If SSIC takes “Our [PCIe 3.0] PHY is designed for servers Fi chip developer will need to support both. “I [ as off, it could crowd out the mobile PCI Express.” and pcs and it runs fast,” said Yanes. “Obviously, a chip maker] am going to put on as many Synopsys says it will start testing SSIC as for mobile and handhelds, the focus is on low interfaces as I can so that I can get the chip into soon as it gets its hands on the first M-PHY power.” PCI-SIG thought about developing its own the most products,” said Huang. based silicon. It is aware of at least a dozen chip design starts featuring SSIC in 2013, both mobile Fig 2: SSIC in applications processors and wireless modules application processors and connecting ics. “Maybe in 2014, customers will have the parts, Wireless module with real products in 2015,” said Huang. Cypress’ Fu also believes it will take time for Apps processor Baseband rf PCIe to be adopted within mobile devices. “We talk USB 3.0 USB 3.0 USB 3.0 USB 3.0 to a lot of customers in mobile and PCIe is not USB host PHY PHY device something they are constantly considering as a SSIC future interface,” said Fu. “But the jury is still out.” USB 3.0 USB 3.0 Meanwhile, Yanes said the PCI-SIG group, host device working with the MIPI-Alliance, hopes to have the PCIe 3.0 mobile specification done in the first

MIPI M-PHY MIPI M-PHY MIPI MIPI MIPI M-PHY MIPI M-PHY MIPI 4DigRF MIPI LLI LLI 4DigRF MIPI quarter of 2013.

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