EECS 242 Lecture 26 Prof. Ali M. Niknejad Outline

Injection Locking EECS 242 Lecture 26 Prof. Ali M. Niknejad Outline

• Injection Locking - Adler’s Equation (locking range) - Extension to large signals • Examples: - GSM CMOS PA - Low Power Transmitter - Dual Mode Oscillators - Clock distribution • Quadrature Locked Oscillators • Injection locked dividers

Ali M. Niknejad University of California, Berkeley Slide: 2 Injection Locking

http://www.youtube.com/watch?v=IBgq-_NJCl0

• Injection locking is also known as frequency entrainment or synchronization • Many natural examples including - pendulum clocks on the same wall observed to synchronize over time - ﬁreﬂies put on a good light show • Injection locking can be deliberate or unwanted

Ali M. Niknejad University of California, Berkeley Slide: 3 Injection Locking Video Demonstration

http://www.youtube.com/watch?v=W1TMZASCR-I • Several metronomes (similar to pendulums) are initially excited in random phases. The oscillation frequencies are presumably very close but vary slightly due to manufacturing imperfections • When placed on a rigid surface, the metronomes oscillate independently. • When placed on ﬂexible table with “springs” (coke cans), they couple to one another and injection lock.

Ali M. Niknejad University of California, Berkeley Slide: 4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 1415 A Study of Injection Locking and Pulling Unwanted Injectionin Oscillators Pulling/Locking Behzad Razavi, Fellow, IEEE

One of Abstract—the difficultiesInjection locking characteristics in designing of oscillators area de- • rived and a graphical analysis is presented that describes injection fully integratedpulling in time and transceiver frequency domains. An identityis obtained from phase and envelope equations is used to express the requisite os- exactlycillator due nonlinearity to pulling and interpret / phasepushing noise reduction. The behavior of phase-locked oscillators under injection pulling is also • If the injectionformulated. signal is strong Index Terms—Adler’s equation, injection locking, injection enough,pulling, it will oscillator lock nonlinearity, the oscillatorsource. pulling, quadrature Otherwiseoscillators. it will “pull” the source and produce unwanted modulation NJECTION of a periodic signal into an oscillator leads In the Ifirstto interesting example, locking orthe pulling transmitter phenomena. Studied by • Adler [1], Kurokawa [2], and others [3]–[5], these effects have is lockedfound to increasingly a XTAL greater importancewhereas for they the manifest them- receiverselves is in locked many of today’s to transceivers the data and frequency clock. synthesis techniques. UnwantedThis paper coupling describes new (package, insights into injection locking and substrate,pulling Vdd/Gnd) and formulates the behaviorcan cause of phase-locked oscillators under injection. A graphical interpretation of Adler’s equation pulling.illustrates pulling in both time and frequency domains while an identity derived from the phase and envelope equations • A PA isexpresses a classic the required source oscillator nonlinearityof trouble across the lock in a direct-conversionrange. transmitter Section II of the paper places this work in context and Fig. 1. Oscillator pullingSource: in (a) broadband [Razavi] transceiver and (b) RF transceiver. Section III deals with injection locking. Sections IV and V respectively consider injection pulling and the required oscil- Injection locking becomes useful in a number of applica- lator nonlinearity. Section VI quantifies the effect of pulling tions, including frequency division [8], [9], quadrature genera- on phase-locked loops (PLLs) and Section VII summarizes the tion [10], [11], and oscillators with finer phase separations [12]. experimental results. Injection pulling, on the other hand, typically proves undesirable. For example, in the broadband transceiver of Fig. 1(a), Ali M. Niknejad University of California, Berkeley the transmit voltage-controlled oscillator, , is lockedSlide: to I. GENERAL CONSIDERATIONS 5 a local crystal oscillator whereas the receive VCO, , is Oscillatory systems are generally prone to injection locking locked to the incoming data and hence potentially a slightly or pulling. As early as the 17th century, the Dutch scientist different frequency. Thus, the two oscillators may pull each Christiaan Huygens, while confined to bed by illness, noticed other as a result of coupling through the substrate. Similarly, that the pendulums of two clocks on the wall moved in unison if the high-swing broadband data at the output of the transmitter the clocks were hung close to each other [6]. He postulated that may pull and as it contains substantial energy in the coupling of the mechanical vibrations through the wall drove the vicinity of their oscillation frequencies. the clocks into synchronization. It has also been observed that Fig. 1(b) depicts another example of undesirable pulling. The humans left in isolated bunkers reveal a “free-running” sleep- power amplifier (PA) output in an RF transceiver contains large wake period of about 25 hours [7] but, when brought back to spectral components in the vicinity of , leaking through the the nature, they are injection-locked to the Earth’s cycle. package and the substrate to the VCO and causing pulling.

II. INJECTION LOCKING Manuscript received December 16, 2003; revised March 17, 2004. Consider the simple (conceptual) oscillator shown in Fig. 2, The author is with the Department of Electrical Engineering, University of California, Los Angeles, CA 90095 USA (e-mail: [email protected]). where all parasitics are neglected, the tank operates at the res- Digital Object Identiﬁer 10.1109/JSSC.2004.831608 onance frequency (thus contributing no phase

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. */0&1)2(/$3(142/5Injection Locking is Non-Linear

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!"#"$%&''()) !*+$,-. • For weak injection, you get a response at both side-bands • As the injection is increased, it begins to “pull” the oscillator • Eventually, for large enough injection, the oscillation locks to the injection signal Ali M. Niknejad University of California, Berkeley Slide: 6 Injection Locking in LC Tanks 1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004 • Consider (a) a free-running oscillator consisting of an ideal positive feedback ampliﬁer and an LC tank. • Now suppose (b) we insert a phase shift in the loop. We know this will cause the oscillation frequency to (c) shift since the loop gain has to have exactly 2π phase shift (or multiples)

GmZT (ω0)=gmR =1

jφ0 Gme ZT (ω1)=1 Fig. 3. Phase difference between input and output for different values of and . jφ0 jφ0 Gme ZT (ω1) e− =1 | | Fig. 2. (a) Conceptual oscillator. (b)Source: Frequency [Razavi] shift due to additional phase which reaches a maximum of shift. (c) Open-loop characteristics. (d) Frequency shift by injection. ∠ZT (ω1)= φ0 − (3) shift), and the ideal inverting buffer follows the tank to create a total phase shift of 360 around the feedback loop. What hap- if Ali M. Niknejad University of California,pens if Berkeley an additional phase shift is inserted in the loop, e.g.,Slide: as 7 depicted in Fig. 2(b)? The circuit can no longer oscillate at (4) because the total phase shift at this frequency deviates from 360 by . Thus, as illustrated in Fig. 2(c), the oscillation frequency Depicted in Fig. 3(c), these conditions translate to a 90 angle must change to a new value such that the tank contributes between the resultant and , implying that the phase differ- enough phase shift to cancel the effect of . Note that, if the ence between the “input,” , and the output, , reaches a buffer and contribute no phase shift, then the drain current maximum of . To compute the value of cor- of must remain in phase with under all condi- responding to this case, we ﬁrst note that the phase shift of the tions. tank in the vicinity of resonance is given by (Section III-A) Now suppose we attempt to produce by adding a sinusoidal current to the drain current of [Fig. 2(d)]. If the am- (5) plitude and frequency of are chosen properly, the circuit indeed oscillates at rather than at and injection locking occurs. Under this condition, and must bear a phase and recognize from Fig. 3(c) that and difference [Fig. 3(a)] because: 1) the tank contributes phase at . It follows that , rotating with respect to the resultant current, , and 2) still remains in phase with and hence out (6) of phase with respect to , requiring that form an angle with . (If and were in phase, then would also be in phase with and thus with ). The angle formed between and is such that becomes aligned with (This result is obtained in [3] using a different approach.) We (and ) after experiencing the tank phase shift, , at . denote this maximum difference by , with the understanding In order to determine the lock range (the range of across that the overall lock range is in fact around .1 which injection locking holds), we examine the phasor diagram The dependence of the lock range upon the injection level, of Fig. 3(a) as departs from . To match the increasingly , is to be expected: if decreases, must form a greater greater phase shift introduced by the tank, the angle between angle with so as to maintain the phase difference between and must also increase, requiring that rotate coun- and at [Fig. 3(d)]. Thus, the circuit moves closer to terclockwise [Fig. 3(b)]. It can be shown that the edge of the lock range. As a special case, if , then (2) reduces to (1) (7) (2) 1We call the “one-sided” lock range.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. Injection Locking in LC Tanks [cont] • A phase shift in the tank will cause the oscillation frequency to change in order to compensate for the phase shift through the tank impedance. • The oscillation frequency is no longer at the resonant frequency of the tank. Note that the oscillation amplitude must also change since the loop gain is now different (tank impedance is lower) • Maximum phase shift that the tank can provide is ± 90° • In a high Q tank, the frequency shift is relatively small since 1.5

ω0 dφ Q = 0.5 2 dω

ω0 ∆φ ∆ω -0.5 ≈ 2 Q

-1

-1.5

9.25 · 108 9.5 · 108 9.75 · 108 1 · 109 1.025 · 109 1.05 · 109 1.075 · 109 1.1 · 109 Ali M. Niknejad University of California, Berkeley Slide: 8 1416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004

Phase Shift for Injected Signal

• It’s interesting to observe that if a signal is injected into the circuit, then the tank current is a sum of the injected and transistor current. • Assume the oscillator “locks” onto the injected current and oscillates at the same frequency. • Since the locking signal is not in general at the Fig. 3. Phase difference between input and output for different values of resonant center frequency, the tank introduces and . a phase shift Source: [Razavi] Fig. 2. (a) Conceptual oscillator. (b) Frequency shift due to additional phase which reaches a maximum of • In order for the oscillator loopshift. (c) gain Open-loop to characteristics. be equal (d) Frequency shift by injection. to unity with zero phase shift, the sum of the (3) current of the transistor andshift), the and injected the ideal inverting buffer follows the tank to create a currents must have the propertotal phase phase shift shift of 360 toaround the feedback loop. What hap- if compensate for the tank phasepens if shift. an additional phase shift is inserted in the loop, e.g., as depicted in Fig. 2(b)? The circuit can no longer oscillate at (4) • We see that the oscillator current,because the totaltank phase shift at this frequency deviates from 360 current, and injected currentby all. Thus,have as different illustrated in Fig. 2(c), the oscillation frequency Depicted in Fig. 3(c), these conditions translate to a 90 angle phases must change to a new value such that the tank contributes between the resultant and , implying that the phase differ- enough phase shift to cancel the effect of . Note that, if the ence between the “input,” , and the output, , reaches a buffer and contribute no phase shift, then the drain current maximum of . To compute the value of cor- of must remain in phase with under all condi- responding to this case, we ﬁrst note that the phase shift of the tions. Ali M. Niknejad University of California, Berkeley Slide: 9tank in the vicinity of resonance is given by (Section III-A) Now suppose we attempt to produce by adding a sinusoidal current to the drain current of [Fig. 2(d)]. If the am- (5) plitude and frequency of are chosen properly, the circuit indeed oscillates at rather than at and injection locking occurs. Under this condition, and must bear a phase and recognize from Fig. 3(c) that and difference [Fig. 3(a)] because: 1) the tank contributes phase at . It follows that , rotating with respect to the resultant current, , and 2) still remains in phase with and hence out (6) of phase with respect to , requiring that form an angle with . (If and were in phase, then would also be in phase with and thus with ). The angle formed between and is such that becomes aligned with (This result is obtained in [3] using a different approach.) We (and ) after experiencing the tank phase shift, , at . denote this maximum difference by , with the understanding In order to determine the lock range (the range of across that the overall lock range is in fact around .1 which injection locking holds), we examine the phasor diagram The dependence of the lock range upon the injection level, of Fig. 3(a) as departs from . To match the increasingly , is to be expected: if decreases, must form a greater greater phase shift introduced by the tank, the angle between angle with so as to maintain the phase difference between and must also increase, requiring that rotate coun- and at [Fig. 3(d)]. Thus, the circuit moves closer to terclockwise [Fig. 3(b)]. It can be shown that the edge of the lock range. As a special case, if , then (2) reduces to (1) (7) (2) 1We call the “one-sided” lock range.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. Injection Locked Oscillator Phasors

0 Itank Vtank = ItankZT (!1) Iosc Itank Itank = Iosc + Iinj

j 0 Iosce Iinj

Iinj 6 Iosc = 6 Vtank = 6 Itank + 0 • Note that the frequency of the injection signal determines the extra phase shift Φ0 of the tank. This is ﬁxed by the frequency offset. • The current from the transistor is fed by the tank voltage, which by deﬁnition the tank current times the tank impedance, which introduces Φ0 between the tank current/voltage. • The angle between the injected current and the oscillator current θ must be such that their sum aligns with the tank current. Ali M. Niknejad University of California, Berkeley Slide: 10 Injection Geometry B A B sin φ0 = Itank B Itank cos(π/2 θ) = sin(θ)= − Iinj Iosc Iinj sin φ0 = sin(θ) Itank

0 Iinj sin(θ) Iinj sin(θ) sin φ0 = jθ = Iosce + Iinj 2 2 | | Iosc + Iinj + 2 cos θIoscIinj !

Iinj • The geometry of the problem implies the following constraints on the injected current amplitude relative to the oscillation amplitude. • The maximum value of the rhs occurs at: I2 I2 Iinj osc inj Iinj cos θ = − sin θ = − sin φ0,max = Iosc ! Iosc Iosc

Ali M. Niknejad University of California, Berkeley Slide: 11 Locking Range • At the edge of the lock range, the injected current is orthogonal to the tank current. • The phase angle between the injected current and the oscillator is 90° + Φ0,max Itank • The lock range can be computed by noting that the tank phase shift is given by

2Q tan φ0 = (ω0 ωinj) ω0 − Iosc

2Q Iinj Iinj tan φ0 = (ω0 ωinj)= = ω0 − Itank I2 I2 0 osc − inj ! ω0 Iinj 1 (ω0 ωinj)= − 2Q I 2 osc Iinj 1 2 Iosc ! −

Maximum Locking Range Iinj Ali M. Niknejad University of California, Berkeley Slide: 12 Weak Injection Locking Range • Adler ﬁrst derived these results in a celebrate paper [Adler] under the conditions of a weak injection signal. • The results for a large injection signal were ﬁrst derived by [Paciorek] and then re-derived (as shown here) by [Razavi] Under weak injection: • I I inj ! osc Iinj sin φ0 sin(θ) ≈ Iosc

Iinj 2Q sin φ0 = sin(θ) tan φ0 = (ω0 ωinj) Itank ≈ ω0 −

2Q Itank sin(θ)= (ω0 ωinj) ω0 Iinj − • At the edge of the locking range, the angle reaches 90°, and the injected signal is occurring at the peaks of the output, which cannot produce locking (think back to the Hajimiri phase noise model) ω0 Iinj (ω0 ωinj)= − 2Q Itank

Ali M. Niknejad University of California, Berkeley Slide: 13 1418 IEEE JOURNALInjection OF SOLID-STATE Pulling CIRCUITS, VOL.Dynamics 39, NO. 9, SEPTEMBER 2004 Since , and , we have

(15) Source: [Razavi] If the current ﬂowing through the tank contains phase modula- Fig. 6. LC oscillator under injection. tion, i.e., , then the phase shift can• Suppose be now that the oscillator is under injection so that oscillator signal feeding the tank can be written as obtained by replacing in (15) with the instantaneous input fre- Equating this result to , we obtain quency, : VX = Vinj,p cos ωinjt + Vosc,p cos(ωinjt + θ)

V =(V + V cos θ) cos ω t V sin θ sin ω t (23) (16)X inj,p osc,p inj − osc,p inj This can be written as a cosine with a phase shift Valid for narrow-band phase modulation (slowly-varying• ), We also note from (19) that this approximation holds well for typical injection phenomena. Vinj,p + Vosc,p cos θ Vosc,p sin θ VX = cos(ωinjt + ψ) tan ψ = cos ψ Vinj,p + Vosc,p cos θ B. Oscillator Under Injection • Which allows us to write the output as Consider the feedback oscillatory system shown in Fig. 6, (24) Vinj,p + Vosc,p cos θ 1 2Q dψ where the injection is modeled as an additive input. The outputV = cos ω t + ψ + tan− ω ω out cos ψ inj ω 0 − inj − dt is represented by a phase-modulated signal having a carrier fre- ! " 0 ! #$# quency of (rather than ). In other words, the output is (25) assumed to track the input except for a (possiblyAli M. Niknejad time-varying) University of California, Berkeley Slide: 14 phase difference. This representation is justiﬁed later. The ob- (26) jective is to calculate , subject it to the phase shift of the tank, and equate the result to . It follows from (23), (24), and (26) that The output of the adder is equal to

(17) (27) (28) (18) Originally derived by Adler [1] using a somewhat different ap- The two terms in (18) cannot be separately subjected to the tank proach, this equation serves as a versatile and powerful expres- phase shift because phase quantities do not satisfy superposition sion for the behavior of oscillators under injection. here. Thus, the right-hand side must be converted to a single Under locked condition, , yielding the same result sinusoid. Factoring and deﬁning as in (9) for the lock range. If , the equation must be solved to obtain the dependence of upon time. Note that (19) is typically quite small because, from (28), it reaches a maximum of only . That is, varies slowly under pulling conditions. we write Adler’s equation can be rewritten as (20) (29) Since and , we have , Noting that , making a change of variable , and carrying out the inte- and hence gration, we arrive at

(30) (21)

Upon traveling through the LC tank, this signal experiences where .2 This paper introduces a a phase shift given by (16): graphical interpretation of this equation that confers insight into the phenomenon of injection pulling.

2Interestingly, is equal to the geometric mean of (the (22) difference between and the upper end of the lock range) and (the difference between and the lower end of the lock range).

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. Injection Pulling Dynamics [cont] • We have assumed that the phase shift through the tank is given by the simple expression derived earlier where the instantaneous frequency is dψ ω + dt

2Q dψ tan α ω ω ≈ ω 0 − − dt 0 ! " • If the injection signal is weak, then the previous result simpliﬁes to:

1 2Q dψ V = V cos ω t + ψ + tan− ω ω out osc,p inj ω 0 − inj − dt ! " 0 ! #$# • Which must equal to the output voltage, or the phase shifts must equal

1 2Q dψ ψ + tan− ω ω = θ ω 0 − inj − dt ! 0 " #$

Ali M. Niknejad University of California, Berkeley Slide: 15 Pulling [cont]

• These equations can be manipulated into a form of Adler’s equation:

dθ ω0 Vinj,p = ω0 ωinj sin θ dt − − 2Q Vosc,p

dθ ω0 Vinj,p = ω0 ωinj ωL sin θ ωL ! dt − − 2Q Vosc,p • This equation describes the dynamics of the phase change of the oscillator under injecting pulling. If we set the derivative to zero, we obtain the injection locking conditions (same as before). • Notice that maximum value of the rhs is quite small, which means that the rate of change of phase is • This equation can be used to study the behavior of locking signals outside the lock range. Note that this equation agrees with our graphical analysis: dθ =0 dt

Ali M. Niknejad University of California, Berkeley Slide: 16 Pull-In Process

1 1 ωL cos θ0 θ(t) = 2 tan− cot θ tanh (t t ) sin θ − 0 2 − 0 ! 0 " #$

1 ω0 ω1 θ0 = sin− − ωL

• θ0 is the steady-state phase shift between the injected signal and the active device signal and t0 is an integration constant that depends on the initial phase shift. • From this equation the lock-in time can be computed (it’s approximately an exponential process):

θL 2 1 1 sin θ0 tan 2 tL = tanh− − + t0 ωL cos θ0 ! cos θ0 " #$

Ali M. Niknejad University of California, Berkeley Slide: 17 Phase Noise in Injection Locked Systems

1422 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004

As illustrated in Fig. 12(b), if the input frequency deviates from , the resulting phase noise reduction becomes less pro- nounced. In fact, as approaches either edge of the lock range, drops to zero, raising the impedance seen by the noise current. In CMOS technology, it is difficult to rely on the phase noise reduction property of injection locking. Since the lock range is typically quite narrow and since the natural frequency of oscillators incurs significant error due to process variations and poor modeling, the locking may occur near the edge of the lock range, Fig. 14. Reduction of phaseSource: noise due [Razavi] to injection locking. thereby lowering the phase noise only slightly. For example, if the two-sided lock range is equal to % and the natural• Under fre- a lock, the phase of the oscillator follows the phase of quency of the oscillator varies by % with process andthe tem- injection signal. If a “clean” signal is used to lock a VCO, perature, then, in the worst case, the injection locking occursthen at the phase noise would improve up to the locking range. . It follows from (37) and the aboveAt obser- the edge of the lock, the injected signal cannot correct for vations that the impedance seen by the noise falls from• infinity to , yielding a 4.4-dB degradation in thethe phase phase noise since it injects energy at a 90° phase offset, noise compared to the case of . where the signal has a peak amplitude

VI. INJECTION PULLING IN PHASE-LOCKED OSCILLATORS The analysis in Section III deals with pulling in nominally Fig. 15. PLL under injection pulling. Ali M. Niknejad University of California, Berkeley Slide: 18 free-running oscillators, a rare case of practical interest. Since oscillators are usually phase-locked, the analysis must account The above result can now be used in a PLL environment. In for the correction poduced by the PLL. In this section, we as- Fig. 15, the PFD, CP, and loop ﬁlter collectively provide the sume the oscillator is pulled by a component at while phase- following transfer function: locked so as to operate at . We also assume that the oscillator control has a gain of and contains a small perturbation, (45) , around a dc level. Examining the derivations in Section III for a VCO, we ob- where the negative sign accounts for phase subtraction by the serve that (19) and (21) remain unchanged. In (22), on the other PFD. We therefore have hand, we must now add to . For small pertur- bations, can be neglected in the denominator of (46) and Substituting for in (44) and differentiating both sides with respect to time, we obtain

(41)

(47) Equating the phase of (41) to and noting that (24) and (26) can be shown to still hold, we have where . This reveals that the PLL behaves as a second-order system in its response to injection pulling. (42) Deﬁning

Fig. 15 shows a PLL consisting of a phase/frequency detector (48) (PFD), a charge pump (CP), and a low-pass ﬁlter ( and ), and the VCO under injection. Since with a low injection level, (49) the PLL remains phase-locked to , it is more meaningful to express the output phase as rather than . Thus, we have and (50) (43) (44) where denotes the phase of the transfer function at a frequency of .5 where it is assumed radian. This approximation is rea- 5A dual-loop model developed by A. Mirzaei arrives at a similar result but sonable if pulling does not excessively corrupt the PLL output. with a different value for the peak amplitude of the cosine [17].

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. 966 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 7, JULY 1999

Fig. 8. Microstrip balun.

964 Example: GSM ClassIEEE E JOURNAL PA OF SOLID-STATE CIRCUITS, VOL. 34, NO. 7, JULY 1999 Fig. 10. Output power and PAE versus frequency for and V.

Fig. 9. Output power, efﬁciency, and PAE versus supply voltage. Fig. 5. Illustration of the mode-locking concept.

10 and 5 mil, respectively. A single-ended signal at port 1 can be converted to differential signals at ports 2 and 3 or B. Mode-Locking Technique Fig. 11. Amplified GMSK modulated signal ( ) and the GSM vice versa. The edge-coupled microstrip lines and the discrete spectral emissionMode mask. lockingSource: refers [Tsai] to the condition in which an otherwise tuning capacitors are shown in the enlarged portion of Fig. 8. self-oscillating circuit is coupled and forced to run at the of thesame PAE in frequency this region as is an due input to the signal, progressively resulting more in a substantial VI. MEASUREMENT RESULTS prominentreduction input power in the term input in driving the PAE requirement. definition. At This 2-V is realized in Fig. 4. Schematic of the complete power amplifier. supply,each the PAE stage was of measured the amplifier to be by 48%. a pair of cross-coupled assisting A. Power-Amplifier Prototype Fig. 10 shows the output power and PAE at two different A 10-dBmLarge single-endedoutput stage input device was converted is hard to supplyto drivedevices, voltages (large asacross shown thecapacitance). range in Fig. of 5. frequencies The two where input the voltages are out differential• signals, using a commercial balun (Murata amplifierof is phase, mode as locked are the successfully. two output This voltages. locking range The is load impedance inductorsLDB20C500A1900),• andUse equivalent the andPA output then to applieddrive load, and to itself! the larger PA. capacitorsRF That’s power andmeasuredan oscillator,at the to be output 490 MHz, right? nodes centering is Yes. designed at about 1.9such GHz. that and run switches.was measured In fact, theat the switch 50- transistorsoutput ports. are Fig.often 9 maximized shows a inTo verifyin phase its potential to control in practical the composite communication switch. applica- As far as each half Use injection locking to inject phasetions, modulation. the mode-locking class-E Need PA was “off” tested with a Gaussian sizetypical to• reduce plot theof the on-resistance output power loss. versus The input, measured capacitance at of circuit is concerned, the operation is similar to the single-ended 1.98 GHz.switch The output to powerturn increases off transmission. from 49 mW to 1.0 minimumversion shift keying as shown (GMSK) in Fig.[21] modulated 1, except input for signal. two features. First, theseW transistors monotonically is as usually the supply tuned is swept out by from inductors. 0.6 to 2 V However, and GMSK and its close relative, Gaussian frequency shift keying at gigahertzis approximately frequencies, proportional beyond to a certain. The maximum transistor size the(GFSK),the are current constant originally envelope modulation circulating schemes at each in which tuned load is now inductanceused in thisvalues case required is determined for tuning by the may peak become drain toovoltage smallinformation to utilized is carried to assist in the switching phase variation of the otherof the half signal, circuit. Second, on chip, which is estimated to be slightly above 5 V at 2-V makingthe them capacitance well suited at to each switching input can power now amplification. be significantly reduced Ali M. Niknejadbe realizable. In addition, the large gate-to-drainUniversity of California, capacitance Berkeley Slide: 19 ofsupply, a transistor approaching can thepotentially drain-gate induce oxide breakdown strong output–input limit of Thesewithout modulation increasing schemes are the used overall by popular composite cellular switch and on-resistance. cordless telephone standards such as GSM ( ) and coupling.the technology. Also shown in Fig. 9 are the drain efficiency Because of its tuned nature, a mode-locked amplifier can (DE) and the power-added efficiency (PAE) DECT ( ). As an example, a random bit sequence Besides the input driving requirement, the single-ended operate only within a certain frequency range. This locking output power was modulated with the modulation parameter , circuit in Fig. 1DE discharges a large amount of current to ground, range is determined by simulations and experiments. supply power and then was applied to the PA. Fig. 11 shows the close-in output spectrum. No observable distortion was found in the or the silicon substrate,ouput once power perinput cycle. power This generates an PAE (2) signal,C. which Inductor remained Realization confined in the GSM spectral emission unwanted substrate noise componentsupply power at the same frequency specification over the full range of output power. as the desired signals, which is particularly undesirable in High- inductors are critical in the design of high-efficiency an integratedAs expected environment. form the switching To alleviate nature of the the PA, aforementioned the drain Besides the close-in modulation spectrum, the wide-band efficiency remains close to the optimum for most of the output noise performancepower amplifiers is another in whichkey aspect a large in modern amount digital of current circu- problems,power range, a series except of techniques for a slight reduction are proposed in the in low the supply followingcommunicationlates in applications. tuned LC networks. This is particularly These inductorstrue in high- may also carry section.voltage region, where the switching action of the transistors performancesubstantial systems direct such current, as GSM, necessitating in which the sizable spurious cross-sectional becomes less effective. The comparatively sharper decline emissionsarea of to the reduce transmitted loss and signals avoid that electromigration. fall in the receiving Unfortunately, a typical CMOS technology suffers from the lack of monolithic III. PA DESIGN AND IMPLEMENTATION high- inductors, largely due to the loss in substrate and metallization. Bondwires can handle substantial current with A. Differential Topology low loss and are therefore used to realize the critical induc- Fig. 4 shows a two-stage CMOS class-E power amplifier tors. Bondwire inductance, however, is sensitive to bonding designed to operate in the gigahertz frequencies. A fully geometry and the existence of neighboring bondwires, making differential configuration is used to alleviate the problem of accurate predetermination of the inductance values difficult. substrate coupling. In a fully differential configuration, current Fortunately, once the configuration for a particular inductance is being discharged to ground twice per cycle. This expels the value is known, it is rather repeatable in subsequent bondings. substrate noise component from the desired signal frequency to To realize the small inductance values shown in Fig. 4, short twice the signal frequency, resulting in a reduced interference. bondwires with currents running out of phase are placed In addition, for the same supply voltage and output power, adjacent to each other in order to take advantage of the the current passing through each switch in a differential negative mutual inductance. Common bondwire metals include configuration is lower than its single-ended counterpart. This gold and aluminum. Gold is generally preferred because of allows a smaller transistor to be used on each side without its higher conductivity and flexibility. This allows higher increasing the total switch loss. A differential configuration bondwires with shorter physical lengths to be bonded for a alone, however, might not provide sufficient relief to the given die height. The option of gold wires, however, was transistor’s input driving requirement, especially when large unavailable at the time of this implementation. on/off driving signals are needed. To mitigate this problem, A pair of bondwires and an off-chip capacitor were used the technique of mode locking is used. to realize an output matching network, which matches each $%&'()*+!,-./0!12*31!(2'(!'!12*4(54!6*789)+!():5!45%&)451!'!6'4;54!6*789)+!4'+;5!!

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! "# A 9.6GHz/4.8GHzA 9.6GHz/4.8GHz Dual-Mode Dual-Mode Voltage-Controlled Voltage-Controlled Oscillator with Injection Locking Oscillator with Injection Locking Zhiming Deng, !"#$%&"'(%)*%+, ,---, and Ali M. Niknejad, (%)*%+, ,--- Zhiming Deng, !"#$%&"'(%)*%+, ,---, and Ali M. Niknejad, (%)*%+, ,---

AbstractAbstract – We – present We present a new a new voltage-controlled voltage-controlled Consider Consider the the interconnection interconnection of of two two /0 /0 tanks tanks as as A 9.6GHz/4.8GHz Dual-Modeoscillatoroscillator (VCO) (VCO) Voltage-Controlled structure structure exhibiting exhibiting simultaneous simultaneous shown shown in Fig.in Fig. 1. Each1. Each tank tank is isa parallela parallel /0 /0 circuit, circuit, but but they they oscillation at two distinct frequencies while sharing a are coupled together through a coupling capacitor 0 . By oscillation at two distinct frequencies while sharing a are coupled together through a coupling capacitor 011. By single single bias current. bias current. These These oscillation oscillation modes modes can can be bevarying varying the the value value of ofcoupling coupling capacitor, capacitor, different different dynamic dynamic Oscillator with Injectionmutuallymutually locked locked by Locking by in jection injection locking. locking. The The phenomenon phenomenon can can be beobserved. observed. characteristic characteristic of coupled of coupled LC tanksLC tanks are are analyzed. analyzed. A A prototypeprototype of a of 9.6GHz/4.8GHz a 9.6GHz/4.8GHz dual-mode dual-mode voltage voltage Zhiming Deng, !"#$%&"'(%)*%+, ,---controlled,controlled and oscillator Ali oscillator M. (DMVCO) Niknejad, (DMVCO) is fabricated(%)*%+ is fabricated , in ,--- ain a 0.18 µm0.18 CMOSµm CMOS process process to demons to demonstratetrate the feasibilitythe feasibility of of the idea.the Theidea. DMVCO The DMVCO has a has tuning a tuning range range of 5% of 5%and and the phasethe phasenoise isnoise -109dBc/Hz is -109dBc/Hz measured measured at 1MHz at 1MHz offset offset Abstract – We present a new voltage-controlledfrom from the locked theConsider locked half the half mode interconnection mode 4.8GHz 4.8GHz reference. reference. of two A A /0 tanks as oscillator (VCO) structure exhibiting simultaneousconventional shownconventional in single Fig. single mode1. Each mode VCO tank VCO is alsois is a alsoparallel fabricated fabricated /0 as circuit, as but theyFig.1 Capacitive-coupled parallel /0 tank reference to show the power saving advantage of the Fig.1 Capacitive-coupled parallel /0 tank oscillation at two distinct frequencies while sharing areference are coupled to show thetogether power throughsaving advantage a coupling of the capacitor 01. By structure.structure. The most important feature for this coupled /0 tank single bias current. These oscillation modes can be varying the value of coupling capacitor,Example: different dynamicTheDual most important Mode feature for VCO this coupled /0 tank is thatis that it inherently it inherently has has two two resonant resonant frequencies. frequencies. A A simple simple mutually locked by injection locking. The Indexphenomenon Index Term Term – canCoupled – beCoupled observed. LC LC tank, tank, dual-mode, dual-mode, calculation yields the following expression for the two voltage-controlled oscillator, injection locking. calculation yields the following expression for the two characteristic of coupled LC tanks are analyzed. Avoltage-controlled oscillator, injection locking. resonant frequencies resonant frequencies prototype of a 9.6GHz/4.8GHz dual-mode voltage 2 " ! 2 % ! I. INTRODUCTION $ #2 "2 ! $ # 2 2% ! Eq. 1 controlled oscillator (DMVCO) is fabricated in a I. INTRODUCTION $ #/ 2 22 $ 3# 2 22 Eq. 1 / 22 3 3 22 3 0.18µm CMOS process to demonstrate the feasibility of Generation of a low phase noise spectrally pure tone where 3 3 Generation of a low phase noise spectrally pure tone where 2 has been a major challenge for communication circuits + ( 2 the idea. The DMVCO has a tuning range of 5% and 03 03 01 022 03 Eq. 2a has beenfabricated a major in challenge CMOS technolo for communicationgy. The lack circuitsof a high Q !+# ) " " % ( & % 4 2 0)3 / 03 / 01/ 02/ & 0/3 / Eq. 2a the phase noise is -109dBc/Hz measured at 1MHz offsetfabricated stable in resonatorCMOS technolo necessitatesgy. Thehigh lackpower of consumptiona high Q in ! # ) * "1 "2 %2 &1 '% 4 1 2 * /1 /2 /2 /1 ' /1/2 from the locked half mode 4.8GHz reference. Astable resonatorthe form of necessitates a phase-locked high loop power frequency consumption synthesizer. in As 03 03 01 0 2 Eq. 2b 2 2 # % % % 03 / 03 / 01/ 0 2/ conventional single mode VCO is also fabricated asthe formwe of move a phase-locked to higher frequencies, loop frequency the problem synthesizer. is exacerbated As 2 # %1 %2 %2 1 Eq. 2b Fig.1 Capacitive-coupled parallel /0 tank 2 we movedue to to higher the increasing frequencies, power the co problemnsumption is ofexacerbated the prescalar /1 /2 /2 /1 23 # 0301 % 0302 % 0102 Eq. 2c reference to show the power saving advantage of thedue to frequencythe increasing dividers power in the co nsumptionfrequency synthesizer. of the prescalar Since Fig.2 23 shows# 0301 the% 0 differential302 % 0102 dual-mode /0 tank Eq. used 2c structure. frequencydigital dividers logic is in often the frequency employed synthesizer.to perform this Since task, the The most important feature for this coupledin Fig.2/0this design.tank shows Thethe differential/0 tank core dual-mode is simply the/0 differentialtank used digital powerlogic isconsumption often employed increases to perform as we operate this task, at a the closer is that it inherently has two resonant frequencies.in thisversion A design.simple of Fig.The 1./0 The tank components core is simply values the aredifferential carefully power fractionconsumption of the increasesprocess .T .as Injection we operate locked at a dividers closer Index Term – Coupled LC tank, dual-mode, calculated and selected for desired resonant frequencies. /1 calculationconsume less power, yields but the have followi narrow lockingng expression range and version for the of two Fig. 1. The components values are carefully fraction of the process .T. InjectionA coupled locked dividers tank has twoand resonant / are on chipmodes. spiral inductors. The center tap voltage-controlled oscillator, injection locking. require an additional oscillator. calculated2 and selected for desired resonant frequencies. /1 consumeresonant less power, frequencies but• have narrow locking range and connection of the two inductors is used as the dc current While multimodeFrom oscillator each have been port proposed of theand oscillator, /2 are on chip one spiral mode inductors. is The center tap require an additional oscillator. path which allows the active circuits presented at the two before [1] [2], in this paper we present a coupled /0 connection of the two inductors is used as the dc current (a) While multimode oscillator2 dominant." ! have been proposed2 % ! ports to share the same dc current. By terminating each I. INTRODUCTION oscillator with dual frequency2 outputs that naturally2 path which Eq. allows 1 the active circuits presented at the two before [1] [2],$ in/ this# paper we present a coupled$ 3 # /0 port with a negative resistance, generated for example by a provides a technique 2for2 combining the VCO and a2 2 ports to share the same dc current. By terminating each oscillator with dual frequencyIn outputs 3a fully that differential naturally 3 versioncross-coupled shown active todevice, the both oscillation modes can be frequency divider •in a phase-locked loop. Typically, we port with a negative resistance, generated for example by a provides a technique for combiningright, thethe VCO impedance and a variationactivated at thewith same frequencytime. This is the basic idea behind the Generation of a low phase noise spectrally pure tone whereuse the higher mode to drive a mixer and the lower mode tocross-coupled active device, both oscillation modes can be frequency divider in a phase-locked loop. Typically,2 we dual-mode oscillator. has been a major challenge for communication circuits drive the PLL dividers.is shown. 2 activated at the same time. This is the basic idea behind the Fig. 3 Schematic of dual-mode VCO with injection locking use the higher mode to drive+ 03 a mixer03 and01 the0 lower2 ( mode0 to3 The coupled /0 network can also benefit phase noise ! # ) " " % & % 4 dual-mode Eq. oscillator. 2a fabricated in CMOS technology. The lack of a high Q drive the PLL dividers. ) Can we build& an oscillatorperformance. that sustains Analytical analys bothis shows that this higher II. DUAL-MODE/ VCO/ WITH/ INJECTION/ L/OCK/ The coupled /0 network can also benefit phase noise stable resonator necessitates high power consumption in •* 1 2 2 1 ' 1 2 order resonant network can enhance the equivalent tank modes?DESIGN performance.quality factor Analytical thereby analys improvingis shows the phasethat this noise. higher An the form of a phase-locked loop frequency synthesizer. As 03 03 01 0 2 Eq. 2b II. D UAL-MODE2 VCO# WITH% I%NJECTION% LOCK orderintuitive resonant way network of understanding can enhance this the approach equivalent is that tank a 2 (b) we move to higher frequencies, the problem is exacerbated The authors are withD the/ESIGN1 Department/ 2 /of2 Electrical/1 Engineeringquality “zero” factor is designed thereby at the improving vicinity of thethe resonant phase noise. frequency, An Fig. 2 (a) Differential dual-mode !" tank (b) Port due to the increasing power consumption of the prescalar and Computer Science, University of California at Berkeley, intuitive shown Eq. wayin Fig.2c of 2(b), understanding so that it increases this approach the roll-off is rate that from a The authorsBerkeley, are CAwith 947202 the3 # Department USA.030 1Email:% 0 of3 [email protected] Electrical2 % 0102 Engineering impedance over frequency frequency dividers in the frequency synthesizer. Since Ali M. Niknejad University“zero”the peakisof California,designed resulting Berkeley at thein a vicinsharperity oftransition the resonant and a frequency,narrower Slide: 21 and ComputerFig.2 Science, shows University the differential of California atdual-mode Berkeley, /0shown tank in Fig.used 2(b), so that it increases the roll-off rate from digital logic is often employed to perform this task, the Berkeley, CA 94720 USA. Email: [email protected] pass band. in this design. The /0 tank core is simply thethe differential peak resulting in a sharper transition and a narrower power consumption increases as we operate at a closer Fig.3 shows the proposed dual-mode VCO version of Fig. 1. The components values are carefully architecture. Cross-coupled transistor pairs, both NMOS fraction of the process .T. Injection locked dividers calculated and selected for desired resonant frequencies. /1 and PMOS, provide negative resistance to compensate the consume less power, but have narrow locking range and loss in the tank. Both of them are necessary to excite and and /2 are on chip spiral inductors. The center tap require an additional oscillator. maintain the simultaneous oscillation of the two modes. At connection of the two inductors is used as the dc current Fig. 4 The operation of injection locking (left) and the While multimode oscillator have been proposed the stable oscillation state, two modes are observed at each corresponding linear time-varying model (right) path which allows the active circuits presented at the two before [1] [2], in this paper we present a coupled /0 port, one strong primary mode and one weak secondary ports to share the same dc current. By terminating each mode. oscillator with dual frequency outputs that naturally port with a negative resistance, generated for example by a Since the active circuits are nonlinear blocks, the two provides a technique for combining the VCO and a cross-coupled active device, both oscillation modes can be modes will mix and generate inter-modulation frequency frequency divider in a phase-locked loop. Typically, we components. To achieve spectral purity, injection locking activated at the same time. This is the basic idea behind the use the higher mode to drive a mixer and the lower mode to is used to entrain the frequency of one mode to half of the dual-mode oscillator. frequency of the other mode. The method of injection drive the PLL dividers. The coupled /0 network can also benefit phase noise locking is based on [3]. A periodically on-and-off switch is performance. Analytical analysis shows that this higher presented at the low frequency port 1 and this switch is II. DUAL-MODE VCO WITH INJECTION LOCK controlled by the high frequency mode from port 2. If the order resonant network can enhance the equivalent tank locking condition is satisfied then the low frequency can be DESIGN quality factor thereby improving the phase noise. An injection locked to half of the high frequency. The locking intuitive way of understanding this approach is that a range analysis uses a linear periodically time-varying Fig. 5 Safe second harmonic level to avoid The authors are with the Department of Electrical Engineering “zero” is designed at the vicinity of the resonant frequency, model. This model is used to determine the start-up threshold-crossing disturbance at low frequency mode and Computer Science, University of California at Berkeley, condition of the injection-locked signal instead of shown in Fig. 2(b), so that it increases the roll-off rate from phase shift value Berkeley, CA 94720 USA. Email: [email protected] examining its steady state [4]. Our model is shown in Fig. the peak resulting in a sharper transition and a narrower 4. By examining both amplitude and phase requirements, *!,$ %)& + cos(2'!+ ) *$) *( )cos(2' ) 2! + )) Eq. 4 an expression for locking range can be derived as There is an upper limit for |!| so that the second ( ' harmonic does not disturb the threshold-crossing of the #! " %1 $ ! Eq. 3 4& # fundamental component. As this upper limit depends on $ , Fig. 5 gives a plot of maximum |!| over different $ A problem called threshold-crossing disturbance arises due to the coexistence of the two modes at the same derived from numerical analysis. To guarantee save port. In the application of a phase-locked loop frequency operation, |!| should be lower than the global maximum synthesizer, the low frequency mode signal is sent to a of -6dB, shown in dotted line. frequency divider, which is often digital logic and has a threshold voltage level for logic transition. A low III. EXPERIMENT RESULTS frequency mode signal can be represented as the sum of the fundamental and second harmonic signal. As shown in Eq. The chip is fabricated in 0.18µm CMOS process. A 4, ! represents the relative amount of high frequency mode die photo is shown in Fig.6. The measurement results were leakage at the low frequency port and $ is an arbitrary obtained by probing the chip and using the Agilent E4440A spectrum analyzer. Table I gives a summary of the DMVCO performance.

Dual Mode VCO (cont)

Source: [Deng]

• Two cross-coupled pairs are used to sustain each mode by providing sufﬁcient negative resistance. The PMOS side is running at a lower frequency whereas the NMOS side runs at the higher frequency. • Transistors M3a/M3b are used for injection locking. Ali M. Niknejad University of California, Berkeley Slide: 22 Dual Mode VCO Spectrum

• Without injection locking, each mode runs independently. The frequencies are not integrally related, so the unlocked spectrum contains not only the two modes and harmonics, but also every intermodulation component. • When the modes are locked, the intermodulation components disappear. The high frequency VCO is divided by two in this conﬁguration. • More on injection locking dividers to come... Ali M. Niknejad University of California, Berkeley Slide: 23 Chapter 2: Overview of Electrical Clock Distribution 14 ClockChapter Distribution 2: Overview of Electrical Clock Distribution 16

PLL

Figure 2.7: A clock grid driven by buffers. Figure 2.6: A buffered H-tree. Source: [Mahony] clock distribution is completely symmetric to simplify the2.3.1.3 design Local and provide nominally low skew (assuming •no Deliveringloading variations). a clock The most in acommonly largeThe final chip used level topologyofis a clocka major distribution is a buff- challenge network is the localand level, a bigwhich is the portion of the network that follows the clock pin. This network drives the final loads of the clock dis- ered H-tree [7] which issource shown in Figureof power 2.6. H-trees consumption. are an extremely Figures popular choiceof merit at include skew, jitter, and power. tribution and hence consumes the most power. As a rule of thumb, the power at the local this level of the clock distribution because they are a simple pattern that efficiently and • A buffered H-tree or alevel grid is about are one common order of magnitude approaches. larger than the power The in the gridglobal and regional lev- symmetrically covers largehas areas. skew H-trees and minimize larger thecapacitance. elsdistance combined, from with the the PLL only to notablethe fur- exceptions being clock networks that use a thest clock pins (without using diagonal traces) and therebylow-impedance minimize grid atthe the interconnectregional level [2]. latency. The number of buffer levels within the global networkThe layout − which of the localalso grid determines is generally included in the design of the macro block and is not the responsibility of global and regional clock network designer. Because of its rela- the latency − depends on the signal dispersion, loss and on the required power fanout. tively limited span, it is sufficient to use automatic layout for this portion of the clock Ali M. Niknejad University of California, Berkeley Slide: 24 network. Due to the irregular nature of most macros, the layout is generally a nonsymmet- 2.3.1.2 Regional rical tree which may be length-matched depending on the skew goals for the distribution. The regional clock level is defined to be the distributionFurthermore, from the the sector clock distributed buffers to to thethe clocked storage elements is often a derivative clock generated locally from the global clock signal. clock pins. As clock frequencies increase, the sector buffers (and hence the regional level) tend to be pushed lower into the clock hierarchy to reduce dispersion and achieve faster edge rates at the clock pins [16]. The regional clock network is sometimes categorized as part of the global clock distribution, but, for the purposes of highlighting how different topologies are used at different levels, it is separated into its own level for this work. This level is the middle ground between global and local clock distribution; it does not span as much area as the global level and it does not drive as much load − or consume nearly as much power − as the local level. 2.5: Directions in global clock distribution 25

note that the tree in Figure 2.12 is not resonant and that resonance is not a requirement to generate standing waves. The measured skew for 160MHz system-level clock distribution described in [41] is 0.17ns (2.7% τclk ), which is an order of magnitude less than the skew that would be expected based on the delay between points on the clock network. Despite its advantages, however, an analysis of the relationship between skew and interconnect loss indicates that wire loss will limit the use of standing-waves in an on-chip, global clock distribution. This type of clock distribution also requires limiting amplifiers to con- Clock2.5: Directions Distribution: in global clock distribution Distributed 27 vert the sinusoidal standing waves to digital levels, which could add additional skew and jitter.

2.5: Directions in global clock distribution 29 l << λ VCO and loop filter Phase detector

Regional ÷N Clock Distribution

Vc Clock load PD, LPF & CP Figure 2.13: Clock distribution using a coupled array of PLLs [44].System Clk (to VCOs) Figure 2.12: Standing-wave clock distribution [41].

Source:algorithm is used [Mahony]to avoid instability during the phase locking process. There are two main advantages to this topology. First, the PLLs filter the noise of the global H-tree and VCO Coupling 2.5.3 Coupled oscillator arrays replace it with the noise of the local VCOs, thereby reducing the jitter that accumulates in wires the H-tree. The second advantage is that, like in [44], the skew is a function of the error in The research that has been described to this point generally concentrates on minimiz- Standing wavethe phase detectors oscillators rather than the accumulated tune skew betweenout branches the of the H-tree. This ing the skew of a global clock• distribution. However, based on the scaling analysis in means that the scaling of this type of distribution does not depend on the latency of the Section 2.4, it appears that jitter maycapacitance be more difficult to reduce of for thefuture high-perfor- line and form a resonantFigure 2.15: Clock distribution using a coupled array of VCOs [48]. H-tree but rather on the scaling of the VCO and phase detector. The presence of the global mance microprocessors. Several clock distributions based on coupled oscillator arrays network. H-tree also allows for low-frequency testing by bypassing the PLLs. The only drawbacks have been proposed that have the potentialA distributed to reduce both tojitter this andapproach approach skew are by theeliminating additional locksresources necessary an forarray multiple2.5.3.3 PLLs of and Coupled the com- distributed oscillators large amounts of latency from• the clock network. Some alsoplexity reduce of synchronization. skew and jitter This by approach has not yet been prototyped so no measured The last type of coupled-oscillator clock distributions uses coupled arrays of distrib- VCO’s to datait’s is available. neighbors. employing a phase-averaging effect that tends to reduce the impact of uncorrelated static uted oscillators. The oscillators are distributed in the sense that the coupling wires are part The neighbors2.5.3.2 VCO can arrays also be injection lockedof the oscillators themselves, so their free-running frequency depends to some degree on • the geometry of the interconnects. The cooperative ring oscillator (CRO) clock distribu- The global clock distributions described in [47] and [48] are similar to the PLL array to one another to eliminate the phasetion described in [49] uses overlapping ring oscillators. The frequency of the oscillators designs, except that they use a single control loop with multiple VCOs. The clock distribu- detectors. depends on both the buffer and interconnect delays around the ring. Figure 2.16 shows a tion shown in Figure 2.15 and described in detail here is based on [48], but the same basic three-phase CRO grid and its electrical equivalent. The oscillators are allowed to run open concepts are used in [47]. A control voltage is distributed to all of the VCOs around the loop, and they phase lock to each other due to mutual coupling between rings, similar to die to set their frequency. A clock signal is fed back from a regional clock tap (driven by a [47] and [48]. Ali M. Niknejad University of California, Berkeley A similar approach is proposed in [50], which implements coupled arraysSlide: of25 rotary oscillators (Figure 2.17). This oscillator is similar to a ring oscillator but instead of using a series of inverter stages, it uses cross-coupled inverters to provide shunt gain. The interconnect for a single rotary oscillator is a differential loop that contains one inversion where the loops cross over. If the gain of the cross-coupled inverters exceeds the loss of the interconnect, then the circuit oscillates and a traveling wave propagates around the Chapter 5: Standing-Wave Clock Distribution Network 80

Clock buffers are used to convert the sinusoidal clock to digital levels. Choosing the cou-

Chapter 4: Standing-Wave Oscillatorspling point is a 60 trade-off between the size of the grid and the coupling strength. In practice, connecting the SWOs 15-25% from the short-circuits is a reasonable compromise that provides strong enough coupling to lock the segments together without causing excessive pair capacitance does not significantly load the interconnect, then optimizing for power skew due to mismatches between SWOs and without making the grid too small. To make may be desirable. In this case, the optimal cross-coupled pair may be one that does not a grid pattern, the portion of each SWO between the short-circuit and the coupling point is necessarily maximize gd/cd but instead maximizes gd/Ibias. This calls for larger devices and a lower bias current. In practice, the designs implemented in this foldedwork fall at intoright the angles, leaving stubs that hang off of the grid. The voltage magnitude is first category where the parasitic capacitances of the cross-coupled pairssmallest significantly at the load stubs since they are near the virtual short-circuit. The stubs can be consid- the line, so they are optimized for maximum gd/cd. The relative sizes eredof the “keep-out” PMOS and regions, areas where the signal amplitude is too low to be tapped by clock NMOS devices can also be optimized, but a good rule of thumb is tobuffers. size them The to voltage be standing-wave pattern for a portion of the grid is shown in Figure 5.4. roughly equal. Note that the largest magnitude occurs around the square portion of the grid and that the Standing Wavenodes Oscillators of the standing-wave are pushed (SWO) onto the stubs. 4.2.3 Design example

Single SWO (folded)

63µm:0.18 µm Clk inj Differential interconnect Cross-coupled pair Injection-locked cross-coupled pair Clock buffer 63µm:0.18 µm 14µm 14µm Chapter 5: Standing-Wave Clock Distribution Network 78 3.5mA 3.5µm 4µm Figure 5.3: A resonant5.1.1 SWO clock coupling grid of coupled SWOs.

Figure 4.8: SWO and transmission line cross-section for design example. This clock grid of coupled oscillatorsccp solvesccp two ccp of the ccp fundamental ccp problems with

A SWO is straightforward to design from (4.11) and (4.2). Table 4.1H-trees: lists the theparame- accumulation of timing uncertainty and sensitivity to buffer delay. As dis- ters that will •be usedThe to design negative a SWO with resistance five equally sized to and sustaincussed equally in spacedChapter 2, H-trees accumulate timing uncertainty because the clock signal is cross-coupled pairs.oscillation The transmission-line is cross-sectiondistributed (Figure 4.8)along is optimizedgenerated the for byline. min- a single source and then regenerated by each buffer along the tree. In con- ccp ccp ccp ccp ccp imum loss given• a totalOne track disadvantagewidth of 32µm and a distance is that of 3.5µ them totrast, the amplitude ground each plane.SWO in theof grid locally generates the clock signal and only uses the central A unit cross-coupledthe pair clock(ccp) is defined varies to have along NMOS andthe PMOS line. devices that are Figure 5.1: Two coupled SWOs. 18µm wide and 0.18µm long and is optimized for maximum gd/cd with 1.0mA of bias cur- Source: [Mahony] • SWO’s can be injection locked together Multiple SWOs can be coupled together by simply connecting their transmission lines. to form larger clock trees. Two coupled SWOs are shown in Figure 5.1. Ideally, the two oscillators are matched in frequency and a transient current between the two oscillators brings them into perfect phase lock. If the oscillators are detuned, they will still lock if they are within their mutual Ali M. Niknejad University of California, Berkeley locking range. A steady-state coupling current will keep them frequencySlide: locked, 26 although there will also be a phase difference between them. If their free-running frequencies are outside of this locking range, the coupled oscillators compete with each other and cause beating. The mutual locking range and relative phase of coupled oscillators are determined by the coupling strength and Q [63][64]. The coupling strength for SWOs is determined by the position of the connection between two oscillators. Coupling strength is at the maximum when the SWOs are connected at the center of the resonators, where the signal amplitude is largest, and goes to zero when they are connected at the ends, where the signal amplitude is zero. Larger coupling strength results in both a larger mutual locking range and less phase difference between detuned oscillators. For a network of coupled oscillators, the locking range is larger and the phase difference is smaller for oscillators with low-Q resonators. For the purposes of low-skew clock distribution, it is advantageous to use low-Q resonators that are strongly coupled. Fortunately, the on-chip transmis- ROUFOUGARAN et al.: SINGLE-CHIP 900-MHz SPREAD-SPECTRUM WIRELESS TRANSCEIVER IN 1- m CMOS—PART I 525 Quadrature Locked VCOs (QVCO)

270° 0° 90° 180° 180° 0° (a) (b) Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and showing the resonator currents; and (b) the relative phases of the voltages across the resonators required for symmetric operation. Source: [Rofoug] •Fig.Two 19. VCO’s Quadrature are coupled oscillator comprises together a pairusing of cross-coupledextra transistorsLC oscil- as latorsshown. synchronized If the oscillators in frequency. are identical, we expect that the amplitude and frequency of oscillation should be identical. • Because of the phase of the coupling, it can be shown that they recently,lock in quadrature... balanced quadrature outputs are obtained from two cross-coupled relaxation oscillators [30]. Another oscillator

Ali M. Niknejad consists of two LC biquadUniversity filters of California, in Berkeley feedback [31]. Four-stage Slide: 27 ring oscillators also produce quadrature at taps two stages apart [32], [33]. However, it is difficult (although apparently not impossible [34]) to obtain the requisite low phase noise in CMOS ring oscillators. This transceiver uses an LC quadrature oscillator. It comprises two unit oscillators as described above, labeled A and B, and additional coupling FET’s inserted in parallel with the oscillator core. The balanced output of Oscillator A is direct- Fig. 21. Magnitude and phase of a realistic resonator’s impedance, show- coupled to the coupling FET’s in Oscillator B, and the output ing three possible oscillation frequencies. The oscillator selects the highest of Oscillator B is cross-coupled into Oscillator A (Fig. 19). frequency because the feedback loop gain is largest here. The two oscillators synchronize to exactly the same frequency but are forced into quadrature phases by the coupling topology. circuit impedance is and its phase is either 45 The following symmetry argument explains how, owing only or 45 (Fig. 20). In an LC resonator with series loss in the to the topology, the circuit oscillates in quadrature. inductor, these phases appear at three different frequencies, , Suppose phasors and , respectively, are the steady- , and (Fig. 21). However, among them only is stable, state outputs of Oscillators A and B, with reference polarities because at this frequency the impedance is largest, and thus the as shown (Fig. 20). Then the phasor current into the tuned load feedback factor in the oscillator is strongest. At the phase of Oscillator A is , but it is into of the resonator’s impedance is 45 , which means that the load of Oscillator B, where is the differential average must lead by 90 , as is shown in Fig. 20. Note also that the large-signal transconductance of the FET’s. Arguing purely by oscillation frequency is higher than the resonance of the tuned symmetry, if the respective components in the two circuits are circuit, which is an advantage when building an RF circuit identical then the two oscillations must also be identical in operating close to the capabilities of an IC technology. The frequency and in amplitude. Therefore, the impedance of the standard theory of phase noise [28] must be modified for this two LC tuned circuits is equal, and the phasor currents driving oscillator, and this will be the subject of another publication. them are also equal in magnitude. This is only possible if Measurements on a standalone prototype of this oscilla- 1 and are in quadrature (Fig. 20), which proves the circuit tor have been reported previously [35]. The accuracy of principle. quadrature cannot be measured on an oscilloscope, because may lead by 90 , or lag it; in either case the a1 phase error at 900 MHz, for instance, corresponds to a conditions for quadrature oscillation are met. To resolve this differential delay of 3 ps between the and outputs, which is ambiguity, the asymmetrical frequency dependence of the very difficult to resolve on a linear time axis. Instead, by using tuned circuit impedance is invoked. First consider the steady- the oscillator in a single-sideband upconversion experiment, state relation between resonator current and voltage. In Oscil- the quadrature error is deduced from measurements on the lator A, for instance, the voltage across the resonator is , logarithmic amplitude display of a spectrum analyzer. The while the current supplied by the FET is . As standalone oscillator’s outputs drive the gates of two four- and are equal and at right angles, the steady-state tuned FET mixers on the same chip; balanced quadrature outputs from a 10-MHz sinewave generator drive the sources of the 1 Suppose , a real number, and . Then implies that , which requires , FET’s; and the drains are shorted together into two 50- loads that is . to select one sideband of the upconverted output [35]. The

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Source: [Rofoug]

• Note that the tank “A” (a)is driven by the tank voltage VA plus (b) the tank voltage of “B”. Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and • Theshowing right the tank, resonator though, currents; is driven and (b)by thevoltage relative VB phases but voltage of the voltages -VA. • Assumingacross the resonatorsthat the LC required tanks for and symmetric FETs are operation. identical, then the phasor currents flowing into the tanks must have equal Fig. 19. Quadrature oscillator comprises a pair of cross-coupled LC oscil- magnitude: v + v = v + V lators synchronized in frequency. | A B| | − A B| 1+ejθ = 1 ejθ | | | − | cos θ =0 θ = 90◦ recently, balanced quadrature outputs are obtained from two → ± cross-coupled relaxation oscillators [30]. AnotherAli M. oscillator Niknejad University of California, Berkeley Slide: 28 consists of two LC biquad filters in feedback [31]. Four-stage ring oscillators also produce quadrature at taps two stages apart [32], [33]. However, it is difficult (although apparently not impossible [34]) to obtain the requisite low phase noise in CMOS ring oscillators. This transceiver uses an LC quadrature oscillator. It comprises two unit oscillators as described above, labeled A and B, and additional coupling FET’s inserted in parallel with the oscillator core. The balanced output of Oscillator A is direct- Fig. 21. Magnitude and phase of a realistic resonator’s impedance, show- coupled to the coupling FET’s in Oscillator B, and the output ing three possible oscillation frequencies. The oscillator selects the highest of Oscillator B is cross-coupled into Oscillator A (Fig. 19). frequency because the feedback loop gain is largest here. The two oscillators synchronize to exactly the same frequency but are forced into quadrature phases by the coupling topology. circuit impedance is and its phase is either 45 The following symmetry argument explains how, owing only or 45 (Fig. 20). In an LC resonator with series loss in the to the topology, the circuit oscillates in quadrature. inductor, these phases appear at three different frequencies, , Suppose phasors and , respectively, are the steady- , and (Fig. 21). However, among them only is stable, state outputs of Oscillators A and B, with reference polarities because at this frequency the impedance is largest, and thus the as shown (Fig. 20). Then the phasor current into the tuned load feedback factor in the oscillator is strongest. At the phase of Oscillator A is , but it is into of the resonator’s impedance is 45 , which means that the load of Oscillator B, where is the differential average must lead by 90 , as is shown in Fig. 20. Note also that the large-signal transconductance of the FET’s. Arguing purely by oscillation frequency is higher than the resonance of the tuned symmetry, if the respective components in the two circuits are circuit, which is an advantage when building an RF circuit identical then the two oscillations must also be identical in operating close to the capabilities of an IC technology. The frequency and in amplitude. Therefore, the impedance of the standard theory of phase noise [28] must be modified for this two LC tuned circuits is equal, and the phasor currents driving oscillator, and this will be the subject of another publication. them are also equal in magnitude. This is only possible if Measurements on a standalone prototype of this oscilla- 1 and are in quadrature (Fig. 20), which proves the circuit tor have been reported previously [35]. The accuracy of principle. quadrature cannot be measured on an oscilloscope, because may lead by 90 , or lag it; in either case the a1 phase error at 900 MHz, for instance, corresponds to a conditions for quadrature oscillation are met. To resolve this differential delay of 3 ps between the and outputs, which is ambiguity, the asymmetrical frequency dependence of the very difficult to resolve on a linear time axis. Instead, by using tuned circuit impedance is invoked. First consider the steady- the oscillator in a single-sideband upconversion experiment, state relation between resonator current and voltage. In Oscil- the quadrature error is deduced from measurements on the lator A, for instance, the voltage across the resonator is , logarithmic amplitude display of a spectrum analyzer. The while the current supplied by the FET is . As standalone oscillator’s outputs drive the gates of two four- and are equal and at right angles, the steady-state tuned FET mixers on the same chip; balanced quadrature outputs from a 10-MHz sinewave generator drive the sources of the 1 Suppose , a real number, and . Then implies that , which requires , FET’s; and the drains are shorted together into two 50- loads that is . to select one sideband of the upconverted output [35]. The

(a) (b) Fig. 20. (a) Quadrature oscillator redrawn, emphasizing its symmetry and showing theQVCO: resonator currents; Lead/Lag and (b) the relative phases Ambiguity of the voltages across the resonators required for symmetric operation.

Fig. 19. Quadrature oscillator comprises a pair of cross-coupled LC oscillators synchronized in frequency. recently, balanced quadrature outputs are obtained from two cross-coupled relaxation oscillators [30]. Another oscillator consists of two LC biquad filters in feedback [31]. Four-stage ring oscillators also produce quadrature at taps two stages apart [32], [33]. However, it is difficult (although apparently not impossible [34]) to obtain the requisite low phase noise in CMOS ring oscillators. This transceiver uses an LC quadrature oscillator. It com- Source: [Rofoug] prises two unit oscillators as described above, labeled A and B, and additional coupling FET’s inserted in parallel with the oscillator core. The balanced output of Oscillator A is direct- NoteFig. that 21. Magnitudethe tank and phase current/voltage of a realistic resonator’s impedance,has a 90° show- relation, or the coupled to the coupling FET’s in Oscillator B, and the• output ing three possible oscillation frequencies. The oscillator selects the highest of Oscillator B is cross-coupled into Oscillator A (Fig.phase 19). frequency of the because impedance the feedback loop is gain ±45°. is largest here.Three frequencies satisfy this The two oscillators synchronize to exactly the same frequencyconstraint, but f3 has the highest loop gain. but are forced into quadrature phases by the coupling topology.It’s clearcircuit that impedance there is are twoand possible its phase is solutions: either 45 lead or lag in The following symmetry argument explains how, owing• only phaseor between45 (Fig. 20). “A” In anandLC “B”.resonator with series loss in the to the topology, the circuit oscillates in quadrature. inductor, these phases appear at three different frequencies, , Suppose phasors and , respectively, are the steady-In any ,real and oscillator,(Fig. 21). However, the two among oscillators them only is are stable, not perfectly state outputs of Oscillators A and B, with reference polarities• symmetric,because at and this frequency it can the be impedance shown is largest,that there and thus is the only one unique as shown (Fig. 20). Then the phasor current into the tuned load feedback factor in the oscillator is strongest. At the phase of Oscillator A is , but it is solutioninto of the (where resonator’s the impedance loop is gain45 ,is which highest means thatand the net phase shift the load of Oscillator B, where is the differential averagearoundmust the lead loopby 90 is, as0°) is shown in Fig. 20. Note also that the large-signal transconductance of the FET’s. Arguing purely by oscillation frequency is higher than the resonance of the tuned Ali M. Niknejad University of California, Berkeley Slide: 29 symmetry, if the respective components in the two circuits are circuit, which is an advantage when building an RF circuit identical then the two oscillations must also be identical in operating close to the capabilities of an IC technology. The frequency and in amplitude. Therefore, the impedance of the standard theory of phase noise [28] must be modified for this two LC tuned circuits is equal, and the phasor currents driving oscillator, and this will be the subject of another publication. them are also equal in magnitude. This is only possible if Measurements on a standalone prototype of this oscilla- 1 and are in quadrature (Fig. 20), which proves the circuit tor have been reported previously [35]. The accuracy of principle. quadrature cannot be measured on an oscilloscope, because may lead by 90 , or lag it; in either case the a1 phase error at 900 MHz, for instance, corresponds to a conditions for quadrature oscillation are met. To resolve this differential delay of 3 ps between the and outputs, which is ambiguity, the asymmetrical frequency dependence of the very difficult to resolve on a linear time axis. Instead, by using tuned circuit impedance is invoked. First consider the steady- the oscillator in a single-sideband upconversion experiment, state relation between resonator current and voltage. In Oscil- the quadrature error is deduced from measurements on the lator A, for instance, the voltage across the resonator is , logarithmic amplitude display of a spectrum analyzer. The while the current supplied by the FET is . As standalone oscillator’s outputs drive the gates of two four- and are equal and at right angles, the steady-state tuned FET mixers on the same chip; balanced quadrature outputs from a 10-MHz sinewave generator drive the sources of the 1 Suppose , a real number, and . Then implies that , which requires , FET’s; and the drains are shorted together into two 50- loads that is . to select one sideband of the upconverted output [35]. The

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on May 8, 2009 at 23:26 from IEEE Xplore. Restrictions apply. ANDREANI et al.: ANALYSIS AND DESIGN OF A 1.8-GHz CMOS LC QUADRATURE VCO 1745

possible oscillation frequencies and , both differing from the natural tank resonance frequency LC:

(18)

These equations can be simplified noting that

(19) Fig. 19. Upconverted baseband signals and LO leakage at 1.75 GHz carrier ANDREANI et al.: ANALYSIS AND DESIGN OF A 1.8-GHz CMOS LC QUADRATURE VCO 1739 frequency (IBR 56 dB). (20)

and assuming that . Using (20), we can approximate the inner square root in (18) as . According to (20), this term is much larger than , which can be neglected. Finally, using (19) and the approximation , valid for , we arrive at

(21)

which is the same as (2).

APPENDIX B Fig. 4. Block schematic of the image rejection architecture (QVCO not shown). Equations (11) and (15) are derived in this appendix. Fig. 20. IBR as a function of the oscillation frequency. In the following, we call the half-P-QVCO affected by noise sources (Fig. 11) and the other half. The low-frequency applies to both S-QVCO and P-QVCO, and the model has been noise on slowly modulates the quadrature current in , thus used to derive the oscillation frequency of the QVCOs, and the effectively modifying the coupling transconductance influence of the various noise sources on the generation of from to . Equation (10) yields phase noise in the region. This analysis provides quanti- ANDREANI et al.: ANALYSIStative AND results DESIGN which OF A 1.8-GHz agree CMOS wellLC QUADRATURE with the outcome VCO of phase noise 1745 (22) simulations performed with SpectreRF, indicating the superior performances of the S-QVCO compared topossible the P-QVCO. oscillation The frequencies and , both differing from measurement results for a prototype of thethe S-QVCO natural tank fabricated resonance frequencyFurther, the sameLC: noise also varies the in-phase current in , in a standard 0.35- m CMOS processFig. 6. show Fair phase-noise an oscillation comparison between P-QVCO and S-QVCO. ANDREANI et al.: ANALYSIS AND DESIGN OF A 1.8-GHz CMOS LC QUADRATUREQVCO VCO Loop Gain which modulates , which1745 changes the effective coupling frequency of 1.8 GHz, a tuning range of 18%, a phase noise of transconductance from to . Using (10) again, Fig. 5. IBR for the P-QVCO, in the presence of different values for . 140 dBc/Hz or less at a 3-MHz offset frequency across the we obtain tuningLinear range, model and an of equivalent QVCO is phase possible error of oscillation at most 0.25 frequencies, and , both differing from power consumption, there• will be no doubt that the S-QVCO for ashown. current The consumption loop gain of 25is easily mA from the naturala 2-V power tank resonance supply. frequency LC: (23) does outperform the P-QVCO.computed5 and the frequency at (18) which the loop gain is zero is III. A SIMPLIFIED QVCO MODEL APPENDIX A To estimate the effect on the frequency, we note that the term the oscillation frequency. These equations can be simplified noting that Fig. 7 introduces a linear model for the P-QVCO, where appears squared in (17) and (18) . It is therefore reasonable InNotice this appendix, that the we oscillation find the possible is off oscillation frequencies represents the transconductance• of the negative-resistance to define in the expression of the loop gain as follows: for theresonance. linearized This QVCO results circuit in in Fig.lower 7. The loop gain is easily pair ( ), and the transconductance of the coupling pair (18)(19) ( ). Referring to thiscalculatedphase figure and asnoise. also in the following, we Fig. 19. Upconverted baseband signals and LO leakage at 1.75 GHz carrierFig. 7. Linear model for a QVCO. Source: [Andreani] (24) ANDREANI et al.: ANALYSIS AND DESIGN OF A 1.8-GHzconsider CMOSfrequencyLC QUADRATURE voltage (IBR and56 VCO dB). current signals to be fully differential: 1745 (20) the current flowing into the tank is the difference between the These equations can be simplified noting that currents in the two branches of the differential stage. As a As shown in Appendix A, the oscillation frequency re- possible oscillation frequencies and , both differing from LC and therefore consequence, is the loss resistance of one half-tank. sultsand slightly assuming displaced that from(17) the tank. Using resonance (20), we can approximate the natural tank resonance frequency LC:by an offset , whose magnitude depends on . This can According to Barkausen’s criteria, the circuitthe inner oscillates square root when in (18) as . According to (20),(19) alsothis be explained term is much in the larger following, than intuitive, which way. Referring can be neglected. to (25) Fig. 19. Upconverted basebandthe signals condition and LO leakage at 1.75 GHzis carrier satisfied; further,inFinally, Fig. 7, using there the losses (19) are andin two tank- the approximationare balanced by a current in , frequency (IBR 56 dB). (20) 5To complicate matters even further, an additional variable is the value of the phasevalid with for , , we arrive at , which is provided by sum of the transistor widths, . The results shown in . The tank is now lossless, and the current from acts on Fig. 6 were obtained when both P-QVCO and S-QVCO shared the same value an ideal LC-parallel. This second current, , is thus in quadra- for . However, can be largely reduced for the P-QVCO, in which and assuming(18) that . Using (20), we can approximate case its phase noise decreases by approximately 2 dB in the region, but ture with , which in turn implies that and are phase (21) increases by several decibels in the region. It should be noted that a lower shiftedthe inner by square. Fig. root 8 shows in (18) the as phasors of the. Accordingvoltage across to (20), value for allows the P-QVCO to achieve a higher maximum oscillation These equations can be simplified noting that thethis tank, term and is of much the currents larger than entering the, tank.which To can find be the neglected. re- frequency, compared to the S-QVCO, or, when the oscillation frequency and the which is the same as (2). tuning range are theAli same M. Niknejad for both P-QVCO and S-QVCO, the capacitanceUniversity in lationFinally, of California, between usingBerkeley (19)and and the, we approximation consider the loop in Fig.Slide: 7 as30 , the tank of the P-QVCO can be made more linear by introducing an additional composedvalid for by two, ideal we arrive tanks coupled at by . The magnitude metal–metal capacitor (when available) in parallel to the varactor, with the ben- (19) of each ideal tank, at an offsetAPPENDIXfrom resonance,B is approxi- Fig. 19. Upconverted baseband signals and LO leakageeficial at 1.75 effect GHz of carrier reducing the conversion of low-frequency noise into phase noise frequency (IBR 56 dB). due to the nonlinearities in the LC tank. matelyEquations(20) (11). Since and (15) the are loop derived gain must in this be appendix. unity at the Fig. 20. IBR as a function of the oscillation frequency. In the following, we call the half-P-QVCO affected(21) by noise sources (Fig. 11) and the other half. The low-frequency and assuming that . Using (20), we can approximate applies to both S-QVCOthe inner and square P-QVCO, root in (18) and as the model has. According beenwhichnoise to (20), is on the sameslowly as modulates(2). the quadrature current in , thus used to derive thethis oscillation term is much frequency larger than of the QVCOs,, which and can the be neglected.effectively modifying the coupling transconductance influence of the variousFinally, usingnoise (19) and sources the approximation on the generation of from , to . Equation (10) yields APPENDIX B phase noise in thevalid for region., we This arrive analysis at provides quantitative results which agree well with the outcome of phase noise Equations (11) and (15) are derived in this appendix. Fig. 20. IBR as a function of the oscillation frequency. (22) simulations performed with SpectreRF, indicating the superior In the(21) following, we call the half-P-QVCO affected by performances of the S-QVCO compared to the P-QVCO. Thenoise sources (Fig. 11) and the other half. The low-frequency measurement results for a prototype of the S-QVCO fabricated applies to both S-QVCOwhich and is P-QVCO, the same as and (2). the model has been noiseFurther, on theslowly same modulates noise also the varies quadrature the in-phase current current in in, thus, used toin derive a standard the oscillation 0.35- m frequency CMOS process of the QVCOs, show an and oscillation the effectivelywhich modulates modifying the, coupling which changes transconductance the effective coupling frequency of 1.8 GHz, a tuning range of 18%, a phase noise of influence of the various noise sources onAPPENDIX the generationB of fromtransconductanceto . Equation (10) yieldsfrom to . Using (10) again, 140 dBc/Hz or less at a 3-MHz offset frequency across the phase noise in the region. This analysis provides quanti- we obtain tuning range, and anEquations equivalent (11) and phase (15) error are derived of at most in this 0.25 appendix., Fig. 20. IBR as a function of the oscillation frequency.tative results which agreeIn well the with following, the outcome we call ofthe phase half-P-QVCO noise affected by for a current consumption of 25 mA from a 2-V power supply. (22) simulations performednoise with sources SpectreRF, (Fig. 11) indicating and the the other superior half. The low-frequency (23) applies to both S-QVCO and P-QVCO,performances and the model has of been the S-QVCOnoise on comparedslowly modulates to the P-QVCO.the quadrature The current in , thus effectively modifying the coupling transconductance used to derive the oscillation frequencymeasurement of the QVCOs, results and the for a prototypeAPPENDIX of theA S-QVCO fabricated To estimate the effect on the frequency, we note that the term influence of the various noise sources on the generation of from to . Equation (10) yields Further, the same noise also varies the in-phase current in , in a standard 0.35- m CMOS process show an oscillation which modulatesappears squared, which in (17) and changes (18) . It the is therefore effective reasonable coupling phase noise in the region. This analysis providesIn this quanti- appendix, we find the possible oscillation frequencies to define in the expression of the loop gain as follows: tative results which agree well with thefrequency outcome of phaseof 1.8 noise GHz, a tuning range of 18%, a phase noise of transconductance from to . Using (10) again, for the linearized QVCO circuit in Fig. 7. The loop gain is easily (22) simulations performed with SpectreRF, indicating140 dBc/Hzcalculated the superior or as less at a 3-MHz offset frequency across the we obtain performances of the S-QVCO comparedtuning to the range, P-QVCO. and The an equivalent phase error of at most 0.25 , (24) measurement results for a prototype of the S-QVCO fabricated for a current consumptionFurther, of 25 the mA same from noise a also 2-V varies power the supply. in-phase current in , (23) in a standard 0.35- m CMOS process show an oscillation which modulates , which changes the effective coupling LC and therefore frequency of 1.8 GHz, a tuning range of 18%, a phase noise of transconductance from to . Using(17) (10) again, 140 dBc/Hz or less at a 3-MHz offset frequency across the According to Barkausen’sweA obtainPPENDIX criteria,A the circuit oscillates whenTo estimate the effect on the frequency, we note that the term tuning range, and an equivalent phase error of at most 0.25 , appears squared in (17) and (18) . It is therefore reasonable(25) for a current consumption of 25 mA from a 2-Vthe power condition supply. is satisfied; further, there are two In this appendix, we find the possible oscillation frequencies to define(23) in the expression of the loop gain as follows: for the linearized QVCO circuit in Fig. 7. The loop gain is easily APPENDIX A calculated as To estimate the effect on the frequency, we note that the term appears squared in (17) and (18) . It is therefore reasonable (24) In this appendix, we find the possible oscillation frequencies to define in the expression of the loop gain as follows: for the linearized QVCO circuit in Fig. 7. The loop gain is easily calculated as LC and therefore (17) (24) According to Barkausen’s criteria, the circuit oscillates when the conditionLC and thereforeis satisfied; further, there are two (25) (17) According to Barkausen’s criteria, the circuit oscillates when the condition is satisfied; further, there are two (25) 1738 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002

II. COMPARING P-QVCO AND S-QVCO The issue of how the performances of two different QVCOs can be compared in a fair and meaningful way is less trivial than it might seem at first sight, since the two qualifying data for a QVCO, that is, phase noise and phase error, are in general not independent of each other. In particular, this is the case for the P-QVCO, where both phase noise and phase error are strong functions of , defined as the ratio of the width of transistor to the width of transistor (assuming that both transistors have the same length)

Fig. 2. SchematicQVCO view of the in quadrature the VCOLiterature presented in [7]. (1)

To see how the phase error varies with , the single-sideband (SSB) upconversion circuit [7], [16] in Fig. 4 has been used, so that the overall phase/amplitude errors between the phases, very difficult to measure directly in a reliable way, are translated into the ratio of the wanted upconverted band, to the unwanted, image band [to be referred to as image band rejection (IBR)]. In the case of the P-QVCO, simulations show that a mismatch of 0.1% between the inductors in the two LC-tanks results in an IBR of 70 dB for , which drops to 60 dB for Source: [Andreani]and to 49 dB for (Fig. 5). Clearly, the phase error gets quickly larger when the coupling between the two VCOs in the P-QVCO is weakened by decreasing . On the other hand, it is • SeveralFig. 3. modiﬁcations Schematic view of the to quadrature the QVCO VCO proposed have inbeen this work. proposed for improved performance easy to check that the phase noise, too, greatly decreases with a • In particular, it has been shown that if a weaker coupling isdecreasing . Thus, it is straightforward to improve the phase- introduced,The present the paper phase analyzes noise animproves alternative (the way circuit [16] of locks cross closernoise performance of the P-QVCO at the expense of its phase- tocoupling the tank two resonance), differential VCOsbut at to the obtain cost a QVCO, of imperfect in which quadrature the error performance. This is the case for the already mentioned generationcoupling transistor is placed in series with , rather P-QVCO presented by Tiebout [12], where a very high phase- • A thanseries in parallelconnected (Fig. quadrature 3). This choice generation is motivated scheme by the con-proposednoise FoM, the highest to date for QVCOs, was achieved by bysideration [Andreani] that has betterin the phase P-QVCO noise is responsible performance. for a large choosing , while the original P-QVCO [7] had equal contribution to the overall phase noise, and connecting to unity. Ali M. Niknejad University of California, Berkeley Slide: 31 in series with , in a cascode-like fashion, should greatly Since we have seen that phase noise and phase error are in reduce the noise from the cascode device. Admittedly, an os- general not orthogonal (and can be traded for each other in the cillator having large signals present at every node works quite P-QVCO), it is not enough to compare only the phase-noise differently than a standard cascode circuit, but SpectreRF simu- FoM between different QVCOs. If possible, the phase-noise lations show [17] that the new QVCO (to be referred to as series FoM should be compared when the same level of component QVCO, S-QVCO) indeed displays an excellent phase noise be- mismatch causes the same phase error. This is certainly possible havior.4 when comparing P-QVCO and S-QVCO, since we have seen The paper is organized as follows. Section II addresses the that the phase error in the P-QVCO can be tuned by changing problem of how the performances of two different QVCOs can . In the case of the S-QVCO, on the contrary, the phase error be compared in an objective way. Section III presents a simplified linear circuit model for the analysis of both P-QVCO and is almost independent of for all reasonable values of . This S-QVCO, while Section IV exploits this model for a quantitative means that, while we can choose the value for which mini- analysis of the phase noise performance of the QVCOs in the mizes the phase noise, the phase error cannot be improved by region (the mechanisms for the conversion of white noise allowing a higher phase noise. In this case, the phase error acts into phase noise will not be dealt with in this paper). Despite more like a design constant (dependent of course on the actual the limitations of the model, the results of the phase noise anal- amount of mismatch between ideally identical components), ysis are in good agreement with those obtained with SpectreRF once the QVCO architecture has been selected. In the case of simulations. Finally, the experimental results for an S-QVCO the S-QVCO, assuming again a 0.1% LC-tank mismatch, the implemented in a standard 0.35 m CMOS process will be il- achievable IBR is 60 dB, that is, approximately the same IBR lustrated in Section V. displayed by the P-QVCO when (Fig. 5). If we now compare the phase noise displayed by P-QVCO and S-QVCO (Fig. 6; varactors were removed in these simulations, so that the 4It is worth noting that there are more ways of achieving a series-like connec- resulting phase noise is due to the oscillator topology alone), tion between and [18]. We have recently discovered that yet another variant of the series QVCO topology has been proposed by Wu and Kao [19]. when both QVCOs have the same IBR, center frequency, and 184 Jri Lee

D Q L D 1 Q

CK out,Q CK in CK out,I f (f ( f ( in ( in ( in ( 2 2 Q D L Q 2 D

Flipflop

(a) 1 f in

CK in

CKout,I

Static Frequency Dividers CKout,Q /0102&34536$-0'780)$9:(;<=(<$-(8<)&'> t

t DQ 23456738 (b) !"#$%&' !"#$%&1 () () /0# Fig. 5.22 (a) Typical static divider, (b) its waveforms. #-. ) ) /0# *+, *+, -. -. dition. As frequency goes up, the idle time decreases, and the divider would work -. /0#

VDD ! !"#$%&%'()*%+,%-".(/$&$'$0-(1.("20"3$-4(560(275"#%'( This is a simple divider structure uses a R D RD D out • 8$9%9:(7(*%4$'5%*;($-(-%475$&%()%%/17"3 R C RC master/slave topology. Dout Q5 Two! latches<75"#%'(=7.(1%($=>2%=%-5%/($-(&7*$0,'(67.'( are cascaded into a Q6 • Q Q Q Q negative7""0*/$-4(50('>%%/?>06%*(*%+,$*%=%-5' feedback loop (the output will 1 2 3 4 M 3 M 4 D in therefore toggle). Din M 1 M 2 Since two clock cycles are required to CKin Q7 Q 8 CKin • CK pass the data from one latch to the in M 56M CKin next, it naturally divides by 2. !"#"$%&''()) !*+$,-.

(a) (b) Ali M. Niknejad University of California, Berkeley Slide: 32 Fig. 5.23 CML latch of (a) CMOS, (b) bipolar technologies. 186 Jri Lee 5.7 Regenerative (Miller) Dividers

Originally proposed by Miller in 1939 [21], the regenerative divider is based on mixing the output with the input and applying the result to a low-pass filter (Fig. 5.25). Under proper phase and gain conditions, the component at !in/2 survives and circulates around the loop, achieving 2 operation. Such a configuration allows joint design of the mixer and the low-pass÷ filter to arrive at a high speed, since the device capacitance of the former can be absorbed as part of the latter. This topology thus becomes attractive and popular at moderate to high frequencies. Miller Divider (Regenerative)

! in, 3! in 2 2 x (t ) LPF y()t

! in 2

Fig. 5.25 Regenerative divider. • The output signal of the feedback loop is mixed with the input signal. The output of the (ideal) mixer has the sum and Let usdifference first examine components. the division behavior and estimate the operation range. For the circuit• Only to divide the difference properly, the component loop gain at is! amplifiedin/2 must exceed(due to unity. the LPF) Redrawing the dividerand in gained Fig. 5.26(a) up. with simple RC filter and input amplitude A, we have • If the loop gain is greater than one and the loop phase is zero degrees, the system regenerates"A !in the input. H( j ) 1, (5.36) The output frequency2 in steady2 state≥ must therefore satisfy: • ! ! ! ! where " denotes the conversionfout gain!= off thein mixer.! fout It can be further derived that − 1 2 2fout = !infin 2 A 1 + 2 . (5.37) ≥ " " 2!c ≥ " Ali M. Niknejad University of California,# Berkeley$ Slide: 33 1 Here, the corner frequency !c = (R1C1)− . Equation (5.37) implies that a minimum level of at least 2/" is required for the input. Unlike the static or the injection-locked dividers, the regenerative ones present no self-resonance frequency, resulting in a relatively flat input sensitivity. Realizing that the LPF is to filter out the component at 3!in/2 and preserve that at !in/2, we examine two cases to determine the operation range. As illustrated in Fig. 5.26(b), the rule of thumb is to keep !in/2 inside the passband while rejecting 3!in/2 and other harmonics. In other words, we can roughly estimate the operation range as !in,max 3!in,min !c and !c, (5.38) 2 ≤ 2 ≥ and hence 2!c !in 2!c. (5.39) 3 ≤ ≤ 5 VCOs and Dividers 189

Minimun Required Input !n ! A "xy x (t ) L C R y ()t 2/" =A cos ! in ! in t = B cos t !in 2 2!n ! in 2 Op. Range

5 VCOs and Dividers (a) 189 (b)

Minimun VDD Required Input L1 L2 C Vout !n ! 1 C A Y 2 "xy X x (t ) L C R y ()t 2/" M 5 M 6 =A cos ! in M 34M ! in t = B cos t !in 2 Vin 2!n ! in 2 Miller DividerOp. RangeA CircuitB Details 190 Jri Lee (a) (b) M 1 M 2 V VDD VDD DD L L L1 L2 L L C Vout Vout 1 C (c) Y 2 X Fig. 5.28 (a)M 5 Regenerative dividerM 6 with bandpass ﬁlter; (b) its input sensitivity, (c) typical CMOS M M M M M M 4 3 realization. 34 3 4 Vin M M M 5 M 6 5 6 ! + A B AB I inj I inj

MM12 It is interestingM to noteM that a mixer has twoV inputM ports, that leadsM to two pos- 1 2 in 1 2 Vin sible conﬁgurations of Miller dividers. As illustrated in Fig. 5.29, the output could (c) (a) (b) Fig. 5.28 (a) Regenerative divider with bandpass ﬁlter; (b) its input sensitivity, (c) typical CMOS realization. Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injection locking. LO Port LO Port

It is interesting to note thatVin a mixer has two inputFilter ports, that leadsVout to twobe pos- redrawn as that inFilter Fig. 5.30(b).V Itout in fact resembles an injection-locked divider sible conﬁgurations of Miller dividers. As illustrated in Fig. 5.29, the output(which could will be discussed in the next section): M3 and M4 form a cross-coupled pair, and M5 and M6 appear as diode-connected transistors to lower the Q of the tank RF Port andRF increase Port the locking range. The differential injection in such a manner is be- LO Port LO Port lieved to helpVin enlarge the range of operation to some extent. It is possible to ﬁnd a self-resonance frequency of the circuit if (W /L)3,4 > (W/L)5,6 [22]. Vin Filter Vout (a) Filter Vout (b) Use a double-balanced Gilbert cell mixer to realize divider Fig.• 5.29 Regenerative divider with the output fed back to (a) RF port, (b) LO port. RF Port RF Port 5.8 Injection-Locked Dividers Ali M. Niknejad Vin University of California, Berkeley Slide: 34 (a) (b) either return to the RF port (type I) or the LOThe port operation (type speed II) of ofthe dividers mixer. can Although be further boosted up if we simplify the struc- Fig. 5.29 Regenerative dividerconceptually with the output indistinguishable, fed back to (a) RF port, (b) these LO port. two approachesture at the circuit still make level. difference Since a cross-coupled in circuit VCO provides ultimate simplicity in implementation. Figure 5.30(a) shows a CMOSgenerating Miller differential divider oscillation,with the one output may di- think of injecting a periodic signal (ap- rectly applied to the LO port. The M -M quadproximately of the twice double-balanced the VCO free-running mixer frequency) can into the common-mode point either return to the RF port (type I) or the LO port (type II) of the mixer.3 6 Althoughof it and forcing the VCO to lock. Recognized as an injection-locked divider, this conceptually indistinguishable, these two approaches still make difference in circuit approach is indeed an inverse operation of push-push oscillators. Among the exist- implementation. Figure 5.30(a) shows a CMOS Miller divider with the output di- ing divider topologies, it basically reaches the highest speed. rectly applied to the LO port. The M -M quad of the double-balanced mixer can 3 6 The injection locking phenomenon can be explained as adding an external sinusoidal current Iin j to a well-behaved oscillator [Figure 5.31(a)]. If the amplitude and frequency of Iin j are chosen properly, the circuit oscillates at the injection frequency of !in j rather than the tank resonance frequency !0. The key point here is that, to accommodate the phase shift contributed by the tank at !in j, Iosc (the intrinsic oscillation current) and Iin j must sustain a certain phase difference such that the total phase shift maintains 0◦. Intuitively, the injection locking would occur only in the vicinity of !0 and the locking range is limited. In fact, it can be analytically derived from different approaches [23][24] that the normalized locking range is given by 814 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999

We assume that all frequency components of far from the resonant frequency of the tank are ﬁltered out, so the frequency of the output signal can be written as . Thus, we need only consider intermodulation terms with frequency , that is, . For an th-order superharmonic ILO (i.e., ), the Fig. 2.Injection Model for a free-running LockedLC oscillator. Dividers [IL-Div] intermodulation terms with possess a frequency equal to of the incident frequency. The signal , which is the component of with frequency , can be written as

(6) •Fig.An 3. injection Model for locked an injection-locked divider is oscillator. nothing but an injection locked system where the input frequency is at a harmonic of the free-Using a complex exponential to replace sines and cosines, Measurementsrunning frequency on a single-ended of the oscillator. ILFD (SILFD) are compared and applying the oscillation condition, the output signal can •withModel simulations. the system The as simulation a non-linearity results of f(e) a differential and a bandpass ILFD be written as (DILFD)transfer arefunction reported H( asω). well. • Assume that the free-running loop has a stable oscillation frequency. The system is injection locked to a super-harmonic of theII. free-running MODEL FOR Ifrequency.NJECTION-LOCKED OSCILLATORS (7) • TheAn non-linearityLC oscillator in can the be loop modeled must ascreate a nonlinear intermodulation block products, followed that by fall a in frequency the passband selective of the block loop. (e.g., an RLC or tank) , in a positive feedback loop as shown in Fig. 2. The nonlinear block models all the nonlinearities in the oscillator, including any amplitude-limiting mechanism. To Ali M. Niknejad University of California, Berkeley Slide: 35 have a steady-state oscillation, a loop gain of unity should be (8) maintained. We would like to express the oscillation condition in terms of gain and phase criteria for reasons that will be clear The real and imaginary parts of (8) can be separated as later. The gain condition is satisfied if the output amplitude is the same as the amplitude of in an open-loop (9) excitation of the system at the oscillation frequency . The phase condition requires that the excess phase introduced in the loop at be zero. (10) With an additional external signal (i.e., the incident signal), this same model can be used to model an ILO. This model is shown in Fig. 3. To investigate the injection-locking Equations (9) and (10) are the fundamental equations for phenomenon in an ILO, we define a superharmonic injection-locked oscillator. The simultaneous solution of these two equations specifies and for any (1) incident amplitude and any incident frequency or, (2) equivalently, for any offset frequency . Equation (10) can be rearranged as (3)

(4) (11)

where is the incident signal, is the output signal, where is Adler’s locking range is the phase difference between those two signals, and and ﬁgure of merit [1]. The fundamental equations, (9) and (10), are the resonant frequency and quality factor of the RLC are very general but provide limited intuition. However, as tank, respectively. The output of the nonlinear block may shown in the next section, for the special case of contain various harmonic and intermodulation terms of (i.e., divide-by-two) and a third-order nonlinearity (i.e., and . As shown in Appendix A, we can write as ), (9) and (10) can be solved analytically, which allows the development of design insight.

(5) A. Special Case ( and Is a Third-Order Nonlinear Function) where each is an intermodulation coefﬁcient of For the special case of and . , the only unknown in (10) is the input–output

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:49 from IEEE Xplore. Restrictions apply. IL-Div Analysis

• Suppose the injection signal is a sinusoidal signal which is added to the oscillator’s signal (at a sub-harmonic of the injection). The non-linearity acts on both signals and is ﬁltered by the RLC circuit:

vi(t)=Vi cos(ωit + φ) vo(t)=Vo cos(ωot) H u(t)=f(e(t)) = f(v (t)+v (t)) 0 o i H(ω)= ω ω 1+j2Q − r ωr • It can be shown that if the output signal contains various harmonics and intermodulation terms which can be written as: ∞ ∞ u(t)= Km,n cos(mωit + mφ) cos(nω0t) m=0 n=0 ! ! • where Km,n is the intermodulation component of f(vi+vo)

Ali M. Niknejad University of California, Berkeley Slide: 36 IL-Div Fourier Analysis • To see this, write the signals in the following form:

vi = Vi cos(β)

vo = Vo cos(α)

f(e)=f(vi + vo) • which means that f is periodic in α and β. For every β deﬁne a periodic function g(α) as follows

g(α)=f(vo + Vi cos(α)) Note that: • g(α +2π)=g(α) g( α)=g(α) − • So that we can write: 1 2π ∞ L0(β)= f(Vo cos(β)+Vi cos(α))dα g(α)= L (β) cos(mα) 2π 0 m 1 2π ! m=0 L (β)= f(V cos(β)+V cos(α)) cos(mα)dα ! m π o i !0

Ali M. Niknejad University of California, Berkeley Slide: 37 IL-Div [Fourier Analysis cont.]

• But since Lm is a periodic and even function of β we can write:

2π ∞ 1 Km,0 = Lm(β)dβ Lm(β)= Km,n cos(nβ) 2π 0 n=0 ! ! 1 2π K = L (β) cos(nβ)dβ m,n π m !0 • which results in: ∞ ∞ f(vi + vo)= Km,n cos(mα) cos(nβ) m=0 n=0 ! ! • Assume that the tank ﬁlters out all frequencies except the ones around ωo. That means that only intermodulation terms that fall at ωo are relevant: mω nω = ω | i − 0| 0

Ali M. Niknejad University of California, Berkeley Slide: 38 IL-Div [Fourier cont] • If the injection signal is an N’th superharmonic, then only the intermodulation terms n = Nm 1 ± • possess a frequency equal to 1/N the incident frequency. This means that our summation can be written in terms of m as 1 ∞ uω (t)=K0,1 cos(ω0t)+ Km,Nm 1 cos(ωot + mφ) 0 2 ± m=1 • Using complex notation and applying! the oscillation condition, the output signal can be written as

jωot ∞ jω0t H0e 1 jmφ vo = Voe = K0,1 + Km,Nm 1e 1+j2Q ∆ω 2 ± ωr ! m=1 # " ∆ω 1 ∞ jmφ Vo 1+j2Q = H0 K0,1 + Km,Nm 1e ω 2 ± ! r " # m=1 % 1 ∞ $ Real Part: Vo = H0 K0,1 + Km,Nm 1 cos(mφ) 2 ± ! m=1 # " Imag Part: ∆ω H0 ∞ 2VoQ = Km,Nm 1 sin(mφ) ω 2 ± r m=1 Ali M. Niknejad University of California, Berkeley! Slide: 39 IL-Div Locking Range • The two equations can be solved for the unknown oscillation amplitude and phase for any incident amplitude and incident frequency, or any offset frequency:

∆ω =(ω /N ) ω i − r

• The second equation can be re-written as:

H0 ∞ ∆ω = ∆ωA Km,Nm 1 sin(mφ) 2V ± ! i m=1 # " • where Adler’s locking range has been identiﬁed:

ωr Vi ∆ωA = 2Q Vo • Unlike static dividers, the locking range is limited.

Ali M. Niknejad University of California, Berkeley Slide: 40 IL Divide by 2 Circuit • The equations can be solved analytically for a divide by 2 with cubic non-linearity 2 3 ( )= 0 + 1 + 2 + 3 2Q ∆ω sin(φ)= H0a2Vi ωr ∆ω H a V sin(φ) < 1 < 0 2 i | | → ω 2Q ! r ! ! ! ! ! ! ! 4 1 ! 3 ! ! ! V = 1 H a !+ a! V 2! + a V cos(! φ) o 3 a H − 0 1 2 3 i 2 i ! 3 0 " # $% • Locking range is improved by using a large H0/Q or a larger injection amplitude. For an LC oscillator, this is equivalent to using a larger inductor: H 0 = ωL Q • A high impedance node is a convenient place to inject the signal to limit the injection power.

Ali M. Niknejad University of California, Berkeley Slide: 41 816 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 6, JUNE 1999

Fig. 7. Schematic of the single-ended injection-locked frequency divider. Fig. 6. Noise transfer function of an ILO. IL-Div Circuit Details which allows simpliﬁcation of (20) to a ﬁrst-order differential equation

(23) The noise transfer function from to the output phase (23) is shown in Fig. 6. From (23) and Fig. 6, it is clear that an ILO has the same noise transfer function as a first-order PLL. The noise from the incident signal is shaped by the low-pass characteristic of the noise transfer function, and the output signal tracks the phase variations of the incident signal within the loop bandwidth . However, unlike a first-order PLL, the loop bandwidth of an ILO is a function Fig. 8. Schematic of the differential injection-locked frequency divider. of the incident amplitude and is larger for a larger• incidentThe injection signal is applied as a current to the tail of a cross- amplitude. coupled differential oscillator. The interpretation of the noise transfer function is a little ity, the biasing circuitry is not shown in this figure. A Colpitts different if the noise comes from the ILO itself. Within• The the transistoroscillator currents forms the core of M1/M2 of the SILFD. are a The non-linear incident signal function is of loop bandwidth, the noise from the ILO is suppressedthe by the outputinjected signal into (feedback) the gate of M1. and Transistors the injected M1 and current M2 are used of M3. ratio of the noise power to the incident power. OutsideInterestingly, the in cascode, even mainly in the to provideabsence more of isolation an injection between signal, the input node loop bandwidth, the noise suppression increases by• 20 dB per and output. Transistor M2 is sized to be smaller than M1 by M3 is moving at twice ωo decade of offset frequency, and a 1 phase noise region is almost a factor of three to reduce the parasitic capacitance at the output node (drain of M2). As a result, a larger observed. Ali M. Niknejad University of California, Berkeley Slide: 42 The noise dynamics in a superharmonic ILO are the same inductor can be used to resonate this reduced capacitance. As as those of a first-harmonic ILO, except is discussed in Section II-A, using a larger inductor increases the of that in a first-harmonic ILO due to the frequency division locking range. The power consumption is also reduced due operation. So (23) for an th-order ILFD can be modified as to the increased effective parallel impedance of the LC tank, assuming that tank losses are mainly from the inductor. Last, Li and Ci in the gate of M1 are used to model the LC tank of the preceding LC oscillator. The analogy of this circuit with the model in Fig. 3 can be realized by observing that transistor (24) M1 functions as the summing element for the incident and output signals. where is no longer a simple function of but is The schematic of a DILFD is shown in Fig. 8. The incident determined by solving the superharmonic ILO’s fundamental signal is injected into the gate of M3, which delivers the equations, (9) and (10). As the division ratio increases, the incident signal to the common source connection of M1 and noise rejection increases proportionally. So in a divide-by-two M2. The output signal is fed back to the gates of M1 and ILFD, the output close-in phase noise is dB M2. The output and incident signals are thus summed across lower than that of the incident signal. the gates and sources of M1 and M2. The common source connection of M1 and M2, even in the absence of the incident IV. CIRCUIT IMPLEMENTATION signal, oscillates at twice the frequency of the output signal, In this paper, we propose two different architectures for which makes this node an appropriate injection node for a ILFD’s. Fig. 7 shows the schematic of an SILFD. For simplic- divide-by-two operation.

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:49 from IEEE Xplore. Restrictions apply. RAZAVI: STUDY OF INJECTION LOCKING AND PULLING IN OSCILLATORS 1417

RAZAVI: STUDY OF INJECTION LOCKING AND PULLING IN OSCILLATORS 1417

Fig. 5. (a) Injection-locked divider. (b) Equivalent circuit.

Fig. 5. (a) Injection-locked divider. (b) Equivalent circuit. Fig. 4. Phase shift in an injection-locked oscillator. , the lock range exceeds (9) by 3.3%. In other words, for a 90 phase difference between its input and output, Fig. 4. Phase shift in an injection-locked oscillator. , the lock range exceeds (9) by 3.3%. In other implying that is small and . Equations (5) an injection-locked oscillator need not operate at the edge of the words, for a 90 phase difference between its input and output, and (7) therefore give lock range. implying that is small and . Equations (5) an2) injection-locked Application to oscillator Dividers: needFig. not 5(a) operate shows at the an edge injec- of the and (7) therefore give tion-lockedlock range. oscillator operating as a stage [15]. While (8) previous2) Application work has treated to Dividers: the circuitFig. as a 5(a) nonlinear shows function an injec- to derivetion-locked the lock oscillator range [15], operating it is possible as a to adoptstage a time-variant [15]. While (8) viewprevious to simplify work has the treated analysis. the Switching circuit as a at nonlinear a rate equal function to the to for the input-output phase difference across the lock range. As oscillationderive the frequency, lock range [15],and it is possibleform a to mixer adopt that a time-variant translates evident from Fig. 3(c), for this difference reaches viewto to simplify, the with analysis. the sum Switching component at suppressed a rate equal by to the the 90forat the the input-output edge of the phase lock range, difference a plausible across the result lock because range. ifAs tankoscillation selectivity. frequency, Thus, as depictedand inform Fig. 5(b), a mixer injection that translates of theevident zero crossings from Fig. of 3(c), the for input fall on thethis peaks difference of the output, reaches at tointo node ,is with equivalent the sum to component injection of suppressed(where by the little90 phaseat the synchronization edge of the lock occurs. range, Thea plausible lock range result in because this case if tankis the selectivity. mixer conversion Thus, as depictedgain) at in Fig. 5(b),directly injection into of the canthe be zero obtained crossings from of (6) the or input (8): fall on the peaks of the output, oscillator.at into If nodeand is equivalentswitch abruptly to injection and the of capacitance(where at little phase synchronization occurs. The lock range in this case is the mixer conversion gain) at directly into the RAZAVI: STUDY OF INJECTION LOCKING AND PULLING IN OSCILLATORS node is neglected, then1417 , and (9) can be written as can be obtained from (6) or (8): oscillator. If and switch abruptly and the capacitance at IL-Div Intuitive(9) Picturenode is neglected, then , and (9) can be written as (12) (9) The subtle difference between (6) and (9) plays a critical role in (12) quadrature oscillators (as explained below). If referred to the input, this range must be doubled: TheFig. subtle 4 plots difference the input-output between phase (6) and difference (9) plays across a critical the role lock in range.quadrature In contrast oscillators to phase-locking, (as explained injection below). locking to If referred to the input, this range must be doubled: mandatesFig. 4 plots operation the input-output away from phase the tankdifference resonance. across the lock (13) range. In contrast to phase-locking, injection locking to 1) Application to Quadrature Oscillators: With the aid of a (13) feedbackmandates model operation [13] or a away one-port from model the tank [14], resonance. it can be shown 1) Application to Quadrature Oscillators: With the aid of a Confirmed by simulations, (13) represents the upper bound on that “antiphase” (unilateral) coupling of two identical oscillators the lock range of injection-locked dividers. forcesfeedback them model to operate [13] or in a quadrature. one-port model It can [14], also itbe can shown be shown [14] Confirmed by simulations, (13) represents the upper bound on thatthat this“antiphase type ofIntuitively coupling” (unilateral) (injection we coupling can locking) of see two shifts identicalthat the the frequency oscillators injectionthe lockat the range tail of injection-lockedof the MOS dividers. fromforces resonance them• to sooperate that each in quadrature. tank produces It can a phase also be shift shown of [14] III. INJECTION PULLING that this typecross-coupled of coupling (injection pair locking) is mixed shifts the frequencydue to the switching action of M1/ from resonanceM2. so thatFig. each 5. (a) tank Injection-locked produces a phase divider. shift (b) of EquivalentIf circuit. the injected signalIII. frequency INJECTION liesPULLING out of, but not very far from the lock range, the oscillator is “pulled.” We study this (10) • For a strong mixing signal, 2/π componentbehaviorIf the by injectedof computing this signal current the frequency output will phase lies out of an of, oscillator but not very under far from the lock range, the oscillator is “pulled.” We study this Fig. 4. Phase shift in an injection-locked oscillator. flow into the tank, at the a lock frequency range exceeds(10) shiftlow-level (9)of byharmonics injection.3.3%. In other of ωo. In behavior by computing the output phase of an oscillator under where denotesparticular, the current a signal injected at by 2 one ω oscillatoro will be into down-converted into ωo, words, for a 90 phase difference betweenlow-level its input injection. and output, the other and whereisan the injection-lockedthe current tank produced has high oscillator by the impedance. core need of each not operate ThisA. Phase signal at the Shift edge Throughtherefore of the a Tank implying that is small and .where Equationsdenotes (5) the current injected by one oscillator into oscillator. Useexperiences of (5) thereforelock range. gives a large the required loop frequency gain and shift can Forlock subsequent the oscillator. derivations, we need an expression for the and (7) therefore give asthe other and is the current produced by the core of each A. Phase Shift Through a Tank 2) Application to Dividers: Fig. 5(a)phase shiftshows introduced an injec- by a tank in the vicinity of resonance. A oscillator. Use of (5) therefore gives the required frequency shift For subsequent derivations, we need an expression for the as tion-locked oscillator operating as a second-orderstage [15]. parallel While tank consisting of , , and exhibits (11) aphase phase shift shift introduced of by a tank in the vicinity of resonance. A (8) previous work has treated the circuit as asecond-order nonlinear function parallel tank to consisting of , , and exhibits derive the lock range [15], it is possible(11) toa phase adopt shift a time-variant of Interestingly, (9) would imply that each oscillator is pushed Ali M. Niknejad view to simplify theUniversity analysis. of California, Switching Berkeley at a rate equal to the Slide: 43 (14) to the edge of the lock range, but (6) suggests that for, say, for the input-output phase difference across the lockInterestingly, range. As (9) wouldoscillation imply frequency, that each oscillatorand is pushedform a mixer that translates (14) evident from Fig. 3(c), for this differenceto the edge reachesof the lockto range, but (6), suggests with the that sum for, component say, suppressed by the 90 at the edge of the lock range, a plausible result becauseAuthorized if licensedtank use limited selectivity. to: Univ of Calif Thus, Berkeley. as Downloaded depicted on April in 26, Fig. 2009 5(b),at 19:53 from injection IEEE Xplore. of Restrictions apply. the zero crossings of the input fall on the peaks of the output,Authorized licensedat use limitedinto to: Univ node of Calif Berkeley.is equivalent Downloaded on to April injection 26, 2009 at 19:53 of from IEEE Xplore.(where Restrictions apply. little phase synchronization occurs. The lock range in this case is the mixer conversion gain) at directly into the can be obtained from (6) or (8): oscillator. If and switch abruptly and the capacitance at node is neglected, then , and (9) can be written as (9) (12)

The subtle difference between (6) and (9) plays a critical role in quadrature oscillators (as explained below). If referred to the input, this range must be doubled: Fig. 4 plots the input-output phase difference across the lock range. In contrast to phase-locking, injection locking to mandates operation away from the tank resonance. (13) 1) Application to Quadrature Oscillators: With the aid of a feedback model [13] or a one-port model [14], it can be shown Conﬁrmed by simulations, (13) represents the upper bound on that “antiphase” (unilateral) coupling of two identical oscillators the lock range of injection-locked dividers. forces them to operate in quadrature. It can also be shown [14] that this type of coupling (injection locking) shifts the frequency from resonance so that each tank produces a phase shift of III. INJECTION PULLING If the injected signal frequency lies out of, but not very far from the lock range, the oscillator is “pulled.” We study this (10) behavior by computing the output phase of an oscillator under low-level injection. where denotes the current injected by one oscillator into the other and is the current produced by the core of each A. Phase Shift Through a Tank oscillator. Use of (5) therefore gives the required frequency shift For subsequent derivations, we need an expression for the as phase shift introduced by a tank in the vicinity of resonance. A second-order parallel tank consisting of , , and exhibits (11) a phase shift of

Interestingly, (9) would imply that each oscillator is pushed (14) to the edge of the lock range, but (6) suggests that for, say,

Authorized licensed use limited to: Univ of Calif Berkeley. Downloaded on April 26, 2009 at 19:53 from IEEE Xplore. Restrictions apply. Miller Divider / Injection Locked Divider 190 Jri Lee

V VDD DD L L L L Vout

M 4 M 3 M 3 M 4 M M M 5 M 6 5 6 ! + AB I inj I inj

MM12 V M M in 1 2 Vin

(a) (b)

Fig. 5.30 (a) Type II regenerative divider, (b) redrawn to shown injection locking.

• The samebe redrawn circuit as that topology in Fig. 5.30(b). Itcan in fact be resembles seen an to inj ection-lockedbe an injection divider locked(which divider will be or discussed a Miller in the next divider. section): M3 and M4 form a cross-coupled pair, and M5 and M6 appear as diode-connected transistors to lower the Q of the tank • The devicesand increase M5/M6 the locking are range. not The differentialneeded injection in thein such normal a manner injection is be- lockedlieved divider, to help enlargebut here the range they of operation act toto some lower extent. It the is possible Q of to ﬁnd the a tank, increasingself-resonance the lock frequency range. of the circuit if (W /L)3,4 > (W/L)5,6 [22]. • A Miller divider can be designed so that it does not oscillate in the absence5.8 Injection-Locked of an input Dividers signal.

The operation speed of dividers can be further boosted up if we simplify the structure at the circuit level. Since a cross-coupled VCO provides ultimate simplicity in Ali M. Niknejad generating differential oscillation,University of one California, may thinkBerkeley of injecting a periodic signal (ap- Slide: 44 proximately twice the VCO free-running frequency) into the common-mode point of it and forcing the VCO to lock. Recognized as an injection-locked divider, this approach is indeed an inverse operation of push-push oscillators. Among the exist- ing divider topologies, it basically reaches the highest speed. The injection locking phenomenon can be explained as adding an external sinusoidal current Iin j to a well-behaved oscillator [Figure 5.31(a)]. If the amplitude and frequency of Iin j are chosen properly, the circuit oscillates at the injection frequency of !in j rather than the tank resonance frequency !0. The key point here is that, to accommodate the phase shift contributed by the tank at !in j, Iosc (the intrinsic oscillation current) and Iin j must sustain a certain phase difference such that the total phase shift maintains 0◦. Intuitively, the injection locking would occur only in the vicinity of !0 and the locking range is limited. In fact, it can be analytically derived from different approaches [23][24] that the normalized locking range is given by References

B. Razavi, “A Study of Injection Locking and Pulling in Oscillators,” IEEE J. of Solid-State Circuits, vol. 39, no. 9, [Razavi] Sept. 2004, pp. 1415-1424.

R. Adler, “A Study Locking Phenomena in Oscillators,” Proc. of the I.R.E. and Waves and Electronics, June 1946, pp. [Adler] 351-357.

[Paciorek] L. J. Paciorek, “Injection Locking of Oscillators,” Proc. of the IEEE, vol. 53, no. 11, Nov. 1965, pp.1723-1728.

K.-C. Tsai and P. R. Gray, “A 1.9-GHz, 1-W CMOS Class-E Power Ampliﬁer for Wireless Communications,” [Tsai] JSSC, vol. 34, July 1999

Y. H. Chee, Ultra Low Power Transmitters for Wireless Sensor Networks, Ph.D. Dissertation, U. C. Berkeley, Spring [Chee] 2006.

Z. Deng, A.M. Niknejad, “9.6/4.8 GHz dual-mode voltage-controlled oscillator with injection locking,” [Deng] Electronics Letters, vol. 42, Nov. 9 2006, pp. 1344-1343.

Frank P. O’Mahony, 10GHZ GLOBAL CLOCK DISTRIBUTION USING COUPLED STANDING-WAVE OSCILLATORS, [Mahony] Ph.D. Dissertation, 2003, Stanford University

A. Rofougaran et al, “A Single-Chip 900-MHz Spread-Spectrum Wireless Transceiver in 1- m CMOS—Part I: [Rofoug] Architecture and Transmitter Design,” IEEE J. of Solid-State Circuits, vol. 33, no. 4, April 1998, pp. 515-533.

P. Andreani et al, “Analysis and Design of a 1.8-GHz CMOS LC Quadrature VCO”, IEEE J. of Solid-State Circuits, [Andreani] vol. 37, no. 12, Dec. 2002, pp. 1737-1747.

H. Ratech and T. H. Lee, “Superharmonic Injection-Locked Frequency Dividers,” IEEE J. of Solid-State Circuits, [Rategh] vol. 34, no. 6, June 1999, pp. 813-821.

Ali M. Niknejad University of California, Berkeley Slide: 45