Intel @ HiPC 2013
Venue: Park Plaza, Bangalore Date: 20th December 2013
About HiPC 2013 The 20th IEEE International Conference on High Performance Computing (HiPC 2013) provides an ideal platform for presenting current work by researchers from around the world as well as to highlight activities in Asia in the area of high performance computing.
Intel’s ‘Birds of a Feather’ Sessions Performance productivity challenges and researches Xeon-Phi Performance 1 for the future of computing - By Victor Lee 2 for Real World Applications – By Abstract: Over the past few decades, compute Dr. Paresh Pattani
Session performance has been improving steadily due to the Session advancements in semiconductor manufacturing Abstract: This talk will technology, circuit design and computer architecture. We discuss applications expect the technology treadmill to continue providing us performance on Intel® with innovations that would take us to Exascale Xeon Phi™ for Numerical computing within this decade. Many technology Weather Simulation, Life advances that brought us the performance improvement Sciences, Oil & Gas, have also increased the level of complexity programmers Manufacturing and must deal with. Similar trends in other technology areas Financial Services will make performance productivity one of the grand verticals. Performance challenges in the future of computing. This talk will of key applications, discuss technology trends for future computing and how programming models these trends have created performance productivity and parallelization/ challenges for developers. It will also provide a survey of vectorization researches that academia and industry have started to methodology will also overcome these challenges. be presented. About the Speakers ee ttani a or L Vict esh P ar . P
Victor Lee received a B.S. in Electrical Dr Dr. Paresh Pattani is Director, Data Center Engineering from University of Computing, in Intel Corporation’s Washington in 1994, an S.M. in Software & Services Group (SSG). Paresh Electrical Engineering and Computer has been with Intel for 13 years in Science from Massachusetts Institute Software & Services Group. Paresh has of Technology in 1996. He joined Intel 20+ years industry experience in Data Corporation in 1997 where he worked Center space and manages engineering on the Intel® Pentium® Pro, the Intel® teams enabling Enterprise, Big Data, Pentium® 4 Processor, the Intel® Cloud and HPC verticals such as Itanium® Processor and the QPI Manufacturing, Energy, Financial Interconnect Architecture. He is also a Services, Life Sciences and Digital key contributor to the Intel Many Content Creation segments. He is Integrated Core Architecture and a leading the customer enabling for Intel® member of the Intel® Xeon Phi™ Xeon®, Intel® Xeon Phi™ and Microserver Coprocessor design team. Victor is an platforms. IEEE senior member, a principal Paresh has a Ph.D. in Civil Engineering engineer and research scientist in with specialization in computational Intel’s Parallel Computing Lab. His mechanics from the University of British research interests include computer Columbia, Vancouver, Canada. He has an architecture, parallel algorithms and MBA from University of Texas at Austin applications and auto-tuning. and Bachelor of Technology from Indian Institute of Technology, Mumbai, India.
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