Bruno Duarte 09/2020 Application Engineer Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
2 1939–1998: 1999–2013: 2014+: Hewlett-Packard years Agilent Technologies years Keysight years
A company founded on Spun off from HP, Agilent became On November 1, Keysight became electronic measurement the World’s Premier Measurement an independent company focused on innovation Company the electronic measurement industry
In September 2013, it announced the spinoff of its electronic measurement business
3 WIRELESS 5G
NETWORKS & AUTOMOTIVE CLOUD & ENERGY
INTERNET OF THINGS IOT AEROSPACE & DEFENSE
ACCELERATING INNOVATION TO CONNECT AND SECURE THE WORLD
4 Transmitter Receiver
Channel
5 CPU Graphic card Cable On board video processor LED display
Interconnects
Signal integrity is about the problems interconnects introduce and how to avoid them. – Dr. Eric Bogatin
6 S-parameter of a PCIe channel
• Signal integrity or SI is a set of measures of the quality of an electrical signal. Signal integrity engineering is the task of analyzing and mitigating these effects. It is an important activity at all levels of electronics packaging and assembly, from internal connections of an integrated circuit (IC), through the package, the printed circuit board (PCB), the backplane, and inter-system connections. • Some of the main issues of concern for signal integrity are ringing, crosstalk, ground bounce, distortion, signal loss, and power supply noise.
7 SIGNAL INTEGRITY METRICS: • How much resolution? • How much noise? • What range of vertical scaling? • How flat is the frequency response? • When do spurs appear in frequency domain? • How accurate is the time scale? • How much intrinsic jitter does the scope have? • How many effective bits for scope?
8 • Lowest noise < 1.0 mV rms* to < 0.5 mV rms* • Lowest intrinsic jitter 20 fs rms* • Lowest inter-channel jitter 10 fs rms* • Highest ENOB > 5.4 bits @ 110 GHz* > 5.5 bits @ 70 GHz* > 6.0 bits @ 33 GHz* • Flattest frequency response (magnitude and phase)
9 Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
10 On an oscilloscope we monitor the waveform transitions and note the jitter at each transition point. This is called the Time Interval Error (TIE) record.
11 PHASE NOISE & JITTER
• In the time domain, rms phase deviation is called jitter • Frequently, people concerned about jitter deal with clock ∆풕 = 풋풊풕풕풆풓 signals, and thus are more concerned about measuring square wave type signals as opposed to the sinusoids we’ve been dealing with • To relate rms phase deviation to jitter, we can use the following mathematical relation: 푻풑풆풓풊풐풅
흓푹푴푺 흓푹푴푺 풋풊풕풕풆풓(풔풆풄풐풏풅풔) = [푻풑풆풓풊풐풅(풔풆풄풐풏풅풔)] = ퟐ흅 ퟐ흅풇풄
Percentage of total angular period Carrier signal period affected by rms phase noise (time) –same as ퟏ/풇풄 12 Total Jitter (TJ)
Bounded UnBounded
Deterministic Random Jitter Acronyms: Jitter (DJ) (RJ) DDJ: Data Dependent Jitter BUJ: Bounded Uncorrelated Jitter ABUJ: Aperiodic Bounded Uncorrected Jitter Correlated with Data Uncorrelated with (DDJ) Data (BUJ)
InterSymbol Non DutyCycle Periodic Gaussians (s, Interference Periodic Distortion (DCD) Jitter (PJ) RJ ) (ISI) (ABUJ) RMS
Tr, Tf D Settling Time Crosstalk Clocks Thermal Shot Non Linear Reflections Crosstalk Clock Recovery 1/f Non Flat Freq One-Time Response Event Burst
13 Waveform Clock Acquisition Reference
Complete TIE Record Evaluate TIE
DDJ Analysis DDJ: TIE per Bit
RJ Extraction RJ/PJ TIE Record
Dual Dirac Reported Values of TJ, RJ, DJ Analysis DD 14 SPECTRAL VS. TAIL FIT EXTRACTION
No Crosstalk With Crosstalk Analyze the bathtub plot with both RJ Spectral Extraction Spectral Extraction extraction
Slope discontinuity. modes to Over reports RJ. explore the presence of Tail Fit Extraction Tail Fit Extraction crosstalk or ground bounce.
15 N5400A EZJIT Plus for N8823A EZJIT E2688A High-Speed N8827A PAM-4 Clock Jitter Analysis and RJ Complete for Vertical SDA for Reference Recovery Scope Removal Noise Analysis Clock Recovery and Calibration Eye Analysis
N8833A Crosstalk N5461A Serial Data N5465A InfiniiSim Analysis and Removal Equalization Software De-embedding Application Software
16 • Demand for increased network bandwidth in data centers • 400G links will be the next step in meeting the need for speed • Multi-level signaling formats such as Pulse Amplitude Modulation (PAM-N) are technologies that will enable 400G implementation
17 PAM4 is a next generation multilevel signaling architecture
NRZ
PAM4
18
JITTER ANALYSIS WITH DE - EMBEDDING AND EQUALIZATION Connector Txp Connector Rxp + + Tx Channel Rx EQ - Txn Rxn -
After Scope De-embedding to the TX point Measurement Node After Scope Equalization
19 Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
20 Connectors
Backplanes Printed Circuit Boards
Cables
Line Cards Note: These are all examples of “Linear Passive Interconnect” 21 C L A S S I C A L T D R / T D T MEASUREMENTS VS S - PARAMETERS
22 HOW DO WE CHARACTERIZE THE CHANNEL?
1 Probing VNA Station or 2 TDR Probe Tips 3 4
Goal: Characterize the channel WITHOUT including effects of non-ideal instrument performance, cables and probes!
23 SIMPLE PCB TRACE EXAMPLE
24 TDR Impedance Transitions Should be capacitive Should be inductive (lower impedance) (higher impedance) 25 Tremendous insight together. Where is the most useful information? - Time domain? - Frequency domain? BOTH are needed!! Port 1 Port 2 Port 3 Port 4 Four-port single-ended device
Return Loss or TDR Insertion Loss or TDT Near End Crosstalk (NEXT) Far End Crosstalk (FEXT)
FFT IFFT Frequency Domain Parameters Time Domain Parameters
26 Port 1 Port 2 Transmission line Differential Mixed-mode Differential Port 1 Port 2 S-parameters V Transmission line Vout indiff diff V Port 3 Port 4 V incomm outcomm
27 Differential Signal Common Signal Smixed-mode Stimulus Stimulus
Differential SSSSDD11 DD 12 DC 11 DC 12 Response SSSSDD21 DD 22 DC 21 DC 22 SSSS Common CDCDCCCC11 12 11 12 Response SSSSCDCDCCCC21 22 21 22
28 T D R OSCILLOSCOPES VS. NETWORK ANALYZERS
vs. or and?
Oscilloscope with Network TDR Function Analyzer
29 DUT: 50 Ohm pattern
VNA-TDR TDR Scope
1 ohm/div 1 ohm/div
VNA Based TDR measurements = Low Noise
30 DUT: 50 Ohm pattern
VNA-TDR TDR Scope
Averaging… 1 ohm/div 1 ohm/div
Averaging can lower noise BUT…
31 DUT: 50 Ohm pattern
VNA-TDR TDR Scopes
Averaging… 1 ohm/div 1 ohm/div
Real-Time Analysis
32 U S E E Y E DIAGRAMS T O EVALUATE A CHANNEL
Data rate: 32 Gbps Nyquist: 16 GHz
Time (psec) 33 The ENA Option TDR is an application software embedded on the ENA, which provides an one- box solution for high speed serial interconnect analysis.
3 Breakthroughs for Signal Integrity Design and Verification
Time Domain Frequency Domain Simple and Intuitive Operation Eye Diagram
Fast and Accurate Measurements
High ESD Robustness
ESD protection inside Advanced TDR Measurements 34 Available for free download at www.keysight.com/find/ena-tdr_compliance
Cable / Connector Tx/Rx Impedance (Hot TDR)
• USB • HDMI • HDMI • SATA • SATA • MIPI • DisplayPort • 10GBASE-KR/40GBASE-KR • 100BASE-TX • MHL • 10GBASE-T • Thunderbolt • 10GBASE-KR/40GBASE-KR • SD Card (UHS-II) • MHL • Cfast • PCIe • BroadR-Reach
35 • Up to 67 GHz of bandwidth with 6.66 ps rise time enables measurement to the latest high-speed serial standards • Unmatched performance • Low noise floor for accurate and repeatable measurements: 20 μV rms • Wide dynamic range to observe the true performance • of your device: > 110 dB • Fast measurement speed for real-time analysis: 251 msec (1601 points, 2-port cal) www.keysight.com/find/pna-tdr
• State-of-the art calibration techniques reduce measurement errors • Automatic deskew ensures easy removal of fixture and • probe effects • Full calibration available for the utmost in measurement accuracy
36 • Dedicated GUI for TDR analysis provides intuitive operation for users TDR Return Loss not familiar to VNAs and S-parameter (Tdd11, Tdd22) (Sdd11, Sdd22) measurements
• Easily locate source of loss, TDT Insertion Loss reflections and crosstalk by (Tdd21, Tdd12) (Sdd21, Sdd12) simultaneous analysis of both time and frequency domains
Similar look-and-feel to TDR scopes
37 Measurements (Modes) S93010A Time domain S93011A PNA-TDR TDR Scope Frequency Domain (S-parameters) Yes Yes Yes Time Domain (TDR/TDT) Yes Yes Yes Eye Diagram / Mask Testing No Yes (simulated) Yes (live) Oscilloscope (measure waveforms) No No Yes Jitter Analysis No No Yes
Features S93010A Time domain S93011A PNA-TDR TDR Scope Speed and Accuracy Best Best Fair ESD Robustness Best Best Fair Simple and Intuitive Operation Fair Yes Yes
38 DATA ANALYSIS WITH N - P O R T P LT S www.keysight.com/find/plts
Advanced TDR Measurements 39 CROSS - H A R D W A R E MEASUREMENT SYSTEMS
DCA-X 86100D with TDR modules
PXIe VNA
ENA/PNA/PNA-X
40 Probing Advantage • Flexibility Disadvantage • Expensive • Need ISS calibration substrate for probe tip ref plane
Fixtures Advantage • Easy to Use Disadvantage • Each application requires different fixture • Not electrically transparent, they have mismatch, loss and delay that must be characterized and removed from the DUT measurement (de-embed)
41 OVERVIEW OF FIXTURE REMOVAL TECHNIQUES
Most Accurate SOLT S-Parameter De-embedding (Short-Open-Load-Thru One-Port Automatic Calibration) Fixture Removal (AFR)
For qualitative comparisons of the different methods
Port Extension
Time Domain gating
Most Simple
Advanced TDR Measurements 42 ONE - P O R T A F R ( AUTOMATIC FIXTURE REMOVAL)
Calibrate at connectors 1 Probing VNA Station or 2 TDR 3 4
Goal: Characterize the channel WITHOUT including effects of non-ideal instrument performance, cables and probes
Process with One-Port AFR: 1. SOLT calibration at VNA/TDR connectors 1&2 2. Do not use VNA/TDR channels 3&4 3. Measure SDD11 of the channel into an open and/or short. “Measurement Planes” 4. Use one-port AFR to determine SDD21 (channel .s4p). Shorted This was initially done using Keysight Physical 1 VNA or Layer Test System software (PLTS). TDR 2 This can be done directly on the Keysight PNA today. And this can be done on the DCA-TDR. Reference Plane
Advanced TDR Measurements 43 AFR Fixtures family • 2X thru • 1x open, 1x short • Asymmetric fixtures • Band pass devices • Non-50 Ohm Z0
AFR Algorithm Fixture S-parameter files • Describe Fixture • Specify Standards • Measure Standards • Remove Fixture • Save Fixture
44 Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
45 Channel Element Removal
Channel TX VMeas(t) Element
Examples: Test Fixtures Cables Connectors TX Lossy PC boards
VSim(t)
46 Channel Element Insertion
V (t) TX Meas
Example: Adding a standard loss Cable model. System Validation TX Channel Element
VSim(t)
47 Channel Element Replacement Channel TX VMeas(t) Element ‘A’
Example: Replace a Test Fixture with a standard channel model. Channel TX Element ‘C’ VSim(t)
48 We are going to perform a Transformation of a Waveform ACQUISITION of signal SIMULATED Result of through 12 feet of cable removing the cable
Transfer Function
r(t) hC (t) = s(t) 49 After De-embedding
Before De-embedding
50 You must have: System Definition: 1. A definition of the measurement / analysis circuit, 2. A definition of the simulation circuit,
51 Design and Validation engineers understand ‘RF effects’ and Measurement concepts. – Signal access, loss affect results, reflections, crosstalk, etc. – Designers need to be thinking of minimizing measurement problems—think ahead!
Time domain de-embedding or embedding can be used effectively to characterize access impaired devices. – Remove loss or loading effects, virtually probe – Simulate worst case components
The Key is to Generate Transfer Functions – Two circuit approach: circuit element definitions and observation points – Superposition is used to relate an observation of Measurement circuit to observation point of simulation circuit
De-Embedding is NOT ‘Free’ – If Loss is Great then measurements’ sensitivity to Signal-to-Noise Ratio must be Considered. – Whole system model Includes driving & load impedances and transmission lines and parasitic
You also need to obtain accurate representations of the model elements – Measure or Estimate S-Parameters/RLC values. – Understand how to measure properly
Very Complex system models can be evaluated.
52 Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
53 AMPLITUDE INTERFERENCE UNCORRELATED WITH DATA PATTERN
Impact on Eye Victim In
No crosstalk Aggressor Dv
Victim Out
Dt = Dv/Slopevictim With crosstalk Dt
54 Crosstalk Sources
Transmission Power Supply Line
Serial data Serial data Power Serial data Serial data victim victim supply victim victim victim Simulta- Power Voltage Near End Far End neous Supply Dependent Crosstalk Crosstalk Switching Induced Amplitude (NEXT) (FEXT) Network Jitter Noise (SSN) (PSIJ) (VDAN)
Eye closure, Eye closure, Ground Bounce, Increased jitter Eye closure increased jitter increased jitter Vcc sag
55 NEXT Rx Tx Rx Tx Tx Victim Rx Tx Victim Rx Tx Rx Tx Rx FEXT
No Serial Aggressor NEXT & FEXT Aggressors
56 NEXT and FEXT Aggressors Off
With NEXT and FEXT Aggressors
Eye diagram correlates
Use the crosstalk app to remove effect of NEXT and FEXT
NEXT and FEXT Removed 57 JITTER DECOMPOSITION IS RUN ON THE WAVEFORMS BEFORE AND AFTER CROSSTALK REMOVAL
Waveform Waveform with XT without XT
TJ = 158ps TJ = 124ps PJdd = 58ps An improvement of 20% to total jitter PJdd = 27ps DJdd = 68ps without crosstalk. DJdd = 33ps
58 Introduction Advanced Jitter Measurements Advanced TDR Measurements Embedding & De-embedding Crosstalk Analysis on Real-Time Scopes Power & Signal Integrity Simulation Summary
59 Simulation Measurement
PC: Wild River Technology Expected Performance Measured Result
60 Simulation Measurement
Printed Circuit Expected Performance Measured Result Board Fabrication Process
61 Software Products Hardware Products
62 Cross Talk, Jitter Material Loss vs Interconnect Matching Tolerances Frequency Impedance Channel Simulation
S-Parameter S-Parameter TDR
IC IC Package Package Connector Connector Cable
PCB PCB Rx Tx Active Passive: 3D-EM Models Active Rise Time Differential Lines - Mode Electrical Length Skew Power Integrity: IR Drop, PDN Bandwidth Conversion - EMI/X-Talk Impedance, Resonances, SSN Transient Mixed Mode BW=0.349/tr
S-Parameter
63 FDTD ( Finite Difference Time Domain ) • 3D arbitrary structures • Full Wave EM simulation • For large and complex problems • Time Domain • EM simulations per each port • Supports GPU based hardware acceleration FDTD FEM ( Finite Element Method ) • 3D arbitrary structures • Full Wave EM simulation • Direct, iterative solvers • Frequency domain • Multiport simulation • High Q FEM MoM
MoM ( Method of Moment ) • 3D planar structures • Full Wave and Quasi-Static • Direct, iterative solvers • Dense & compressed solvers • Frequency Domain • Multiport simulation
64 64 A COHESIVE WORKFLOW FOR SI AND PI ANALYSES
Layout Import into ADS SIPro / PIPro Signal/Power Integrity Analysis (Direct *.brd Import, Allegro ADFI, CR8000 ABL PCB Characterization and Model (Transient Convolution, Extraction Channel Sim, or ODB++ flow) DDR Bus Sim)
Layout ADS Schematic
4 New EM Simulators
IR Drop PDN Z Resonances Power Plane Power AwareSI
- imp PIPro SIPro
65 Eye diagram Mixed-mode S-parameters
Time domain reflectometry Single pulse response
66 The case of the failing virtual channel
1 Analyze the channel
Find the root cause of 2 degradation
3 Explore design solutions
67 1
Channel 0
68 2UI 2UI 2UI
69 70 PRBS at the transmitter Received PRBS at Receiver
71 72 The case of the failing virtual channel
1 Analyze the channel
Find the root cause of 2 degradation
3 Explore design solutions
73 Expectation Expectation
SDD11 (dB) - 30 dB SDD21 (dB) -10 dB at 16 GHz
Freq (GHz) Freq (GHz)
3-inch 3-inch Structure Via microstrip stripline
Estimated Loss 5 Small 5 (dB at Nyquist) Impedance <100 ~100 (Ohm) ? Not what we expect!
74 microstrip differential pair 3-inch 3-inch Structure Via microstrip stripline Differential Via structure Estimated Loss 5 Small 5 (dB at Nyquist) stripline differential pair
Transmission line only
75 vv in len= → =4 len f == v 6 4 res 4len nsec 1.5 f (GHz) = res For FR4, expect fres = 20 GHz Len ~ 75 mil len (in)
Len ~ 75 mil
76 The Root Cause: The via stub is resonating at frequency close to Nyquist and degrading the frequency spectrum of the input signal.
77 The case of the failing virtual channel
1 Analyze the channel
Find the root cause of 2 degradation
3 Explore design solutions
78 Channel with via stub
Channel with via stub removed
79 Date Rate: 32 Gbps Date Rate: 18 Gbps Nyquist Frequency: 16 GHz Nyquist Frequency: 9 GHz
Loss at Nyquist: ~-14 dB Loss at Nyquist: ~-6 dB
80 After lowering data rate: • Larger unit interval • Larger eye opening
81 Received waveform
Feedforward Symbol Decision Filter Detector
Decision Feedback Filter
DFE: If I am seeing a “1”, emphasize the next “0”, vice versa.
82 Decision Feedback Equalizer: At the arrival of received data (symbols), DFE algorithm detects and makes a decision. Assuming the decision is correct, proper tap values are chosen and feedback to the originally received data.
83 VRMs and Sinks Current Density View Temperature View
4 4 4
1 1 1 2 2 2
3 3 3
• Additional heat sources can be added to the analysis (thermal stimulus is not just the heat from VRMs, sinks and joule losses in the traces)
• Thermal boundary conditions: heatsinks, airflow, thermal pads, board boundaries
84 1. Simulate the channel 2. Identify the root cause of degradation
3. Explore design solutions
85 YouTube Video: https://youtu.be/mpyMWuVrKKc Workspace Download: http://www.keysight.com/find/eesof-how-to-solve-si-problems Tim’s Knowledge Center: http://edadocs.software.keysight.com/display/TKC/20181108+CU+SI+Seminar
86 ONLY KEYSIGHT HELPS DESIGNERS WITH EACH STEP IN THE DESIGN CYCLE
Design and Simulation Analysis and Debug Compliance
Debug System Prototype & Turn-on and Product Concept Validate System Test Compliance Specification Simulation Stablize Characterize
EDA Design EDA Design Network Analyzer- Network Analyzer- Network Analyzer- TDR TDR EDA Design EDA Design TDR Oscilloscopes Oscilloscopes Oscilloscopes Oscilloscopes Physical Layer Test Physical Layer Test BERT BERT BERT Software Software BERT Logic Analyzer Oscilloscopes Logic Analyzers Physical Layer Test Software Physical Layer Test Protocol Logic Analyzer Physical Layer Test Analyzer/Exerciser Software Logic & Protocol Protocol Analyzer/Exerciser Analyzer/Exerciser
87 Bruno Duarte [email protected] (11) 98353-0059