Today’s agenda (2-FEB-2010)

• Will check your web page (links), which should include –Block diagram – Acronym (what it is called) – Schedule outline –Description paragraph

• To be augmented with table of specifications

• IBM submission updates • Final Design Review Final • BeginLayout • Readiness Review Design • Specification Review • Final confirmation of key parameters – documentation, hold review Compile – Post layoutsimulations – hierarchybuild LVS checksduring – Apriltocomplete layout All – Floorplanning – ofkeyparameters Confirmation – Design simulations,iteration – ofkeyparameters Table – –Block schematics Complete – diagram Suggested Milestones [March 15] [early May] [Feb 15] [March 1-14]

2 Lecture 5 • VLSI Economics VLSI • •Scaling – Future Challenges Future – –Interconnect–Transistors Outline

3 Lecture 5 Growth limitedbypower • >65,000 Predicted • Transistor countdoubled • In 1965, GordonMoorepredictedthe • transistors by1975! every yearsinceinvention transistors onanIC exponential growth ofthenumber Moore’s Law [Moore65]

4 Lecture 5 Transistor countshavedoubledevery26 •

months forthepast threedecades. Transistors 1,000,000,000 100,000,000 10,000,000 1,000,000 100,000 10,000 1,000 4004 9017 9018 9019 2000 1995 1990 1985 1980 1975 1970 8008 8080 8086 More Moore 80286 Intel386 Year Intel486 Pentium Pentium Pro Pentium II Pentium III Pentium

5 Lecture 5 Clock frequencies have alsoincreased • exponentially

A corollaryof Moore’s Law – Clock Speed (MHz) Speed Clock 10,000 1,000 100 10 1 9017 9018 9019 002005 2000 1995 1990 1985 1980 1975 1970 Speed Improvement Year Pentium 4 Pentium Pro/II/III Pentium Intel486 Intel386 80286 8086 8080 8008 4004

6 Lecture 5 Why fastercomputers? • Why moretransistorsperIC? • Why?

7 Lecture 5 Why fastercomputers? • Why moretransistorsperIC? • –Larger Smallertransistors – dice Why?

8 Lecture 5 Why fastercomputers? • Why moretransistorsperIC? • – Fewer gate delayspercycle Fewer – Better microarchitecture (moreIPC) – Smaller, faster transistors – –Larger Smallertransistors – dice Why?

9 Lecture 5 • Scale factorS Scale • Feature sizeshrinks by30%every2-3years • The onlyconstant inVLSIisconstantchange • – Wires donotimprove Wires – becomefaster Transistors – becomecheaper Transistors – Technology nodes – Typically – (and maygetworse) S = 2 Scaling

Feature Size (μm) 0.1 10 1 9517 9518 9519 9520 2005 2000 1995 1990 1985 1980 1975 1970 1965 10 6 3 1.5 Year 1 0.8 0.6 0.35 0.25 0.18 0.13 0.09

10 Lecture 5 Lateral Scaling • Constant FieldScaling • What changesbetween technologynodes? • Oftendoneasaquick gateshrink(S=1.05) – Only gatelength L – (V Voltage – Alldimensions(x,y,z=>W,L,t – –Doping levels Scaling Assumptions DD ) ox )

11 Lecture 5 Device Scaling

12 Lecture 5 Device Scaling

13 Lecture 5 Device Scaling

14 Lecture 5 Device Scaling

15 Lecture 5 Device Scaling

16 Lecture 5 Device Scaling

17 Lecture 5 Device Scaling

18 Lecture 5 Device Scaling

19 Lecture 5 Device Scaling

20 Lecture 5 Device Scaling

21 Lecture 5 Device Scaling

22 Lecture 5 Device Scaling

23 Lecture 5 • Velocity saturationmakeslateral scaling Velocity • Current densitygoesupwith scaling (bad) • powergoesdownwithscaling (good) Dynamic • getfasterwithscaling (good) Gates • ONresistance *micronimproveswithprocess But • capacitancepermicron isnearlyindependentof Gate • unsustainable process Observations

24 Lecture 5 • Estimate theONresistanceofaunit(4/2 Estimate • The FO4inverterdelayin theTTcornerfora • Gate capacitance istypicallyabout2fF/ • transistor. ps process offeature size

Example f (in nm)isabout0.5 μ m λ

) f

25 Lecture 5 •If•RC W =•FO4 = 2 (0.5 = 5 (4/2 theON resistanceofaunit Estimate • FO4 inverterdelayintheTTcornerfor a The • capacitanceistypicallyabout 2fF/ Gate • transistor. process offeaturesize

– Unit resistanceisroughly independentof Unit –

f τ f

, R=8.33k

) /15=( = 15RC f /30) ps/nm Solution

Ω f

(in nm)isabout0.5 f μ m λ

) f ps

26 Lecture 5 •Wire Wire thickness length• Global interconnect – Local / scaledinterconnect – Hold constantvs.reduceinthickness – Die size scaledbyD • Scaling Assumptions c ≈ 1.1

27 Lecture 5 Interconnect Scaling

28 Lecture 5 Interconnect Scaling

29 Lecture 5 Interconnect Scaling

30 Lecture 5 Interconnect Scaling

31 Lecture 5 Interconnect Scaling

32 Lecture 5 Interconnect Scaling

33 Lecture 5 Interconnect Scaling

34 Lecture 5 Interconnect Scaling

35 Lecture 5 Interconnect Scaling

36 Lecture 5 Interconnect Delay

37 Lecture 5 Interconnect Delay

38 Lecture 5 Interconnect Delay

39 Lecture 5 Interconnect Delay

40 Lecture 5 Interconnect Delay

41 Lecture 5 Interconnect Delay

42 Lecture 5 Interconnect Delay

43 Lecture 5 Global wires aregettingslower • Local wires aregettingfaster • Capacitance permicronis remainingconstant • – But notamajorproblem But – quitetrackingtransistorimprovement Not – 1/10ofgate capacitance Roughly – 0.2fF/ About – – No longerpossible tocrosschipinone cycle No – μ Observations m

44 Lecture 5 • IndustryAssociationforecast Semiconductor • – Intl. Technology RoadmapforSemiconductors Intl. – ITRS

45 Lecture 5 Physical Limits • Challenges Productivity • •Power Interconnect Woes • Improved Cost • Woes Improved Performance • Scaling Implications

46 Lecture 5 In 2003,$0.01bought you100,000 • transistors – Moore’s Lawisstillgoingstrong Moore’s – Cost Improvement [Moore03]

47 Lecture 5 •But… SIA madeagloomyforecast in 1997 • ea ol ec iiu t20–180 nm,then wouldreachminimumat250 – Delay – get worsebecauseof wires Interconnect Woes [SIA97]

48 Lecture 5 100 kgateblocks ok • •But… SIA madeagloomyforecast in 1997 • –Global scale Misleading – wires 180 nm,then wouldreachminimumat250 – Delay – get worsebecauseof wires Interconnect Woes

49 Lecture 5 But themicroarchitect canplanaroundthis • We can’tsendasignalacross alargefastchip • in onecycleanymore Justas off-chip memorylatenciesweretolerated – Reachable Radius reachable radius reachable of Scaling Chip size Chip

50 Lecture 5 But attention topoweris • stock dropped 8% • (ISSCC2001) Intel VPPatrickGelsinger • increasing on thenext day “Business asusualwillnot workinthefuture.” – scalingcontinuesatpresent pace,by2005,high If – 2015, surfaceofsun. nuclear reactor,by2010, arocketnozzle,andby speed processorswould havepowerdensityof Dynamic Power [Moore03]

51 Lecture 5 •V •V Major future challenge • But thiscauses exponential • increase in OFFleakage maintain device performance – No pointinhighvalue becauseofvelocitysat. No – Protect thingateoxidesandshortchannels – –Save dynamic power t DD must decreaseto decreases Static Power [Moore03] Dynamic Static

52 Lecture 5 isincreasingfasterthan • designer productivity (gates/week) – Need for goodengineeringmanagers Need – Pressuretoraiseproductivity – expensivedesigncost More – –Bigger design teams • Rely onsynthesis, IPblocks Rely • to500forahigh-endmicroprocessor Up • Productivity

53 Lecture 5 • Many reasonshavebeen predictedforendof Many • Moore’s Lawrunoutofsteam? Will • Rumors ofdemise havebeen exaggerated • scaling Interconnect delay – –Electromigration–Fabrication channeleffects Short – Subthreshold leakage, tunneling – Dynamicpower – costs build transistorssmallerthananatom… Can’t – Physical Limits

54 Lecture 5 •C •m = profit priceS Selling • margin – Fixed cost Fixed – Recurring cost – engineering cost(NRE) Nonrecurring – –S total total = totalcost = C total / (1-m) VLSI Economics total

55 Lecture 5 • Prototype manufacturing Prototype • cost Engineering • CADtools: – benefits, Include training,computers – onsizeofdesign team Depends – – Test fixture and packagetooling Test – in 130 nmprocess 1M costs:$500k– Mask – Digitalback end:$1M • frontend:$100K Analog • Digitalfront end:$10K • NRE

56 Lecture 5 Fabrication • •Test•Packaging – Yield: Y=e Yield: – perwafer: Dice – $3000 cost:$500- Wafer – cost/(Dice perwafer*Yield) Wafer – •For small A, Y •For large A, Y Recurring Costs -AD ≈ → 1, costproportional toarea N 0, costincreases exponentially

=− π ⎣ ⎢ ⎡ rr A 2 2 2 A ⎦ ⎥ ⎤

57 Lecture 5 • Yield analysis Yield • Marketing andadvertising • Data sheetsandapplicationnotes • Fixed Costs

58 Lecture 5 Because youaresmarterthan everyoneelse, • wanttostartacompany tobuilda You • years: you cangetawaywith asmallteaminjusttwo venture capitalmust youraise? wireless communications chip.Howmuch – Five supportpersonnel Five – –Three Seven digital designers – analog designers Example

59 Lecture 5 • Analog designers Analog • •Digital designers: –Total: tools CAD – –computer overhead – –salary–Total: tools CAD – –computer overhead – –salary Solution Support staff • Summary • Fabrication • –Total:–computer overhead – –salary –Total:–Masks: Back-end tools: –

60 Lecture 5 • Analog designers Analog • •Digital designers: Total: $240k*3=$720k – $100kCADtools – $10kcomputer – –$30k $100k salary – overhead Total: $120k*7=$840k – $10kCADtools – $10kcomputer – –$30k–$70k overhead salary Solution Support staff • Summary • Fabrication • Total: $70k*5=$350k – –$5k–$20k computer–$45k overhead salary –$8M 2 years @ $3.91M/year – design Total: $2M/year – Masks: $1M – & Back-end tools:$1M prototype–

61 Lecture 5 Maybe youcando it forless? • New chip designisfairlycapital-intensive • backend backend fab tools Cost Breakdown 25% 25% 9% 26% entry entry 4% tools salary computer 11% overhead

62 Lecture 5 •For fornexttime Prepare1slide “update” today:• Simulation LabonThursday • Suggest tokeepforging ahead: • –(3-5 keyquestions/issues? Any – Informal verbal report min.– max) –Schedule? Website update? – Theoretical inputtoyourproject? – For nexttime

63 Lecture 5