A Thesis
entitled
Investigation of Semitransparent Cu2O/ZnO Based Heterostructure Diodes for Memory
and Related Applications
by
Ammaarah Haleemah El-Amin
Submitted to the Graduate Faculty as partial fulfillment of the requirements for the
Master of Science Degree in
Electrical Engineering
______Dr. Rashmi Jha, Committee Chair
______Dr. David Strickler, Committee Member
______Dr. Srinivasa Vemuru, Committee Member
______Dr. Richard Molyet, Committee Member
______Dr. Patricia R. Komuniecki, Dean College of Graduate Studies
The University of Toledo May 2014
Copyright 2014, Ammaarah Haleemah El-Amin
This document is copyrighted material. Under copyright law, no parts of this document may be reproduced without the expressed permission of the author. An Abstract of
Investigation of Semitransparent Cu2O/ZnO Based Heterostructure Diodes for Memory and Related Applications
by
Ammaarah Haleemah El-Amin
Submitted to the Graduate Faculty as partial fulfillment of the requirements for the Master of Science Degree in Electrical Engineering
The University of Toledo
May 2014
The purpose of this study is twofold: (1) to investigate the diode properties of semitransparent Cu2O/ZnO based heterostructures and to (2) demonstrate the memory applications of these properties. This structure is included in a Ru/Zn/ZnO/Cu2O/Cu stack and characterized as a pn heterojunction diode for crossbar array (CBA) implementation.
CBA architecture is the most favorable architecture for many novel memory devices. The basic diode parameters are extracted and discussed in relation to their functional relevance.
For example if the diode were used in a diode tile for use in Boolean logic mosaics
(composites of device tiles) or other diode applications (using CBA architecture). The diode is also characterized for use in conjunction with RRAM (two terminal digital memristive) devices. In that capacity it is used to prevent crosstalk (sneak current between devices leading to false readings). Several diode parameters are studied, in addition the reverse saturation current is modulated by varying the thickness of the Cu2O layer.
The Cu2O/ZnO heterojunction is also used to form an FTO/ZnO/Cu2O/Cu memdiode. This is a novel memelement, displaying a combination of rectification and hysteretic behavior in the IV. FTO and ZnO are both transparent, while Cu2O is partially iii so. The Cu is less important to memdiode operation and could theoretically be replaced with a transparent material. All of these materials are deposited at temperatures less than
100 °C which is a safe range for fabrication on plastic substrates. The basic parameters for this memdiode are extracted and a comprehensive device physics model is presented to explain the experimental results. Dielectric relaxation and spontaneous polarization effects are seen in ZnO/Cu2O, while the FTO is expected to contribute to the defect movement through the device. This Cu2O/ZnO heterojunction is very favorable for memory applications due to its unique analog behavior in the FTO/ZnO/Cu2O/Cu stack. Its characterization as a RRAM access device also provides a helpful model for the experimental methods required for this type of characterization.
iv
For my parents, whose belief in me has never wavered…
Acknowledgements
Over the past two and a-half years I have received support and encouragement from a great number of individuals. In particular, I am profoundly indebted to my research advisor Dr. Rashmi Jha, who was very generous with her time and knowledge. Her guidance has made this a thoughtful and rewarding journey. I would like to thank my thesis committee members Dr. David Strickler, Dr. Richard Molyet and Dr. Srinivasa Vemuru for their time and input. I am grateful to the College of Engineering for not only providing some financial support but also creating a warm and welcoming environment. I would be remiss to not thank my all of group mates both current and former. Without their friendship this would have been a very long and lonely couple of years, their help and support - whether academic or personal- has been invaluable. I would like to specifically thank
Saptarshi Mandal and Dr. Branden Long. Finally but not least, thanks goes to my friends and family, who have been an important and indispensable source of spiritual support.
Special thanks goes to my brother for innumerable rides to and from the lab, no matter the unpredictable and unreasonable hours. It goes without saying that I’m grateful to God for all the people and opportunities that I have been blessed to have in my life.
v
Table of Contents
Abstract ...... iii
Acknowledgements ...... v
Table of Contents ...... vi
List of Tables ...... ix
List of Figures ...... x
1. Introduction ...... 1
2. Background and Literature Review ...... 7
2.1 Novel memory schemes and devices ...... 7
2.1.1 Memcomputation ...... 9
2.1.2 Memristive devices ...... 11
2.1.2.1 RRAM switching types and mechanisms...... 12
2.1.2.2 Analog memristive device types and mechanisms ...... 15
2.1.3 Logic Implementations ...... 17
2.2 Architecture for the implementation of memristive devices ...... 19
2.2.1 Crossbar Array (CBA) Architecture ...... 20
2.2.1.1 Role of Access device ...... 22
2.3 Material considerations ...... 25
vi 2.3.1 Zinc Oxide ...... 26
2.3.2 Cuprous Oxide...... 26
2.4 Overview of diode operation ...... 27
2.5 Memdiode (Memory-diode) ...... 32
3. Reconfigurable Memdiode Characteristics in Cu/Cu2O/ZnO/FTO
Heterostructures ...... 35
3.1 Abstract of Chapter ...... 35
3.2 Fabrication and characterization setup ...... 35
3.3 Diode Response ...... 36
3.4 Memdiode Characteristics ...... 40
3.5 Device Model ...... 43
4. Characterization and Modulation of Relevant Cu2O/ZnO Diode Parameters for
CBA Implementation ...... 56
4.1 Abstract of Chapter ...... 56
4.2 Introduction ...... 56
4.3 Fabrication and characterization setup ...... 61
4.4 Data and Analysis...... 62
5. Conclusions and Future Work ...... 77
References ...... 79
vii A. Supplementary Information for Chapter(s) 3 and 4 ...... 89
A.1 Fabrication process flows...... 89
B. FTO and ZnO thin film characterization ...... 96
B.1 Summary of samples, data obtained etc...... 97
B.2 Test Setup and Measurement Detail...... 979
B.1 Planar (Horizontal) Electrical Characteristics...... 102
B.1 Summary of samples, data obtained etc...... 103
viii
List of Tables
Table 3-1 Ideality factors for regions in Figure 3.3 ...... 38
Table 3-2: Parameters extracted from the fitting in figure 3-9 using equation 3.3...... 44
Table 3-3: Parameters extracted from fitting I(t) at various applied bias(s) to equation 3.7,
corresponding to figure(s) 3-12...... 49
Table 3-4: a) Parameters extracted for fittings (to equation 3.8). Pulse 1 is shown in figure
3-13, Pulses 2-5 are shown in figure 3-15 ...... 54
Table 4-1: Summary of characterizations metrics for access device used in chapter 4. .. 63
Table 4-2: The variation of the ideality factor as a function of device area is shown. These
values are extracted using equation 4.1, the fittings are shown in figure 4-5...... 66
Table A-1: Fabrication detail for sample presented in chapter 4...... 89
Table A-2: Fabrication detail for sample presented in chapter 3...... 93
Table B-1: Summary of samples ...... 97
Table B-2: Parameters from variablity map ...... 97
ix
List of Figures
Figure 2-1: Schematic diagram of a memristive cell. The switching layer (S.L.) is
sandwiched between two metal electrodes. A possible voltage input pulse is shown,
this is a common way in which switching is initiated...... 11
Figure 2-2: Unipolar IV characteristics, resistive switching is induced by a voltage of the
same polarity but a different magnitude. There will be a compliance current (CC),
a circuit induced current limitation during the SET process. The schematic shows a
perfectly symmetric behavior, however practically, the SET voltage (Vth1) will be
higher than the voltage at which RESET takes place (Vth2), though the RESET
current will be higher the CC...... 14
Figure 2-3: Bipolar IV characteristics, one polarity is used to SET to LRS, and the opposite
polarity is used to RESET back into HRS. A current compliance (CC) is usually
required during the SET process to ensure the current density through the device
does not cause excess oxide degradation resulting in a permanent breakdown [45].
...... 15
Figure 2-4: A simple neural network containing three electronic neurons (N1, N2 and N3)
connected by two memristive synapses (S1 and S2). The output is assumed to
follow the threshold model, summing the inputs and “firing” when the programmed
threshold is reached. Basic neural operations have been mimicked electronically
x using this basic concept. For example, timing based learning law such as STDP
have been mimicked using this model...... 17
Figure 2-5: Schematic depiction of crossbar, highlighting a single device, the top and
bottom electrodes are referred to as wordlines and bitlines respectively...... 20
Figure 2-6: A schematic description of a crossbar array shown, the highlighted device
(yellow) is meant to be electrically isolated from the other devices. The diodes
shown in series with each RRAM device are meant to inhibit current flow to
unselected devices, this is 1D1R architecture...... 23
Figure 2-7: a) p-type material contains negatively charged acceptors (immobile) and
positively charged holes (free). The total charge is 0. b) n-type material contains
positively charged donors (immobile) and negatively charged electrons (free) The
total charge is 0. c) The free elections (n-majority carrier) near the contact region
will diffuse into the p-side. Similarly holes (p-majority carrier) will diffuse to the
n-side...... 29
Figure 2-8: a) Energy band bending under thermal equilibrium conditions. In the bulk
regions (away from the junction) the original material conditions dominate and the
band diagram is unaffected. Near the junction the bands bend to keep the Fermi
level constant. The diagram shows the direction of carrier drift/diffusion, as well as
some carriers due to thermal generation/recombination...... 30
Figure 2-9: Under forward bias (Va), the potential drop across the pn junction is reduced,
the drift current reduces slightly and the diffusion current increases. The net current
is no longer zero. This is the forward conduction region of the diode...... 31
xi Figure 2-10: Under reverse bias (Va), the potential drop across the pn junction increases,
the diffusion current decreases. The net current is no longer zero, however it is very
small. This current is called the reverse saturation current...... 32
Figure 2-11: "Reprinted with permission from S Saraf, Applied Physics Letters, 102(2),
022902-022902, (2013). Copyright 2013, AIP Publishing LLC.” ...... 34
Figure 3-1: A picture of the substrate and devices presented in this chapter, while the ZnO
is transparent, the Cu2O is semi-transparent, and responsible for the overall
discoloration of the stack. The schematic of the device stack is also shown, a
resistor is shown in series to represent any serial resistance contributions aside from
the pn junction...... 36
Figure 3-2: a) Current vs. Voltage (IV) response for devices of the following sizes:
(30um)2, (50um)2, (100um)2, (200um)2 and (500um)2. b) Current density vs.
voltage for several devices of the following sizes are shown: (50um)2, (100um)2
and (200um)2. The overlap in the plot shows device repeatability and scalability.
...... 37
Figure 3-3: Natural log of forward current for (50um)2 device vs. applied voltage. This
lnI-V curve is separated into the four regions for which the ideality factors are
extracted ...... 38
Figure 3-4: a) Temperature variant IV curves. The presented device is swept from, 2V to
+1.5V in the temperature ranges from 77K to 354K. b) The ideality factor as a
function of temperature, this value is extracted from the regions II-IV...... 39
xii Figure 3-5: a) Capacitance vs. Voltage (CV) measurements performed on (30um)2 device
at 10kHz, 100KHz and 1Mhz. The diode is seen to turn on sooner at lower
frequencies. b) The forward capacitance is fit to equation 2...... 40
Figure 3-6: a) IV characteristics at T=83.81K of a (50um)2 device demonstrate non-zero
crossing at low temperatures. This particular temperature value is significant only
in that lies in the low-temperature range which display these characteristics. b)
Non-zero crossing on (10um)2 device at room temperature...... 41
Figure 3-7: Hysteresis under forward bias. Multiple loops can be seen for each bias. The
current increase saturates at a single bias after 2-3 loops, however, further
conductance change is seen with increased applied bias. Inset 1a shows the forward
conductance at +1V before forward hysteresis (1) after forward hysteresis (2) and
after negative hysteresis (3). The data in this figure was obtained in this order. The
device used was (200um)2...... 42
Figure 3-8: Hysteresis loops resulting from reverse bias sweeps, decreasing device
conductance is shown with subsequent loops, as well as larger decrease for larger
negative bias. This measurement was performed on the same device ((200um)2)
used in figure 3.7, and its start coincides with state (2) in the inset of that figure.
...... 43
Figure 3-9: a) A (30um)2 device was stressed using a 10ms (width), +3V (amplitude)
pulse, the pulse amplitude was limited by the measurement equipment to ~ 2.76V.
b) The current was extracted over this flat portion (V=2.76V) and fit to equation
3.3...... 44
xiii Figure 3-10: Dielectric relaxation is modeled using the Curie-Von Schwiedler law
(equation 3.6). A 0.3V voltage stress was applied, this measurement was on the
same device and directly followed the increase in figure 3-9. The device used was
(30um)2...... 46
Figure 3-11: a) A +0.15V bias is applied to an untested (30um)2 device for five 250s
increments. The time delay between applications was estimated to be between 1-2
seconds. b) The first and last point of each relaxation curve in a showing the
increasing conductance in the absence of bias...... 47
Figure 3-12: a),b),c). CVS is applied to separate untested (30um)2 devices at biases
ranging from 0.15V to 1.3V. One is able to see the transition from relaxation effect
domination to SILC domination. I(t) is fit to equation 3.7 showing both mechanisms
present throughout. I(t) vs. t is plotted for each bias, (the value of which is inset in
each figure)...... 50
Figure 3-13: d),e). CVS is applied to separate untested (30um)2 devices at biases ranging
from 0.15V to 1.3V. One is able to see the transition from relaxation effect
domination to SILC domination. I(t) is fit to equation 3.7 showing both mechanisms
present throughout. I(t) vs. t is plotted for each bias, (the value of which is inset in
each figure)...... 51
Figure 3-14: The first negative pulse (-5V/10ms) following a 100 pulse (+3V,10ms)
conductance increase is shown. This I(t) is modeled using equation 3.8. The
absolute value of the current is used. b) The raw pulse is shown. The device used
was (30um)2, the entire series of pulses is shown in figure 3-14...... 52
xiv Figure 3-15: a) The current is shown in absolute. IV sweeps are performed after each
+3V/10ms pulse for 100 cycles (The first 40 are shown). An incremental increase
in conductance is shown. This change is traced showing the current at +0.3V and
0.3V. b) IVs were similarly collected following the 100 (-5V/10ms) pulse decrease,
this is also shown using the +/- 0.3V edge of the IV. The device used was (30um)2.
...... 53
Figure 3-16: The four pulses succeeding that which is fit in figure 3.13 are also fit to
equation 3.8. All data extracted from the measurement shown in full in figure 3.14,
but for which data is used in figures 3-13-3-15 were performed on the same
(30um)2 device...... 53
Figure 3-17: a) The linear increase in conductance relative to the number of pulses is
shown to demonstrate the conduction modulation with number of pulses. This is
shown relative to the initial state of each device to account for any initial variability.
b) The device is “switched” between two states, a 5ms, +3V pulse increase (ON)
vs. a -5V, 5s decrease (OFF). All measurements in figure 3-16 were performed on
(30um)2 devices...... 55
Figure 4-1: Redrawn in the style of reference [17]. An AB+C gate logic block using pull-
up and pull-down resistor tiles between crossbars on a substrate that supplies power
and ground. Junctions in these tiles supply the pull-up and pull-down resistors,
while the configurable diode tile is used for AND and OR gates. Diode crossbars
such as this in conjunction with RRAM crossbars can be used to form state
machines [114] which can complete nearly any function...... 59
xv Figure 4-2: Crosstalk or sneak current is shown schematically. When attempting to read
the selected device, current does not only follow the desired path but instead may
leak into the selected device (blue) causing a false read. Additionally when
attempting to write the device current may leak from the device (orange), leading
to programming failure...... 60
Figure 4-3: Schematic diagram of the fabricated device. The Titanium layer acts to ensure
the adhesion of the Ruthenium bottom electrode. Zinc ensures an Ohmic contact
between the n-layer (ZnO) and the bottom electrode. The testing probe is contacted
to the Ru electrode which is exposed to ambient...... 61
Figure 4-4: a) Current vs. voltage curves are shown for several devices of the following
sizes: (50um)2, (100um)2 and (200um)2. The overlap amongst devices of the same
size shows repeatability across the sample. These IV characteristics also show
scaling with area. (The ordinate is a logarithmic scale and the current is shown in
absolute) b) The threshold voltage is extracted graphically from the linear region
of the IV (0.8V-2V), at the area sizes mentioned in 4.4.1.a. The inset shows fv(A).
...... 62
Figure 4-5: Fittings from which the ideality factors are extracted. a) Region I (0V-0.4V)
b) Region II (0.4V-0.8V) c) Region III (0.8V-1.15V) d) Region IV (1.15V-2V). 67
Figure 4-6: Ideality factor for Region I (0V-0.4V) b) Ideality factor for Region II (0.4V-
0.8V) c) Ideality factor for Region III (0.8V-1.15V) d) Ideality factor for Region
IV (1.15V-2V)...... 67
xvi Figure 4-7: a) The IV characteristics are shown for a (50 um)2 device for temperatures
varying between 77K and 354.56K. b) ln I vs. V for 0.7V- 2V, fitting(s) to equation
4.4...... 69
Figure 4-8: a) The trace of the on current and off current at +1V and -1V. b) The ON/OFF
ratio as a function of temperature...... 70
Figure 4-9: Switching circuit is shown as well as a) output data from oscilloscope. b) A
single cycle is shown for clarity ...... 72
Figure 4-10: This is done by repeatedly applying alternative “ON/OFF” pulses of ±2V
followed by test pulses taken at ±1V. Resistance vs. iteration is plotted for several
devices over a) 106 and b) 109 iterations...... 73
Figure 4-11: The thickness of the Cu2O layer is varied from 0nm to 15nm. All other
fabrication parameters remain the same. The IV characteristics are s is shown for
(200um)2 devices...... 74
Figure 4-12: The on and off current at +/- 1V is shown for all 0nm, 7nm and 15nm Cu2O
layers. The threshold voltage is extracted for each thickness of Cu2O...... 75
Figure 4-13: a) The on and off current at +/- 1V is shown for all 0nm, 7nm and 15nm
Cu2O layers. b) The threshold voltage is extracted for each thickness of Cu2O .. 76
Figure B-1: Pictures of samples. TEC15 glass sheets coated in FTO and then ZnO. PNA-
6, PNA,-7, PNA-2, PNA-5 are shown...... 98
Figure B-2: Pictures of samples. TEC15 glass sheets coated in FTO and then ZnO. PNA-
1, PNA,-3, PNA-4 are shown...... 98
Figure B-3: a) Keithley 4200 Semiconductor Characterization System and b) a Lake Shore
Cyogenic Probe Station...... 99
xvii Figure B-4: Schematic diagram showing the arrangement of the metal contacts used for
electrical characterization...... 100
Figure B-5: TLM or transfer length measurement allows you to measure various length
(contact separation) resistors with different square contacts. The resistance values
are plotted against the resistor length, and a line is fit and extrapolated to a resistor
of zero length. The result will be twice the contact resistance...... 100
Figure B-6: Vertical current transport characteristics can be captured by depositing metal
contacts on the ZnO and then measuring the IV characteristics between this point
and the FTO bottom electrode...... 101
Figure B-7: J vs. E plots for 3 contact sizes of 300nm thick ZnO, plots of this type are used
to generate the variability maps below...... 101
Figure B-8: TLM results for three thicknesses of ZnO, 300nm, 70nm and 20nm. As
described in figure B-5. The contact resistance can be extracted from the value of
the y-intercept...... 102
Figure B-9: Average IV curves for 200um x 200um, 100um x 100um and 50um x 50 um
devices. Spacing (contact separation) is 200um and 100um...... 103
Figure B-10: Conductivity varies as a function of device area, this implies that the contact
resistance is affecting the measurement somewhat, this will not alter the description
of variability but should be mentioned...... 104
Figure B-11: 3D variability map of 300nm sample - 50 um devices-set2 ...... 105
Figure B-12: 2D variability map of 300nm sample - 50 um devices-set2 ...... 105
Figure B-13: 3D variability map of 300nm sample - 100 um devices-set2 ...... 106
Figure B-14: 2D variability map of 300nm sample - 100 um devices-set ...... 106
xviii Figure B-15: 3D variability map of 300nm sample - 200 um devices-set2 ...... 107
Figure B-16: 2D variability map of 300nm sample - 200 um devices-set2 ...... 107
Figure B-17: 3D variability map of 200nm sample - 50 um devices-set2 ...... 108
Figure B-18: 2D variability map of 200nm sample - 50 um devices-set2 ...... 108
Figure B-19: 3D variability map of 200nm sample - 100 um devices-set2 ...... 109
Figure B-20: 2D variability map of 200nm sample - 100 um devices-set2 ...... 109
Figure B-21: 3D variability map of 200nm sample - 200 um devices-set2 ...... 110
Figure B-22: 2D variability map of 200nm sample - 200 um devices-set2 ...... 110
Figure B-23: 3D variability map of 70nm sample - 50 um devices-set2 ...... 111
Figure B-24: 2D variability map of 70nm sample - 50 um devices-set2 ...... 111
Figure B-25: 3D variability map of 70nm sample - 100 um devices-set2 ...... 112
Figure B-26: 2D variability map of 70nm sample - 100 um devices-set2 ...... 112
Figure B-27: 3D variability map of 70nm sample - 200 um devices-set2 ...... 113
Figure B-28: 3D variability map of 70nm sample -200 um devices-set2 ...... 113
Figure B-29: 3D variability map of 20nm sample - 50 um x 50um devices-set2 ...... 114
Figure B-30: 2D variability map of 20nm sample - 50 um x 50um devices-set2 ...... 114
Figure B-31: 3D variability map of 20nm sample - 100 um x 100um devices-set ...... 115
Figure B-32: 2D variability map of 20nm sample - 100 um x 100um devices-set2 ...... 115
Figure B-33: 3D variability map of 20nm sample - 200 um x 200um devices-set2 ...... 116
Figure B-34: 2D variability map of 20nm sample - 200 um x 200um devices-set2 ...... 116
xix Chapter 1
1. Introduction
The growth of the electronics industry has thus far been primarily dependent on the
ever decreasing size of traditional circuit components, especially the Complementary
Metal Oxide Semiconductor (CMOS) transistor. Scientists and engineers have been using
Moore’s law to set the bar (and meeting this challenge) for CMOS transistor scaling since
this prediction (turned pseudo-law) was first made by Gordon Moore in 1965 [1],[2].
Moore’s law in its modern form states that the number of transistors per Integrated Circuit
(IC) will double every 18 months [2]. The initial prediction stated that the number of
components per IC, not just the transistor, would double. However, as digital circuitry
became predominant, transistor count became a more useful metric and the law was
refined. During the late 1970s there was a bifurcation of Moore’s law, where logic chips
(such as microprocessors) and memory chips began to follow different trend lines. Due to
the increase of transistor/chip density outpacing design capabilities, microprocessors
ceased to scale exactly with Moore’s law. This is not to say microprocessors are not
advancing; companies such as Intel are still increasing transistor density aggressively,
promising in 2002 to produce billion-transistor processors by the end of the decade [3].
The one billion mark was reached in 2005 [4], the two billion by 2008 [5] and as of 2012
the 10-core Westmere-EX Xeon had the highest commercially available transistor count of
1 over 2.5 billion [6]. Despite this incredible progress, transistor scaling in the logic trend line can no longer be described exactly by Moore’s law. Nevertheless the overall adherence was persevered due to the scaling of memory chips. Even amongst these, no single memory technology has been able to keep the expected pace; thus far this has not been a problem in terms of absolute adherence as when one chip type reaches limitations another picks up.
For example the dynamic random access memory (DRAM) was expected to produce 64
Gb chips by 2010. While such a high density was not reached, 64 Gb Flash memory chips were produced. However, this trend of shifting technologies to keep pace with Moore’s law is coming to an end, as it is well known in both academia and industry that the physical limits to Moore’s law are approaching [2],[7],[8].
In order to maintain growth momentum there is a driving interest in shifting the paradigm of innovation to produce novel versions of the most fundamental electronic components rather than relying solely on the scalability of the transistor and its adjuncts.
These novel electronics are expected to push past the scalability limits of CMOS devices as well as introduce a revolutionary wave of research into areas such as transparent electronics (TE) and Flexible electronics (Flextronics). In this interest, nano-scale devices using actual molecules, carbon nanotubes and nanowires are being fabricated and characterized [9]. Along with these novel device elements, compatible fabrication architectures are also being investigated [10].
TE is a growing field that is now witnessing practical realization of ideas that once existed only in science fiction. One of the best examples is the mainstay use of conductive displays in hand-held electronics as well as more traditional computer monitors. TE are also being studied and implemented for next generation displays, solar cells, charge-
2 coupled devices (CCDs), ultraviolet (UV) detectors etc. However the mostly solitary applications mentioned above are only the most benign of prospects for this field; fully realized transparent computation remains the hope of many researchers. This will first require the development of various individual elements, such as thin-film transistors [11], and memory devices [12],[13],[14]. Unfortunately material composition is a limiting factor in achieving both transparency, flexibility and computational viability. Glass and plastics are the most suitable substrates to begin tackling this transparency issue. Glass is finding increasing use as a building construction material, especially when TE such as solar cells can be incorporated, and of course glass is the go-to material for the conductive display industry. Plastics are finding increasing functionality as well, providing the benefit of introducing the possibility of flextronics. However plastics also generally require lower fabrication temperatures, which again brings up the issue of limited material composition possibilities.
Computational viability is being tackled in many ways, one of which is through the development of memcomputation. Memcomputing refers to a wide array of massively parallel computation schemes utilizing memory-elements or memelements [15]. This device class of memelements includes memristive, memcapacitive and meminductive systems. The physical architecture for optimal memelement implementation is the high density cross-bar array (CBA) [15],[16].
CBA architecture offers a unique approach to nano-electronic computation, with simplistic fabrication and independent device configurability. Due to an inherent redundancy, which offers fault tolerance [15], this architecture is especially useful for many novel defect based devices. Crossbar refers to an interconnection topology as well as
3 a fabrication geometry [17]. A CBA is composed of two or more parallel levels of wire arrays, separated by chemical interlayers. These chemical interlayers comprise the device, which defines the type and use of the CBA. Nearly any two-terminal device can be placed in this structure, given the fabrication system exists to support its construction.
CBA architecture is being used to implement many novel memory devices such as resistive random access memory (RRAM) and phase change memory [18]. This is a class of non-volatile storage elements. RRAM memory elements are two-terminal digital memristive devices capable of behaving as a memory through bias-controlled resistance modulation. One major issue when using CBA architecture for memory storage is isolating each device for a proper read without read error induced by crosstalk (sneak current between devices leading to false reads) [19]. The solution is to use an asymmetric access device, such as diodes for RRAM applications. These include p-n junction diodes, Schottky diodes and punch through diodes among others. Transistors can also be used; however these active three-terminal devices introduce additional complexity not suitable to the simplistic potential of RRAM CBA architecture.
Diodes in their purest form, are switches that allow for the flow of current in one direction through an electric circuit and block current in the opposite direction. The term diode is used to refer to any semiconductor junction that has this unidirectional conduction capability. These junctions are used in an integrated capacity, for both supportive and primary functions. Diodes are critical in a wide array of applications, including light emitting devices, photodetectors, logic gates [17], radios, solar cells, hazardous gas detectors [20], and they are integral components in transistors. They also find use as nanoelectronic pulse generators [21], high-frequency oscillators [22] and analog to digital
4 converters [23]. In addition to being used to suppress crosstalk in RRAM CBAs, diodes can themselves display unique memory capabilities. Diodes showing analog memory capability are referred to as memdiodes [24]. Memdiodes are the most recent addition to the family of memristive devices. Memdiodes show a change in conductivity under positive and negative stress voltages, while preserving some asymmetry in their current-voltage curves.
It is evident that if we are to fully realize viable nanoscale computation, further study of compatible diodes is required. Diodes are necessary as individual elements and in integrated systems; be it as integral junctions of transistors, access devices for separate memory elements, as memory elements themselves, for logic arrays and numerous other purposes. Furthermore it will also be necessary for the fields of TE and Flextronics to have compatible transparent and flexible diodes. We must therefore use materials that can be deposited at low temperatures so that they can be safely fabricated on plastics. These materials must also be transparent or semi-transparent. It is also generally beneficial to find earth friendly economical materials that fit the previous qualifications for diode fabrication.
These requirements make earth-abundant, non-toxic, low cost materials such as ZnO and
Cu2O of interest. ZnO is a wide band gap (3.37eV) [25] transparent semiconducting material that is intrinsically n-type without any deliberate doping. Cu2O is similarly intrinsic p-type possessing a high absorption coefficient and a bandgap of 2.17 eV [26].
These materials individually are widely used in a range of fields and the ZnO/Cu2O heterojunction has been heavily studied for solar cell applications. However diodes based on this stack have not been characterized for implementation in CBA. In this thesis, a
ZnO/Cu2O heterojunction is presented as the heart of several different heterostructures, the
5 first of which is as part of a FTO/ZnO/Cu2O/Cu memdiode. The fluorine doped tin oxide
(FTO), not only contributes to device properties but offers advantages over the more used indium doped tin oxide. FTO is more earth friendly, less expensive and easier to apply as a sufficiently thin film, amongst other benefits [27],[28]. We present the general characteristics of the memdiode as well as some insight into the effects of interface and non- stoichiometric defects which generate the quasi-memristive characteristics. The
Cu2O/ZnO diode is also presented in a Ru/Zn/ZnO/Cu2O/Cu heterostructure. This structure is characterized generically as a diode and to be used as an access device in RRAM CBAs.
6 Chapter 2
2. Background and Literature Review
2.1 Novel memory schemes and devices
Analog, digital and quantum- comprise three major paradigms of modern
computation [29]. Digital computation currently dominates both in terms of technological
advancement and commercial utilization. In fact it would be difficult to find a computer
that did not speak “computer language”, a binary series of highs (1’s) and lows (0’s). This
type of computation has proven to be enormously useful, and extremely efficient. From the
leaps and bounds of modern medicine (e.g. decoding the human genome…) to the
increased global connectivity through the internet (e.g. social networks used on nearly
every corner of the planet…). These and so many other advancements are only possible
because of computers that are based on digital computation. This type of computation will
not –and should not- be going anywhere anytime soon, but will only see further
advancement. However some problems can be too cumbersome or difficult for digital
computation, examples include: adaptive behavior, learning by association, pattern
recognition and fuzzy logic etc. [29],[30],[31]. These types of problems are more suited to
analog based schemes such as neuromorphic computation.
Quantum computation, arguably one of the oldest forms to still be considered novel
is not only a burgeoning field but a source of inspiration, reminding scientists and engineers 7 of the possible advancements that lie ahead. Feynman said it best in a speech given in 1960 discussing the future of computation:
What I want to talk about is the problem of manipulating and controlling things on a small scale….As soon as I mention this, people tell me about miniaturization, and how far it has progressed today. But that's nothing; that's the most primitive, halting step in the direction I intend to discuss. It is a staggeringly small world that is below. In the year 2000, when they look back at this age, they will wonder why it was not until the year 1960 that anybody began seriously to move in this direction.” [32]
Richard Feynman
While we have not reached the potential that Feynman suggests we will, we have made massive strides in that primitive stage of technological miniaturization. We have moved at a remarkable pace, inventing new technologies, exhausting the miniaturization capacity of those technologies and then moving on to the next. We are now at an intermediary where traditional scaling of cornerstone devices such as the transistor is coming to an end and we must again move to some new technology.
Any technology that falls into the scope of nanotechnology holds a certain sensational appeal in addition to scientific curiosity. This field is broad, and very loosely defined. The prefix nano, simply refers to anything that is 1 billionth of the size of some point of reference. Therefore it would be easy to reach into history and see that nanoparticles have been manipulated since the ancient Greeks found use for soot. In modern times this loose definition would be even more accurate as there is an awareness and deliberateness to the use of nanoparticles in everything from paints and sunscreens to cosmetics. However true nanotechnology as a research field is somewhat more focused and encompasses the broad array of nanoelectronic devices used for computation.
8 The future of modern computation will lie in the evolution of all three computational paradigms using materials, devices and methodologies that operate on a nanometer and sub nanometer scale. This requires not only truly sparking the potential of nanotech with molecular engineering but also computation topographies and schemes that fall outside of the conventional paradigms. There is a race amongst the multitude of new technologies that are being actively researched, to come to practical commercial utilization.
However, no technology may start at the finish line; new materials, devices and configurations must be studied first in a way that is more predictable and controllable. Thus many of the devices discussed in this work contain some dimensions that are at the microscale. However these devices are members of a technological class that is expected to not only maintain its character, but thrive at the nanoscale.
2.1.1 Memcomputation
Memcomputation is a parallel computation scheme in which information is stored and processed in the same physical space; i.e the units for information storage and computation are the same [33]. This is conceptually different, from traditional computation, where information is stored in volatile-random access memory or non- volatile hard memory (flash, magnetic hard drives etch.) and processed in the CPU (central processing unit). Memcomputation is accomplished using memelements, passive
(producing no gain or signal amplification) analog circuit elements that control the system by keeping track of (i.e. remembering) the systems past dynamics. The device class of memelements includes memristive, memcapacitive and meminductive systems that are capable of analog state change, though they may also show digital characteristics. Such
9 mem-systems occur naturally at the nano-scale [29]. The mathematical definition of the memelement is that it is an nth order u-controlled element governed by the following equations [29],[34].
푦(푡) = 푔(푥, 푢, 푡)푢(푡) 푥̇ = 푓(푥, 푢, 푡)
Where f is the n-dimensional function of internal state variables that controls the device properties. These internal state variables will depend on the specific system, x is the set of n state variables, g is the generalized response, u(t) and y(t) are the input and output respectively. This work will focus on Memristive systems, where u(t) and y(t) are generally given as such:
푢(푡) = 푣표푙푡푎푔푒 푦(푡) = 푐푢푟푟푒푛푡
Memristive devices are utilized in both a digital and analog capacity. Memristive devices will be discussed in further detail in proceeding sections.
10 2.1.2 Memristive devices
Figure 2-1: Schematic diagram of a memristive cell. The switching layer (S.L.) is sandwiched between two metal electrodes. A possible voltage input pulse is shown, this is a common way in which switching is initiated.
Memristive (a derivative of “memory resistive”) devices are two terminal devices capable of information storage (i.e. memory) through resistance modulation. The mathematical definition is given in section 2.1.1. Resistance modulation is controlled using an applied current or voltage at either terminal. This is generally a small voltage pulse.
(figure 2-1). There exist both analog and digital memristive devices. Analog memristive devices have a potentially infinite number of storage values, since their resistance is modulated incrementally. Truly digital memristive devices, as the name implies have two states: on and off. RRAM or resistive RAM (random access memory) is the name given to digital memristive devices by HP laboratories in 2008 [35]. These devices are based on phenomena that have been shown for decades [36]. However, it wasn’t until 2008 that the simile to the memristor was shown, while the memristor itself was predicted theoretically by Leon Chua in 1971 [37]. It should be noted that there is an intermediate between digital and analog memristive devices in the form of Multi-Level cell (MLC) RRAM devices. 11 However, this work will focus on RRAM devices that are operating in a strictly digital capacity. The process of state change in RRAM is referred to as “switching”, this term may be used loosely for analog devices as well -in as so much- as they share some of the same resistance change mechanisms.
2.1.2.1 RRAM switching types and mechanisms
There are memristive devices based on both chemical and physical switching.
Chemical switching occurs when there is some redox reaction involved [44]. Most resistive switching will involve some chemical process. The chemical switching processes can be separated into Cation and Anion based devices [38]. Both types of devices are based on the metal/switching layer/metal structure. The switching layer is usually insulating and so is often generalized to an MIM (metal/insulator/metal) structure. The switching layer is not necessarily one single layer composed of one single material.
For anion based devices the switching material is generally oxide based and can be one or more layers of the following: insulating oxides, complex oxides, transition metal oxides, large bandgap dielectrics and some non-oxide insulators (e.g nitrides and chalcogenides)[39]. Cation based devices generally contain one electrochemically unstable metal electrode such as copper or an insulator doped with an electrochemically unstable metal [40]. Oxide based memristive devices without this signature are usually treated as anion based even if the mobile species is the cation interstitial [38]. The counter electrode in cation based devices is usually an inert metal. While the traditional cation switching materials is an electrolyte; sulphides, iodides, selenides, tellurides, ternary chalcogenides and water have all been used as well.
12 The switching mechanisms in cation and anion based materials are very similar, however, the overall mechanisms behind switching are better understood for anion based devices. Determining the exact mechanism of resistance switching can be difficult, the entire structure must be taken into account rather than simply the switching material(s).
Also switching may take place at either main interfaces (electrodes) or minor interfaces
(given a multi-layer stack). The fact that very different switching behavior is found in so many materials has made it impossible thus far to develop a single cohesive theory behind memristive behavior.
RRAM memristive systems are generally more ordered and predictable than their analog counterparts. For many systems the switching mechanism is assumed to be filamentary based [35],[41], wherein a filament is grown in the S.L. during electroforming
(the first time the device is switched, involving a higher than normal bias to form a electrochemical path in the material). The switching region is usually localized in a small micrometer size area that is 10’s or 100’s of nanometers in diameter (filamentary based)
[39]. Switching originating at an interface is also localized to a small area [42],[43].
Switching in RRAM can be separated into two types based on the polarity of the applied voltage used [35],[45].
1) Bipolar (Opposite polarities to turn-on (SET) and turn-off (RESET) a) Bipolar Non-linear b) Bipolar Linear 2) Nonpolar (or unipolar) a) Bistable b) Threshold switching
13 Devices may be also classified based on symmetry. Symmetric devices are those in which the electrode material is the same (i.e. the interfaces are identical), asymmetric devices are those in which the interfaces have different properties. Two opposite switching polarities could exist in the same device, because both interfaces may be switching under certain conditions. The symmetry of the device is an important parameter as it will determine the type and polarity of the RRAM device, which will in turn limit the possible forms of implementation. RRAM devices start with an initial or virgin state, this is termed the VRS (virgin resistance state). They can then be SET into the on state, representing a digital 1. This is a highly conductive state termed the LRS (Low resistive state), they are then RESET into the off state (a digital 0) this is termed the HRS.
Figure 2-2: Unipolar IV characteristics, resistive switching is induced by a voltage of the same polarity but a different magnitude. There will be a compliance current (CC), a circuit induced current limitation during the SET process. The schematic shows a perfectly symmetric behavior, however practically, the SET voltage (Vth1) will be higher than the voltage at which RESET takes place (Vth2), though the RESET current Referenceswill be higher the CC.
14
Figure 2-3: Bipolar IV characteristics, one polarity is used to SET to LRS, and the opposite polarity is used to RESET back into HRS. A current compliance (CC) is usually required during the SET process to ensure the current density through the device does not cause excess oxide degradation resulting in a permanent breakdown [45].
2.1.2.2 Analog memristive device types and mechanisms
As mentioned in the previous section for RRAM devices, the mechanism behind memristive change is not thoroughly understood [46]. Therefore an inclusive theory does not exist to explain their behavior in a unified manner. The mechanisms are even less understood for analog memristive systems; through which the resistance change is more gradual. However the mechanisms are assumed to be similarly based as those for RRAM switching. The usually accepted mechanisms include the migration of conductive oxygen vacancies [44], the memristive filament model [46],[47], and electron trapping/detrapping due to defect states [48] as well as interface modification after an applied bias
[49],[50],[51]. The incremental resistance change exhibited by analog memristive systems
15 can be used for numerous purposes. For example they meet the analog switch requirements for neuromorphic computation [39].
Carver Mead coined the term neuromophic to describe analog circuits that mimic neurobiological architectures present in the nervous system [52],[53]. Neuromorphic computation has been implemented to various degrees of success since then. Before memristive devices were studied for this purpose, neuromophic computation was only accomplished using very large scale integration (VLSI) systems via silicon synapses and neuron circuits [54]. A silicon synapse must be able to convert a digital output of the neuron into an injection current, so that as an input pulse arrives it is integrated such that the output current encodes the frequencies of the input spike train. Therefore the silicon synapse is composed of an integrator circuit. These silicon synapses are used in conjunction with silicon neurons, these neurons are actually circuits that emulate the electrical properties of biological neurons. There are two main classes of silicon neurons, integrate-and-fire neurons [55],[56] and conductance based neurons [52],[57],[58].
One of the most important functions of a biological synapse is spike-timing- dependent plasticity (STDP) [59],[60]. The existing electrical models for implementing
STDP are based on the aforementioned VLSI circuits, which utilize three terminal transistors [52]. Memristive devices are extraordinarily useful in these circuits since they intrinsically mimic the behavior of biological synapses (unlike the silicon integrator circuit). There are memristive based design schemes which in conjunction with a limited amount of CMOS elements allow for STDP that is a much closer analogue to the biological form. These memristive based systems will also allow for a closer mimicry of the density and output of the human brain, as many of these systems are nano and sub nanoscale.
16 Memristive implementation of neuromorphic computation will further allow for the omission of the silicon transistor and the associated scaling limitations. A simple neural network is shown in figure 2-3.
Figure 2-4: A simple neural network containing three electronic neurons (N1, N2 and N3) connected by two memristive synapses (S1 and S2). The output is assumed to follow the threshold model, summing the inputs and “firing” when the programmed threshold is reached. Basic neural operations have been mimicked electronically using this basic concept. For example, timing based learning law such as STDP have been mimicked using this model.
2.1.3 Logic Implementations
Despite their title, memristive devices will not be used simply to replace conventional memory technologies. As mentioned previously one of the premier benefits of memcomputation is the ability to store and process information in parallel. Therefore in addition to complex schemes such as -the synaptic neuromorphic computation- mentioned
17 in the previous section, logic operations utilizing digital memristive devices are being studied.
In 1936 Claude Shannon showed that basic Boolean logic operations p OR q and p
AND q could be implemented with simple electronic circuits that contained two switches in series (OR) and parallel (AND) and the NOT operation could be implemented with a relay [61],[62]. This small set of electrical components can compute any compound
Boolean logic operation. For the two available binary digital values 0 and 1 there are 16
Boolean functions, these functions involve the aforementioned three operations of Boolean algebra: AND, OR, and COMPLEMENT.
퐀퐍퐃: 퐀 퐁 퐎퐑: 퐀 + 퐁 퐂퐎퐌퐏퐋퐄퐌퐄퐍퐓: 퐀̅ = 퐍퐎퐓 퐀
Digital logic is based on Boolean algebra. It has shown that 14/16 of the Boolean functions can be completed using a single BRS (bipolar resistive switch...e.g.RRAM) or CRS
(complementary resistive switch) cell in at most three sequential cycles [63]. A CRS is formed by placing two anti-serial memristive elements in a crossbar array [64]. Perhaps the best example of memristive logic implementation is the use of a memristive device to execute material implication (IMP). While material implication is not a frequently used
Boolean logic operation among electrical engineers or computer scientists, it is well known to logicians. IMP can be very useful when applied using memristive systems, in fact IMP and FALSE (logic value 0) form a computationally complete logic basis [62].
The physical representation or state variable for the logic value of an IMP operation would be the resistance state of the switch, this means IMP logic is stateful. Stateful refers to the fact that the memristive device can perform logic operations and store logic operations. The same devices can be defined to be either logic gates or memory latches
18 [62]. This parallel capability is a major highlight of Memcomputation and will lead to a large reduction in power consumption, since data no longer has to be transferred to memory. Yet, while this seems a tempting alternative to conventional von Neuman architecture, it is not yet used due in part to the problem of cell isolation (due to sneak current). This is the same problem facing RRAM usage in general. This issue of sneak current will be discussed further in proceeding paragraphs.
2.2 Architecture for the implementation of memristive devices
Given the complexity and usage of traditional CMOS based computation infrastructure, it is unlikely that memristive devices, for either memory or logic will -nor should- simply replace CMOS technology. There also exists the limitation that memristive technologies require external support for signal translation and amplification [65].
Therefore the best way to take advantage of the memristive systems will be through a hybrid CMOS/memristive hybrid circuitry [65]. This type of circuitry possesses many benefits, for example many of the Boolean logic operations mentioned above are best accomplished using a hybrid circuitry rather than solely memristive. Another example of hybrid circuitry would be the elimination of the storage inefficiency of FPGA’s (Field programmable gate arrays). This inefficiency is due to the fact that the circuit configuration information must be stored in the local memory. This is usually done using SRAM or Flash, which takes 50-90% of the chip [29].Using nanoscale memdevices could reduce this by
10-100 times [66]. The physical architecture for memristive device implementation, either for memory storage, logic implementation, and hybrid circuitry is the CBA (crossbar array)
[63],[19],[67]. 19 2.2.1 Crossbar Array (CBA) Architecture Wordline
Bitline
Figure 2-5: Schematic depiction of crossbar, highlighting a single device, the top and bottom electrodes are referred to as wordlines and bitlines respectively.
Crossbar refers to an interconnection topology as well as a fabrication geometry
[17]. A crossbar array is composed of two or more parallel levels of wire arrays, separated by chemical interlayers (figure 2-5). Crossbar array (CBA) architecture has many applications. Multiple types of crossbars assembled into larger composite structures may be used to implement general computation using standard circuit elements such as diodes and resistors. An array of a single type of device is a tile, groups of tiles become logic building blocks, and composite blocks may be used to create different families of logic.
The diode resistor logic block is the simplest to fabricate (figure 4-1). There is an even more powerful logic using p-FETs and n-FETs known as a complementary/symmetry array, this is capable of implementing AND/OR/INVERT and is usable for general computation [68]. However, the devices used in a CBA that show the most potential are memristive devices.
20 CBA architecture is not only that which is most suited to memristive implementation but it is an integral part of memristive system appeal. These structures are also relatively easy to fabricate and integrate with conventional CMOS processes.
Memristive devices are inherently passive, therefore CBA implementation requires a connection to some CMOS circuitry to provide signal restoration and gain [65],[69]. In fact the memristive device CBA in conjunction with CMOS components -forming a hybrid system- is a realistic candidate for the future of memory and logic applications. There are several methods of integration to form this hybrid circuitry, the most promising of which involves a CMOS layer and is referred to as CMOL (CMOS + MOLecular-scale devices)
[70],[71]. Additionally, these memristive devices utilized through CBA architecture possess the key benefit of a small footprint, of 4F2 where F is the lithographic feature size or half pitch [69].
CMOL circuitry allows for three dimensional stacking [71]. However this requires a non-linear memristive device, i.e. with an integrated access device (for sneak current elimination). Analog as well as digital memristive system applications would benefit from this type of circuitry. In fact many analog memristive systems (which are more likely to contain inherent non-linearity) would be perfectly suited. Traditional memristive/CMOS hybrid implementation involves the use of a CMOS transistor as an access device in conjunction with a 2D memristive CBA. The CBA can be fabricated using nanoimprint lithography, making them the ideal architecture for nano-devices. However, the wafer based transistor will be a limiting factor [69],[70]; inherently non-linear devices can circumvent this issue. It should also be noted that there are applications that do not require nanoscale devices, in these cases CBA memristive arrays may be fabricated at the micro
21 scale avoiding some of the issues often seen at the nanoscale such as sensitivity to noise, subatomic particles, and even quantum uncertainty [17],[72].
Transient faults will also increase at the nanoscale and defects will be numerous.
Crossbars architecture however, offers a high degree of redundancy, this functions as a method of defect tolerance [17],[73]. Memristive CBA circuitry is also configurable.
Configurability of the circuit refers to the fact that individual devices may be repeatedly activated or deactivated so that an inactive device is functionally non-existent. This means a single defective device would not ruin an entire tile. As mentioned above, devices with inherent non-linearity would be extremely useful, however many of the RRAM devices possessing other desirable qualities require a separate access device. The role of this device is discussed in the next section.
2.2.1.1 Role of Access device
Several different types of memory device can be placed in a CBA, such as PCM
(phase change memory) and RRAM. The read/write operations will be somewhat unique for each memory technology. In general the read operation involves detecting changes in a physical quantity such as charge, which is used to quantify the state of that particular memory device. Accessing a particular cell in the CBA requires the selection of one wordline and one bitline (figure 2-5, figure 4-2) to establish connections between this cell and the peripheral input/output circuitry. The issue is that this is an operating circuit system and there will be crosstalk (i.e. sneak current) between devices [64],[74]. Sneak current occurs due to the existence of lower resistance paths (relative to the selected device) [64].
22
Figure 2-6: A schematic description of a crossbar array shown, the highlighted device (yellow) is meant to be electrically isolated from the other devices. The diodes shown in series with each RRAM device are meant to inhibit current flow to unselected devices, this is 1D1R architecture.
The way to subvert these major issues is by using an access device. This will inhibit unauthorized communication between devices. The major problems resulting from this crosstalk are false read, misprogramming as well as device degradation. The false read error would obviously inhibit normal operation which relies on the accuracy of this information. The device degradation would be a great problem for devices that may already inherently defect rich. There also exists the issue of programming failure, wherein the voltage drop across the selected device is not high enough to change its state (i.e. write/erase).
The access device will have certain requirements that will depend on the type of memory used. Many access devices have been suggested for RRAM implementation, finding the proper access device first requires determining the type of RRAM being used. 23 As discussed earlier, there are several broad types, the main concern here being whether they are bipolar or unipolar. Due to their switching capability, diodes are used as access devices, these include p-n junction diodes [75],[76], threshold switching devices [77],
Zener diodes [78], Punch-through [79],[80] and Schottky diodes [74]. Transistors are also used [81], however these active three-terminal devices introduce additional complexity not suitable to the simplistic potential of RRAM CBA architecture. Since unipolar RRAM may have its state both SET and RESET using an electrical signal (voltage/current pulse) of the same polarity, a quality pn junction diode is a suitable access device (figure 2-6). In the case of unipolar RRAM the access device need only turn on in one direction and block in the other. However, bipolar RRAM has a slightly more complicated set of requirements, this is due to the existence of two opposite polarity thresholds. The access device must in turn have corresponding opposite polarity thresholds. This makes the Zener diode a popular choice. However there are issues with degradation. The Endurance of the diode would have to be equal or greater than that of the RRAM device. Typical RRAM endurance values are of the order of 106 cycles (on/off repetitions) though there have been reports as high as 1011 cycles [82].The diode would also have to have scaling potential similar to that of the
RRAM device is it being used to access.
The other major deciding factor is material and fabrication compatibility. Most
RRAM devices are made using metal oxides. Therefore it is necessary to fabricate and characterize compatible oxide based access devices. In succeeding sections, we will discuss the Cu2O/ZnO based diode for CBA implementation.
24 2.3 Material considerations
Resistive switching was first reported in 1962 by Hickmott, for Al/Al2O3/Al MIM structures [83]. He reported hysteretic current–voltage (I–V) characteristics in these
Al/Al2O3/Al structures, indicating that resistive switching occurs as a result of applied electric field [84]. Resistive switching phenomena has since been shown in many binary metal oxides [84],[85]. Memristive behaviour in particular has been reported in a wide variety of MIM structures composed of binary metal oxides, such as SiOx [86], NiOx
[87],[88], ZnO [89],[90],[49],[75],Cu2O [91], VO2 [92] and TaO [93]. The most famous material however, is TiO2, this is because it is the material used by HP laboratories in 2008 when they were the first to demonstrate the simile to Chua’s memristor [35],[37]. Since then, many more materials, configurations etc. have been considered. While these binary oxides are at the forefront, memristive behaviour has been shown in numerous other materials, including organic materials, nanotubes, nanorods and individual molecules.
Heterojunctions, doped materials, etc. are also used to show resistance storage for both digital and analog memristive devices [49],[86],[24]. As mentioned above access devices of compatible materials will be necessary. In this interest a Cu2O/ZnO diode is characterized. A heterostructure composed of Cu2O and ZnO is also shown to have memdiode characteristics. Therefore the next section will give a brief overview of these two materials.
25 2.3.1 Zinc Oxide
Zinc Oxide (ZnO) typically forms an n-type semiconductor without any deliberate doping [24],[94], n-type conductivity is caused by unintentional introduction of impurities during fabrication. First principle calculations [95] show that interstitial hydrogen can act as a donor level leading to n-type conductivity. ZnO contains many defects with typically low formation enthalpies, the defect chemistry in ZnO is described using Kroger-Vink notation where i = interstitial site, Zn = zinc, O = oxygen, and V = vacancy. Some primary defect reactions are Zn interstitials and O vacancies. Zn interstitials come from the Frenkel reaction resulting in a Frenkel defect (vacancy + interstitial pair).
푥 푥 푍푛푍푛 ↔ 푍푛𝑖 + 푉푍푛 (3)
Oxygen vacancies are Schottky defects arising from the Schottky reaction caused by the removal of an atom from the compound in the chemical formula, in this case Zn and O.
푥 푥 푁푢푙푙 ↔ 푉푍푛 + 푉푂
There are numerous other possible defect reactions, however given the nature of the material fabricated, and the electrical characteristics of the fabricated devices it is logical to conclude that these are the most important to consider. The properties of any given ZnO thin film will of course depend on the details of fabrication.
2.3.2 Cuprous Oxide
Few semiconducting oxide materials have been as heavily investigated as cuprous oxide (Cu2O). Cu2O has been investigated since the early 1920’s and is a known intrinsically p-type semiconductor. The most widely researched use has been for inclusion
26 in solar cells due to its direct band-gap of ~2.1eV [96],[97],[98],[99]. Various deposition techniques are used to synthesize Cu2O, including chemical oxidation, electrodeposition
[97], thermal oxidation [96] and sputtering [100]. RF sputtering is done using either a Cu2O target or by using oxygen to reactively sputter a Cu metallic target with argon gas. The reactive sputtering process usually leads to a mixture of Cu2O and cupric oxide (CuO).
Depending on the deposition conditions a range of film phases and stoichiometry’s may be obtained from metal rich Cu2O to Oxygen rich CuO [96],[100]. Cu2O is a characteristically non-stoichiometric material that tends to have a higher resistivity. Materials of lower resistivity may be obtained through careful control of the parameters. RF sputtered semiconducting Cu2O thin films are used in this study. Given the low temperatures used during fabrication, it is possible that these films contain more than one phase, and some stoichiometric variation.
2.4 Overview of diode operation
Pn junctions are integral parts of many semiconductor devices, and their theory of operation forms the basis for many of the equations and theories of the associated devices.
These theories are so fundamental that an understanding of pn junction theory is required for a complete understanding of the physics of semiconductor devices.
The p-n junction diode is a two terminal device, formed by placing a p-type semiconductor in physical contact with an n-type semiconductor. pn junctions may be formed using homojunctions (the same material with opposite doping), as well as anisotype heterojunctions (two different materials, of opposite doping). The device geometry, doping profile, relative doping (different doping concentrations in each side e.g. p+n) and biasing
27 conditions are some of the basic parameters affecting ideal abrupt pn junction operation.
Defect states and material stoichiometry (which will depend on deposition conditions etc.) are additional realistic parameters that will affect operation.
Pn junction theory is most simply explained using the abrupt ideal junction. This is first approached under equilibrium conditions, where thermal equilibrium is assumed. The assumption is also made that there is no external stimulus such as incident light or applied bias, leading to zero net current, either from hole or electron movement. Ideally neither semiconductor is degenerate therefore Boltzmann statistics are applicable. When the two oppositely doped materials are placed into contact, the majority carrier from each side will diffuse to the other, this will continue until a sufficient electric field has been built to oppose this diffusion. This electric field will be due to the depletion of carriers in both sides, forming a region of stationary negative charge in the p region and similarly a region of stationary positive charge in the n region. This region is called the depletion layer or space charge layer. This is shown schematically in figure 2-7 and further discussed in the corresponding caption of that figure.
28
Figure 2-7: a) p-type material contains negatively charged acceptors (immobile) and positively charged holes (free). The total charge is 0. b) n-type material contains positively charged donors (immobile) and negatively charged electrons (free) The total charge is 0. c) The free elections (n-majority carrier) near the contact region will diffuse into the p-side. Similarly holes (p-majority carrier) will diffuse to the n-side. The electrons and holes that diffuse will leave stationary positive and negative charge behind respectively. This charge buildup results in an electric field, this field sweeps electrons in the p-side to the n-side and vice versa, this is the drift current. When equilibrium is reached the net current will be zero, therefore diffusion current must be equal to the drift current.
29 Given the condition of thermal equilibrium the average energy must be constant.
This means that the Fermi energy is constant across the energy gap of the diode junction.
The built in potential is the potential across the depletion region (layer) in thermal equilibrium. This built in potential is equal to the sum of the bulk potentials in each region,
(since the bulk potential quantifies the distance between the Fermi energy and the intrinsic energy). It can therefore be calculated as the potential difference between the Fermi energies in the n-type material and the p-type material. Therefore the built in potential is given by the following:
푁푑푁푎 휑푡 = 푉푡 2 (2.1) 푛𝑖
2 Where Vt is the thermal voltage, Nd, Na, and ni are the donor, acceptor concentrations and intrinsic concentrations respectively. The bending in the representative energy bands is shown in figure 2-8.
Figure 2-8: a) Energy band bending under thermal equilibrium conditions. In the bulk regions (away from the junction) the original material conditions dominate and the band diagram is unaffected. Near the junction the bands bend to keep the Fermi level constant. The diagram shows the direction of carrier drift/diffusion, as well as some carriers due to thermal generation/recombination.
30 When a forward bias is applied (positive voltage to p-type “anode” relative to n- type “cathode”) there is a decrease in the potential across the depletion layer, and a corresponding decrease in the width of the depletion layer (figure 2-9). When a negative bias is applied, the depletion region widens and the potential across the depletion layer increases. The total potential across the diode junction is given by the difference between the applied bias and the built in potential.
휑 = 휑푡 − 푉푎 (2.2)
These changes in the depletion width with applied bias lead the pn diode to conduct under forward bias and block reverse bias. This effects on the energy bands and thus the junction are shown in figures 2-9 and 2-10. These are theoretical calculations that require absolutely ideal conditions. The response of real pn junctions are discussed in chapters 3 and 4.
Figure 2-9: Under forward bias (Va), the potential drop across the pn junction is reduced, the drift current reduces slightly and the diffusion current increases. The net current is no longer zero. This is the forward conduction region of the diode.
31
Figure 2-10: Under reverse bias (Va), the potential drop across the pn junction increases, the diffusion current decreases. The net current is no longer zero, however it is very small. This current is called the reverse saturation current.
2.5 Memdiode (Memory-diode)
Memdiodes are the most recent addition to the family of memristive devices; two- terminal devices capable of memory through controlled resistance modulation. These are novel memelements, displaying a combination of rectification and hysteretic behavior in the IV. While many RRAM devices show non-linearity in the initial IV, few maintain this non-linearity after setting (section 2.1.2.1) or changing their resistance state. It is during this LRS that most RRAM devices are in need of a supplementary access device. The memdiode possesses the key benefit of providing analog storage as well as fulfilling the access device and the memory device requirements with one single device. This would be
32 enormously beneficial in a crossbar array. In addition to the memdiode shown in chapter
3, there is only one other memdiode published in literature, [24]. Though some other devices show similar behavior [49],[101]. The published characteristics of this memdiode are shown in figure 2-11. This memdiode and that in chapter 3 are made using pn junctions.
These junctions show diode behavior, hysteresis in the IV and nonzero crossing.
Reverse bias polarization gives rise to a nonzero open circuit voltage (OCV) that persists after the junction is disconnected from the external circuit. The bipolar OCV states enable writing (setting) and erasing (resetting) metastable memory bits, wherein the read function involves potential measurement rather than resistance measurement as in other memristive devices. However, this non-zero crossing while fascinating and offering a unique memory storage possibility is not a necessary requirement for inclusion as a memdiode. The memdiode is discussed in further detail in chapter 3.
33
Figure 2-11: "Reprinted with permission from S Saraf, Applied Physics Letters, 102(2), 022902-022902, (2013). Copyright 2013, AIP Publishing LLC.”
STO (SrTiO3) based memdiode characteristics. Semi-logarithmic plot (the inset in the upper left corner shows a linear plot) of I-V characteristics measured in sweep mode from -3V to +3V (blue circles) and subsequently from +3 back to -3 V (red squares), or in alternating polarity mode (black squares). The arrows indicate the sequence of the sweep mode measurement. Currents to the left (right) of the minimum current points are negative (positive), and the voltages at the minimum current points are the OCVs. The inset in the lower right corner shows a schematic illustration of the device structure (the layer thicknesses are not to scale).
34 Chapter 3
3. Reconfigurable Memdiode Characteristics in BLANK BLACu/Cu2O/ZnO/FTO Heterostructures
3.1 Abstract of Chapter
In this chapter, we present the characteristics of a memdiode fabricated using a
ZnO/Cu2O heterojunction on Fluorine doped Tin Oxide (FTO) coated glass substrates.
These devices show a change in conductivity under positive and negative stress voltages,
while preserving asymmetric current-voltage curves. The mechanism of reconfiguration
was identified as generation and annihilation of traps under applied bias. A comprehensive
device physics model is presented to explain the experimental results.
3.2 Fabrication and characterization setup
n-ZnO/p-Cu2O heterojunctions were fabricated on clean FTO coated glass substrates
(Received from Pilkington North America, Northwood, Ohio) using RF magnetron
sputtering. A Zn target (99.99%) was reactively sputtered with O2 (Ar plasma) to achieve
15 nm ZnO films. 15 nm of Cu2O was similarly deposited using a Cu target (99.99%). The
substrate temperatures for ZnO and Cu2O were 100 ˚C and 27 ˚C respectively. Cu was
deposited as the top electrode at room temperature (~20 °C). The Cu electrodes were
defined using contact lithography and etched using Cu wet etchant. Electrical
35 characterization was done using a Keithley 4200 Semiconductor Characterization System
(SCS) equipped with an ultra-fast 4225 Pulse Modulation Unit (PMU). Temperature variant measurements were taken using a Lake Shore cryogenic TTP4 probe station cooled with liquid nitrogen. In all of the following measurements the top electrode was biased while the bottom (FTO) was grounded. The device schematic is presented in figure 3-1.
The device sizes used for testing range from 30 um x30 um to 500 um x500 um. The size of devices used for each test are mentioned in the figure captions.
3.3 Diode Response
Figure 3-1: A picture of the substrate and devices presented in this chapter, while the ZnO is transparent, the Cu2O is semi-transparent, and responsible for the overall discoloration of the stack. The schematic of the device stack is also shown, a resistor is shown in series to represent any serial resistance contributions aside from the pn junction. The initial current voltage (IV) response of the device is highly asymmetric as shown in figure 3-2. This is primarily due to the pn-heterojunction formed by n-ZnO and p-Cu2O. ZnO typically forms an n-type semiconductor without any deliberate doping [94], n-type conductivity is caused by unintentional introduction of impurities during fabrication.
36
)
0.01 2 104 10-4 102 10-6 0 -8 10 10 30um 50um
Current (A) Current -2 10-10 100um 10 200um 500um -12 10-4 10 (A/m Density Current -1.5 -1 -0.5 0 0.5 1 1.5 -1.5 -1 -0.5 0 0.5 1 1.5 Voltage (V) Voltage (V)
Figure 3-2: a) Current vs. Voltage (IV) response for devices of the following sizes: (30um)2, (50um)2, (100um)2, (200um)2 and (500um)2. b) Current density vs. voltage for several devices of the following sizes are shown: (50um)2, (100um)2 and (200um)2. The overlap in the plot shows device repeatability and scalability.
The insidious nature of hydrogen contamination in thin-film fabrication indicates this is the likely dopant. Experimental [102] as well as first principle calculations [95] support this theory showing that interstitial hydrogen can act as a donor level leading to n- type conductivity. Cu2O is generally considered p-type even in the absence of deliberate doping, due to a low energy acceptor level caused by negatively charged Cu vacancies
[103]. Cu2O is a characteristically non-stoichiometric material, containing many charged as well as neutral point defects [104].
The diode IV curves in figure 3-2 are fit according to the ideal diode equation:
푞푉 퐼 = 퐼 [exp ( ) − 1] (3.1) 푠 푛푘푇
I is the current response of the junction, Is is the reverse saturation current, q is the unit electron charge, k is the Boltzman constant, T is the absolute temperature and n is the
37 ideality factor. The ideality factor n is extracted from the slope of an ln (I) vs. V plot. The ideality factor for the ideal diffusion controlled junction is n=1 while deviations up to n≤2 reflect the presence of defect induced recombination in the space-charge region. Larger deviations of n (n>>2) indicate the presence of surface or interface states, as well as the contributions due to series resistance and multiple contacts [105].
-6 Table 3-1 Ideality factors for IV regions in Figure 3.3 -8 III -10 Region n
-12 II I 1.89 -14 II 2.09 -16 I -18 III 2.59 -20 ln (Current) (ln (A)) (ln (Current) ln IV 3.17 -22 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Voltage (V)
Figure 3-3: Natural log of forward current for (50um)2 device vs. applied voltage. This lnI-V curve is separated into the four regions for which the ideality factors are extracted
The ideality n is not constant indicating the dominance of different mechanisms, the curve is broken down (figure 3-3) into 4 major regions. Initially the ideality is n=1.89
(region I) given the expected domination of generation/recombination effects at low bias.
We take the turn on voltage to be Vturn_on=0.55V the point at which the slope is first seen to change appreciably. Immediately following turn on the memdiode ideality is seen to be n=2.09 (region II) indicating the presence defect induced recombination, further increase shows deviation to 2.59 (region III) and 3.17 (region IV), However in this region we expect the series resistance to be quite high causing a large part of this deviation. This high
38 resistance can be explained in part by the presence of a low barrier Schottky contact at the
Cu2O/Cu interface. This barrier is expected due to the electron affinity (4.84eV) [106] and work function (4.35eV) [107] of Cu2O and Cu respectively. The ideality factor in regions
II-IV were extracted from the IV curves at temperatures ranging from 77K-354K (figure
3-4). The ideality factor in these regions varied with a ~ 1/T dependence. This relationship is expected, given the diode equation and suggests that the defects in this range have no appreciable temperature dependence (in this bias range).
77 K 99.31 K 128.09 K 165.20K 213.08 K 274.82 K 354.46 K 83.81 K 108.10 K 139.43 K 179.83 K 231.94 K 299 K 91.23 K 117.67 K 151.77 K 195.75 K 252.47 K 325.63K 0.01 35
10-4 30
10-6 25
10-8 20
10-10 15
Current (A) Current
Ideality Factor Ideality 10-12 10
10-14 5 -3 -2 -1 0 1 2 50 100 150 200 250 300 350 400 Voltage (V) Temperature (K)
Figure 3-4: a) Temperature variant IV curves. The presented device is swept from, 2V to +1.5V in the temperature ranges from 77K to 354K. b) The ideality factor as a function of temperature, this value is extracted from the regions II-IV.
Further characterization is done through Capacitance-Voltage measurements. These were performed on a 30um x 30um device. The forward capacitance shows a linear dependence on the corresponding forward current. This diffusion capacitance is expected from the forward biased pn junction, and is given by equation 3.2.
푞2 푞푉 퐶 = (퐿 푝 + 퐿 푛 ) [exp ( 0)] 퐹/푐푚2 (3.2) 푑0 2푘푇 푝 푛표 푛 푝표 푘푇 39 In Equation 3.2, q is the electronic charge, npo and pno are minority carriers in the n- and p-regions respectively. Le and Lh are the electron and hole diffusion lengths. V0 is the applied dc potential, k and T are the Boltzmann constant and temperature.
10-6 1.4 10-9 -9 10-7 1.2 10 -9 -8 1 10 10 8 10-10 10-9 v=10kHz -10 v=100kHz 6 10 10-10 v=1MHz 4 10-10 -11 -10
Capacitance (F) Capacitance 10
Capacitance (F) Capacitance 2 10 10-12 0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 10-54 10-56 10-58 10-51 10-41.2 10-4 Voltage (V) Current (A)
Figure 3-5: a) Capacitance vs. Voltage (CV) measurements performed on (30um)2 device at 10kHz, 100KHz and 1Mhz. The diode is seen to turn on sooner at lower frequencies. b) The forward capacitance is fit to equation 2.
3.4 Memdiode Characteristics The defining quality of the memdiode is the hysteresis in the diode IV characteristics. It should be mentioned that the only other known publication discussing the memdiode also presents a non-zero crossing in the IV [108]. This was also seen in this device for small areas (A≤100um2) and at lower temperatures (T~ <213K). In this case the likely cause is the presence of dielectric relaxation current, which is dependent on the polarity of the applied bias. The change of voltage dV/dt can be in the same or opposite direction as the leakage current [107]. This results in the non-zero crossover to change positions depending on the direction of the sweep. Therefore, a sweep from negative to positive bias would cause the crossover to be on the right side of the origin and vice versa.
40 However, while this is an interesting behavior it is not a necessary inclusion in the requirements for definition as a memdiode.
-11 1.8 10 1 10-8
-11 1.6 10 0
Current (A) Current (A) Current
-11 1.4 10 -1 10-8 -0.35 0 0.35 -0.35 0 0.35 Voltage (V) Voltage (V)
Figure 3-6: a) IV characteristics at T=83.81K of a (50um)2 device demonstrate non- zero crossing at low temperatures. This particular temperature value is significant only in that lies in the low-temperature range which display these characteristics. b) Non- zero crossing on (10um)2 device at room temperature.
Hysteresis in the IV was observed when the device was swept to a positive bias and back. The hysteresis loops observed had a region of overlap between subsequent sweeps.
This indicates that there is some decay when the bias is not present. Figure 3-7 shows successive hysteresis loops resulting from the same voltage sweep, these loops saturate after 2-3 sweeps and no further increase is seen. A higher voltage sweep is required to observe further hysteresis. The overall conductance of the device increases with each subsequent increasing voltage sweep. Similarly we are able to reduce the conductance of the device by applying negative voltage sweeps (figure 3-8), the device conductance is decreased below even the initial level as seen in the inset of figure 3-7. This is explained in proceeding paragraphs.
41 0.1 15 2 10 0.05 5 1 3 +2V_sweep 1 Current (mA) Current 0 +2V_sweep 2 +2V_sweep 3 +2.5V_sweep 4 0 +2.5V_sweep 5
Current (A) Current +2.5V_sweep 6 +3V_sweep 7 +3V_sweep 8 +3V_sweep 9 -0.05 -2 0 2 4 Voltage (V)
Figure 3-7: Hysteresis under forward bias. Multiple loops can be seen for each bias. The current increase saturates at a single bias after 2-3 loops, however, further conductance change is seen with increased applied bias. Inset 1a shows the forward conductance at +1V before forward hysteresis (1) after forward hysteresis (2) and after negative hysteresis (3). The data in this figure was obtained in this order. The device used was (200um)2.
42 0.002 0 -0.002 -1.5V_sweep 1 -3.5_sweep 12 -0.004 -1.5V_sweep 2 -3.5_sweep 13 -2V_sweep 3 -3.5_sweep 14 -0.006 -2V_sweep 4 -4_sweep 15 -2V_sweep 5 -4_sweep 16 -0.008 -2.5V_sweep 6 -4.5_sweep 17 -2.5V_sweep 7 -5_sweep 18
Current (A) Current -0.01 -2.5V_sweep 8 -5_sweep 19 -3V_sweep 9 -0.012 -3V_sweep 10 -3V_sweep 11 -0.014 -6 -5 -4 -3 -2 -1 0 1
Voltage (V)
Figure 3-8: Hysteresis loops resulting from reverse bias sweeps, decreasing device conductance is shown with subsequent loops, as well as larger decrease for larger negative bias. This measurement was performed on the same device ((200um)2) used in figure 3.7, and its start coincides with state (2) in the inset of that figure.
3.5 Device Model
The forward hysteresis is the result of a trap-based conductance change that behaves similarly to stress induced leakage current (SILC), a mechanism which is typically associated with trap rich high k dielectrics. The material conductance increase can be modeled using the following SILC equation:
푡 + − 휈 퐼 = 퐼0 + 푁 (퐸표푥) [1 − 푒 휏] + 훼 푡 (3.3)
+ Where I0 is initial current (used as a fitting parameter) and 푁 (퐸표푥) is the saturation value of native charge trapping, τ is the trapping time constant, α is leakage current caused by SILC induced traps and υ is the trap generation rate. A device was stressed using a 10ms
43 (width), +3V (amplitude) voltage pulse, the resulting current fits well to equation 3.3
(figure 3-9). When a forward bias is applied to the top electrode all native traps containing
electrons are emptied and those electrons are allowed to participate in conduction. This is
represented by the 2nd term of equation 3.3 and the initial exponential increase in current
(figure 3-9.).
3 8 8.5 8 2.5 6 7.5 2 4 7 1.5 2 6.5 1 6
Voltage (V) Voltage
Current (mA) Current Experimental (mA) 0.5 0 (mA) Current a 5.5 Theoretical (mA) 0 -2 5 b -2 0 2 4 6 8 10 12 14 -2 0 2 4 6 8 10 Time (ms) Time (ms)
Figure 3-9: a) A (30um)2 device was stressed using a 10ms (width), +3V (amplitude) pulse, the pulse amplitude was limited by the measurement equipment to ~ 2.76V. b) The current was extracted over this flat portion (V=2.76V) and fit to equation 3.3.
Table 3-2: Parameters extracted from the fitting in figure 3-9 using equation 3.3.
I 5.05 mA 0 + N 1 mA
τ 1.57 (s) ν α 0.95 (mA/s )
ν 0.379
44 Point defects in ZnO (which will be abundant, due to low formation enthalpies)
[109], are the most likely trap states participating in this conduction. In addition we expect oxygen vacancy migration from the FTO layer to ZnO layer, further increasing the defect concentration under positive bias. This theory of migration is supported by the use of a control sample in our lab in which the bottom electrode was replaced with Ru/Zn. All other conditions remained the same in this control sample and, similar diode characteristics were seen. However no appreciable memdiode behavior was observed.
The defect chemistry in ZnO is described using Kroger-Vink notation where i = interstitial site, Zn = zinc, O = oxygen, and V = vacancy. The primary defect reactions are
Zn interstitials (which are known to be mobile even at room temperature) [109] and O vacancies. Zn interstitials come from the Frenkel reaction resulting in a Frenkel defect
(vacancy + interstitial pair).
푥 푥 푍푛푍푛 ↔ 푍푛𝑖 + 푉푍푛 (3.4)
Oxygen vacancies are Schottky defects arising from the Schottky reaction caused by removal of an atom from the compound in the chemical formula, in this case Zn and O.
푥 푥 푁푢푙푙 ↔ 푉푍푛 + 푉푂 (3.5)
The magnitude of increase is slightly less than it would be for SILC alone, this can be explained through the presence of dielectric relaxation which occurs in ZnO when the device is stressed. This relaxation current can be detected when the leakage current is low
[107], the relaxation current follows the Curie-von Schweidler relation [108].
퐼 ∝ 퐶 푡−푛 (3.6)
Where C=Pα, P is the total polarization, α is a constant and n is a real number [108].
This is first shown by applying a +0.3V constant voltage stress after the SILC increase in
45 figure 3-9. The resulting I(t) fits well to (3.6) (see figure 3-10). In addition to the dielectric relaxation seen after an increase we are able to see a decrease below the initial measured conductance of the device. This is seen not only with negative hysteresis (as in figure 3-7-
3-8), but also by applying a low positive bias to a virgin device.
124
122 C 129.06 n 0.01867 120
118
116
Current (nA) Current 114
112 0 200 400 600 800 100012001400 Time (s)
Figure 3-10: Dielectric relaxation is modeled using the Curie-Von Schwiedler law (equation 3.6). A 0.3V voltage stress was applied, this measurement was on the same device and directly followed the increase in figure 3-9. The device used was (30um)2.
46 13.2 13.2 1st 13.1 13 2nd 3rd 13 4th 12.8 5th 12.9 Increase without bias 12.8 12.6 12.7
Current (A) Current 12.6 12.4 (nA) Current 12.5 12.2 a 12.4 b 0 50 100 150 200 250 300 0 2 4 6 8 10 12 Time (s) Test (#)
Figure 3-11: a) A +0.15V bias is applied to an untested (30um)2 device for five 250s increments. The time delay between applications was estimated to be between 1-2 seconds. b) The first and last point of each relaxation curve in a showing the increasing conductance in the absence of bias.
It is reasonable to attribute the above phenomena to a spontaneous polarization in
ZnO [110]. Cu2O and ZnO have differing compositions, microstructures, and strain states.
The stress of placing the two materials together may be acting on the piezoelectric nature of ZnO and inducing the creation of dipoles. The applied electric field couples with these dipoles forcing a near total relaxation even below the initial virgin state of the device. This is shown in figure 3-11 with the application of a 0.15V constant voltage stress; the device conductance is reducing beyond the initial point. The intrinsic polarization reasserts itself, in the absence of this field, as the dipoles attempt to realign figure 3-11b. Therefore when the applied electric field is removed the device conductance is seen to increase. The reapplication of the field continues the decrease and finally we are able to show the device saturation resulting from the bias induced neutralization of the initially polarized ZnO.
47 The field dependence of the dominating conductance mechanism is demonstrated by Constant Voltage Stress (CVS) measurements at various biases. Relaxation effects are shown to dominate at low field fitting to (3.6) while SILC dominates at high fields fitting to (3.3). However at moderate bias we are able to show the transition between the two mechanisms. This intermediate state is fit to (3.7) (figure 3-12) which combines the two opposing mechanisms.
푡 + − 휈 −푛 퐼 = 퐼0 + 푁 퐸표푥 [1 − 푒 휏] + 훼 푡 + 퐶 푡 (3.7)
In fact we are able to fit the entire range of CVS curves to (3.7) however at low bias, the field is not strong enough to empty native traps. In this low range the second term and most of the extracted parameters have no physical meaning. The time constants yielded from low bias measurements exceed 2000s, further implying that there is not enough time at the given energy to induce native traps to participate in conduction. At the lowest bias measured (0.15V) the best fitting is acquired from (3.6) suggesting only dielectric relaxation is taking place here. However at 0.3V we are able to show a more perfect fitting using (3.7) which includes the SILC terms, of which 훼 푡휈 is specifically relevant to the efficacy of the fitting. This suggests that while we are not able to induce conduction from native traps, there is some small leakage current due to low energy trap generation.
Further increasing the bias to 1V shows very clearly the transition between the two mechanisms we are able to acquire the best fitting from (3.7). The extracted parameters are shown in Table 3-3. At 1V, the 2nd term which takes into account native traps does not have a great effect on the fitting, this correlates with the small time constant τ=1.55s, suggesting that the initial native de-trapping happens very quickly. When the bias is increased to 1.15V we are able to acquire a good fitting using only the SILC equation, 48 however a more accurate fit is taken using (3.7). Finally at 1.3V, while (3.7) does yield a
more accurate fit it is only marginally better than using only the SILC equation suggesting
dielectric relaxation plays a very small role here as the leakage current is too high. If the
bias is increased further the pure SILC fitting (3.3) will be better than (3.7) due to the high
leakage current, making dielectric relaxation difficult to detect [107]. This type of fitting
is shown in figure 3-9 for a high bias, short duration pulse.
Table 3-3: Parameters extracted from fitting I(t) at various applied bias(s) to equation 3.7, corresponding to figure(s) 3-12.
Table II 0.15V 0.3V 1V 1.15V 1.3V
I0 (μA) 0.5 35 100 345 955
+ N (μA) 1 1 36 40 160
Τ (s) 2000 2000 1.55 13 13
ν α (μA/s ) 0.5 0.7 11 15 20 ν 0.09 0.56 0.373 0.478 0.632
n 0.045 0.09 -0.36 -0.0065 -0.0065
C 14.2 177.3 170 13 13
49 15 14.5 0.15V 14 13.5 Current (A)_experimental Current (A)_theoretical 13 12.5
Current (nA) Current 12 a 0 50 100 150 200 250 300 Time (s) 210 200 0.3V 190 180 Current (A)_experimental 170 Current (A)_theoretical 160 Current (nA) Current 150 b 0 50 100 150 200 250 300 Time (s) 290 280 270 Current (A)_experimental 260 Current (A)_theoretical 250 240 1.0 V Current (uA) Current 230 220 c 0 50 100 150 200 250 300 Time (s) Figure 3-12: a),b),c). CVS is applied to separate untested (30um)2 devices at biases ranging from 0.15V to 1.3V. One is able to see the transition from relaxation effect domination to SILC domination. I(t) is fit to equation 3.7 showing both mechanisms present throughout. I(t) vs. t is plotted for each bias, (the value of which is inset in each figure). 50
1800 1600 1.3 V 1400 1200 Current (A)_experimental 1000 Current (A)_theoretical Current (uA) Current 800 d 0 50 100 150 200 250 300 Time (s) 650 600 550 1.15 V 500 450 Current (A)_experimental Current (A)_theoretical
Current (uA) Current 400 350 e 0 50 100 150 200 250 300 Time (s)
Figure 3-13: d),e). CVS is applied to separate untested (30um)2 devices at biases ranging from 0.15V to 1.3V. One is able to see the transition from relaxation effect domination to SILC domination. I(t) is fit to equation 3.7 showing both mechanisms present throughout. I(t) vs. t is plotted for each bias, (the value of which is inset in each figure).
51 The negative hysteresis which is shown figure 3-8 follows the decrease in device conductance after it has been excited to some higher state figure 3-7. After the removal of this excitation bias, the trap states will be filled, this includes intrinsic as well as SILC induced traps. The negative bias enables de-trapping of intrinsic states as well as neutralization of SILC induced traps, possibly by driving oxygen vacancies back into FTO from ZnO. The decrease due to these processes is given by the modified SILC equation:
푡 + − 휈 퐼 = 퐼0 + 푁 퐸표푥 [푒 휏] + 훼 푡 (3.8)
Equation 3.8 is simply the logical and mathematical complement of equation 3.3, and makes no assumptions about the particular mechanism of trap annihilation. A good fit is acquired using this model (figure 3-13), which suggests that the opposite reactions to those described in (3.5) and (3.6) are taking place.
2 0 0.5
Current (mA) 1.8 |current (mA)| 0 -1 1.6 Theoretical (mA) -0.5 1.4 -2 -1 1.2 -3 -1.5 1 -2
Voltage (V) Voltage -4 0.8 -2.5 |Current (mA)| |Current 0.6 a -5 b -3 0 2 4 6 8 10 12 -2 0 2 4 6 8 10 12 14 Time (ms) Time (s)
Figure 3-14: The first negative pulse (-5V/10ms) following a 100 pulse (+3V,10ms) conductance increase is shown. This I(t) is modeled using equation 3.8. The absolute value of the current is used. b) The raw pulse is shown. The device used was (30um)2, the entire series of pulses is shown in figure 3-14.
52 20 10-5 a 10-6 b +0.3V 15 10-7 10-8 10 10-9 10-10 5 -0.3V (A) Current -11 Current (uA) Current 10 0 10-12 0 50 100 150 200 250 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 Cycle (#) Voltage (V)
Figure 3-15: a) The current is shown in absolute. IV sweeps are performed after each +3V/10ms pulse for 100 cycles (The first 40 are shown). An incremental increase in conductance is shown. This change is traced showing the current at +0.3V and 0.3V. b) IVs were similarly collected following the 100 (-5V/10ms) pulse decrease, this is also shown using the +/- 0.3V edge of the IV. The device used was (30um)2.
1.1 Current (mA)_cycle 2 Theoretical (mA)_cycle 2 Current (mA)_cycle 3 1 Theoretical (mA)_cycle 3 Current (mA)_cycle 4 Theoretical (mA)_cycle 4 0.9 Current (mA)_cycle 5 Theoretical (mA)_cycle 5 0.8
Current (mA) Current 0.7
0.6 0 2 4 6 8 10 12 Time (ms)
Figure 3-16: The four pulses succeeding that which is fit in figure 3.13 are also fit to equation 3.8. All data extracted from the measurement shown in full in figure 3.14, but for which data is used in figures 3-13-3-15 were performed on the same (30um)2 device.
53 Table 3-4: a) Parameters extracted for fittings (to equation 3.8). Pulse 1 is shown in figure 3-13, Pulses 2-5 are shown in figure 3-15
+ ν I0 (mA) N (mA) τ (ms) ν α (mA/s ) Pulse 1 0.650 150 2.12e-04 -0.9 0.0023
Pulse 2 0.551 9 2.12e-04 -0.48 0.02 Pulse 3 0.0032 4 2.12e-04 -0.138 0.366 Pulse 4 0.0012 1 2.12e-04 -0.131 0.366 Pulse 5 0.001 1 2.12e-04 -0.123 0.37
The N+ value extracted from figure 3-13 is initially large and then decreases
dramatically for succeeding pulses (figure 3-15, table 3-4). This suggests almost all native
defects are reset in the first pulse, whereas the refilling of the SILC defects is a more
gradual process, seen by the slow change of 훼 and 휐 (table 3-4). I0 is used as a fitting
parameter and represents the current saturation, as the pulse progress this number decreases
with device conductance. Equation 3.8 does not take into account contributions from
dielectric relaxations which are not expected to be highly relevant in this bias regime.
We further explore the unique behavior of this device with possible applications in
mind figure 3-14a shows the incremental change in current with the application of 100
(+3V, 10ms) pulses. An IV sweep from -0.3V to +0.3V is taken after each pulse this
steadily shifting I-V curve is shown in figure 3-14b. Significant asymmetry in the I-V is
maintained initially over ~ 30 pulse applications or state changes, however it does diminish
when the conductance of the device is very high. The linear increase in conductance
relative to the number of pulses is shown in figure 3-16a; this is shown relative to the
initial state of each device to account for any initial device variability. Finally the device
is “switched” between two states, a 5ms, +3V pulse increase vs. a -5V, 5s decrease shown
54 in figure 3-15b. Unfortunately the voltage necessary to reduce the conductance is significant; this would have to be reduced for practical applications.
5 10-5 0.0001 current -5 4 10 Initial ON OFF 3 10-5 10-5 2 10-5
Current (A) Current 1 10-5 (A) Current a b 0 10-6 0 20 40 60 80 100 120 140 0 2 4 6 8 10 12 Number of applied pulses (#) Cycle (#)
Figure 3-17: a) The linear increase in conductance relative to the number of pulses is shown to demonstrate the conduction modulation with number of pulses. This is shown relative to the initial state of each device to account for any initial variability. b) The device is “switched” between two states, a 5ms, +3V pulse increase (ON) vs. a -5V, 5s decrease (OFF). All measurements in figure 3-16 were performed on (30um)2 devices.
The analog resistance change of this device, along with the inherent non-linearity make it the ideal device for memory implementation using crossbar architecture. However, some parameter modulation will be necessary, for example the switching characteristics require an unreasonable “RESET” voltage. The IV non-linearity is not maintained throughout the entire increase cycle, however this could simply require smaller incremental increase to allow for a greater density of storage states in the non-linear operational region of the device. Finally the pad size of all tested devices was in the micron range, scaling to the nano-regime would yield interesting results, as well as scaling of the pn junction thickness, which is presently 30nm. 55
Chapter 4
4. Characterization and Modulation of Relevant blank blanbCu2O/ZnO Diode Parameters for CBA Implementation
4.1 Abstract of Chapter
In this chapter, the Cu2O/ZnO pn junction is used to form a Ru/Zn/ZnO/Cu2O/Cu
heterostructure and the diode parameters are extracted. This diode is characterized for
crossbar array (CBA) implementation. Crossbar implementation includes usage as a
primary or supplementary device. For example in a diode tile for use in Boolean logic
mosaics (composites of device tiles) or other diode applications; this would be a primary
device application. As a secondary device it is used in conjunction with RRAM to inhibit
sneak current. Hybrid circuitry using these two CBAs will allow for high density, low
power general computation. Several diode parameters are studied, in addition, the reverse
saturation current is modulated by varying the thickness of the Cu2O layer. The effects of
this modulation on general device operation and related diode parameters is discussed.
4.2 Introduction
Cu2O/ZnO is a widely used heterojunction, finding applications in a wide array of
fields. This non-toxic, abundant, cost effective material stack has been studied mostly for
use in solar cells. This is due to the favorable properties of Cu2O (intrinsic p-type, high
56 absorption coefficient, band gap of 2.17eV) [26],[111] and ZnO (intrinsic n-type, transparent, wide-band gap 3.37eV) [25]. However diodes based on this stack have not been characterized for implementation in crossbar arrays (CBA).
CBA architecture offers a unique approach to nano-electronic computation, with simplistic fabrication and independent device configurability. Different types of devices can be fabricated onto adjacent regions within a single CBA, where there are electrically conductive paths between regions. Regions containing a single type of device are called tiles or blocks [17]. Composites of tiles can be used to implement different Boolean logic operations. For example, diode tiles can be used to implement AND/OR gates (figure 4-
1). Even more complicated composites of tiles or blocks are referred to as mosaics.
Mosaics of tile combinations can be organized for some useful functions such as signal amplification.
CBA tiles using novel nano-elements such as memristive devices are being produced to replace or be used in conjunction with conventional memory schemes. One such novel nano-element is RRAM (resistive random access memory). This is a two terminal digital memelement capable of storing information in the form of a resistance value. This value may be changed or “switched” between two digital states LRS (low resistive state) = ON or 1 and HRS (high resistive state) = OFF or 0. Diode tiles may also be implemented with memory tiles such as RRAM in cascade processes that resemble dynamic logic and allow for inversion and gain enabling general computation operations
[17],[112],[113],[114]. The Cu2O/ZnO based diode is an ideal complement for ZnO
[49],[75],[89],[90], or Cu2O [91] based RRAM devices.
57 Most RRAM devices require an access device to prevent between devices (figure
4-2). RRAM arrays without an access device may suffer from programming failure and signal degradation, in addition to false read results. Programming failure similarly results from sneak current and occurs during write operation. Leakage or sneak current can cause the voltage drop at the interconnect of the device selected for programming to be insufficient leading to misprogramming. Additionally crosstalk induces reliability issues such as stress-induced retention failure.
These devices have certain requirements that will depend on the type of RRAM used. Type refers to both material composition and switching mechanism. There are two broad switching schemes that RRAM devices fall into: Unipolar/Ambipolar and Bipolar.
As the names indicates, unipolar RRAM may have its state both set and reset to the high and low state using an electrical signal (voltage/current pulse) of the same polarity.
Though, if unipolar switching can occur symmetrically using both positive and negative bias, it is referred to as nonpolar. Bipolar switching requires an electrical signal of the opposite polarity to set and reset. The access device required will have to be specialized based on these properties.
Due to their switching capability, diodes are used as access devices. This is referred to as 1D1R architecture. It is preferable over 1T1R (one transistor, one resistive switch), for many reasons such as more cost effective manufacturing. This is due to the simpler fabrication structure. 1D1R structures will also allow for higher density, allowing for 4F2
(where F is the feature size) per layer, and even higher densities using 3D stacking.
Whereas 1T1R would be limited to 6F2, similarly to DRAM, the current volatile memory used in computers). 1D1R architecture is generally limited to unipolar devices, since the
58 unidirectional conduction of most diodes would inhibit the opposite polarity set/reset required for bipolar devices. 1S1R (1-selector, 1 resistive switch) is therefore the preferable structure for bipolar RRAM, where selector is the generic title given to a suitable bidirectional access device. Diodes also provide more flexible oxide based deposition options, for both materials and substrates (i.e. they can be deposited at low temperatures for uses such as flexible electronics on plastic substrates). This increases the likelihood of satisfying the material requirements of the RRAM selection device; most RRAM devices are made using metal oxides. Therefore it is necessary to fabricate and characterize compatible oxide based access devices. In succeeding sections, the Cu2O/ZnO based diode is discussed for CBA implementation. It is characterized as an access device for RRAM
CBAs; the general diode characteristics of the device for solitary operation are also discussed.
Figure 4-1: Redrawn in the style of reference [17]. An AB+C gate logic block using pull- up and pull-down resistor tiles between crossbars on a substrate that supplies power and ground. Junctions in these tiles supply the pull-up and pull-down resistors, while the configurable diode tile is used for AND and OR gates. Diode crossbars such as this in conjunction with RRAM crossbars can be used to form state machines [114] which can complete nearly any function. 59
Figure 4-2: Crosstalk or sneak current is shown schematically. When attempting to read the selected device, current does not only follow the desired path but instead may leak into the selected device (blue) causing a false read. Additionally when attempting to write the device current may leak from the device (orange), leading to programming failure.
Different bias methods may be used to read or write the selected memory cell in the array, such as the 0V (read operation only), floating, 1/2V, and 1/3V methods. In the zeroed, floating and 1/2V methods the wordlines and bitlines are set to be grounded, floating and 1/2 the value of voltage of the selected wordline. In the 1/3V method, the unselected wordlines and bitlines are set to be 1/3 and 2/3 of the value of the selected wordline. For a successful write operation, the voltage drop across the selected cell must be larger than the switching voltage, whereas the voltage drop on the unselected cell should be lower than the switching voltage to avoid misprogramming. Whereas for a nondestructive read, the voltage drop across all the devices should be lower than the switching voltage. The access device must prevent crosstalk without interfering with the aforementioned operations.
60 4.3 Fabrication and characterization setup
Figure 4-3: Schematic diagram of the fabricated device. The Titanium layer acts to ensure the adhesion of the Ruthenium bottom electrode. Zinc ensures an Ohmic contact between the n-layer (ZnO) and the bottom electrode. The testing probe is contacted to the Ru electrode which is exposed to ambient.
n-ZnO/p-Cu2O heterojunctions were fabricated on Zn/Ru coated silicon substrates using RF magnetron sputtering. Zn and Ru were sputtered onto prepared Ti coated p-Si wafers. The Si wafers were cleaned using an HF acid rinse, the wafers were then coated with 3nm Ti (RF sputtered) to assist with adhesion. A Zn target (99.99%) was reactively sputtered with O2 (Ar plasma) to achieve 15 nm ZnO films. 15 nm of Cu2O was similarly deposited using a Cu target (99.99%). The substrate temperatures for ZnO and Cu2O were
100 ˚C and 27 ˚C respectively. Cu was deposited as the top electrode at room temperature
(~20 °C). The Cu electrodes were defined using contact lithography and etched using Cu wet etchant. Electrical characterization was done using a Keithley 4200 Semiconductor
Characterization System (SCS) equipped with an ultra-fast 4225 Pulse Modulation Unit
(PMU). Temperature variant measurements were taken using a Lake Shore cryogenic
TTP4 probe station cooled with liquid nitrogen. In all of the following measurements the
61 top electrode was biased while the bottom (Ru) was grounded. The device schematic is presented in the inset of FIG1a. The device sizes used for testing range from 50 um x50 um to 200 um x200 um. The size of devices used for each test are mentioned in the captions of figures. A schematic diagram of the device is shown in figure 4-3.
4.4 Data and Analysis
a b
Figure 4-4: a) Current vs. voltage curves are shown for several devices of the following sizes: (50um)2, (100um)2 and (200um)2. The overlap amongst devices of the same size shows repeatability across the sample. These IV characteristics also show scaling with area.
(The ordinate is a logarithmic scale and the current is shown in absolute) b) The threshold voltage is extracted graphically from the linear region of the IV (0.8V-2V), at the area sizes mentioned in 4.4.1.a. The inset shows f (A). v The initial I-V characteristics are shown in figure 4-4. The curves are highly asymmetric due to the pn-heterojunction formed by n-ZnO and p-Cu2O. ZnO is intrinsically n-type [94], typically showing n-conductivity without any deliberate doping.
Cu2O is similarly p-type [103]. The threshold voltage (Vturn-on) is extracted graphically from the initial IV characteristics (figure 4-4). This turn-on voltage is extracted for various device areas. The turn-on voltage is one of many different parameters that must be monitored when scaling devices in the microscopic range.
62
Table 4-1: Summary of characterizations metrics for access device used in chapter 4.
The manner in which the threshold voltage changes with area will be especially important when entering the nanoscale regime. This is due to the fact that quantum mechanical effects and other small area anomalies begin in this regime, we cannot know exactly how any parameter may behave. However, we can extract a trend and predict its general behavior. The threshold voltage monitor parameter fv is inversely proportional to the device area (inset of figure 4-4b). It should be noted that the threshold voltage is effectively only relevant compared to the necessary operating or ON voltage. This is because the barrier limited turn on voltage based on the built in potential of a pn junction is only a few electron volts. However, the turn on is often extracted as being beyond this point, this extracted point is that which is relative to the ON/operating current of the device.
This is supported by the ideal diode equation (4.1). This equation requires no threshold, instead it dictates only a smooth exponential increase. It is because of this that the threshold
63 voltage is extracted crudely using methods such as the graphical method used in figure 4-
4.
The turn-on point of the diode can be engineered not only based on material parameters, but also on the relative operating point. Furthermore the threshold voltage will be a compatibility parameter when paired with a RRAM device. The desirable threshold value for the diode as an access device would be such that it turns on, and the state of the device could be determined without further alteration. However it would also have to turn on in order for the set/reset process to take place. For idealized unipolar operation this is relatively simple and requires the following condition be met.
푉푡ℎ푟푒푠ℎ표푙푑 ≤ 푉푟푒푎푑 ≤ 푉푠푒푡/푟푒푠푒푡
A large part of the appeal of CBA architecture lies in the quality of individual configurability. This feature requires that any single device may be accessed independently, therefore the other devices must be kept electrically neutral. For example to access a desired device (for read or programming), an access voltage Vaccess may be applied to one crosspoint of the device while the other is kept at V=0V. During this process, the other devices must be kept below the minimum switching threshold of the system. This operating scheme can be modeled with an inhibiting factor, β, where β = Vmin-threshold/
Vaccess. Larger inhibiting factors will lead to wider design latitiude for the random access of the CBA [115]. Knowledge of the diode threshold voltage and trend will allow for CBA design using parameters such as β.
For bipolar operation, it becomes slightly more complicated as the RRAM device is meant to reset using an opposite polarity bias. This is contrary to basic diode operation, in which the diode should only conduct in one direction. This may be addressed through
64 the use of a Zener diode [78] or other asymmetrically conducting diode such as the punch through diode [79]. The threshold voltage is among many parameters monitored and/or modulated in this work. A summary of these parameters and the dependencies discussed is shown in Table 4.1.
The IV characteristics of a pn diode should follow the ideal diode equation (1).
However, when there are changes in the dominating conduction mechanism with applied bias, the slope of the curve will change and we are unable to obtain a continuous fitting.
The IV is therefore broken down into sections according to appreciable changes in the slope.
푞푉 퐼 = 퐼 [exp ( ) − 1] (4.1) 푠 푛푘푇
In equation 1, I is the current response of the junction, Is is the reverse saturation current, q is the unit electron charge, k is the Boltzman constant, T is the absolute temperature and n is the ideality factor. The ideality factor n is extracted from the slope of an ln (I) vs. V plot where (-1) is neglected. According to Sah-Noyce-Schockley (SNS) theory, on which the ideal diode equation is based; the ideality factor for the ideal diffusion controlled junction is n=1 while deviations up to n≤2 reflect the presence of defect induced recombination in the space-charge region. Larger deviations of n (n>>2) indicate the presence of surface or interface states, and the contributions due to series resistance and multiple contacts [105]. Additionally series resistance may be introduced by the test setup.
The ideality n is not constant throughout the measured range, indicating the dominance of different mechanisms, the curve is broken down into 4 major regions. These regions are plotted individually in figure 4-5. Initially the ideality is n=1.76, 1.77, and 1.89 for the (50 um)2, (100 um)2 and (200um)2 devices respectively. This is an acceptable result
65 given the expected domination of generation/recombination effects at low bias. Region I
encompasses only the current response for low bias (≤0.4V), region II shows significant
deviation indicating the presence of defect induced recombination. However
recombination is not a suitable explanation for such large deviation. The ideality factors as
a function of area and bias region are listed in table 4-2 and plotted in figure 4-6.
Further increase shows deviation up to 29 (region IV). Ideality factors this large
cannot be explained within the confines of SNS theory. Some of this deviation at higher
bias is indicative of high series resistance. This high resistance can be explained in part by
the presence of a low barrier Schottky contact at the Cu2O/Cu interface. This barrier is
expected due to the electron affinity (4.84eV) [106] and work function (4.35eV) [106] of
Cu2O and Cu respectively. When the pn junction is forward biased, by applying a positive
bias to the TE, this Cu2O/Cu Schottky barrier would contribute a reverse current and vice-
versa. The additional voltage drop of the Schottky barrier combined with the pn junction
forward current, may be contributing to the large non-ideality as explained using
conduction models that present a serial arrangement of mechanisms [105].
Table 4-2: The variation of the ideality factor as a function of device area is shown. These values are extracted using equation 4.1, the fittings are shown in figure 4-5.
Device Area Region I Region II Region III Region IV 2 (50um) 1.766226 5.173776 10.36108 29.9259 (100um)2 1.771707 4.733381 11.16444 24.22155 (200um)2 1.891254 4.697241 12.75753 21.77345
66 Figure 4-5: Fittings from which the ideality factors are extracted. a) Region I (0V-0.4V) b) Region II (0.4V-0.8V) c) Region III (0.8V-1.15V) d) Region IV (1.15V-2V).
Figure 4-6: Ideality factor for Region I (0V-0.4V) b) Ideality factor for Region II (0.4V- 0.8V) c) Ideality factor for Region III (0.8V-1.15V) d) Ideality factor for Region IV (1.15V-2V)
67 Further insight into the diode behavior is acquired through analysis of the temperature variant IV characteristics. IV curves at temperatures varying from 77K to
400K were taken. The results show the expected increase in conductivity with increasing temperature T. The ideal diode equation in its expanded form is shown in (4.2).
푁 퐷 푁 퐷 푞푉 푞푉 퐼 = 푞퐴 ( 푑 푒 + 푎 ℎ) exp (− 푑) {exp ( ) − 1} (4.2) 퐿푒 퐿ℎ 푛푘푇 푛푘푇
Where q is the electronic charge, A is the cross-sectional area of the device. Nd and Na are donor and acceptor concentrations, De/Le and Dh/Lh are the electron and hole concentrations/diffusion lengths. Vd is the diffusion potential, n and k are the ideality factor and Boltzmann constant respectively. For qV>>kT (4.2) can be rewritten such that:
푁 푁푎퐷 푉 −푉 퐼 = 푞퐴 ( 푑퐷푒 + ℎ) exp (−푞 푑 ) (4.3) 퐿푒 퐿ℎ 푛푘푇
Equation 3 can further be rewritten as (4) showing that for a given forward bias V the diode current exhibits an exponential relationship with respect to the reciprocal of the temperature T.
1 ln 퐼 = −푆 + ln 퐵 (4.4) 푇
Where the terms S and B are given as:
푉 −푉 푁 퐷 푁 퐷 푆 = (푞 푑 ) , 퐵 = 퐴 ( 푑 푒 + 푎 ℎ) (4.5, 4.6) 푘푇 퐿푒 퐿ℎ
The diffusion potential as well as the carrier diffusion constants are dependent on temperature, however, given reasonably doped p an n regions, this dependence is negligible over a wide temperature range [116]. Figure 4-7 shows that there is a temperature independence at low temperature and bias, this indicates a tunneling mechanism dominates in this regime (~0V to 0.7V and 77K-108K). However beyond this range the data fits well to equation 4.4 (Figure 4-7b), essentially fitting to the ideal diode equation. This
68 mechanism change is causing the threshold voltage to shift, this shift is inversely proportional to the temperature. An accurate numerical extraction of this threshold shift is not possible due to the way the IV shape changes with temperature; it is however evident in figure 4-7a that the threshold is inversely proportional to temperature. This temperature variant analysis shows that while there may be some contact induced non-ideality there is still a dominant pn junction, governed by SNS theory.
a b
Figure 4-7: a) The IV characteristics are shown for a (50 um)2 device for temperatures varying between 77K and 354.56K. b) ln I vs. V for 0.7V- 2V, fitting(s) to equation 4.4.
The ON/OFF ratio as a function of temperature is shown in figure 4-8. Room temperature
(T~298K) is shown to be the optimal operating region with the highest ON/OFF ratio. This is of course only if we consider +1V/-1V to be on and off respectively. We are able to follow the evolution of the ON current at +1V and OFF current at -1V which are also shown figure 4-8. The values for current density and the ON/OFF ratio are shown in table 4-3 for room temperature devices. There is an anomaly where the ON current density is higher for the (100um)2 devices than for (200um)2 devices; this leads to a better ON/OFF ratio. The
69 likely cause of this higher current density is a higher series resistance for the (200um)2 devices.
Table 4-2: The current density and on/off ratio at room temperature for (50um)2 ,(100um)2 and (200um)2 devices.
Device Area Current Current ON/OFF ratio Density Density A/cm2 A/cm2 (ON at +1V) (OFF at -1V) 2 (50um) 18.84 3.68E-03 5.13E+03 (100um)2 34.44 5.39E-03 6.39E+03 (200um)2 28.39 7.65E-03 3.71E+03
a b
Figure 4-8: a) The trace of the on current and off current at +1V and -1V. b) The ON/OFF ratio as a function of temperature.
Fundamentally a diode is a switch. As an ideal switch, the diode should conduct
(ON) when forward biased, behaving as a short circuit, and behave as an open circuit when reverse biased (OFF). The speed, or switching time required for the diode to turn-on and turn-off will be a limiting factor for RRAM memory applications, and also the speed of
70 logic operations. How quickly a memory cell can be written will depend on how quickly the diode can turn-on, while how soon one can accurately “read” this state after it has been written will be limited by the reverse recovery time of the diode. The switching characteristics of the Cu2O/ZnO diode were captured using an oscilloscope, the circuit setup is shown in figure 4-9.
A high frequency input function was chosen to best mimic the diode switching behavior in actual computational applications. The diode is switched 10 times at 1MHz, using a +2V/0V input from the Keithley SCS. The diode response from the two channels of the oscilloscope are shown in figure 4-9a. The diode turn-off time is calculated at the end of each cycle. A single cycle is shown in figure 4-9b. The turn-off time is taken as the time difference between the point when the resistor current first goes to zero (Ch1: input goes to zero after 100ns fall time) and the time when the diode current (Ch2) goes to zero.
The turn on time is also extracted from this curve as the difference between the pre-turn on zeroed (0V or very close) value and the peak of the diode voltage. The rise time from the supply (100ns) is subtracted. We find the turn-on time average over the 10 cycles to be
12ns while the turn-off time is 110ns.
71
Figure 4-9: Switching circuit is shown as well as a) output data from oscilloscope. b) A single cycle is shown for clarity
72
Figure 4-10: This is done by repeatedly applying alternative “ON/OFF” pulses of ±2V followed by test pulses taken at ±1V. Resistance vs. iteration is plotted for several devices over a) 106 and b) 109 iterations.
The other major timing consideration is device endurance. In order for a diode to function properly as a RRAM access device it will have to be at least as durable as that
RRAM element. Therefore it is necessary to test any access device under similar conditions to those of the RRAM element. In this interest, endurance testing similar to that done for
RRAM devices was performed. The durability of the diode was captured by monitoring the ON/OFF ratio as a function of the number of switching cycles. This is done by repeatedly applying alternative “ON/OFF” pulses of ±2V followed by test pulses taken at
±1V. This measurement was taken for several devices as seen in figure 4-10, each of these devices were stressed for 106 iterations. However, RRAM endurance values can range from
106 to 1011, we therefore further stressed a device to 109 cycles. The results in figure 4-10 show that not only is the diode at least as durable as the standard RRAM device but that the on/off ratio actually improves with use. While this slight improvement may be an
73 anomalous result, the durability is at least not in question. This is a fundamental requirement, as the access device failure will mean bit failure.
Figure 4-11: The thickness of the Cu2O layer is varied from 0nm to 15nm. All other fabrication parameters remain the same. The IV characteristics are s is shown for (200um)2 devices.
As a unipolar RRAM access device, the ideal reverse saturation current would be
0. This is not realistic behavior for any real diode, we can however modify the reverse saturation current. The immediately obvious strategy for reducing Is would be reducing the overall conductivity of the diode, however this may affect the forward behavior. We have modified the thickness of the Cu2O layer, while leaving all other parameters the same. We first eliminate the Cu2O layer altogether, leaving an asymmetrical MIM structure, consisting of Ru/Zn/ZnO/Cu. The results are shown in figure 4-11 show the reverse saturation current is most altered.
74 While there is some alternation in the forward current, it is significantly less than the change in the reverse current, suggesting that controlling the Cu2O thickness may be a method of controlling Is. One may observe the relative threshold voltage change in figure
2 4-12. This Vt is extracted for (200um) devices that have been swept from -1V to +1V therefore the possible operating range from this data is 0 to 1V. The turn-on voltage Vturn- on is extracted from a limited range. The turn-on is actually higher for the thicker Cu2O layer, suggesting this parameter could also be modulated by controlling the thickness of the p-type layer. The tradeoff is that the reverse current is higher for the thinner layer. This suggests that materials engineering will allow for some stack optimization and control.
Figure 4-12: The on and off current at +/- 1V is shown for all 0nm, 7nm and 15nm Cu2O layers. The threshold voltage is extracted for each thickness of Cu2O.
75 Figure 4-13: a) The on and off current at +/- 1V is shown for all 0nm, 7nm and 15nm Cu2O layers. b) The threshold voltage is extracted for each thickness of Cu2O
76 Chapter 5
5. Conclusions and Future Work
In conclusion, a low temperature semi-transparent reconfigurable memdiode using
a ZnO/Cu2O heterostructure on an FTO coated glass substrate has been demonstrated. The
reconfiguration mechanism is explained based on trap based conduction mechanism
derived from SILC and dielectric relaxation effects. We believe that in addition to the
ZnO/Cu2O materials, FTO electrode used in this work plays an integral role in providing
the reconfigurable diode conductance. However, the voltage needed for reconfiguration
was observed to be high. Therefore, our future work will explore routes to optimize
ZnO/Cu2O materials composition and thickness to achieve reconfiguration at lower bias.
Further study of the junction dynamics is also necessary to understand the substantial
conductance changes in the reverse bias current and how this can be modified to be
advantageous to the device operation.
The ZnO/Cu2O heterostructue is used to form a pn heterojunction diode. This diode
is characterized for use in Crossbar arrays. A discussion is presented on the general
characteristics of the device and extract diode parameters if it were to operate for example
in a diode tiles for Boolean logic. This diode is also discussed as an access device for
RRAM digital memristive device usage. In this capacity the device is characterized as an
access device for RRAM, discussing relevant parameters. The thickness was also
77 modulated for the p-type layer, showing the effect on the forward and reverse current. The importance of this parameter (reverse saturation) and the effects and tradeoffs of modulation through Cu2O thickness changes are discussed.
78
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88 Appendix A
A. Supplementary Information for Chapter(s) 3 and 4
Process flows for the samples presented in this thesis are included below.
A.1 Fabrication Process Flows
Table A-0-1: Fabrication detail for sample presented in chapter 4.
Fabrication of Zn/ZnO/Cu2O/Cu P-N Junction (PNJ_4) Description: Si wafer substrate: 50mm, 525um, 0.075-0.082 ohm-cm (3x10^17 cm-3) Quantity 1
Steps Description 1 Wafer Labeling (Scribing): Total Number of Wafers: 1 Substrate ID: PNJ_4 Comments: Facility: UT NF
2 Cleaning & Surface Treatment Substrate ID: PNJ_4 Recipe: 5% HF dip for 30 s followed by 2 min DI water rinse Comments: Facility: UT NF
3 Deposition of Adhesion Layer Substrate ID: PNJ_4 Tool: UT Sputtering Target: Ti Reactive Gas: None Base Pressure:
89 Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, Room Temperature Thickness: 30 A Time: 67 seconds Comments: Facility: UT NF
4 Deposition of Lower Metal Electrode Substrate ID: PNJ_4 Tool: UT Sputtering Target: Ru Reactive Gas: None Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, Room Temperature Thickness: 1000 A Time: 42 minutes Comments: Facility: UT NF
5 Deposition of Ohmic Contact Layer Substrate ID: PNJ_4 Tool: UT Sputtering Target: Zn Reactive Gas: None Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, Room Temperature Thickness: 100 A Time: 3 minutes and 43 seconds (Unknown Deposition Rate. Assume similar to Ti) Comments: Cover part of wafer for lower contact. Facility: UT NF
6 Deposition of ZnO Substrate ID: PNJ_4 Tool: UT Sputtering Target: Zn Reactive Gas: Oxygen Flow: Ar = 9.6 and O = 2.4 Base Pressure: Process & Parameters: 50 W, 3.3 mTorr, 40 rpm, 10 mm, 100 °C Thickness: 150 A Time: 17 minutes and 44 seconds Comments: Cover part of wafer for lower contact.
90 Facility: UT NF
7 Deposition of CuO Substrate ID: PNJ_4 Tool: UT Sputtering Target: Cu Reactive Gas: Oxygen Flow: Ar = 10.7 and O = 1.3 Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, 27 °C Thickness: 150 A Time: 12 minutes and 15 seconds Comments: Cover part of wafer for lower contact. Facility: UT NF
8 Deposition of Upper Metal Electrode Substrate ID: PNJ_4 Tool: UT Sputtering Target: Cu Reactive Gas: None Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, Room Temperature Thickness: 1000 A Time: 22 minutes and 17 seconds Comments: Cover part of wafer for lower contact. Facility: UT NF
9 Prebake Substrate ID: PNJ_4 Tool: UT Digital Hotplate Temperature: 115 C Time: 5 minutes Comments: Cool for 5 minutes Facility: UT NF
10 Spincoating Photoresist Substrate ID: PNJ_4 Tool: UT Spinner Primer: HMDS Spread Speed: 300 Time: 5 Spin Speed: 3000 Time: 30 Photoresist: S1813 Spread Speed: 500 Time: 10 Spin Speed: 4000 Time: 60 Seconds
91 Comments: Facility: UT NF
11 Soft Bake Substrate ID: PNJ_4 Tool: UT Digital Hotplate Temperature: 115 C Time: 1 Minute Comments: Facility: UT NF
12 Lithography to Pattern Electrodes Substrate ID: PNJ_4 Photoesist: S1813 Tool: UT Mask Aligner Mask: UT Etch Mask Intensity: 20 mW/cm^2 Time: 10 seconds Comments: Cover part of wafer for lower contact Facility: UT NF
13 Develop Photoresist Substrate ID: PNJ_4 Developer: MF319 Time: 1 minute and 30 seconds Comments: Facility: UT NF
14 Hard Bake Substrate ID: PNJ_4 Tool: UT Digital Hotplate Temperature: 115 C Time: 1 Minute Comments: Facility: UT NF
15 Metal Etching Substrate ID: PNJ_4 Etchant: Copper Etchant Time: 18 seconds Comments: Facility: UT NF
16 Photoresist Removal
92 Substrate ID: PNJ_4 Remover: PG Remover Time: 1 Minute Comments: Facility: UT NF
Table A-0-2: Fabrication detail for sample presented in chapter 3.
Fabrication of FTO/ZnO/Cu2O/Cu Memdiode (OXSC-14) Description: ~1 x1 (lateral dimension) FTO coated glass substrate Quantity 1
Steps Description 1 Wafer Labeling (Scribing): Total Number of Wafers: 1 Substrate ID: OXSC_4 Comments: Facility: UT NF
2 Cleaning & Surface Treatment Substrate ID: OXSC-14 Recipe: Micro-90 rinse w. DI water a > 70 C Comments: Facility: UT NF
3 Deposition of ZnO Substrate ID: OXSC-14 Tool: UT Sputtering Target: Zn Reactive Gas: Oxygen Flow: Ar = 9.6 and O = 2.4 Base Pressure: Process & Parameters: 50 W, 3.3 mTorr, 40 rpm, 10 mm, 100 °C Thickness: 150 A Time: 17 minutes and 44 seconds Comments: Cover part of glass with Kapton tape for lower contact. Facility: UT NF
4 Deposition of CuO Substrate ID: OXSC-14 Tool: UT Sputtering Target: Cu Reactive Gas: Oxygen Flow: Ar = 10.7 and O = 1.3 93 Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, 27 °C Thickness: 150 A Time: 12 minutes and 15 seconds Comments: Cover part of glass with Kapton tape for lower contact. Facility: UT NF
5 Deposition of Upper Metal Electrode Substrate ID: OXSC-14 Tool: UT Sputtering Target: Cu Reactive Gas: None Base Pressure: Process & Parameters: 100 W, 5 mTorr, 40 rpm, 10 mm, Room Temperature Thickness: 1000 A Time: 22 minutes and 17 seconds Comments: Cover part of glass with Kapton tape for lower contact. Facility: UT NF
6 Prebake Substrate ID: OXSC-14 Tool: UT Digital Hotplate Temperature: 115 C Time: 5 minutes Comments: Cool for 5 minutes Facility: UT NF
7 Spincoating Photoresist Substrate ID: OXSC-14 Tool: UT Spinner Primer: HMDS Spread Speed: 300 Time: 5 Spin Speed: 3000 Time: 30 Photoresist: S1813 Spread Speed: 500 Time: 10 Spin Speed: 4000 Time: 60 Seconds Comments: Facility: UT NF
9 Soft Bake Substrate ID: OXSC-14 Tool: UT Digital Hotplate Temperature: 115 C
94 Time: 1 Minute Comments: Facility: UT NF
10 Lithography to Pattern Electrodes Substrate ID: OXSC-14 Photoesist: S1813 Tool: UT Mask Aligner Mask: UT Etch Mask Intensity: 20 mW/cm^2 Time: 10 seconds Comments: Cover part of wafer for lower contact Facility: UT NF
11 Develop Photoresist Substrate ID: OXSC-14 Developer: MF319 Time: 1 minute and 30 seconds Comments: Facility: UT NF
12 Hard Bake Substrate ID: OXSC-14 Tool: UT Digital Hotplate Temperature: 115 C Time: 1 Minute Comments: Facility: UT NF
13 Metal Etching Substrate ID: OXSC-14 Etchant: Copper Etchant Time: 18 seconds Comments: Facility: UT NF
14 Photoresist Removal Substrate ID: OXSC-14 Remover: PG Remover Time: 1 Minute Comments: Facility: UT NF
95 Appendix B
B. Characterization of ZnO Thin Films on FTO Coated Glass Substrates
Below are the summarized results of the detailed quality inspection and electrical
characterization of CVD (chemical vapor deposition) deposited FTO/ZnO thin films.
(Received from Pilkington North America). These ZnO films will eventually be used for
several applications, one of which is as the HRT (highly resistive transparent) layer in solar
cells. The purpose of this investigation was to determine the uniformity and quality of the
films, using electrical measurements. As part of this study, other methods of quality control
were investigated. These include in situ kelvin probe testing and ellipsometry. Literature
review of these methods suggested that they could possibly be implemented in a
commercial laboratory for simple in-line quality control. The received glass sheets were
coated completely with FTO, a small portion of each sheet was covered during ZnO
deposition to ensure an electrical contact point to the FTO (bottom electrode). Pictures of
the original samples are shown in figure(s) B-1 and B-2.
96 B.1 Summary of Samples
Table B-1:
97
Figure B-1: Pictures of samples. TEC15 glass sheets coated in FTO and then ZnO. PNA- 6, PNA,-7, PNA-2, PNA-5 are shown.
Figure B-2: Pictures of samples. TEC15 glass sheets coated in FTO and then ZnO. PNA- 1, PNA,-3, PNA-4 are shown.
98 B.2 Test Setup and Measurement Detail
Two different measurement structures were used for this characterization. These are shown in detail in figure B-3 and B-4. These two measurement structures allow for the capture of the vertical and horizontal electrical transport properties. Tungsten square contacts were deposited on pieces of the glass cut from the sheets mentioned above. The samples were tested inside a Lake Shore cryogenic TTP4 probe station. Electrical characterization was done using a Keithley 4200 Semiconductor Characterization System
(SCS) equipped with an ultra-fast 4225 Pulse Modulation Unit (PMU). These are shown in figure B-3.
Figure B-3: a) Keithley 4200 Semiconductor Characterization System and b) a Lake Shore Cyogenic Probe Station.
Smaller more manageable pieces of glass were cut from the slabs shown above.
These pieces were ~ 1” x 1” and 2” x 2” in size. Metal square contacts were deposited on pieces of the glass cut from the sheets mentioned above. These contacts are labeled in sets, each set including devices ranging from 500um x 500um to 10um x 10 um. The sets are
99 referred to as TFT set1, set2 etc. Each piece of glass had at least one full metal contact TFT set deposited. The devices tested are mentioned in the corresponding figures.
Figure B-4: Schematic diagram showing the arrangement of the metal contacts used for electrical characterization.
Figure B-5: TLM or transfer length measurement allows you to measure various length (contact separation) resistors with different square contacts. The resistance values are plotted against the resistor length, and a line is fit and extrapolated to a resistor of zero length. The result will be twice the contact resistance.
100
Figure B-6: Vertical current transport characteristics can be captured by depositing metal contacts on the ZnO and then measuring the IV characteristics between this point and the FTO bottom electrode.
Current Density 50um device average Current Density 100 um device average Current Density 200 um device average
2 107
1.5 107
1 107
5 106
0
Current (A) Current -5 106
-1 107
-1.5 107 -8 106-6 106-4 106-2 106 0 2 1064 1066 1068 106 Voltage (V)
Figure B-7: J vs. E plots for 3 contact sizes of 300nm thick ZnO, plots of this type are used to generate the variability maps below.
The equations for conductivity are shown low in equation B.1
퐼 퐽 ⁄퐴 푑퐽 ∴ = 푉 , 퐽 = 휎퐸 → 휎 = (B.1) 퐸 ⁄푑 푑퐸
J is the current density, I the current, E the electric field, and is the electrical conductivity.
101 B.3 Planar (Horizontal) Electrical Characteristics
TLM results: TLM results: 2 Contact Size =(100um)2 Contact Size =(100um) devices, t =300nm sample devices, t =20nm sample ZnO ZnO 40 18
35 17
30 16
25 15
R (ohms) R
R (ohms) R
20 14
15 13 0 50 100 150 200 250 0 50 100 150 200 250 Length (um) Length (um)
TLM results: Contact Size =(100um)2 devices, t =70nm sample 20 ZnO
19 y = 14.789 + 0.020151x R2= 0.62404
y = 13.994 + 0.025597x R2= 0.90917 18
17
R (ohms) R 16
15
14 0 50 100 150 200 250 Length (um)
Figure B-8: TLM results for three thicknesses of ZnO, 300nm, 70nm and 20nm. As described in figure B-5. The contact resistance can be extracted from the value of the y- intercept.
The shape of the curve yielded for the t=300nm is not suitable to a contact resistance extraction. The values extracted from t=70nm and t= 20nm are Rc20=6.899 ohm/square and Rc70=6.997 ohm/square respectively. The slightly higher contact resistance for the
70nm sample is expected, as the ZnO layer will be more insulating than the FTO, a thicker layer will limit horizontal current transport to a greater extent.
102 B.4 Variability Mapping Using Vertical Conductance Measurements
Plots of the current density vs. electric field are used to generate 3D maps of the conductivity across the sample. The samples were cleaned using a warm water (~50 C) wash in Micro-90 (ultrasonicated 10min), followed by DI water rinse and finally by an
Acetone rinse. The bottom electrode was exposed using an RIE (reactive ion etching) dry etch. This was necessary to make contact to the FTO on sample pieces that did not have this area left exposed during initial CVD deposition of the ZnO layer. Blanket Tungsten top electrodes were deposited using RF sputtering. Photolithography was used to define top electrodes.
Figure B-9: Average IV curves for 200um x 200um, 100um x 100um and 50um x 50 um devices. Spacing (contact separation) is 200um and 100um. The conductivity is extracted from the slope of these curves to generate the plots shown below. These IV curves are for 300nm ZnO, similar curves were generated for other thicknesses. 103 Conductivity (ohm*m)-1 Conductivity as a function of device area 2 1.9944
-1 1.5
1
0.52380 0.5
Conductivity (ohm*m) Conductivity 0.13424 0 0 1 104 2 104 3 104 4 104 5 104 Device Area (um2)
Figure B-10: Conductivity varies as a function of device area, this implies that the contact resistance is affecting the measurement somewhat, this will not alter the description of variability but should be mentioned.
The variability across the sample is mapped below. Additionally the average conductivity, standard deviation, percentage variation across the sample are tabulated in table B-2.
104 0.02
0.015
0.01
0.005
d10 d2 d3 d4 d5 d6 d7 d8 Br2 d9 Tr2 d10 Br1 Tr1
0-0.005 0.005-0.01 0.01-0.015 0.015-0.02
Figure B-11: 3D variability map of 300nm sample - 50 um devices-set2
Br2
Tr2
Br1
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
0-0.005 0.005-0.01 0.01-0.015 0.015-0.02
Figure B-12: 2D variability map of 300nm sample - 50 um devices-set2 105 0.02
0.015
0.01
0.005
0 d1 d2 d3 d4 d5 d6 Br2 d7 d8 Tr2 d9 Br1 d10Tr1
0-0.005 0.005-0.01 0.01-0.015 0.015-0.02
Figure B-13: 3D variability map of 300nm sample - 100 um devices-set2
Br2
Tr2
Br1
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
0-0.005 0.005-0.01 0.01-0.015 0.015-0.02
Figure B-14: 2D variability map of 300nm sample - 100 um devices-set
106 0.019 0.018 0.017 0.016 0.015 0.014d1 d2 d3 d4 d5 d6 d7 d8 d9 Br2 Tr2 d10 Br1 Tr1
0.014-0.015 0.015-0.016 0.016-0.017 0.017-0.018 0.018-0.019
Figure B-15: 3D variability map of 300nm sample - 200 um devices-set2
Br2
Tr2
Br1
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
0.014-0.015 0.015-0.016 0.016-0.017 0.017-0.018 0.018-0.019
Figure B-16: 2D variability map of 300nm sample - 200 um devices-set2 107 0.01
0.008
0.006 0.008-0.01 0.004 0.006-0.008 0.002 0.004-0.006
0 0.002-0.004 d1 0-0.002 d2 d3 d4 d5 d6 d7 Br2 d8 Br1 d9 Tr2 d10Tr1
Figure B-17: 3D variability map of 200nm sample - 50 um devices-set2
Br2
Br1 0.008-0.01 0.006-0.008 Tr20.004-0.006 0.002-0.004 0-0.002 Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
Figure B-18: 2D variability map of 200nm sample - 50 um devices-set2 108
0.015
0.01
0.005
0 d1 d2 d3 d4 d5 d6 Br2 d7 d8 Br1 0.01-0.015 0.005-0.01 0-0.005 d9 Tr2 d10Tr1
Figure B-19: 3D variability map of 200nm sample - 100 um devices-set2
Br2
Br1
Tr2
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
0-0.005 0.005-0.01 0.01-0.015
Figure B-20: 2D variability map of 200nm sample - 100 um devices-set2 109 0.015
0.01
0.005 0.01-0.015 0.005-0.01 0 0-0.005 d1 d2 d3 d4 d5 d6 d7 Br2 d8 Br1 d9 Tr2 d10Tr1
Figure B-21: 3D variability map of 200nm sample - 200 um devices-set2
Br2
Br1
Tr2
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
0.01-0.015 0.005-0.01 0-0.005
Figure B-22: 2D variability map of 200nm sample - 200 um devices-set2
110
Figure B-23: 3D variability map of 70nm sample - 50 um devices-set2
Figure B-24: 2D variability map of 70nm sample - 50 um devices-set2 111
Figure B-25: 3D variability map of 70nm sample - 100 um devices-set2
Figure B-26: 2D variability map of 70nm sample - 100 um devices-set2
112
Figure B-27: 3D variability map of 70nm sample - 200 um devices-set2
Figure B-28: 3D variability map of 70nm sample -200 um devices-set2
113 0.019 0.018 0.017 0.018-0.019 0.016 0.017-0.018 0.015 0.016-0.017 0.014 0.015-0.016 d1 0.014-0.015 d2 d3 d4 d5 d6 Br1 d7 d8 d9 Tr1 d10
Figure B-29: 3D variability map of 20nm sample - 50 um x 50um devices-set2
Br2
Br10.018-0.019 0.017-0.018 0.016-0.017 Tr2 0.015-0.016 0.014-0.015 Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
Figure B-30: 2D variability map of 20nm sample - 50 um x 50um devices-set2
114 0.019
0.018
0.017 0.016 0.015 0.014d1 d2 d3 d4 d5 0.018-0.019 d6 0.017-0.018 d7 0.016-0.017 d8 0.015-0.016 d9 Br2 0.014-0.015 Br1 d10 Tr2 Tr1
Figure B-31: 3D variability map of 20nm sample - 100 um x 100um devices-set
Br2
0.018-0.019 Br1 0.017-0.018 0.016-0.017 Tr2 0.015-0.016 0.014-0.015 Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
Figure B-32: 2D variability map of 20nm sample - 100 um x 100um devices-set2
115 0.015-0.02 0.02 0.01-0.015 0.015
0.01 0.005-0.01 0.005 0-0.005 0 d1 d2 d3 d4 d5 d6 Br1 d7 d8 d9 Tr1 d10
Figure B-33: 3D variability map of 20nm sample - 200 um x 200um devices-set2
Br2
Br1 0.015-0.02 0.01-0.015 Tr2 0.005-0.01 0-0.005
Tr1 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10
Figure B-34: 2D variability map of 20nm sample - 200 um x 200um devices-set2
116 Table B-2: Parameters extracted from variability maps for 20nm, 70nm and 300nm thick ZnO.
Device Size 50um x 50um 100um x 100um 200um x 200um Average 0.01580103 0.014694109 0.017382425 Median 0.01597 0.017354 0.017489 Standard 0.00085763 0.005275635 0.000646788 Deviation Ave. std. 0.00068602 0.003761042 0.000538461
Maximum 18.27% 199.9998224 13.33875796 Variation:
Percentage ≈18.3 % ≈ 200% ≈ 13.3% difference
300 nm thick ZnO Device Size 50um x 50um 100um x 100um 200um x 200um Average 0.0218075 0.0216975 0.02107 Median 0.0222 0.0218 0.0214 Standard 0.00162613 0.000567264 0.000882072 Deviation Ave. std. 0.00079725 0.000398125 0.0005105
Percentage 53.93% 14.70% 21.21% difference
70nm thick ZnO Device Size 50um x 50um 100um x 100um 200um x 200um Average 0.01769515 0.01746765 0.01590862 Median 0.0177225 0.017572 0.0170735 Standard 0.00058417 0.00065404 0.003378 Deviation Ave. std. 0.0004879 0.00049427 0.00283143
Percentage 13.856149 15.7743703 81.0817671 difference 20nm thick ZnO
117