eZ80190 eZ80 Webserver

PB005203-0501 Product Brief

Product Block Diagram • Operating Temperature: – Standard Temperature Range: 0ºC to +70ºC – Extended Temperature Range: –40ºC to +105ºC WDT 50-MHz eZ80 CPU • Debug Interface (ZDI) 6 PRT Bus Controller

ZDI General Description 32-Bit GPIO 2 UZI The eZ80190 Webserver is a high-speed, opti- 2 DMA mized pipeline architecture , oper- ating at 50MHz. It is the first in a line of new eZ80- Multiply- based standard products targeted toward embed- Accumulator ded Internet applications. with 1KB 8KB RAM CS, WSG Dual-Port The eZ80 is one of the fastest 8-bit CPUs available RAM today, executing code four times faster than a stan- dard Z80 operating at the same clock speed. In addition, the eZ80 Webserver includes a high-per- Features formance Multiply-Accumulator, ideal for signal processing. Single-cycle instruction fetch, high-performance • The eZ80 can operate in Z80-compatible (64 KB) eZ80 CPU core mode, or full 24-bit (16 MB) addressing mode. • 16x16-bit Multiply and 40-bit Accumulate with 1- Considering both the increased clock speed and KB dual-port SRAM processor efficiency, the eZ80’s processing power • Four Chip Selects with individual Wait State rivals the performance of 16-bit . generators eZ80 Core • Six Counter/Timers with prescalers The eZ80 core is an 8-bit microprocessor that per- • Watch-Dog Timer forms in either a 16- or 24-bit addressing mode. • 2-channel DMA controller The eZ80 improves on the world-famous Z80 • 8-KB high-speed data SRAM architecture. Like the Z80, it features dual bank • 2 Universal ZiLOG Interface (UZI) channels registers for fast context switching. (I2C, SPI, UART) with built-in Baud Rate Gener- ator eZ80190 Peripheral Description • Fixed-priority vectored interrupts (32 external, Universal ZiLOG Interface (UZI) 11 internal) Each of the two UZI devices contains three serial • 32 bits of General-Purpose I/O communication controller blocks (SPI, UART, and I2C) along with control registers and a Baud Rate • On-chip oscillator Generator (BRG). Only one of the serial devices is • 3.0–3.6V supply voltage with 5V tolerant inputs active at any time. • 100-pin LQFP package • The Baud Rate Generator provides a lower fre- • Up to 50-MHz clock speed quency clock from the system clock. This mod-

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ule consists of a 16-bit counter, two 8-bit preload start, stop, restart to continue, or restart from an registers and associated decoding logic. initial value. • The UART module implements all the logic Watch-Dog Timer (WDT) required to support asynchronous communica- The WDT features four programmable time-out tions. The module also contains 16-byte deep periods: 218, 222, 225, 227 Clock Cycles. It allows FIFOs for both transmit and receive. the user to monitor the status of a time-out and • The SPI is a synchronous interface allowing generate a RESET or Non-Maskable Interrupt. several SPI-type devices to be interconnected. The SPI may be configured as either a master General Purpose Input/Output (GPIO) or a slave. There are 32 bits of General Purpose Input or Out- put. All port signals can be individually programma- • The I2C operates in four modes: Master Trans- mitter, Master Receiver, Slave Transmitter, and ble in either the Input or Output mode of operation.The 32 port bits can be used as vectored Slave Receiver. interrupt sources. The pins can be set to recognize RAM either level- or edge-triggered interrupts. On-board memory consists of 8KB x 8 general- ZiLOG Debug Interface (ZDI) purpose RAM and 1KB x 8 dual-port RAM for the Multiply-Accumulator. Both RAMs can be individu- ZDI incorporates most of the functions of an In-Cir- ally enabled or disabled and can be relocated to cuit Emulator on-chip. ZDI allows the user to single the top of any 64-KB page. step code, change registers, edit programs, and view status of internal registers. DMA Controller On-Chip Crystal Oscillator The DMA controller can be used for direct mem- ory-to-memory data transfers without CPU inter- The eZ80 Webserver features an on-chip crystal vention. There are two DMA channels, channel 0 oscillator that supplies clocks to both the internal and channel 1. Each channel features independent eZ80 CPU core and peripherals and to an external registers. Transfers can be either in burst mode or pin. The clock circuitry uses three dedicated pins: . X and Φ (PHI). cycle-steal mode. XIN OUT Multiply-Accumulator Chip Select/Wait State Generator The Multiply-Accumulator on the eZ80 Webserver There are four chip selects for external devices. performs DSP functions without incurring the over- Each chip select may be programed for either head associated with a separate DSP. memory or I/O space. Each memory chip select can be individually programmed on a 64-KB Features include: boundary. The I/O chip selects can choose a 16- • A 16x16-bit multiplier feeds 32-bit product into byte section of I/O space. Each chip select may be one input of the adder. The other input of the programmed for up to seven wait states. adder is fed from one of two 40-bit accumula- Programmable Reload Timers tors. The eZ80 Webserver features six Programmable • Two dual-port RAMs called X and Y. One port of Reloadable Counter Timers (PRT). Each timer is a each RAM is 16-bit Read-Only and supplies one 16-bit down counter and offers a 4-bit clock pres- side of the multiplier. The second port is 8-bit caler with four selectable taps for CLK ÷ 2, Read/Write RAM, and is connected to the micro- CLK ÷ 4, CLK ÷ 8 and CLK ÷ 16. The timers’ two processor bus. This connection allows RAM to modes of operation are single-pass and continu- simultaneously be part of the multiprocessor’s ous count mode. The timer can be programmed to memory space and constitute the X and Y banks of the Multiply-Accumulator.

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• A set of registers in the microprocessor's I/O culation, and retrieves the resulting accumula- space start the Multiply-Accumulator, determine tion. Software can provide calculation when the Multiply-Accumulator completes a cal- parameters to these registers.

Pin Diagram

Figure 1. eZ80190 100-Pin LQFP Pin Configuration DD IN OUT DD Φ BUSREQ GND V PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BUSACK X X GND V PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/SS0/CTS0 PD2/SCK0/RTS0 PD1/MOSI0/RxD0/SDA0 PD0/MISO0/TxD0/SCL0

75 TEST 90 80 76

MREQ 100 1 PC7/RI1 WR PC6/DCD1 RD PC5/DSR1 CS0 PC4/DTR1 CS1 70 PC3/SS1/CTS1 CS2 PC2/SCK1/RTS1 CS3 PC1/MOSI1/RxD1/SDA1 V DD PC0/MISO1/TxD1/SCL1 GND GND A0 10 V A1 DD PB7 A2 100-Pin LQFP PB6 A3 eZ80 Webserver PB5 A4 PB4 A5 60 PB3 A6 PB2 A7 PB1 V DD PB0 GND ZDA A8 20 ZCL A9 RESET A10 IORQ A11 INSTRD A12 HALT A13 25 51 26 30 40 50 D0 D1 D2 D3 D4 D5 D6 D7 DD DD DD A16 A17 A18 A19 A20 A21 A22 A23 A14 A15 NMI V V V GND GND GND

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Block Diagram

Figure 2. eZ80 Webserver Block Diagram

1K Byte MACC Dual-Port Multiply MACC Accumulator SRAM

UZI BUSACK Universal ZiLOG Interface BUSREQ (2) INSTRD Bus Controller IORQ I2C MREQ SCL0/1 Serial RD Interface SDA0/1 (2) WR DATA[7:0] 8K Byte General HALT SCK0/1 SPI Purpose NMI Serial eZ80 SS0/1 SRAM Peripheral CPU RESET MISO0/1 Interface TEST (2) MOSI0/1 ZDI Two-Channel ZiLOG ZCL DMA Debug Interface ZDA

ADDR[23:0] Controller CTS0/1

DCD0/1 Interrupt CS0 Chip Select Vector DSR0/1 UART [7:0] & CS1 Universal DTR0/1 Asynchronous Wait State Interrupt CS2 Receiver/ Generator Controller RI0/1 Transmitter CS3 (2) RTS0/1 DATA[7:0] RXD0/1

TXD0/1 ADDR[23:0]

WDT GPIO Crystal Programmable Watch-Dog General Oscillator Reload Purpose & Timer I/O Port System Clock Timer/Counter (4) Generator (6) Φ IN X OUT X PA[7:0] PB[7:0] PC[7:0] PD[7:0]

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Electrical Features Summary • Evaluation board • Power supply: 3.3V ± 300 mV • Embedded Internet Software Suite including TCP/IP stack • Standard temperature: 0ºC to 70ºC • Real Time • Extended temperature: –40ºC to +105ºC • C-Compiler Support Tools • ZiLOG Development Suite (ZDS) including assembler, linker, debugger, and simulator The following development tools are available to program and debug the eZ80 Webserver device:

Related Products Other Integrated Controllers of interest are:

Z84C00 Z80™ CPU (up to 20 MHz) Z84C15 Z80 CPU, 2 SIO, 4x8 CTC, 2 PIO, WDT, up to 16MHz clock speed Z80S180™ Improved Z80 CPU, 1-MB MMU, 2 DMA, 2 16-bit PRTs, 2 UARTs, CSIO, up to 33-MHz clock speed Z80181 Z8S180 CPU, SCC, CTC, 16-bit GPIO, up to 33-MHz clock speed Z80182 Z8S180 CPU, 2 ESCC, 24-bit GPIO, 16550 Mimic interface, up to 33-MHz clock speed Z80L183 Z8S180 CPU, 8x10-bit A/D, 10-bit D/A, WDT, 1-KB Boot ROM, 2-KB SRAM, 1-MB MMU, 2 CSIO, 2 UARTs, 2 DMA, 32-bit GPIO, up to 33-MHz clock speed, Embedded Internet software suite Z80S183 Z8S180 CPU, 8x10-bit A/D, 10-bit D/A, WDT, 1-KB Boot ROM, 2-KB SRAM, 1-MB MMU, 2 CSIO, 2 UARTs, 2 DMA, 32-bit GPIO, up to 33-MHz clock speed, Embedded Internet software suite

Ordering Information

Part PSI Description eZ80190AZ050SC 50 MHz, Standard Temperature eZ80 Webserver eZ80190AZ050EC 50 MHz, Extended Temperature eZ80 Webserver

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appearing in the ZiLOG, Inc. Terms and Conditions of ZiLOG, Inc. Sale. ZiLOG, Inc. makes no warranty of merchantability 910 East Hamilton Avenue, Suite 110 or fitness for any purpose Except with the express Campbell, CA 95008 written approval of ZiLOG, use of information, devices, Telephone: (408) 558-8500 or technology as critical components of life support FAX: (408) 58-8300 systems is not authorized. No licenses are conveyed, Internet: www.ZiLOG.com implicitly or otherwise, by this document under any intellectual property rights.

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