EDA Vendor Support

This document describes the EDA environments that Actel Actel’s Alliance Partners supports. This document also covers each of the Actel’s Alliance program was established to assist EDA Actel-supported vendors. Within each vendor’s tool set the vendors in providing support for Actel FPGAs. The Alliance features will be described that are supported by Actel. Also program provides early technical information on new Actel listed are the software and computer requirements for releases to all partners so they can offer timely support. integrating Designer Series with the EDA front-end tools. Table 1 lists the complete set of EDA vendors that support 2 the design of Actel FPGAs. Table 1 • Alliance Program EDA Vendors

Company Contact Address Acugen J. W. Brooks (603) 881-8821 427-3 Amherst St., Suite 391, Nashua, NH 03063 Aldec Stanley Hyduke (805) 499-6867 3525 Old Conejo Road, Suite 111 Newbury Park, CA 91320 Cadence Itzhak Shapira (408) 944-7734 2655 Seely Road, Bldg. 6, San Jose, CA 95134 Compass John Goldsworthy 1865 Lundy Ave., San Jose, CA 95131 (408) 383-4720 ext. 52931 Escalade Mark Miller (408) 481-1300 2475 Augustine Dr., 2nd Floor, Santa Clara, CA 95054 Exemplar Logic Mary Murphy (510) 337-3785 815 Atlantic Ave., Suite 105, Alameda, CA 94501-2274 Intergraph Will Wong (415) 691-6447 381 East Evelyn Avenue, Mountain View, CA 94041 Isdata Ralph Remme 49 721 751087 Daimlerstr. 51, Karlsruhe, D-76185, Germany IST Gabriele Saucier 33 76 574687 Europole, 4 Place Robert Schuman 38024 Grenoble Cedex 1, France Logic Modeling Marnie McCollow (503) 531-2412 19500 N.W. Gibbs Drive, Beaverton, OR 97006 (Synopsys) Logical Devices David Motarjemi (305) 974-0967 1201 N.W. 65th Place, Ft. Lauderdale, FL 33309 Mentor Graphics Sam Picken (503) 685-1298 8005 S.W. Boeckman Road, Wilsonville, OR 97070-7777 Minc Wayne Merrill (719) 590-1155 6755 Earl Drive, Colorado Springs, CO 80918 OrCAD Troy Scott (503) 671-9500 9300 S.W. Nimbus, Beaverton, OR 97005 Quad Design Hector Lai (805) 988-8250 1385 Del Norte Road, Camarillo, CA 93010 Simucad John Williamson (415) 487-9700 32970 Alvarado-Niles Rd., Suite 744, Union City, CA 94587 Synario Design Dave Kohlmeiyer (206) 867-6802 10525 Willows Road N.E., Redmond, WA 98073-9746 Automation Synopsys Lynn Fiance (415) 694-4289 700 East Middlefield Road, Mountain View, CA 94043 Synplicity Alisa Yaffa (415) 961-4962 465 Fairchild Dr., Suite 115, Mountain View, CA 94043 Teradyne Bill Loring (617) 422-2769 179 Lincoln St., M/S L50, Boston, MA 02111 Veda Design Automation Rastgow Shale (408) 496-4518 2041 Mission College Blvd., Suite 259 (formerly Genrad) Santa Clara, CA 95054 Viewlogic Dave Orecchio (508) 480-0881 293 Boston Post Road, Marlboro, MA 01752 Zuken Dwight Dagenais (408) 562-0177 3945 Freedom Circle, Suite 1100, Santa Clara, CA 95054

April 1996 2-17 © 1996 Actel Corporation

Designer Series for Cadence Design Systems

Concept Concept Synergy RapidSIM Verilog, RapidSIM Leapfrog EDA Tools

ACTgen Compile ACTmap

Pin Editor Layout DirectTime ChipEdit Standard/DirectTime Editor

DT Analyzer & Back Annotation Designer Series Development System

Actel Actel Data I/O Activator 2 Activator 2s Programmers Programmers

Figure 1 • The Cadence EDA Environment The Designer Series Development System for the Cadence then simulated with unit delays to verify the design Design Systems environment (see Figure 1) allows FPGAs functionally before running place and route. After place and with from 1,000 to 30,000 gates to be designed with Cadence’s route, actual module and net delays are backannotated to the Concept (Logic Workbench) or Composer schematic capture netlist for timing simulation. Actel’s DirectTime Analyzer is tools. Designer Series provides libraries that support the used to perform static timing analysis on a design— design of ACT 1, the Integrator Series, and the Accelerator identifying critical path delays and performance deltas Series families of FPGAs. In addition, Designer Series relative to design specifications. Once the implementation provides ACTmap VHDL Synthesis (a complete VHDL has met all timing requirements, the design can be synthesis and logic optimization tool) and ACTgen Macro programmed into an FPGA. Builder, which creates complex logic functions to match Actel’s optional DirectTime Layout feature can be added to user-specified parameters. the basic Designer Series Cadence interface. DirectTime For Cadence, Designer Series supports the following Layout supports specification-driven design. With DirectTime combinations of schematic capture and simulation: Layout, the system clock frequency or delay constraints for • Composer and Verilog XL individual signals can be entered. After Actel’s standard place-and-route algorithm is executed, the results are shown • Concept and RapidSIM in the DirectTime Analyzer. DirectTime Analyzer displays a • Concept and Verilog comparison between required versus actual delays. These design flows allow schematics to be created using DirectTime Layout can typically improve design performance Composer or Concept. Designer Series products include by an amount equivalent to the next fastest speed grade. It netlisters that convert Composer or Concept schematics into makes performance-runtime trade-offs during placement and a netlist format that Designer Series can accept. The netlist is routing to achieve the requested timing.

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EDA Vendor Support

If the results of standard layout are substantially slower than The Designer Series Development System for Cadence the required timing, more aggressive measures are needed. provides a tight link between Cadence’s suite of design The designer has the option of moving to a faster-speed-grade capture and analysis tools and Actel’s FPGA implementation FPGA or even to a faster family. DirectTime Analyzer makes software. The integration of Designer Series with the these decisions easy by clearly showing whether the target Cadence tools provides a design environment that delivers performance is reached and showing the distance between high-performance, high-capacity FPGA solutions quickly. target and achieved when target is missed. Combining the Actel architecture with powerful There are many high-level design solutions that support Actel place-and-route software provides short turnaround time for in the Cadence environment. Cadence’s Synergy and PIC ECNs. Designer Series makes it easy to include custom logic Designer products as well as Synopsys’s Design and FPGA in any product. Compilers all work within the Cadence environment. Sun SPARC or HP 700 Synthesized blocks in any of these synthesis tools can be combined with schematics to support mixed-level design Hardware Requirements 2 definition. Cadence provides Actel libraries for the PIC • 64 MB RAM Designer and Synergy synthesis products. Actel’s Synopsys • 125 MB DISK (executables), 5 MB DISK (per design) synthesis libraries can be added to the Designer Series Development System to support Synopsys synthesis in the • CD-ROM drive Cadence environment. Actel also makes available Verilog and Software Requirements VITAL VHDL libraries so that designs captured in these • Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or languages can be simulated directly with Verilog XL or later Leapfrog. • Version 9404 or later

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Designer Series for Mentor Graphics

Design Architect Autologic QuickSim II QuickVHDL EDA Tools

ACTgen Compile ACTmap

Pin Editor Layout DirectTime ChipEdit Standard/DirectTime Editor

DT Analyzer & Back Annotation Designer Series Development System

Actel Actel Data I/O Activator 2 Activator 2s Programmers Programmers

Figure 2 • The Mentor Graphics EDA Environment The Designer Series Development System for the Mentor Actel’s optional DirectTime Layout feature can be added to Graphics environment (see Figure 2) allows FPGAs with from the basic Designer Series Mentor Graphics interface. 1,000 to 30,000 gates to be designed with Mentor Graphics’ DirectTime Layout supports specification-driven design. With Design Architect. Designer Series provides libraries that DirectTime Layout, the system clock frequency and delay support the design of ACT 1, the Integrator Series, and the constraints for individual signals can be entered. After Actel’s Accelerator Series families of FPGAs. In addition, Designer standard place-and-route algorithm is executed, the results Series provides ACTmap VHDL Synthesis (a complete VHDL are shown in DirectTime Analyzer. DirectTime Analyzer synthesis and logic optimization tool) and ACTgen Macro displays a comparison between required versus actual delays. Builder, which creates complex logic functions to match DirectTime Layout can typically improve design performance user-specified parameters. by an amount equivalent to the next fastest speed grade. It The design flow for Mentor Graphics allows schematics to be makes performance-runtime trade-offs during placement and entered using Design Architect. Designer Series products routing to achieve the requested timing. include netlisters that convert Design Architect schematics If the results of standard layout are substantially slower than into EDIF, which Designer Series can accept. The netlist is the required timing, more aggressive measures are needed. then simulated with unit delays to verify the design The designer has the option of moving to a faster-speed-grade functionally before running place and route. After place and FPGA or even to a faster family. DirectTime Analyzer makes route, actual module and net delays can be backannotated to these decisions easy by clearly showing whether the target the netlist for timing simulation. Actel’s DirectTime Analyzer performance is reached and showing the distance between can be used to perform static timing analysis on a design— target and achieved when target is missed. identifying critical path delays and performance deltas There are many high-level design solutions that support Actel relative to design specifications. Once the implementation in the Mentor Graphics environment. Mentor Graphics’ has met all timing requirements, the design can be Autologic and Autologic II products as well as Synopsys’s programmed into an FPGA. Design and FPGA Compilers all work within the Mentor

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EDA Vendor Support

Graphics environment. Synthesized blocks in any of these Sun SPARC or HP 700 synthesis tools can be combined with schematics to support Hardware Requirements mixed-level design definition. Mentor Graphics provides the Actel libraries for Autologic synthesis products. Actel’s • 64 MB RAM Synopsys synthesis libraries can be added to the Designer • 125 MB DISK (executables), 5 MB DISK (per design) Series Development System to support Synopsys synthesis in • CD-ROM drive the Mentor Graphics environment. Actel also makes available Verilog and VITAL VHDL libraries so that designs captured in Software Requirements these languages can be simulated directly with QuickSim or • Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or QuickVHDL. later The Designer Series Development System for Mentor • Version 8.2_5 or later (A.1 recommended) Graphics provides a tight link between the Mentor Graphics suite of design capture and analysis tools and Actel’s FPGA 2 implementation software. The integration of Designer Series with the Mentor Graphics tools provides a design environment that delivers high-performance, high-capacity FPGA solutions quickly. Combining the Actel architecture with powerful place-and-route software provides short turnaround time for ECNs. Designer Series makes it easy to include custom logic in any product.

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Designer Series for Viewlogic

PRO Series PowerView

PRO Capture ViewDraw ViewSyn PRO Sim ViewSim SpeedWave EDA Tools

ACTgen Compile ACTmap

Pin Editor Layout DirectTime ChipEdit Standard/DirectTime Editor

DT Analyzer & Back Annotation Designer Series Development System

Actel Actel Data I/O Activator 2 Activator 2s Programmers Programmers

Figure 3 • The Viewlogic EDA Environment The Designer Series Development System for the Viewlogic timing simulation. Actel’s DirectTime Analyzer is used to environment (see Figure 3) allows FPGAs with from 1,000 to perform static timing analysis on a design—identifying 30,000 gates to be designed with Viewlogic’s Workview Office critical path delays and performance deltas relative to design or PowerView tools. Designer Series provides libraries that specifications. Once the implementation has met all timing support the design of ACT 1, the Integrator Series, and the requirements, the design can be programmed into an FPGA. Accelerator Series families of FPGAs. In addition, Designer Actel’s optional DirectTime Layout feature can be added to Series provides ACTmap VHDL Synthesis (a complete VHDL the basic Designer Series Viewlogic interface. DirectTime synthesis and logic optimization tool) and ACTgen Macro Layout supports specification-driven design. With DirectTime Builder, which creates complex logic functions to match Layout, the system clock frequency and delay constraints for user-specified parameters. individual signals can be entered. After Actel’s standard For Viewlogic, Designer Series supports the following place-and-route algorithm is executed, the results are shown workstation-product combinations: in DirectTime Analyzer. DirectTime Analyzer displays a • 486 and Pentium PCs: Workview Office comparison between required versus actual delays. DirectTime Layout can typically improve design performance • HP 700 and Sun workstations: PowerView by an amount equivalent to the next fastest speed grade. It These design flows allow schematics to be created using makes performance-runtime trade-offs during placement and PowerView on the workstations or Workview Office on the PC. routing to achieve the requested timing. The Designer Series products include netlisters that convert If the results of standard layout are substantially slower than PowerView or Workview Office schematics into an EDIF the required timing, more aggressive measures are needed. netlist that Designer Series can accept. The netlist is then The designer has the option of moving to a faster-speed-grade simulated with unit delays to verify the design functionally FPGA or even to a faster family. DirectTime Analyzer makes before running place and route. After place and route, actual these decisions easy by clearly showing whether the target module and net delays are backannotated to the netlist for

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EDA Vendor Support performance is reached and showing the distance between 486 or Pentium PC target and achieved when target is missed. Hardware Requirements There are many high-level design solutions that support Actel • VGA, EGA graphics card in the Viewlogic environment. Viewlogic’s ViewSynthesis as well as Synopsys’s Design and FPGA Compilers all work • 32 MB RAM within the Viewlogic environment. Synthesized blocks in any • 60 MB virtual disk of these synthesis tools can be combined with schematics to • 70 MB DISK (executables), 5 MB DISK (per design) support mixed-level design definition. Viewlogic provides Actel libraries for the ViewSynthesis product. Actel’s • CD-ROM drive Synopsys synthesis libraries can be added to the Designer Software Requirements Series Development System to support Synopsys synthesis in • Windows 3.1 or later, Windows NT 3.5.1 or later, the Viewlogic environments. Actel also makes available Windows 95 Verilog and VITAL VHDL libraries so that designs captured in 2 these languages can be simulated directly with Chronologic • PROSeries 6.1 or later or Speedwave. • Workview Office 7.1 or later The Designer Series Development System for Viewlogic Sun SPARC or HP 700 provides a tight link between Viewlogic’s suite of design capture and analysis tools and Actel’s FPGA implementation Hardware Requirements software. The integration of Designer Series with the • 64 MB RAM Viewlogic tools provides a design environment that delivers • 125 MB DISK (executables), 5 MB DISK (per design) high-performance, high-capacity FPGA solutions quickly. Combining the Actel architecture with powerful • CD-ROM drive place-and-route software provides short turnaround time for Software Requirements ECNs. Designer Series makes it easy to include custom logic in any product. • Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or later • PowerView 5.3 or later

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Designer Series for Synopsys

Synopsys Verilog HDL/VHDL Synthesis EDA Tools

ACTgen Compile ACTmap

Pin Editor Layout DirectTime ChipEdit Standard/DirectTime Editor

DT Analyzer & Back Annotation Designer Series Development System

Actel Actel Data I/O Activator 2 Activator 2s Programmers Programmers

Figure 4 • The Synopsys EDA Environment The Synopsys libraries support synthesis of Actel FPGAs from multiplexer-based, flip-flop-oriented FPGA architecture. The Verilog HDL or VHDL. (See Figure 4.) Support for synthesis, combination of Synopsys’s optimizations for Actel FPGAs and DesignWare, and VHDL System Simulator (VSS) is included. the optimized DesignWare logic elements generates designs The Synopsys libraries provide a complete top-down design that are typically within 5 percent of what can be achieved by solution. Actel FPGA designs can be compiled with either the laborious handcrafting. Design Compiler or the FPGA Compiler, with the FPGA Simulation of the design with its surrounding test bench can Compiler yielding more efficient, high-performance FPGA be accomplished by using VSS and Actel’s VHDL libraries for implementations. Synopsys or by using any Verilog simulator and the separately The combination of Actel’s fine-grain, routing-resource-rich available Verilog libraries. Both the Verilog and VHDL architecture and Synopsys’s powerful synthesis program simulation libraries support preroute functional simulation to delivers high-performance, high-capacity FPGAs. The verify the design’s functionality and accurate postroute Synopsys libraries allow designs to be efficiently mapped to timing simulation with backannotated (using SDF) actual the Actel architecture, taking complete advantage of all delays. Timing simulation can be performed with best-case, possible logic module functions. Design implementation worst-case, or typical delays to account for variations in efficiency is enhanced by the DesignWare library, which voltage, process, and temperature. This accurate timing contains Actel-optimized adders, counters, multiplexers, simulation can identify areas in which timing error is causing registers, and so on. These logic elements all can be a design to malfunction. instantiated into a high-level design description. Adders, The Synopsys libraries support many of the FPGA-specific comparators, and subtracters can be inferred from arithmetic architectural feature, such as ACT 3’s complex I/O cells, operators that are used in the behavioral description. 1200XL’s wide-decode feature, and 3200DX’s quad-clock and Synopsys has included Actel-specific optimization, such as embedded RAM features. Synopsys’s support of architectural sequential mapping, which takes full advantage of the specialties allows designers to maximize FPGA performance

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EDA Vendor Support and usefulness by synthesizing a design that includes Sun SPARC or HP 700 high-speed FIFOs or dual-port RAMs in a 32200DX device, or Hardware Requirements by targeting the I/O flip-flops of the ACT 3 family to locate a high-speed counter right on a data bus. • 64 MB RAM The DesignWare libraries provide a strong advantage in the • 125 MB DISK (executables), 5 MB DISK (per design) design of Actel FPGAs. Actel provides a synthetic library in • CD-ROM drive DesignWare, which includes commonly used functions such as accumulators, adders, comparators, counters, decoders, Software Requirements multiplexers, and registers up to 32 bits wide. Each logic • Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or function can be created with a designer-selected later combination of control signals. By taking advantage of the • Synopsys 3.2b or later synthetic library, the VHDL or Verilog code can be fine-tuned for optimal Actel implementation. These libraries are based 2 upon Actel’s ACTgen Macro Builder parameterized macro generator, which allows designers to achieve performance comparable to schematic-drawn macros. DesignWare elements can be instantiated into the code or inferred by the compilers, resulting in an extremely efficient design process.

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