Virtutech Simics

Jakob Engblom, PhD Business Development Manager Virtutech [email protected] Our Technology

9Full system simulation – Networking, backplanes – System-level from the beginning 9Runs complete software stack – Firmware, device drivers, OS, etc… , PhD 9Very high performance – Typically 100s of MIPS – Multiple GIPS top benchmark

Development Simics Model Virtual Development Hardware Platform

RAM Device RAM Device

CPU FLASH CPU FLASH RA M Device RAM Device

CPU FLASH CPU FLASH

Device Device Device Device Device Device Device Device Enet DSP Enet Backplane

Enet DSP Enet

Backplane

User program

Server DB Middleware Complete production Operating system software Drivers Firmware

Application Service Capability Application Servers Simulated Service hardware MSC HSS GMSC/Transit CS MGCF Control CF SGSN Media Connectivity Media Gateway Gateway/S G PSTN/ BSC Backbone ISDN GSM/ Switches/Routers EDGEBTS GGSN Internet User dataIntranets WCDMA RNC CPP AXD RBS Control AXE TSP WPP

Identical build The software can’t Runs binaries tools chain tell the difference from real target

User program

Server DB Middleware Complete production Operating system software Drivers Firmware

CPU Simulated Network hardware Bus Disk net CPU

PCI LCD RAM FLASH

I2C Timer ROM ASIC Hardware

bash/web server

Montavista Linux

Ebony PPC440GP Card

ebony0: 10.10.0.50 Simics Network Simulation bash shell

Montavista Linux VxWorks

Artesyn PMPPC 750 Card Ebony PPC440GP Card orange0: 10.10.0.51 ebony1: 10.10.0.70 Simics

HostHost OS: operatingWindows systemXP (32-bit)

HostHost: hardware PC

TooToo abstractabstract toto provideprovide informationinformation onon actualactual targettarget behaviorbehavior Service API (Java library) NotNot samesame binariesbinaries asas Operating System API Standard (POSIX) targettarget

HW/SWHW/SW Operating system API (VxSim) interfaceinterface

Functional instruction-set Abstraction Stable & narrow Stable & narrow & device behavior interface,interface, enablesenables fastfast simulationsimulation Cycle-accurate instruction-set ExcessiveExcessive details gives details gives Timing-correct cycle-level (SystemC) veryvery slowslow simulationsimulation Implementation-level (VHDL/Verilog)

AllAll softwaresoftware:: arbitraryarbitrary & & unmodified.unmodified. SameSame asas onon aa User program realreal system.system.

Target operating system ArbitraryArbitrary;; currentlycurrently supportssupports Alpha,Alpha, AMD64,AMD64, ARM,ARM, IA64,IA64, MIPS,MIPS, Simulated target hardware PowerPC,PowerPC, Sparc,Sparc, x86,x86, TITI C6400,C6400, msp430msp430 Simics

Linux,Linux, Solaris,Solaris, Host operating system WindowsWindows

Host hardware PCPC (32-(32- & & 64-bit)64-bit) oror SparcSparc

• Instruction-set simulation (ISS) • Complete and correct processor functionality – All instructions semantics bit-correct vs real machine – Supervisor-mode & user-mode – Runs the complete target instruction set • Including Altivec, SSE, 3dNow, VIS, etc. extensions – All accessible values represented • User-level registers • Supervisor-level registers • Model-specific registers, ASIs, debug register, etc. • Memory-management unit • Timing abstracted – Add details if required

• Hardware modeled as a set of devices – Memory map of machine (as seen by processor) – At the programming register level • Model the program-visible behavior – Configuration registers – Control register – Data transmitted & received • Transaction-level modeling – Reads, writes, DMA transfers, network packets • ASICs & FPGAs – Model programming interface behavior – Not detailed implementation • Detailed timing can be added if required

• Boards/machines: – Single processor – Multiprocessor – Shared memory, local memories • Backplane/interconnect: – Network (ATM, Ethernet, FibreChannel, ...) – Shared memory • System level: – Multiple boards and machines – Heterogeneous processors, boards, machines • Scalability: – Always allows 64-bit memory space – Simulation can be distributed

9/22/2005 Copyright © 1998-2005 Virtutech, All rights reserved. CONFIDENTIAL 11 Network Simulation with SimicsSimulatedSimulated network network of of simulatedsimulated machines: machines: nono topologicaltopological relationrelation toto thethe SimulatedSimulated physicalphysical network network machines,machines, oneone or or moremore per per hosthost machinemachine

InterfaceInterface toto realreal network:network: mixmix simulatedsimulated & & realreal machinesmachines

Real network of physical machines

• Globally synchronized timing – Across processors – Across machines – Across the network – One processor stops Æ all stop • Correct relative speed – 500 MHz processor will execute 10 times more instructions than a 50 MHz processor, in the same time • Virtualized & controlled time – Insulated from external time – Time does not advance when simulation is stopped – Slower or faster than real world time – Global across the simulated network

• Telecomms Switch – Multiple processor types – ATM Backplane • PowerQUICC II • PowerPC 750 – 10+ different card types • PowerPC 405 • Control cards • TI C64 DSP • Compute cards – Multiple network types • Line cards • ATM, Ethernet, Serial • Timer units • Multimedia cards – 20+ cards in a rack

PPC PPC PPC atm PQ asic FLASH PPC PPC PPC Card Card ControlCard Compute LineCard Card

Rack Backplane

• Aerospace board – Single processor • PowerPC 750gx PPC – Integrated system unit ser mem RAM • Memory controller • Ethernet network eth PCI FLASH • Serial ports •PCI Board – On-board memory • FLASH •RAM

– PCI/X connections PPC – VxWorks, in-house OS ser mem RAM – Multiple cards networked eth PCI FLASH Board

TargetTarget

consoleconsole Shell

Montavista Linux 2.1

Ebony PPC440GP Board

Simics SimicsSimics Host OS:operating Windows system XP consoleconsole HostHost: hardware PC

Date and Time

Windows NT 4.0

Pentium 4 PC + Voodoo3 GPU

Simics SimicsSimics Host OS:operating Windows system XP consoleconsole HostHost: hardware PC

9/22/2005 Copyright © 1998-2005 Virtutech, All rights reserved. CONFIDENTIAL 20 9/22/2005 Copyright © 1998-2005 Virtutech, All rights reserved. CONFIDENTIAL 21 Simics in the CompSys Course Virtual MIPS Computer

• Processor •Memory •Serial port •LCD

RAM

Serial port MIPS 4kc CPU Malta LCD

mips-simple board • Simpler than most real-world boards = easy to program • Runs on Sparc workstations & PCs

• Counter – Built into the MIPS processor – Use for periodic interrupts •Serial port – Use for text input and output – Interrupt-driven use mandatory • Malta LCD – Output-only, use for fun features •Memory – Used to store your code – 8 MB default, should be plenty

• Checkpointing – Store current state; pick up and continue later – Position workload once, use many times – Distribute a system state to multiple developers

• Determinism – Same initial state gives same execution – Repeat the same execution any number of times – Investigate a problem time after time – Add instrumentation and reexecute

• Visibility (insight without intrusion) – All state can be observed • And used to set breakpoints – All events can be traced and logged • Including interrupts, status register changes, ... – Input and output visible • Log activity, trace accesses, break on IO

• Controllability – Any part of machine or state can be changed – Fault injection

• Virtual time – Time is completely virtual – Machine does not run away

• Backwards debugging – Roll back execution to previous state – Step backwards in time – Reverse breakpoints – Set bookmarks in time

• Going forwards: any debugger

• Back up and find out what happened: Hindsight

Go forward again Backup

The main path

Take a different path

Backup

The main path

Programs Superficially,Superficially, thethe simulatedsimulated hardware hardware isis whatwhat you you getget withwith SimicsSimics Target Operating System

Standard Custom Processors Devices Devices

Simics

Programs InfrastructureInfrastructure & & genericgeneric featuresfeatures applicableapplicable to to allall targets,targets, thethe resultresult of of Target Operating System manymany years years of of developmentdevelopment Standard Custom Processors Devices Devices

Multiprocessor Checkpointing Proven API Tracing

Multimachine Determinism Scripting Profiling

Advanced Large Memories Visibility Events Breakpoints Configuration Distribution CLI Symbolic debug handling 32/64-bit & endian Networking GUI Hindsight handling Simics

IP-basedIP-based User program connectionconnection Debugger Target operating system

gdb Target hardware server Simics Simics FullyFully externalexternal toto Host operatingHost OS system thethe targettarget hardware:hardware: notnot visiblevisible inin targettarget Host hardware

SerialSerial consoleconsole Shell Student OS

Simple MIPS machine

Simics SimicsSimics Host OS:operating Windows system XP consoleconsole HostHost: hardware PC

• Serial port activity logging • Hindsight

• LCD activity logging • Starting & stopping

• IO trace, break • Console scripting, programmed input • Exception trace, break

• Control register trace, break

• Used in Erik Hagersten’s research group • Runs on all machines at MIC

• Current: Simics 1.6, 2.0, 2.2 installed

• Simics 3.0 will be installed in time for the course – This is what you will be using – Includes Hindsight backwards debugger – Awaiting final release from Virtutech

• Simics is offered to academia for free • Academia gets the full Simics tool, all targets

• Personal licenses – Free, renewable yearly – Node-locked to a single computer –Obtainvia www.simics.net • Site licenses – Free – 10000 licenses baseline, floating – Much cheaper than buying specialized hardware labs