Logic Synthesis for Ambipolar Fets Luca Gaetano Amaru´ LSI & TCL, I&C, EPFL
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EDIC RESEARCH PROPOSAL 1 Logic Synthesis for Ambipolar FETs Luca Gaetano Amaru´ LSI & TCL, I&C, EPFL Abstract— Double-Independent-Gate (DIG) Field Effect Transistors carbon nanotubes [1], graphene [2] and silicon nanowires [3]. Tunable (FETs) are expected to extend Moore’s law in the coming years. Many polarity DIG FETs, commonly referred to as ambipolar transistors, emerging technologies present the possibility to have DIG FETs with can be in-field configured as p-type or n-type applying a specific one gate controlling online the device polarity. Such devices are called ambipolar transistors and efficiently embed the XOR function. Logic voltage on the additional gate, usually called the Polarity Gate gates based on ambipolar transistors can implement more complex logic (PG). The Conventional Gate (CG) instead controls the ambipolar functions with less physical resources than conventional Complementary transistor’s on-state as in usual unipolar FETs. Fig.1(a) summarizes Metal Oxide Semiconductor (CMOS) gates. However, most of the state- the in-field configuration of the ambipolar transistor’s polarity. of-art logic design and synthesis methods have been developed expressly for CMOS technology and may miss some optimization opportunity if directly employed for ambipolar technology. This motivates us to propose new methods, or adapt existing ones, for automated logic synthesis A A’ targeting ambipolar transistors. In this report, we first present design techniques for logic gates D B’ B based on ambipolar devices. Then, we introduce logic optimization CG D Y and technology mapping methods, originally proposed for CMOS, that PG=1 S A A’ are also of interest for ambipolar technology. Finally, we present our CG PG=0 D B B’ proposal for an efficient logic synthesis methodology targeting ambipolar PG S transistors. CG Index Terms—Logic synthesis, Design automation, DG transistor, S Tunable polarity (a) (b) I. INTRODUCTION Fig. 1: (a) Ambipolar FETs polarity control (b) XOR-2 gate in [4]. OVING toward Multiple-Independent-Gate (MIG) Field Effect M Transistors (FETs) is a promising alternative to rejuvenate Ambipolar transistor’s on-state is logical biconditional (XNOR) Moore’s law. With respect to single-gate FET, MIG FET offers on both gates values. For this reason, ambipolar transistors enable an improved design flexibility: each gate separately influences the a compact realization of the XOR function, such as the XOR-2 electrical characteristics of the device. Among controllable device gate depicted by Fig.1(b). Moreover, negative unate functions (e.g. characteristics, device polarity has recently drawn researchers interest NAND/NOR) have the same efficient implementation with ambipolar due to the possibility to achieve denser logic circuits. To this end, transistors as in the well established Complementary Metal Oxide Double-Independent-Gate (DIG) FETs with tunable polarity have Semiconductor (CMOS) technology. Indeed, ambipolar transistors been proposed in many emerging nano-scale technologies, such as can behave as unipolar FETs fixing the voltage on the PG. In summary, ambipolar devices are efficient to implement both neg- Proposal submitted to committee: September 4th, 2012; Candidacy ative unate (NAND/NOR) and binate (XOR/XNOR) logic functions exam date: September 11th, 2012; Candidacy exam committee: Yusuf thanks to the in-field configuration of the device polarity. However, Lebleblici, Giovanni De Micheli, Andreas Burg, David Atienza taking full advantage of controllable ambipolarity in automated logic Alonso. synthesis involves several challenges. First, logic optimization is This research plan has been approved: usually carried out with heuristics that, for pragmatic reasons, target only one type of functions. Then, traditional library-based technology mapping methods restrict the design flexibility (due to the limited Date: ———————————— size of the standard-cell library) missing efficient complex gates implementations offered by ambipolar transistors. A logic synthesis methodology capable of exploiting ambipolar transistors potentiality Doctoral candidate: ———————————— must overcome the aforementioned limitations while maintaining a (name and signature) tractable computational complexity. In this report, we will first discuss three papers of interest for logic Thesis director: ———————————— design and synthesis of circuits based on ambipolar transistors. The (name and signature) first paper, [4], describes circuit level methods to design ambipolar logic gates. The second paper, [5], highlights the limitations of state-of-art synthesis tools to deal with XORs and propose selective Thesis co-director: ———————————— XOR rewriting heuristics to reduce the circuit delay. The last paper, (if applicable) (name and signature) [6], presents two efficient library-free technology mapping methods targeting static CMOS and mixed static CMOS/Pass Transistor Logic (PTL) circuits. After these three papers survey, we present Doct. prog. director: ———————————— our proposal for an efficient logic synthesis methodology targeting (R. Urbanke) (signature) ambipolar transistors. The remainder of this report is organized as follows. Section II EDIC-ru/05.05.2009 summarizes the work in [4] on ambipolar logic gate design. In section EDIC RESEARCH PROPOSAL 2 III, we review the work in [5] on selective XOR expansion to min- imize circuit delay. Section IV describes the library-free technology mapping approach in [6]. We present our research proposal in Section V. We conclude the paper in Section VI. II. AMBIPOLAR LOGIC GATES DESIGN Double-gate controllable ambipolar Carbon NanoTube (CNT) FETs are capable to implement complex functions, embedding the XOR operation, with low physical resources. The work in [4] exploits this opportunity to achieve denser and faster logic circuits. For this purpose, the authors provide guidelines to design logic gates based on controllable ambipolar CNTFETs. In order to evaluate the advantage of combinational circuits realized with such gates, the authors defined an efficient library of ambipolar logic gates (ambipolar library) employable in a standard synthesis flow. Circuits synthesized with the ambipolar library are then compared to their standard unipolar implementation in terms of area, speed and power consumption. In this section, we briefly describe the design methods introduced in [4] and we summarize the results achieved. Fig. 3: Static and pseudo logic style implementations of (A ⊕ B)· C A. Logic Design with Controllable Ambipolar Devices with ambipolar transistors [4]. Static and pseudo logic styles are considered in [4] to design am- bipolar logic gates. In static style, complementary Pull-Up Network (PUN) and Pull-Down Network (PDN) enable full-voltage swing 3) Transistor Sizing: In CNTFETs, holes and electrons mobility logic provided that p-type devices are present only in the PUN while is equal. Therefore, devices in the PUN and PDN are equally sized. n-type devices are used only in the PDN. In pseudo style, the PUN Considered this, successive CNTFETs area sizing to equalize gate is replaced by a single p-type pull-up device weakly biased in order rise and fall times as an unit inverter follows standard rules as in [7]. to allow the output signal to fall within the tolerated margin. Pseudo 4) TG vs. PT Ambipolar Logic: Transmission gate logic has style is preferred to static style when gate area is more critical than several advantages compared to the pass-transistor approach. First, power consumption. TG logic does not require an output buffer, or inverter, saving one The XNOR function is implemented with a single ambipolar device delay stage. Then, the transistor sizing operation is more critical with as shown by Fig. 1(a), but, depending on the input values, the pass-transistor style than with transmission-gates, due to the possible polarity can be n or p. This causes a signal degradation if such p or n type configuration of ambipolar devices in PDN or PUN, device is used in the PUN or PDN. In order to achieve full-voltage respectively. Indeed, CNTFETs acting as controllable ambipolar PTs swing logic, authors in [4] propose to replace each ambipolar device must be oversized (about double the standard area) to equalize gate implementing the XNOR, or XOR, function with a Transmission rise and fall times as an unit inverter. On the other hand, with TGs the Gate (TG) composed by two parallel ambipolar devices fed with sizing operation is far less dramatical thanks to the parallel of p and complementary signals. In this way, any voltage level is passed n type configured ambipolar transistors. For this reason, ambipolar without signal degradation, as depicted by Fig. 2. TG logic has been proved in [4] to be superior to ambipolar PT logic, despite the additional circuitry needed to generate inverted signals. B. Ambipolar Library In [4], a library of 46 logic gates with no more than 3 series stacked ambipolar or unipolar CNTFETs is employed to synthesize multi- level logic benchmarks. Table I summarizes the proposed library (ambipolar library). Note that if the ambipolar library is implemented Fig. 2: Transmission Gate based on ambipolar transistors [4]. using transmission-gate logic, it is possible to swap signals with different polarities applied to the TGs and achieve more functions 1) Transmission-Gate Logic: The use of ambipolar TGs permits to utilizing the same resources. For example, considering the TG-based design compact full-voltage swing logic gates. However, complemen- realization of (A ⊕ B)· C in Fig. 3, it is possible