Issue 7 Issue EDITION

VYBRID Bits Rich applications time in real Vybrid Controller Controller Vybrid Solutions Beyond

Freescale Semiconductor, Inc. Beyond Bits — VYBRID® EDITION Issue 7

Vybrid Family Overview 4 Vybrid Controller Solutions 8 Vybrid VF3xx Family 10 Vybrid VF5xx Family 12 Vybrid VF6xx Family Technical Highlights 15 Core Technology 18 Multicore Communication 20 Multimedia Subsystem 23 Security Subsystem 25 Power Management 27 Ethernet Subsystem 29 USB Subsystem 31 Memory Subsystem 35 Universal Asynchronous Receiver/Transmitter Software and Development Tools 38 Freescale Virtual Hardware Platform 40 Freescale MQX™ Software Solutions 44 Freescale Tower System 46 Swell PEG Product Line 47 Timesys LinuxLink 48 ARM® Development Studio 5 (DS-5) 50 IAR Embedded Workbench 52 Atollic 53 Multilink and Cyclone 54 SEGGER: J-Link and Flasher 55 SEGGER: RTOS, GUI and Middleware 56 Lauterbach

Table of Contents Table of Contents Vybrid Family of Products Vybrid Controller Solutions

Vybrid Controller Solutions A multicore platform solution

The increasing complexity and Vybrid Portfolio Key Attributes demands of embedded systems creates greater need for sophisticated human-machine interfaces (HMI) and multiple connectivity options Total Unprecedented with safe, secure and predictable System System operation. To concurrently provide Solution Integration rich HMI and real-time control means bringing together two very different system paradigms. For example, HMI computation focuses on efficiently processing pixels and displaying them on a screen, while guaranteed determinism requires highly predictable response times for tasks. A traditional systems-level solution for Optimal such divergent needs would combine Low-Power System different pieces of silicon, such as Process Performance an applications MPU and a real-time MCU, on a board. It would also require developing software and a protocol to Rich Apps in Real Time enable simultaneous communication between real-time control and rich HMI. Application developers face a tremendous challenge of seamlessly integrating these diverse technologies in a single system. Our Vybrid portfolio brings to market This, along with a communication a unique, low-power system solution API between the rich domain and the that provides customers a way real-time domain and a tool chain to combine applications requiring that eases debug of such systems, rich human-machine interfaces dramatically shortens customer time and connectivity with real-time to revenue. The families in the Vybrid determinism. The Vybrid portfolio portfolio span entry-level products for enables customers to create systems customers who want to upgrade from that concurrently run a high-level the Kinetis MCU to devices with large operating system such as Linux® on-chip SRAM, up to highly integrated, and a real-time operating system dual-core solutions intended to serve such as MQX on the same device. industrial markets.

4 Beyond Bits Vybrid Edition

VybridVybrid Family Family Details Details For tasks that need predictable interrupt management, for example, a typical need for real-time applications, the Vybrid platform has the ARM® Vybrid Cortex™-M4 core with a Nested Families Vector Interrupt Controller (NVIC) External Bus DDR Camera Interface Video ADC USB Host w/PHY USB OTG w/PHY Segment LCD TFT LCD Ethernet Controller L2 Switch Security (HAB, Det.) Tamper, while allowing graphical applications VF6xx Family [Heterogenous Dual Core] and connectivity stacks to be run ARM Cortex-A5 up to 500 MHz 22 Y on the ARM Cortex-A5 applications ARM Cortex-M4 up to 167 MHz processor. 364-pin MAPBGA Software can be segmented so that VF5xx Family tasks that need predictable latencies ARM Cortex-A5 up to 500 MHz 2 Y can be run on the ARM Cortex-M4 364-pin MAPBGA core and computer intensive processes VF3xx Family run on the ARM Cortex-A5 core. ARM Cortex-A5 up to 266 MHz Y 2 176-pin LQFP Total System Solution Vybrid devices take a total system Common Platform, Analog and Digital Tools approach. Complementing the low- CRC and TZ Address power silicon is a reference Linux BSP, 12-bit ADC Space Controllers a full-featured MQX RTOS, reference Packaged IDE I2C 12-bit DAC MQX BSP and a processor-to- processor communication API that lets Programmable Secure JTAG customers partition their code between Delay Block Packaged OS the ARM Cortex-A5 (e.g., running Flash Controller Secure Fuses and Multicore Linux) and ARM Cortex-M4 (e.g., Communication API running MQX) to implement the lowest UARTs Timers power solution for their application Application Software demands. In addition, customers Secure RAM Low-Voltage, Ind. Protocols, have access to industry-leading IDE Low-Power Multiple Peripheral Drivers tool chains such as ARM DS-5™ Operating Modes, eSDHC Clock Gating and IAR. A selection of connectivity, (1.73V–3.6V) motor control, LCD, security stacks DMA Third-Party and drivers is also available. Vybrid Ecosystem Support ESAI SRAM devices are supported by Freescale’s Tower System, offering the flexibility to easily scale and expand customer Scalable and Compatible Cortex™-A9 core, while also providing designs based on market need. Tower across Multiple Cores scalable devices that can address the Systems allow rapid prototyping in a needs of a market that demands critical development platform that maximizes Vybrid devices have a dual-core safety and security, connectivity and hardware reuse and speeds time to architecture that combines the ARM rich HMI in the same piece of silicon. market. Cortex-A5 application processor and the ARM Cortex-M4 for real-time One of the key benefits of the Vybrid control. The Vybrid portfolio is designed architecture that combines the to be compatible with Kinetis MCUs ARM Cortex-A5 core with the ARM featuring the ARM Cortex-M4 core and Cortex-M4 core is the partitioning of the i.MX 6 series featuring the ARM tasks based on their characteristics.

freescale.com/Vybrid 5 Vybrid Family

Process Technology Node Comparison ARM Cortex-M4 Core The ARM Cortex-M4 core retains all the Technology Node advantages of the ARM Cortex-M3 core with an NVIC which gives deterministic interrupt handling capability demanded by real-time applications. The ARM Cortex-M4 adds digital signal processing capability in the form of DSP and SIMD instruction extensions, a single cycle MAC unit and single precision FPU. In addition, Freescale has added a direct memory access (DMA) controller, crossbar switch, L1 on-chip cache memories and tightly coupled memories (TCM) which maximize processor performance and bus bandwidth.

Communication Interfaces Vybrid devices feature a number of 90LP 65LP 55LP 40LP connectivity peripherals, including dual USB 2.0 (Low-, Full- and High- Active Power Standby Power Speed Speed) device/host/On-The-Go with integrated PHYs, dual 10/100 Low-Power Process Unprecedented System Ethernet with Layer 2 Ethernet switch with IEEE® 1588 hardware One of the critical foundational pieces Integration time stamping and reduced media of the Vybrid platform is its low-power The Vybrid platform has an independent interface (RMII) support process technology. The devices in this unprecedented level of system for real-time industrial control. Multiple portfolio are fabricated in the 40 nm integration for a solution of its class. serial interfaces include UARTs with low-power process. The static leakage The centerpiece is the core complex support for ISO7816 SIM/smart cards, of the 40 nm LP process is 2x less featuring the ARM Cortex-A5 and SPI and I2C, while dual CAN modules than 65 nm and almost 3x less than 90 ARM Cortex-M4 cores. enable industrial network bridging. nm. This enables more integration for a given power envelope thus dissipating ARM Cortex-A5 Core Support for External Peripherals much less power for the same device. The ARM Cortex-A5 processor is a and Memory high-performance, low-power core In addition to having up to 1.5 MB with an L1 and L2 cache subsystem of on-chip SRAM for speedy code that provides full virtual memory and data execution, Vybrid devices capabilities, double precision floating- can interface to a variety of external point unit (FPU) and the NEON media peripherals and memories for system processing engine. It is intended expansion and data storage. Dual- as an upgrade for the ARM9® and quad SPI interfaces with execute-in- ARM11® cores and is architecturally place (XiP) support can interface with compatible with Cortex-A9. The the latest flash memory to offer up to ARM Cortex-A5 also has TrustZone® 160 MB/s of throughput. This allows Technology for creating secure for a very powerful single-chip solution applications. when the large DDR memory sizes are not required. A secure digital host controller supports SD, SDIO, MMC

6 Beyond Bits Vybrid Edition

or CE-ATA cards for in-application Reliability, Safety and Security Optimal System software upgrades, media files or Vybrid devices include a variety of Performance adding Wi-Fi® support. For interfacing data integrity and security hardware Vybrid devices are ideal for modern to external peripherals such as features for safeguarding memory, industrial applications that require external SRAM, EEPROM and other communication and system data. higher integration of communication peripherals, a FlexBus external bus A cyclic redundancy check module and connectivity interfaces, as well as interface is provided. NAND flash and is available for validating memory HMI and UI acceleration. Customers DRAM controllers with ECC support contents and communication can easily take full advantage of all allow connection to a wide variety of data, while a memory protection the integrated Vybrid features to memory types for critical applications. unit provides data protection and create differentiated products by Battery-backed RAM is critical for increased software reliability. For leveraging the provided reference secure systems to store authentication failsafe applications, an independently board support packages (BSP) for keys; Vybrid devices provide 16 KB clocked watchdog offers protection high-level operating systems (such of secure RAM. The platform also against runaway code. When it comes as Linux) and real-time operating provides 96 KB ROM used for high to security, a hardware encryption systems (such as MQX), which assurance boot (HAB). unit supports several encryption include libraries and media framework and hashing algorithms for program tuned to the silicon architecture. Multimedia Options validation as well as authentication The combination of high-efficiency The Vybrid platform offers a host and securing data for transfer and silicon design, low-leakage process of multimedia options enabling storage. The system security module technology and software tuned for customers to run rich applications with includes a unique chip identifier, the silicon architecture results in real-time control. secure key storage and a hardware low power consumption, eliminating tamper detection system. The tamper Audio the need for a fan or heat sink and detection system has integrated Three different types of audio helping to lower overall system BOM sensors for voltage, frequency, interfaces are supported: synchronous cost. As an example, because the temperature and external sensing for audio interface (SAI) for full-duplex platform architecture partitions tasks physical attack detection. audio transfer, enhanced serial audio between the applications processor interface (ESAI) that is also full duplex and the deterministic MCU, the ARM and adds support for interfacing with Cortex-M4 core helps to improve SPDIF transceivers and the Sony/ efficiency in industrial motor control Philips Digital Interface (SPDIF) for applications which can result in a digital audio support. reduced carbon footprint.

Display Controller Two independent display controller units (DCU) interface with TFT LCD displays. The DCU can drive LCD displays up to a resolution of XGA (1024x768). Also included is a segment LCD controller.

Video Interface Unit (VIU) For image and vision capture, a VIU provides a 24-bit parallel interface for digital video. In addition, an optional video ADC will convert composite video into digital format.

freescale.com/Vybrid 7 Vybrid Family

Vybrid VF3xx Family ARM Cortex-A5, 1.5 MB SRAM, display, security, dual Ethernet with L2 switch

The VF3xx family is the entry Vybrid VF3xx Family Vybrid V300 Block Diagram point into the Vybrid portfolio Debug and Trace System Core Analog and features the ARM JTAG AMBA NIC 12-bit ADC x2 ARM® Cortex™-A5 Trace Internal and Up to 266 MHz 12-bit DAC x2 Cortex-A5 core. It provides External Watchdog PLL Interrupt Timers DP-FPU an efficient solution for an Router FlexTimer (8-ch.) Clocks applications processor with DMA NEON FlexTimer (2-ch.) Up to 64-ch. Clock Monitors FlexTimer (2-ch.) up to 1.5 MB of on-chip Power Management L1 I/D Cache Internal Reference ® Regulators IEEE 1588 Timers Clocks Trace/Debug SRAM and a rich suite of Periodic Interrupt Timers Memory Protection Low/High Frequency communication, connectivity Low-Power Timers Unit GIC Oscillators and human-machine Memory Display Security (Optional) Communication interfaces (HMI). Boot ROM TFT LCD Crypytography Module UART x4 CAN x2 Tamper Detect 1.5 MB SRAM Segment LCD DSPI x3 I2C x2 Target Applications Secure RTC IEEE 1588 Memory Interfaces Video 10/100 Ethernet x2 Secure RTIC • Industrial automation NAND Flash Digital Video L2 Switch Controller Camera Interface Secure RAM Applications requiring simple USB OTG + PHY Quad Audio Secure Fuses LS/FS/HS SPI x2 2D graphics (HMI) ASRC SDHC x1 Secure WDOG SAI x3 External Bus 125 GPIO • Industrial scanners and printers Interface ESAI Secure JTAG (with Interrupt) • Large or high-quality small appliances • Portable patient monitors Memory Performance • Simple vending machines • Dual quad SPI supporting a double • ARM Cortex-A5 core running at 266 data rate interface, an enhanced MHz, with double precision floating Mixed-Signal Capability read data buffering scheme, XiP and point, NEON media processing • Two 12-bit ADCs with configurable support for dual-die flashes engine for acceleration of media and resolution. Single or differential • Boot ROM with optional high signal processing, and TrustZone output mode operation for improved assurance boot for secure booting security extensions. 32 KB each of noise rejection. 500 ns conversion capability instruction and data L1 cache and 512 KB L2 cache for optimized time achievable with programmable • Up to 1.5 MB on-chip SRAM with bus bandwidth and on-chip SRAM delay block triggering ECC support on 512 KB execution performance • Two 12-bit DACs for analog waveform generation for audio • Up to 64-channel DMA for applications or peripheral and memory servicing sensor manipulation with reduced CPU loading and faster system throughput • Crossbar switch enables concurrent multi-master bus accesses, increasing bus bandwidth

8 Beyond Bits Vybrid Edition

Timing and Control • Four UARTs with IrDA support, • Real-time integrity checker • Three FlexTimers with a total of including two UART with ISO7816 Periodic check on system 12 channels. Hardware dead-time smart card support. Variety of data memory for unauthorized insertion and quadrature decoding size, format and transmission/ modifications for motor control reception settings supported for • Secure non-volatile storage multiple industrial communication • Four-channel 32-bit periodic Secure non-rollover real-time protocols interrupt timer provides time base counter for RTOS task scheduler or trigger • Two CAN modules for industrial Non-rollover monotonic counter source for ADC conversion and network bridging Zeroizable 256-bit secret key 2 programmable delay block • Three DSPI and two I C interfaces External Peripheral Support HMI Reliability, Safety and • Secure digital host controller supports SD, SDIO, MMC or • TFT LCD display capable of Security CE-ATA cards for in-application WQVGA resolution • TrustZone Address Space software upgrades, media files or • 288 segment LCD controller Controllers provide memory adding Wi-Fi® support protection for all masters on the Multimedia crossbar switch, increasing software • NAND flash controller supports up reliability to 32-bit ECC current and future • Video interface unit with parallel NAND types. ECC management • Cyclic redundancy check engine camera support for 8- and 10-bit handled in hardware, minimizing validates memory contents and ITU656 video, up to 24-bit digital software overhead communication data, increasing RGB system reliability • FlexBus external bus interface • Three synchronous audio provides glueless interface options • Independent clocked COP guards interfaces implementing full- to memories and peripherals such against clock skew or code runaway duplex serial interfaces with frame as graphics displays. Supports up 2 for fail-safe applications such as synchronization such as I S, AC97 to four chip selects the IEC 60730 safety standard for and CODEC/DSP interfaces household appliances • Optional enhanced serial audio Software and Tools • External watchdog monitor drives interface that provides a full-duplex • Freescale Tower System hardware output pin to safe state external serial port for communication with development environment with components if watchdog event a variety of serial devices, including complimentary MQX BSP occurs industry-standard codecs, SPDIF • Integrated development transceivers and other processors Optional Secure environments • Asynchronous sample rate converter Application Support Green Hills MULTI IDE for rate conversion between 32, ARM Development Studio 5 • Cryptography acceleration and 44.1, 48 and 96 kHz (DS-5) assurance module Atollic TrueSTUDIO Connectivity and Supports acceleration and IAR Embedded Workbench Communications off-loading for selected crypto algorithms such as AES, DES, • Runtime software and RTOS • USB 2.0 OTG controller with 3 DES, ArcFour Symmetric key Motor control libraries integrated high-speed PHY blog ciphers Green Hills INTEGRITY • 10/100 Ethernet controllers with • Random number generation • Full ARM ecosystem hardware time-stamping NIST compliant SP800-90 • U-boot • Layer 2 Ethernet switch Combination of a true random number generator and a pseudo- random number generator

freescale.com/Vybrid 9 Vybrid Family

Vybrid VF5xx Family ARM Cortex-A5, DDR, 1.5 MB SRAM, display, security, dual Ethernet with L2 switch

The VF5xx family features Vybrid VF5xx Family the ARM Cortex-A5 core Faraday F500 Block Diagram with speeds up to 500 MHz Debug and Trace System Core Analog JTAG AMBA NIC 12-bit ADC x2 ® Trace ARM Cortex™-A5 with 512 KB L2 cache, dual Internal and Up to 500 MHz 12-bit DAC x2 External Watchdog Timers PLL USB 2.0 OTG controllers Interrupt DP-FPU FlexTimer (8-ch.) Router NEON Clocks with integrated PHY, dual FlexTimer (2-ch.) DMA Up to 64-ch. Clock FlexTimer (2-ch.) L1 I/D Cache Monitors 10/100 Ethernet controllers FlexTimer (8-ch.) Power Management L2 Cache (Optional) Regulators Internal Reference IEEE® 1588 Timers Clocks with L2 switch, up to 1.5 MB Trace/Debug Periodic Interrupt Timers Memory Protection Low/High Frequency of on-chip SRAM and a rich Low–Power Timers Unit GIC Oscillators suite of communication, Memory Display Security (Optional) Communication connectivity and human- Boot ROM TFT LCD x2 Crypytography Module UART x6 CAN x2

2 machine interfaces (HMI). Up to 1.5 MB SRAM Video Tamper Detect DSPI x4 I C x4 Digital Video Secure RTC IEEE 1588 Memory Interfaces Camera Interface 10/100 Ethernet x2 The VF5xx family is pin and Secure RTIC DDR Controller L2 Switch software compatible with the Audio Secure RAM 2x USB NAND Flash Controller ASRC VF6xx family. Secure Fuses OTG + PHY SAI x4 2x Secure Digital I/O Quad SPI x2 Secure WDOG ESAI Up to 135 GPIO Target Applications External Bus Interface SPDIF Secure JTAG (with Interrupt) • Industrial automation Applications requiring simple Memory Performance 2D graphics (HMI) • Industrial scanners and printers • Dual quad SPI supporting a double • ARM Cortex-A5 core with frequency data rate interface, an enhanced up to 500 MHz, with double • Industrial vehicle control with HMI read data buffering scheme, XiP and precision floating point, NEON • Large or high-quality small support for dual-die flashes media processing engine for appliances • Boot ROM with optional high acceleration of media and signal • Metering assurance boot for secure booting processing, and TrustZone security Data concentrator capability extension. 32 KB each of instruction and data L1 cache and 512 KB L2 • Portable patient monitors • Up to 1.5 MB on-chip SRAM with cache for optimized bus bandwidth • Simple vending machines ECC support on 512 KB and on-chip SRAM execution • 16-bit DDR controller with PHY and Mixed-Signal Capability performance ECC support capable of DDR3/ • Up to 64-channel DMA for • Two 12-bit ADCs with configurable LPDDR2 800 MHz data rate resolution. Single or differential peripheral and memory servicing output mode operation for improved with reduced CPU loading and noise rejection. 500 ns conversion faster system throughput time achievable with programmable • Crossbar switch enables concurrent delay block triggering multi-master bus accesses, • Two 12-bit DACs for analog increasing bus bandwidth waveform generation for audio applications or sensor manipulation 10 Beyond Bits Vybrid Edition

Timing and Control Connectivity and • Real-time integrity checker Periodic check on system • Four FlexTimers with a total of 20 Communications memory for unauthorized channels. Hardware dead-time • Dual USB 2.0 OTG controller with modifications insertion and quadrature decoding integrated PHY • Secure non-volatile storage for motor control • Dual 10/100 Ethernet controller with Secure non-rollover real-time • Four-channel 32-bit periodic hardware time-stamping counter interrupt timer provides time base • Layer 2 Ethernet switch Non-rollover monotonic counter for RTOS task scheduler or trigger • Up to six UARTs with IrDA support, Zeroizable 256-bit secret key source for ADC conversion and including two UARTs with ISO7816 programmable delay block • Tamper detection smart card support. Variety of data Support for up to six external HMI size, format and transmission/ passive tamper detection pins reception settings supported for or five active external tamper • TFT LCD displays capable of XGA multiple industrial communication detection pin pairs resolution protocols Multimedia • Two CAN modules for industrial External Peripheral Support network bridging • Secure digital host controller • Video interface unit with parallel 2 supports SD, SDIO, MMC or camera support for 8- and • Four DSPI and four I C interfaces CE-ATA cards for in-application 10-bit ITU656 video, up to Reliability, Safety and software upgrades, media files or 24-bit digital RGB Security adding Wi-Fi® support • Up to four synchronous audio • NAND flash controller supports up interfaces implementing full- • TrustZone Address Space to 32-bit ECC current and future duplex serial interfaces with frame Controllers provide memory NAND types. ECC management synchronization such as I2S, AC97 protection for all masters on the handled in hardware, minimizing and CODEC/DSP interfaces crossbar switch, increasing software reliability software overhead • Optional enhanced serial audio • FlexBus external bus interface interface that provides a full-duplex • Cyclic redundancy check engine provides glueless interface options serial port for serial communication validates memory contents and to memories and peripherals such with a variety of serial devices, communication data, increasing as graphics displays. Supports up including industry-standard codecs, system reliability to four chip selects SPDIF transceivers and other • External watchdog monitor drives processors output pin to safe state external Software and Tools • Sony Philips Digital Interface components if watchdog event • Freescale Tower System hardware receives and transmits digital audio occurs development environment with using the IEC60958 standard Optional Secure complimentary MQX and Timesys consumer format Application Support Linux® BSPs • Asynchronous sample rate converter • Cryptography acceleration and • Integrated development for rate conversion between 32, assurance module environments 44.1, 48 and 96 kHz Supports acceleration and Green Hills MULTI IDE off-loading for selected crypto ARM Development Studio 5 (DS-5) algorithms such as AES, DES, Atollic TrueSTUDIO 3 DES, ArcFour Symmetric key IAR Embedded Workbench blog ciphers • Runtime software and RTOS • Random number generation Motor control libraries NIST compliant SP800-90 Green Hills INTEGRITY Combination of a true random • Full ARM ecosystem number generator and a pseudo- • U-boot random number generator freescale.com/Vybrid 11 Vybrid Family

Vybrid VF6xx Family ARM Cortex-A5 + Cortex-M4, DDR, 1.5 MB SRAM, display, security, dual Ethernet with L2 switch

The VF6xx is the VybridVybrid VF6xx VF6xx Block Family Diagram heterogeneous dual-core Debug and Trace Core System Core Analog family combining the ARM JTAG AMBA NIC 12-bit ADC x2 ® TM Trace ARM Cortex™-A5 ARM Cortex -M4 Up to 500 MHz Internal and Up to 167 MHz 12-bit DAC x2 Cortex-A5 and Cortex-M4 External Watchdog Timers PLL DP-FPU SP-FPU FlexTimer (8-ch.) Interrupt Router cores. It includes dual USB Clocks NEON FlexTimer (2-ch.) DMA DSP Up to 64-ch. Clock 2.0 OTG controllers with FlexTimer (2-ch.) L1 I/D Cache Monitors FlexTimer (8-ch.) Power Trace/Debug integrated PHY, dual 10/100 L2 Cache (optional) Management Internal Reference ® IEEE 1588 Timers Regulators I/D Cache Clocks Trace/Debug Periodic Interrupt Timers Memory Low/High Frequency Ethernet controllers with NVIC Low-Power Timers GIC Protection Unit Oscillators L2 switch, up to 1.5 MB of Memory Display Security (Optional) Communication on-chip SRAM and a rich Boot ROM TFT LCD x2 Crypytography Module UART x6 CAN x2

Tamper Detect DSPI x4 I2C x4 suite of communication, Up to 1.5 SRAM Video Secure RTC IEEE 1588 connectivity and human- Memory Interfaces Digital and Analog Video 10/100 Ethernet x2 Camera Interface Secure RTIC DDR Controller L2 Switch machine interfaces (HMI). Secure RAM Audio 2x USB NAND Flash Controller OTG + PHY ASRC Secure Fuses 2x Secure Digital I/O Target Applications Quad SPI x2 SAI x4 Secure WDOG ESAI Up to 135 GPIO External Bus Interface • Motor drives SPDIF Secure JTAG (with Interrupt) • Industrial pumps and fans • Power inverters • Two 12-bit DACs for analog Performance • Mobile patient care waveform generation for audio • ARM Cortex-A5 core with frequency Infusion pumps and respirators applications or sensor manipulation up to 500 MHz, with 32 KB each • Energy grid protection Memory instruction and data L1 cache and Circuit breakers, monitors and 512 KB L2 cache double precision • Dual quad SPI supporting a double hubs floating point, NEON media data rate interface, an enhanced • Infrastructure control processing engine for acceleration read data buffering scheme, XiP and Water treatment and gas pipelines of media and signal processing, and support for dual-die flashes • Building control TrustZone security extension • Boot ROM with optional high Elevator and automated doors • ARM Cortex-M4 core running up to assurance boot for secure booting • Kiosks with 2D displays 167 MHz, with 16 KB of instruction/ capability • Service robots data L1 cache plus 64 KB of tightly • Up to 1.5 MB on-chip SRAM with coupled memory, DSP support Mixed-Signal Capability ECC support on 512 KB for single cycle 32-bit MAC, single • 16-bit DDR controller with PHY and instruction multiple data extensions • Two 12-bit ADCs with configurable ECC support capable of DDR3/ and single precision floating point resolution. Single or differential LPDDR2 800 MHz data rate unit output mode operation for improved noise rejection. 500 ns conversion • Up to 64-channel DMA for time achievable with programmable peripheral and memory servicing delay block triggering with reduced CPU loading and faster system throughput

12 Beyond Bits Vybrid Edition

• Crossbar switch enables concurrent • Dual 10/100 Ethernet controller with • Real-time integrity checker multi-master bus accesses, hardware time-stamping Periodic check on system increasing bus bandwidth • Layer 2 Ethernet switch memory for unauthorized modifications Timing and Control • Up to six UARTs with IrDA support, including two UARTs with ISO7816 • Secure non-volatile storage • Four FlexTimers with a total of 20 smart card support. Variety of data Secure non-rollover real-time channels. Hardware dead-time size, format and transmission/ counter insertion and quadrature decoding reception settings supported for Non-rollover monotonic counter for motor control multiple industrial communication Zeroizable 256-bit secret key • Four-channel 32-bit periodic protocols • Tamper detection interrupt timer provides time base • Two CAN modules for industrial Support for up to six external for RTOS task scheduler or trigger network bridging passive tamper detection pins source for ADC conversion and or five active external tamper • Four DSPI and four I2C interfaces programmable delay block detection pin pairs Reliability, Safety and HMI External Peripheral Support Security • TFT LCD displays capable of up to • Secure digital host controller • TrustZone Address Space XGA resolution supports SD, SDIO, MMC or Controllers provide memory CE-ATA cards for in-application protection for all masters on the Multimedia software upgrades, media files or crossbar switch, increasing software • Digital and analog video interface adding Wi-Fi® support reliability unit with parallel camera support for • NAND flash controller supports up • Cyclic redundancy check engine 8- and 10-bit ITU656 video, to 32-bit ECC current and future validates memory contents and up to 24-bit digital RGB NAND types. ECC management communication data, increasing • Up to four synchronous audio handled in hardware, minimizing system reliability interfaces implementing full- software overhead • Independent-clocked COP guards duplex serial interfaces with frame • FlexBus external bus interface against clock skew or code runaway synchronization such as I2S, AC97 provides glueless interface options for fail-safe applications such as and CODEC/DSP interfaces to memories and peripherals such the IEC 60730 safety standard for • Optional enhanced serial audio as graphics displays. Supports up household appliances interface that provides a full-duplex to four chip selects serial port for serial communication • External watchdog monitor drives with a variety of serial devices, output pin to safe state external Software and Tools components if watchdog event including industry-standard codecs, • Freescale Tower System hardware occurs SPDIF transceivers and other development environment with processors Optional Secure complimentary MQX and Timesys ® • Sony Philips Digital Interface Application Support Linux BSPs receives and transmits digital audio • Integrated development • Cryptography acceleration and using the IEC60958 standard environments assurance module consumer format Green Hills MULTI IDE Supports acceleration and • Asynchronous sample rate converter ARM Development Studio 5 (DS-5) off-loading for selected crypto for rate conversion between 32, Atollic TrueSTUDIO algorithms such as AES, DES, 44.1, 48 and 96 kHz IAR Embedded Workbench 3 DES, ArcFour Symmetric key • Runtime software and RTOS blog ciphers Connectivity and Motor control libraries • Random number generation Communications Green Hills u-velOSity NIST compliant SP800-90 • Dual USB 2.0 OTG controller with Green Hills INTEGRITY Combination of a true random integrated PHY number generator and a pseudo- • Full ARM ecosystem random number generator • U-boot freescale.com/Vybrid 13 Technical Highlights Technical Highlights

Core Technology ARM Cortex-A5 and ARM Cortex-M4 processors

In developing a new generation, 40 nm attributes that make it the appropriate The processor architecture can also integrated 32-bit family, Freescale choice for specific embedded be configured as a uniprocessor with defined a dual-core architecture, application spaces. The Vybrid family either the ARM Cortex-A5 or the ARM combining the best features of the is ideally suited for industrial and Cortex-M4 as the operating core. industry-standard ARM Cortex-A5 general embedded applications. This application processor with the real- For markets needing a single-core solution is highly integrated, reducing time focus of an ARM Cortex-M4 applications processor in the ARM control processor. Indeed, the 32-bit system cost for the target applications. Cortex family, the ARM Cortex-A5 is Vybrid family provides rich application It includes a number of advanced the best “value” application processor capabilities with real-time control architectural features so it can support (in terms of MIPS/mW). Other key because each core has unique either MCU or MPU configurations. device components include a large

Vybrid Processor Cores and Slave Memories Block Diagram

ARM® Cortex™-A5 Core Complex ARM® Cortex™ Core Complex

Debug (ITM, ETM, ETB, CTI) NVIC FPU TPIU CM4 CPU CTI FPU + NEON FPB DWT Inst PFU and Branch Predictor AP Bus Matrix ITM ALU/Shift Q SystemBus CodeBus Mul Ld/St DAP Data uTLB Inst uTLB RAM RAM Array, 32K TCMU TCML Array, 32K

STB D-$ TLB I-$ 4 x 8K 2 x 16K Tag/Data Sys-$ Tag/Data Arrays, 2x 8K Code-$ Arrays, 2x 8K

AXI BIU Sys Code BIU BIU

64 64 64 AHB System Bus AHS Code Bus AHB Backdoor Port Tag 7

Tag 0 L2 Cache Controller 0 1 (Optional)

Data

7

64 AXI System Bus

NIC-301

OCRAM OCRAM OCRAM Boot DDRC Quad SPI _sys _sys _gfx ROM FlexBus PBRIDGE

freescale.com/Vybrid 15 Technical Highlights

on-chip RAM, display controller units, Vybrid Core Architecture Summary Comparison Quad SPI interfaces to external flash Vybrid Key memories and available RTOS. All Architecture Features ARM® Cortex™-A5 ARM Cortex™-M4 these components combine to provide Instruction set architecture ARMv7-A™ ARMv7-ME™, +-M4F (FPU) a low system cost BOM because Architecture width 32 bits 32 bits DRAM is not required. Operating frequency (2,3) x platform MHz 1x platform MHz relative to platform Target applications for single-core ARM Integer performance 1.57 DMIPS 2.1 per MHz 1.25 DMIPS 2.1 per MHz Cortex-M4/Cortex-A5 MPU devices in Microarchitecture the multi-market, general embedded • Pipeline Eight stages Three stages space include asset tracking devices, • Instruction issue Limited superscalar (ALU + Br) Single 2D scanners, point-of-sale terminals, • Execution units VFPv3 (SP + DP FPU) SPFPU NEON SIMD v7-ME (DSP + SIMD) networked audio and data acquisition. MMU, TrustZone In the industrial space, a single-core L1 processor, local memories I-Cache, D-Cache CodeCache, SystemCache, ARM Cortex-A5 MPU is targeted at TCM (Lower, Upper) industrial control, gas pumps and • Capacity, organization I-Cache = 32 KB, CodeCache = 16 KB, 2-way SA 2-way SA building control applications. Medical D-Cache = 32 KB, SystemCache = 32 KB, applications include patient monitoring 4-way SA 2-way SA and drug delivery mechanisms. 32 byte cache line size 32 byte cache line size (4 beat, 64-bit burst) (4 beat, 64-bit burst) A common theme in developing TCML(ower) = 32 KB a dual-core architecture for these TCMU(pper) = 32 KB Accesses from other market segments is the inherent issues masters via backdoor port associated with a high-performance L2 processor memories Optional L2 Cache single (applications) processor running • Capacity, organization L2-Cache = 512 KB, 8-way SA a high-level operating system coupled 32 byte cache line size, with the need for good real-time (4 beat, 64-bit burst) control. Vybrid devices address this System bus interface 1x 64-bit AMBA3 AXI 2x 64-bit AMBA2 AHB-Lite growing number of consumer and On-chip RAM (OCRAM) Three 64-bit AXI ported memory controllers + arrays, 1.5 MB total • 2x system RAM (_sys) controllers, each 256 KB in capacity, industrial embedded applications that 512 KB total need higher application performance Optionally includes single-bit correction, double-bit detection plus real-time responsiveness with its (SECDED) ECC • 1x Graphics RAM (_gfx) Controller, 1 MB total dual-core architecture combining the 512 Kbytes optionally used as L2 cache data array ARM Cortex-A5 application processor Programmable support for on-the-fly conversion of 16-bit pixel data to/from 32-bit ARGB8888 and the ARM Cortex-M4 for real-time DDR DRAM controller 2x 64-bit AXI input ports and 16-bit external DDR data bus control. Quad SPI memory controller 2x Quad SPI external memory controller Gluelessly interfaces to external (non-DRAM) memories and/or This approach offers considerable FlexBus memory controller flexibility in partitioning the software ASICs, six chip selects architecture across the dual-core hardware resources and provides basic microarchitecture includes interfaces including a multi-ported options for reducing the RunIDD the dual-core structure interfacing DDR DRAM controller, dual Quad SPIs current consumption. It also removes to the network interconnect system and a FlexBus controller for glueless the need for system designers to bus fabric, providing the hardware interfaces to simple (non-DRAM) specify a higher performance single interconnect matrix and supporting a memories and/or ASIC devices. processor device in an effort to 64-bit third-generation ARM-AMBA “oversample” the real-time events, Advanced eXtensible Interface split thereby reducing system cost and transaction protocol. This is followed power dissipation. by connections to a full complement of on-chip memories and slave peripherals A “processor-centric” high-level connected via peripheral bridges as Vybrid device block diagram is well as memory controllers for external presented in the previous figure. The

16 Beyond Bits Vybrid Edition

ARM® Cortex™-A5 Processor Pipeline Organization1

Mul1 Mul2 Writeback Instruction Queue r ue u Fetch 1 Fetch 2 Fetch 3 c Decode Issue Shift ALU Writeback

Delta Delta Addr Cache Cache Writeback Gen 1 2

1“ARM’s Midsize Multiprocessor, Next Cortex-A5 Supports FP1 FP2 FP3 FP4 FP5 Four-Way Coherent Multiprocessing,” Tom R. Halfhill, Microprocessor Report, 10/26/2009

ARM® Cortex™-M3 and ARM Cortex™-M4 Pipeline communication, semaphores, run/ LSU branch halt/reset control, memory protection result via ARM’s TrustZone architecture with Fe De Ex Freescale security extensions and Data Address Phase shared dual-core debug resources Address Phase Load/ including cross-triggering capabilities. Generation and Store Unit Writeback and Branch With significant amounts of both processor-local memories (L1 core Multiply caches, ARM Cortex-M4’s tightly Instruction and WR coupled memories with its backdoor Divide Decode port for alternate bus master Fetch and Register accesses, and the optional ARM Read ALU Cortex-A5 512 KB L2 cache) and Shift and the SoC resources associated with Branch on-chip RAM and boot ROM plus the controllers for the external DDR Branch DRAM, Quad SPI (flash) memories and FlexBus, the Vybrid architecture is a high-performance dual-core implementation, providing rich Branch Forwarding applications in real time for a number and Speculation of growing embedded application LU Branch No Forwarded/Speculated spaces. LSU Branch Result

For the standard configuration, Vybrid address space is effectively accessible systems can best be characterized as from either core. Memory coherency is a heterogeneous, symmetric, cache- wholly managed by software. There is based dual-core MPU architecture. hardware support for basic multicore The two ARM Cortex cores share requirements including peripheral an instruction set architecture with interrupt steering plus directed a common memory map, and the CPU interrupts for inter-processor freescale.com/Vybrid 17 Technical Highlights

Multicore Communication A flexible API for communicating between heterogeneous cores

A multicore architecture brings new Multicore Communications Architecture challenges to system design because the software must be rewritten to distribute tasks across the available ARM® Cortex™-A5 ARM® Cortex™-M4 cores. In addition, all the peripheral (Linux®) (MQX™) resources need to be properly allocated to avoid resource contention and share the data spaces between the cores efficiently. IPC API IPC API

The Vybrid multicore solution with heterogeneous cores anticipates a Transport Layer Transport Layer customer running a high-level OS Data Path Data Path such as Linux on the ARM Cortex-A5 OS Specific Driver OS Specific Driver and an RTOS such as Freescale’s MQX™ on the ARM Cortex-M4. Shared Memory Because of its real-time nature, the RTOS has a priority-based preemptive scheduler that is the heart of its Multicore, multi-OS architecture provides shared memory and message-based communication paths. task management services. These services could be communication and synchronization among tasks running The Solution: Multicore Applications communicate using a on the same processor including Communication client-server methodology. To do this, messaging, semaphores, mutexes each application participating on the Freescale’s solution to the multicore and event flags. A multicore SoC separate OS creates a connection architecture with different OSs is also needs mechanisms for reliable to a specific protocol port with one a multicore communication (MCC) communication and synchronization endpoint receiving data and the protocol that takes maximum among tasks running on different other sending data. In addition, each advantage of heterogeneous processing cores. endpoint has its own associated asymmetric multiprocessing (AMP) port for each channel, similar to BSD SoCs. It includes an easy-to-use API sockets. To simplify the design, all that can be easily extended to support communication is message-based and additional operating systems and avoids connection-oriented or packet- features. based data streams. Messages can The MCC protocol is designed for low be queued on the receive end up to a latency and low overhead operation configurable limit. and is optimized for embedded As shown in the figure above, environments with constrained CPU messages pass between endpoints and memory resources. To achieve this, via bidirectional connection-less the protocol is exclusively implemented communication channels. using shared memory with no data translation or message headers.

18 Beyond Bits Vybrid Edition

A tuple (node, port) uniquely identifies CPU-to-CPU interrupts signal when Additional use cases that can take each endpoint. In addition, each new blocks are available for data advantage of the Vybrid device independent thread of execution sending and when data exists capabilities include: with a private memory space can to be received. This mechanism • Segmenting real-time application operate as a node. This implies that implements the blocking versions of code. This involves running real- a single-process RTOS like MQX will the message-send and message- time code on the ARM Cortex-M4 have, at most, one node. In contrast, receive API calls. core to operate independently of ® a multi-process OS like Linux could higher-latency code running on MCC Advantages contain one node per process. A port the ARM Cortex-A5 core. The new operates as a mailbox location where The MCC solution utilizes shared MCC can be used to share data data can be delivered. Each node can memory as the data transport between them utilize multiple ports and the same mechanism. This design minimizes • Off-loading CPU-intensive port can be used simultaneously by communication latency by using operations. An audio software multiple nodes. zero-copy, so data passes by platform may experiment with reference rather than physically Implemented as a user space library, executing audio stream parsing and being copied. the protocol includes an external decoding on the ARM Cortex-M4 API and transport layer. Supported A good example of where this low core to improve the real-time operating systems include kernel latency can provide significant responsiveness of the UI and other components that allow the protocol to application benefits is in network applications running on the ARM take advantage of Freescale hardware processing. With network processing, Cortex-A5 architecture features to synchronize data transmission occurs frequently • Minimizing power draw. The shared memory access. and in large quantities based on ARM Cortex-M4 core can be the high-bandwidth network traffic the primary component of the Hardware Architecture that Ethernet and proprietary system during periods of low The new heterogeneous AMP SoC communication protocols can deliver. CPU utilization/idling and the includes several hardware features MCC with zero-copy can off-load ARM Cortex-A5 can be activated that allow optimal implementation of the network processing. In a typical during periods of high-demand or the MCC. application, the ARM Cortex-M4 core for specific CPU-intensive tasks. receives and processes complex The shared memory region used by This synchronization would be network data and feeds the raw data all cores has two distinct areas: one accomplished using Freescale MCC back to the ARM Cortex-A5 core for for configuration and bookkeeping, • Partitioning sensitive code for use by an application. and the other for data buffers. medical or safety reasons Hardware semaphores are used as the synchronization primitive to surround critical sections of code that access shared memory blocks. The hardware semaphore synchronization is required since each core is separately running an instance (or instances) of the MCC library.

freescale.com/Vybrid 19 Technical Highlights

Multimedia Subsystem Enabling rich apps with hardware acceleration

The Vybrid multimedia subsystem Video Subsystem Features consists of the video interface unit VIU • Supports QVGA to XGA (VIU), display control unit, touch screen The VIU provides a 24-bit parallel • Input options: controller, segment LCD and the audio interface for digital video. The VIU subsystem. 8/10-bit ITU656 video accepts ITU-R BT.565-compatible Up to 24-bit digital RGB This multimedia subsystem helps video, digital RGB and YUV444 to minimize and possibly eliminate formats on its parallel interface, • Scaling: the need for the cores to handle decodes it and optionally performs Up to 1/8 video down-scaling with any pixels, allowing them to manage processes such as down-scaling, different scaling ratios in horizontal system level tasks. horizontal up-scaling, brightness and vertical directions and contrast adjustment, YUV to This section will describe the more Up to 2x video up-scaling in RGB conversion, deinterlacing and complex IP in the multimedia horizontal direction horizontal mirroring. The resulting subsystem and give a pictorial • Brightness and contrast adjustment video stream is stored to system representation of the pixel processing • YUV to RGB888 or RGB565 memory for subsequent post- of the subsystem. conversion processing and displayed by a display control unit. • De-interlace function Multimedia Block Diagram The video subsystem supports both Display digital and analog inputs. In the case of digital video, the interface is directly TFT LCD into the VIU module either as RGB

Touch Screen Controller data or an ITU-R BT-565 compatible YUV data stream. For composite video Segment LCD the on-chip video analog decoder (video ADC) is required, the output of Video which will feed the VIU digital input. The input formats supported for Video Camera Interface composite video are PAL and NTSC and up to four input channels are Audio muxed down to one ADC.

ASRC

SAI x 4

ESAI

SPDIF

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Multimedia Pixel Processing Audio Subsystem The audio subsystem has IP to provide options for everything from asynchronous sample rate conversion to a stereo transceiver that can receive Image Sensor Display and transmit digital audio.

Camera Display Control Unit Display Enhancement (DCU) Synchronous Audio Interface Image Signal Synchronous audio interfaces (SAI)

Digital Analog Video/Graphics Combining are used to transfer audio data. Input Input RLE Decompression of Compressed Image The SAI supports full-duplex serial in Memory Video ADC Rotation interfaces with frame synchronization such as I2S, AC97 and CODEC/ DSP Image Processing ColorSpace and Scaling Conversion interfaces.

Video Interface Unit (VIU) Run Length Encoder (RLE) Lossless Decompression Features • Transmitter with independent bit System Memory clock and frame sync supporting one data line Memory

Combining with Audio Separation from Audio Hardware Accelerated • Receiver with independent bit clock

Communication Network and frame sync supporting one data line Audio Compression ARM Audio Decompression • Word size programmable from 8- to 32-bit Display Subsystem Features • Asynchronous 64/32 x 32-bit FIFO for each transmit and receive data • Resolutions supporting up to XGA Display Controller Unit line The display controller unit (DCU) is (1024x768) the interface to TFT LCD displays. • Generates full RGB888 data and It generates all the signals required control signals for TFT display to drive the display. Layer data is • Direct blitting engine with real time stored in on-chip or external memory alpha-blending and is fetched by the internal DMA • Blending of each pixel using up to channels of the DCU. The layer six source layers data is described using layer control • Total of 64 graphics layers descriptors that form part of the register set of the DCU. • Gamma correction with 8-bit resolution on each color component • Temporal dithering • Window feature allowing easy cropping and horizontal scrolling with low CPU overhead

freescale.com/Vybrid 21 Technical Highlights

Enhanced Serial Audio Interface Audio Subsystem Block Diagram The enhanced serial audio interface (ESAI) provides a full-duplex serial port for communication with a variety of serial devices including industry- SAI3 SAI2 SAI1 SAI0 standard codecs, SPDIF transceivers, and other processors. The ESAI consists of independent transmitter ASRC and receiver sections, each section with its own clock generator.

Sony/Philips Digital Interface The Sony/Philips Digital Interface SPDIF ESAI_FIFO module is a stereo transceiver that External allows the processor to receive and (Virtual) Clocks ESAI transmit digital audio over it using Legend Data/Control Dedicated the IEC60958 standard, consumer Audio I/F Audio format. Audio Clocks Modules

Features

• SPDIF receiver Asynchronous Sample Rate Features Input sample rate measurement Converter • Supports up to 10 channels split Supports the following sampling The incoming audio data may be into up to three sampling rate rates: 32, 44.1, 48, 64, 88.2 and received from various sources at conversion sets 96 kHz different sampling rates. The outgoing • Individual association of each CD text support audio data may have different channel to one of the sampling rate CS and U bit recovery sampling rates and it can also be pairs associated to output clocks that are • SPDIF transmitter asynchronous to the input clocks. The • Designed for rate conversion One SPDIF output, IEC 60958 asynchronous sample rate converter between 32, 44.1, 48 and 96 kHz. consumer format (ASRC) converts the sampling rate of The useful audio signal bandwidth is CS bit support a signal associated with an input clock below 24 kHz • Low-power mode into a signal associated to a different • Other sampling rates in the range SPDIF can be disabled to save output clock. The ASRC supports of 8 to 200 kHz are also supported, power when not in use concurrent sample rate conversion of but with reduced audio performance up to 10 channels of about -120 dB • Automatic accommodation to slow THD+N. variations in the incoming and outgoing sampling rates • ASRC has a disable mechanism to save power when not in use

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Security Subsystem Secure your applications in an insecure world

Security is an increasingly Security Subsystem: More flexibility is achieved by using important feature for industrial A Trusted Platform electrically programmable fuses to and consumer applications as the The foundation of a secure system enable or disable particular system number of hacking incidents that consists of the hardware platform functions. For example, it is possible expose sensitive information and and the critical code that executes on to configure a production version, unauthorized use of copyrighted security-enabled device so that content is on the rise. Helping to that platform. This foundation is built the JTAG debug port is completely ensure secure applications is a with an on-chip ROM-based boot-up disabled. For early prototype devices, high priority for the Vybrid platform. process that initiates validation of the portions of the security system can be Sensitive information and digital rights platform, including the following tasks: selectively disabled, allowing access management data can be stored in a • Examining key hardware elements to otherwise inaccessible areas of the protected manner and used, allowing to help ensure that they are e-commerce and advanced content- device. Full flexibility between these functioning properly based subscriber services. two extremes is possible. • Verifying the authenticity and integrity of the critical code that Software that is security aware is controls the overall operation of imperative for those products that Security Block Diagram the system need security. Sensitive data in plaintext form must not appear on The boot process gains control of Security external data buses, and it should be the system immediately after reset Crypytography Module restricted to the minimum number of by executing known boot code that (CAAM) data paths internal to the chip. is resident in the on-chip ROM. After Tamper Detect verifying the authenticity of a start-up High Assurance Boot script residing in external memory (i.e., The high assurance boot (HAB) feature Secure RTC NOR or NAND flash) the boot process in the system boot ROM protects the Real-Time Integrity platform from executing unauthorized Checker (RTIC) follows that script using established cryptographic techniques to validate software (malware) during the boot Secure RAM the authenticity and integrity of the sequence. Unauthorized software can enter the platform during upgrades or operating system code and data in Secure Fuses re-provisioning or when booting from external memory. USB/UART connections or removable Secure WDOG devices. If permitted to gain control of the boot sequence, unauthorized Secure JTAG software can be the attack vector for a variety of goals including exposing stored secrets, circumventing access controls to sensitive data, services or networks and re-purposing the

freescale.com/Vybrid 23 Technical Highlights

platform. HAB supports booting the Encrypted High Assurance Boot device to a known initial state by using digital signatures to recognize Encryption Using Decryption Using authentic software and running Secret Key Secret Key software signed by the device manufacturer. Build Environment Device Boot Decrypted SW Image SW Image In addition, HAB can protect the confidentiality of software during Secret Key Decrypt off-chip storage by decrypting the (AES) OTP Key software loaded into RAM prior Encrypt Secret Key OTP Key Decrypt (AES) (AES) to execution. The figure to the CAAM (AES) right shows HAB encrypted boot Key Blob Key Blob Manufacturing supported on the Vybrid platform. The software image is encrypted Flash using a secret key before being Encrypted Encrypted programmed on the off-chip memory SW Image SW Image (typically flash). During boot, HAB uses the same secret key (stored in hardware fuses not visible to the user) to decrypt the software image. • Real-time integrity checker • TrustZone Address Space Controller Periodic check on system Supports 2, 4, 8 or 16 Hardware Security memory for unauthorized independent address regions Elements modifications Access controls are Vybrid platform security architecture Supports up to four memory independently programmable for includes the following hardware regions each address region components: Use SHA-1 or SHA-256 as Protects all AXI slave • Cryptography acceleration and hashing algorithm memories—DDR, on-chip SRAM assurance module Once started, RTIC can only be All AHB slave memories, Supports acceleration and stopped and restarted by trusted FlexBus, Quad SPI are protected off-loading for selected crypto software by AHB equivalent address algorithms • Secure non-volatile storage space controller Supports NIST SP800-90 Secure non-rollover real-time • Other security sub-blocks compliant hardware random counter Secure fuses (OTPs) number generator Non-rollover monotonic counter Central security unit 16K secure memory (automatic Zeroizable 256-bit secret key AHB TrustZone Controller zeroization) with up to four independent partitions Support for tampers Trust Zone Watchdog Supports AES, DES, 3 DES, • Tamper Detection Secure JTAG Controller ArcFour Symmetric key blog Support for up to six external ciphers tamper detectors Supports MD5, SHA-1, SHA-224, Active tamper detection SHA-256 hashing algorithms Wire mesh tamper • Random number generation Voltage, temperature and clock NIST compliant SP800-90 tamper detectors Combination of a true random number generator and a pseudo-random number generator

24 Beyond Bits Vybrid Edition

Power Management Programmable power options for performance and long battery life

The Vybrid platform was designed with Modes of Operation power efficiency as one of its main Normal Recovery goals. To reduce current consumption, ModesModes General DescriptionGeneral Description Normal Recovery Method Method the design has: RUNRUN All functionalityAll functionality of Faraday of Vybrid is available platform is available N/A N/A • Dynamic power management of WAITWAIT CA5 andCA5 CM4 and cores CM4 Halted cores halted InterruptInterrupt core and peripherals LPRUNLPRUN 24MHz24 operation, MHz operation, PLL Bypass PLL bypass InterruptInterrupt • Software-controlled clock gating of ULPRUN 32/128 kHz operation, PLL off Interrupt ULPRUN 32kHz /128kHz operation, PLL Off Interrupt Lowest power mode with all power retained, peripherals STOP Interrupt STOP LowestRAM power retention mode with and all LVDpower protection retained, RAM Interrupt • Multiple power domains and voltage retention and LVD protection 64K RAM retention. I/O states held. scaling to minimize leakage in low- LPSTOP3LPSTOP3 64K (ADCs/DACstbd) RAM retention. optionally I/O states power-gated. held. ADCs/DACs RTC Wakeup/ResetWake-up/Reset power modes optionally power-gated.FPO RTC functional. Wakeup from interruptsfunctional. Wakeup from interrupts 16K RAM retention. I/O states held. Vybrid devices have a power LPSTOP2 16K (tbd) RAM retention. I/O states held. ADCs/DACs Wake-up/Reset LPSTOP2 ADCs/DACs optionally power-gated. RTC Wakeup/Reset management unit supporting a variety optionally power-gated. RTC functional. Wakeup from interruptsfunctional. Wakeup from interrupts of operating modes to optimize SoC/ LPSTOP1 I/O statesI/O states held. ADCs/DACs held. ADCs/DACs optionally powergated optionally. RTC Wake-up/Reset application power consumption. LPSTOP1 functional.powergated. Wakeup from RTC interrupts functional. Wakeup from Wakeup/Reset There are nine modes of operation Battery All suppliesinterrupts OFF, SRTC, 32kXOSC ON, tampers and monitors POR to allow the user to optimize Backup ON. All supplies OFF, SRTC, 32k XOSC ON, Battery Backup POR power consumption for the level of tampers and monitors ON. functionality needed as well as several LPRUN and ULPRUN are part of RUN Mode and there are no separate modes. wakeup sources for the power modes. A low-leakage wakeup unit has up Features • Ultra-low power regulator: For to eight internal peripheral wake-up • Single 3.3V+/-10% supply voltage LPStop modes. 10 mA capacity and sources, as well as up to sixteen quiescent current < 5 uA • High-power voltage regulator external pins for wakeups. Several with an external ballast transistor • Well bias generator to increase well wakeup sources are available in the generating internal 1.2V supply by ~300mV to minimize leakage in lowest power mode: low-power timer, voltage, 1.2A capacity and low-power modes real-time clock, ADC, DAC and several quiescent current less than 1 mA • Multiple power domains and power pin interrupts. Depending on the gating to minimize low-power requirements of the user application, a • Ability to switch supply voltage consumption variety of stop modes are available that down from 1.2 to 1.1V in low- • Low voltage detection (LVD) on main provide state retention, partial power power modes to minimize power supplies and 1.2V supplies down and/or full power down of certain consumption logic and/or memory. I/O states are • Soft start of main high-power • 16 wakeup pins for low-power held in all modes of operation except regulator to minimize in-rush wakeup power gated modes (LPSTOP1, currents. Start-up time < 500 us • The single 3.3V supply is used in LPSTOP2, LPSTOP3). I/O state for • Low-power regulator: For Stop the system for I/O power with the 16 wakeup pads is still retained in modes. 50 mA capacity and exception of the DRAM interface. power gated modes. quiescent current < 50 uA The DRAM interface power will be generated external to the Vybrid SoC

freescale.com/Vybrid 25 Technical Highlights

Power Domains PMU Block Diagrams The Vybrid SoC is divided into six power domains: PD 4:0 and Vbat. PD4 Main Power Domain: • PD4: Main power domain. Contains 3.3V Core, platform, memories, full platform, cores, peripherals, HPreg graphics, peripherals, clocking, PLLs and main 24 MHz 1.2V clocks, PLLs XOSC. This domain is power External ballast gated off during LPSTOP modes ADC/DAC Domain: PD3 of operation to minimize leakage LPreg LVDs 2x DAC, 2X ADC power 1.2V Internal ballast • PD3: ADC-DAC domain: This PD2 SRAM Domain1: domain can be optionally powered 48k SRAM off in LPSTOP modes depending if powered, ADC and DAC SRAM Domain0: PD1 conversions can be performed in POR ULPreg 16k SRAM(tbc) LPSTOP modes 1.2V • PD2: 48 KB SRAM power domain: Internal ballast PD0 Regulator Always-on Domain: This domain can be optionally Wakeup LPTim powered off in LPSTOP modes 2.5V LDO I/O and Analog depending on the amount of SRAM that needs to be maintained 1.1V LDO Analog • PD1: 16 KB SRAM power domain: Battery Domain: Coin Cell 1.1V LDO This domain can be optionally SRTC, 32 kHz, powered off in LPSTOP modes if no Tampers, monitors SRAM retention is required 3.3V LDO • PD0: Always-on logic domain: This domain is always powered on in LPSTOP modes. It has wakeup logic, 24 MIRC, 128 KHz IRC and the voltage regulators • VBat: Battery/RTC domain: Contains the SecureRTC, 32 kHz XOSC, tamper and monitors. Powered by a coin cell when the main power supply is switched off

26 Beyond Bits Vybrid Edition

Ethernet Subsystem Real-time networked measurement and control

Vybrid devices, depending on the chaining which would otherwise need Supports wakeup from low- particular family, have dual Ethernet an expensive external switch. The power mode through magic controllers and an L2 switch. The function of the L2 switch is to route packets dual Ethernet controller modules, in packets from one Ethernet port to the Multiple clock source options for conjunction with an external Ethernet other Ethernet port without any CPU time-stamping clock PHY, are used to add Ethernet intervention. • L2 Ethernet switch connectivity. Hardware IEEE® 1588 3-port switch Ethernet Subsystem time stamping provides precision Supports two MAC-NETs Features clock synchronization for real-time Supports 64-bit Atlantic/FIFO • Dual 10/100 Ethernet MAC (MAC- control in networked automation, test ports NET) and measurement applications. Mid- IEEE 1588 support Hardware support for IEEE 1588 to high-end industrial applications standard for a precision clock Fast cut-through mode typically use dual Ethernet controllers. synchronization protocol for QoS with eight queues per port One Ethernet MAC can be used to networked measurement and Port mirroring manage the control nodes while the control systems Level 3 IP snooping other Ethernet MAC can be used to Reduced media independent • Dual unified DMA connect to a remote sever for control interface (RMII) support On-chip transmit and receive or for redundancy. Dual Ethernet Interfaces with unified DMA FIFOs with the L2 switch allows daisy

Ethernet Subsystem

Ethernet MAC

TOE Functions

RX Control TCP/IP MII/RMII uDMA Receive Performance Receive 3 2 FIFO + AHB I/F Optimization Pause Interface CRC Frame Check Terminate L2 Switch

TX Control uDMA TCP/IP MII/RMII Transmit Performance Receive + AHB I/F 0 1 FIFO Optimization Pause Interface CRC Frame Generate

Application I/F Application I/F Terminate

PHY Configuration MDIO Management Statistics Master Interface

Register Interface freescale.com/Vybrid 27 Technical Highlights

Supports legacy buffer Adjustable Timer descriptor programming models and functionality

Enhanced buffer descriptor Counter programming model for new Ethernet functionality

Ethernet Subsystem ENETn_ATPER Mod Clocking Options The Ethernet subsystem uses the following clocks: • Dedicated on-chip PLL with fixed To MAC multiplier to generate 50 MHz RMII External Free-Running Ethernet clock. This clock also Counter comes as chip output and goes to Correction Counter off-chip Ethernet PHY ENETn_ATCR [SLAVE] • Optional externally-supplied 50 MHz RMII clock. This clock is used as ENETn_ATINC ENETn_ATINC ENETn_ATINC the timing reference for the RMII [INC_COR] [INC] interface • A time-stamping clock for the IEEE 1588 timers • The core FIFO receive/transmit Dual Ethernet and L2 Switch IEEE 1588 Timers functions are disabled Bypassed The Ethernet module includes a four- • The MAC receive logic is kept in In low-power STOP mode, the MAC channel timer module for IEEE 1588 normal mode but it ignores all traffic stops immediately and freezes register time stamping. The timer supports from the line except magic packets values, state machines and external input capture (rising, falling or both pins. During this mode, the Ethernet edges) and output compare (toggle Dual Ethernet and L2 Switch subsystem clocks are shut down. or pulse with programmable polarity). Operation Coming out of STOP mode returns the The counter is able to operate In low-power STOP mode, the Ethernet MAC to operating from the asynchronously to the Ethernet bus MAC stops immediately and freezes state prior to STOP mode entry. by using one of the clock sources. register values, state machines and Battery Mode of Operation Ethernet Operation in external pins. During this mode, the Ethernet subsystem clocks are The Ethernet MAC does not support Low-Power Modes shut down. Coming out of STOP any standby mode of operation or a Ethernet-Only Operation mode returns the Ethernet MAC capability to operate on battery power The Ethernet MAC supports magic to operating from the state prior to in case the main supply fails. The packet detection that can generate a STOP mode entry. MAC will be disabled during wakeup in low-power mode. During this mode. low-power operation: • The MAC transmit logic is disabled

28 Beyond Bits Vybrid Edition

USB Subsystem Flexible USB connectivity with integrated PHY

The USB subsystem in Vybrid devices USB OTG/HOST PHY Architecture is comprised of several blocks that together provide flexible USB Test SYNC Bit Rx Shift functionality. The USB subsystem OTG Interface Detector Unstuffer and Hold NRZI HS/FS/LS HS DLL includes: Receivers Decoder • Dual USB On-The-Go (OTG) Squelch/ Elasticity Buffer 2.0 compliant controller (specific Disconnect Receive Clock State controller depends on the device). Buffers MUX Machine Options are: High-Speed (HS), Full- Receiver Control Speed (FS) and Low-Speed (LS) Transmitter FS DPLL Logic Local Bias Transmit • Dual on-chip HS USB PHY D+/D- Pull-up/ State Pull-down Logic Machine • USB regulator HS HS/FS/LS NRZI Bit Tx Shift FS FS/LS Encoder Stuffer and Hold Transmitters Transceiver MUX USB 1.1 USB Controller Single-Ended Transceiver BIAS The USB controller is a USB Receivers FS/LS Analog Block Digital Block 2.0-compliant serial interface engine for implementing a USB interface. The Test SYNC Bit Rx Shift USB controller provides USB host PLL Interface Detector Unstuffer and Hold NRZI HS/FS/LS HS DLL and device communications along Common Receivers Decoder Block with support for OTG operation. The Squelch/ Elasticity controller supports HS, (480 Mbps), Disconnect Buffer Receive FS (12 Mbps) and LS (1.5 Mbps) Clock State Buffers MUX Machine data transfer rates. The registers and Receiver Control data structures are based on the Transmitter FS DPLL Logic Local Bias Transmit enhanced host controller interface D+/D- Pull-up/ State specification (EHCI) for USB standard. Pull-down Logic Machine HS HS/FS/LS NRZI Bit Tx Shift The USB OTG module can act as a FS FS/LS Encoder Stuffer and Hold Transmitters Transceiver host or device. The USB controller MUX USB 1.1 Single-Ended Transceiver is programmable to support host or Receivers FS/LS device operations under firmware Analog Block Digital Block control. On-chip HS PHY is used for the 60 MHz clock source to the as VBUS), however, the USB OTG For OTG operations, external circuitry controller. The USB controller provides standard provides a minimum 8 mA is required to manage the host control and status signals to interface VBUS supply requirement. If the negotiation protocol (HNP) and session with external USB OTG and USB connected device attempts to draw request protocol (SRP). External ICs host power devices. Customers can more than the allocated amount of that are capable of providing the OTG use these control and status signals current, the USB host must disable the VBUS with support for HNP and SRP, on the chip interface and the I2C bus port and remove power. USB VBUS is as well as support for programmable to communicate with external USB not provided on-chip. The Vybrid SoC pull-up and pull-down resistors on the On-The-Go and USB host power provides pins for control and status to USB DP and DM lines, are available devices. USB host modules must an external IC capable of managing from various manufacturers. supply 500 mA with a 5V supply the VBUS downstream supply. on its downstream port (referred to freescale.com/Vybrid 29 Technical Highlights

Features SOF Implementation on the Vybrid Platform • Complies with USB specification rev 2.0 FTM0 64 Cycles USB0 SOF_PULSE Pulse • USB host mode Stretcher USB0 SOF Supports EHCI USB OTG 0 FTM1 Supports HS operation using internal on-chip HS PHY FTM2

® Supported by Linux and other 64 Cycles USB1 SOF_PULSE Pulse commercially available operating Stretcher USB1 SOF FTM3 USB OTG 1 systems • USB device mode Supports HS operation using internal on-chip HS PHY 1. The two SOF signals (one from each USB port) must be brought to two timer Supports FS/LS operation using channels of one FlexTimer. This flexibility is provided in FTM2 and FTM3 as internal HS PHY shown in figure. Supports one upstream facing 2. At least one of the SOF should be connected to one channel of a second port FlexTimer. This will allow measuring of two sets of audio clock/SOF signals. To accommodate this, the USB0 SOF is connected to all FlexTimers. Supports six programmable, Audio Master Clock should also be provided as one of the clock options to FlexTimers. bi-directional USB endpoints, including endpoint 0 signal has a rate of 1 ms pulse that • Suspend mode/low-power USB OTG/HOST PHY asserts for 64 system clock cycles As host, firmware can suspend Architecture when the SOF token is detected on individual devices or the entire The USB OTG HS PHY is a HS/FS/ the USB bus and the USB controller is USB and disable LS USB 2.0 PHY, integrated with the in device mode. Chip clocks for low-power controller. In order to properly support USB audio operation The USB OTG HS HY comprises two isochronous asynchronous mode of Device supports low-power USB 2.0 transceiver sub-modules, one operation, it is necessary to measure suspend OTG sub-module and one common how many audio sample clock ticks Remote wakeup supported for module shared between USB OTG occur between two consecutive host and device and USB H1 channels. occurrences of the SOF signal. This Integrated with processor doze measurement is used to provide USB OTG PHY Features and stop modes for low-power feedback to the USB audio source in operation • Complete physical interface module order to speed up or slow down the for USB 2.0 On-the-Go audio sample delivery over the USB Start of Frame • UMTI+ Level 3 specification compliant bus. USB audio use cases require some • Supports USB HS (480 Mbps), FS This is the method of estimating the sort of audio clock recovery capability. (12 Mbps) and LS (1.5 Mbps) ratio between the USB host clock The Vybrid system USB OTG controller • Host, slave and OTG dual role device (SOF occurrences) and the Vybrid supports use of the start of frame operational modes of OTG port (SOF) signal, which is generated at device local audio clock. • Host modes of host port the start of a microframe in the USB The figure above shows the USB SOF • Integrated self-calibrated 2.0 HS protocol. This is a signal with connectivity with FlexTimer to enable termination resistors for HS mode a rate of 125 microseconds. When this scheme. operating in full-speed mode, the SOF and full set of pull-up/pull-down resistors defined by USB 2.0 electrical requirements

30 Beyond Bits Vybrid Edition

Memory Subsystem Flexible memory hierarchy for optimal code footprint, security and BOM cost

Vybrid devices have multiple memory Vybrid Memory Hierarchy interface options. In addition to having up to 1.5 MB of on-chip SRAM ARM® Cortex™-A5 Core Complex ARM® Cortex™-M4 for speedy code execution, Vybrid ITM + ETM + ETB + CTI Core Complex NVIC FPU FPU + NEON TPIU CM4 CPU Inst PFU & Branch FPB DWT devices can interface to a variety of Alu/ Predictor CTI Q AP Bus Matrix ITM Mul Ld/Sc Shift DAP external peripherals and memories for Data uTLB Inst uTLB System Bus Code Bus RAM TCMU TCML RAM D-$ TLB I-$ Array, 32k Array, 32k system expansion and data storage. STB 4 x 8K 2 x 16K Tag/Data Tag/Data Arrays, 2x 8k Sys-$ Code-$ Arrays, 2x 8k Dual-quad SPI interfaces with XiP AXI-BIU Sys BIU Code BIU support can interface with the latest 64 flash memory. A secure digital host 64 64 64 Tag 7 AHB System Bus AHB Code Bus AHB Backdoor Port controller supports SD, SDIO, MMC Tag 6 L2 Cache Controller 0 0 or CE-ATA cards for in-application (Optional) Data software upgrades as well as media 7 files or adding Wi-Fi® support. NAND AXI System Bus 64 flash and DRAM controllers with ECC NIC-301 support allow connection to a wide variety of memory types for critical applications. Battery-backed RAM is critical for secure systems to store SDIO x2 NAND Flash DDRC Quad SPI x2 OCRAM OCRAM OCRAM Boot FlexBus PBRIDGE authentication keys. Vybrid devices _sys _sys _gfx ROMx2 provide 16 KB of secure RAM and the platform provides 96 KB ROM for high assurance boot. The “Vybrid Memory Hierarchy” diagram illustrates the memory Vybrid DRAM Controller hierarchy of Vybrid devices and the various memory interfaces. DRAM Memory Controller

Command Transaction Queue Processing Multi-Port Device 64-bit AXI Arbitration Ordering Interfaces

Engine DFI Interface PHY DRAM Interface Network Inter-Connect Sequence Write DLL (NIC) Engine Arbitration Queue DFI Interface DDR3 64-bit AXI Engine LPDDR2 Performance and Power Read Tuning ECC Queue Registers

freescale.com/Vybrid 31 Technical Highlights

Vybrid DRAM Controller Vybrid NAND Flash Controller Block Diagram The Vybrid DRAM controller offers boot_done boot_fail connectivity with application interfaces irq on one side and DRAM memory on boot_after_reset Boot Control boot_mode the other. lpg_clk NFC_IO[15:0] lps_clk CMD Residue Vybrid DRAM Features reset_b Data Generation Control Control • Supports 8-bit and 16-bit DRAM Register NFC_CLE Config memories BCH Encoder Seven ECC NFC_ALE • Supports two 64-bit AXI port slave Modes NFC_CEn interfaces • Support for synchronous and NFC_RE Addr SRAM asynchronous modes Dec. Control NFC_WE ECC Control • Supports components up to 8 GB NFC/R/Bn • Supports LPDDR2 (S2 and S4) and NAND FLASH CONTROL IPS BUS CPU Access Bus DDR3 DMA Control BCH Supported LPDDR2 grades: Decoder SRAM Buffer REQ LPDDR2-800 and under BUS IDLE

Supported DDR3 grades: GRT EMB IF SRAM Buffer DDR3-800 9 KB

• ECC support (only for 8-bit DRAM IPM DMA Bus interface) • DFI interface to PHY Quad SPI Vybrid device’s Quad SPI implements Quad SPI Features NAND Flash Controller a double data rate interface, enhanced • Double data rate support for The NAND flash controller (NFC) read data buffering schemes, XiP Spansion (data learning) and interfaces standard NAND flash and support for dual-die flashes. Macronix (DTR2 mode) serial flash devices with Vybrid devices and hides Quad serial flash memories with DDR • XiP the complexities of accessing the interfaces are available on the market NAND flash. It provides a seamless • Multi-master buffering support with throughput up to 66 Mbps interface to both 8- and 16-bit NAND • Up to four independent master peak data rates. With a dual-quad flash parts with page sizes of 512 channels SPI architecture this is increased to bytes, 2 kilobytes, 4 kilobytes and 132 Mbps. An enhanced read data • Support for dual-die packages with 8 kilobytes. buffering architecture, minimizes the two chip selects There are two specific use-cases for latency impact of cache misses. Only NAND flash usage with Vybrid devices. the CPU will access the Quad SPI a) Boot from NFC: This allows systems in the XiP mode of operation. The to directly boot from external NAND external serial flash can be used at memory. Bootloader may either runtime for data storage (graphics, reside in ROM or external NAND fonts etc.). It can also contain the device while the OS kernel would be application code image that will be part of external NAND memory. copied to external DRAM at boot.

32 Beyond Bits Vybrid Edition

Secure Digital Controller and data transfer protocol are forward compatible with the multimedia card with some additions. Enhanced Secure Digital Host Controller The Vybrid family has two SDHC Transceiver controllers, supporting up to an 8-bit DMA IP Bus Card interface for high-speed MMC/SDIO Interface IP Gasket cards.

SDHC Features • Conforms to SD Host Controller AHB Bus IP Bus Standard Specification version 2.0 • Compatible with the MMC System Specification version 4.2

For the cases where ROM includes • Two configurable DMA channels • Compatible with the SD Memory the bootloader (most likely), the Card Specification version 2.0 • Bypassable ECC mode, NFC system will boot from ROM, jump supports 4/6/8/12/16/24/32-bit • Supports high capacity SD memory to external NFC and continue error correction card loading the OS kernel. For the cases • Compatible with the SDIO Card where a bootloader as well as OS Secure Digital Controller Specification version 2.0 kernel resides in the external NAND The SD host controller version • Compatible with the CE-ATA Card memory, system will switch to provides an interface between the Specification version 1.0 external NFC after ROM initialization. host system and SD, SDIO, MMC or • Supports 1-bit/4-bit SD and SDIO b) NFC for bootloader: After ROM CE-ATA cards. The module has a built- modes, 1-bit/4-bit/8-bit MMC initialization, system switches to in transceiver as shown in the figure modes, 4-bit/8-bit CE-ATA devices external NAND device to load the above. The SDHC acts as a bridge, • Up to 200 Mbps data transfer for bootloader. passing host bus transactions to SD/ SD/SDIO cards using four parallel SDIO/MMC/CE-ATA cards by sending Features data lines commands and performing data • NAND flash interface: 8-bit/16-bit accesses to/from the cards. It handles • Up to 416 Mbps data transfer for • Supports all NAND flash products SD/SDIO/MMC/CE-ATA protocols at MMC cards using eigiht parallel data regardless of density/organization the transmission level. lines (with page sizes of 512+16B/2K+64 The SD card is designed to meet the B/4K+128B/4K+218B/8K) security, capacity, performance and • Supports flash device commands environmental requirements inherent such as page read, page program, in newly emerging audio and video reset, block erase, read status, read consumer electronic devices. The ID, copy-back, multi-plane read/ physical form factor, pin assignment program, interleaved read/program, random input/output and read in EDO mode, but is not limited to these commands

freescale.com/Vybrid 33 Technical Highlights

FlexBus FlexBus Modes Modes of Operation of Operation The FlexBus interface on the Vybrid devices is designed to gluelessly Non Muxed Mode connect with up to six external Data Data Data Data devices. Each version has 8-, 16- and 32-bit port sizes with configuration for multiplexed or non-multiplexed Address Address Address Address addresses and data buses. Data and Address Have Separate Ports Features Muxed Mode • Byte-, halfword-, word- and 16-byte line-sized burst transfers Address Data Data Address • Programmable burst and burst Data and Address Are Interleaved on the Same Port inhibited transfers selectable for each chip select and transfer Smart LCD Mode direction Data Data Data Data • Auto-acknowledge feature

Primary wait state counter up to Data Is Sent Sequentially on One Port 63 clocks

Optional secondary wait state FlexBus Key Features Customer Benefits counter 8-, 16-, 32- and 128-bit line sized transfers Maximize throughput according to the specific Useful for interfacing to burst application

memories that have a long Programmable burst and burst-inhibited transfers Optimized traffic patterns for each client in access time for the first beat of selectable for each chip select and transfer the bus data, but can deliver subsequent direction data faster Auto-acknowledge feature Increased flexibility and lower BOM costs in glueless external device connections • Programmable address setup time Programmable address-setup time with respect to the assertion of chip Programmable address-hold time select • Programmable address hold time with respect to the negation of chip select and transfer direction

Flexbus supports the connection to: • Flash • Smart LCDs • FPGAs • SRAM • PROM • EPROM • EEPROM

34 Beyond Bits Vybrid Edition

Universal Asynchronous Receiver/ Transmitter A flexible approach to full-duplex serial communication

The universal asynchronous receiver/ UARTUART Transmit Transmit Logic Logic transmitter (UART) module in Vybrid Internal Bus devices allows for asynchronous, full-duplex serial communication in a Module Baud Rate Generator SCI Data Register (SCID) variety of formats. Clock RTS_B SBR12:0 BRFA4:0 Features of the UART include: Variable 12-bit Transmit M10 Shift Register R485 Contol CTS_B • Standard mark/space non-return-to- Stop Start M zero format TXINV Shift Direction MSBF • Supports IrDA 1.4 return-to-zero- TXD Pin Control inverted format PE Parity Transmitter Tx port en PT Generation Tx output buffer en • Supports ISO 7816 protocol for Control Tx input buffer en DMA Done interfacing with SIM cards and TXDIR smartcards (feature supported on SBK TE one UART module only) 7816 Logic TxD • 13-bit baud rate selection with IRQ/DMA DMA Requests Logic IRQ Requests by-32 fractional divide TxD Infrared Logic • Programmable eight- or nine-bit data formats Loop Control To Receiver • Ability to select MSB or LSB to be first on the wire LOOPS RSRC • Hardware flow control support for request to send and clear to send signals ISOISO 7816 7816 Timing Timing Diagrams Diagrams • Separate transmit and receive (feature supported on two UART ISO 7816 Format without Parity Error (T=0) PARITY NEXT modules only) FIFOs with DMA START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP STOP BIT request capability BIT BIT

ISO 7816 Format with Parity Error (T=0) NACK ISO 7816 Support ERROR PARITY NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP BIT Two of the UART modules support BIT the ISO 7816 standard, allowing communication with SIM cards and ISO 7816 Format (T=1) PARITY NEXT smartcards. This feature has the START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT STOP BIT following characteristics: BIT • Supports T=0 and T=1 protocols • Automatic retransmission of NACKed packets with programmable retry threshold • Supports 11 and 12 ETU transfers • Detects initial packet and automated transfer parameter programming freescale.com/Vybrid 35 Technical Highlights

• Interrupt-driven operation with seven UARTUART Receive Receive Logic Logic ISO-7816 specific interrupts:

Wait time violated Internal Bus Character wait time violated

Block wait time violated SBR12:0 BRFA4:0 Data Buffer Initial character detected Module Baud Rate M Clock Generator Variable 12-bit Receive Transmit error threshold Shift Register M10 Stop Start exceeded RE Receive LBKDE RAF Control MSBF Receive error threshold Shift Direction RXINV exceeded RxD LOOPS Receiver Guard time violated RSRC Source PE Parity Wakeup Control PT Logic Logic From Variety of Communications Transmitter Formats Available IRQ/DMA DMA Requests The UART offers a number of options RxD Active Edge Logic Detect IRQ Requests for data size, format and transmission/ reception settings. The variety of available options makes the UART To TxD 7816 Logic capable of implementing a wide variety of serial communications protocols. Infrared Logic Features • Eight- and nine-bit data formats supporting parity over all nine bits UARTUART Data Data Formats Formats • MSB or LSB first on wire Eight Bits of Data with LSB First • Programmable transmitter output ADDRESS MARK polarity START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT • Programmable receiver input polarity BIT FIFOs with DMA Eight Bits of Data with MSB First ADDRESS MARK Request Capability START START BIT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT The UART FIFOs reduce the frequency BIT of CPU processing required by the Nine Bits of Data with LSB First UART. ADDRESS MARK START START The DMA can be configured to BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT BIT transfer an entire packet of data and then interrupt the CPU when all bytes Nine Bits of Data with MSB First are received. This means the CPU can ADDRESS MARK START START process the entire packet all at once BIT BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 STOP BIT instead of needing to stop the current BIT program flow to move data bytes as they are received. The size of the FIFOs vary depending on the particular device and the specific UART. The Vybrid platform supports 16-byte FIFO on two UARTS (UART0 and UART1) and 8-byte FIFO on the other UARTS (UART2, UART3, UART4, UART5).

36 Software and Development Tools Software and Development Tools

Freescale Virtual Hardware Platform A rapid product development tool designed to accelerate software development

Vybrid families support a wide variety This is combined with broad system • Fast instruction execution for one or of complex I/O controllers, display modeling techniques, resulting in both ARM cores subsystems and communication a Vybrid device with an example Full support for ARM Cortex-A5 interfaces while supporting a highly EVB hardware environment that and ARM Cortex-M4 cores as configurable multicore and multi- can be virtually represented on any implemented in Vybrid families ® memory programmer’s model. Vybrid Windows enabled machine. Code execution capable of families are designed to efficiently running high-level operating Features handle numerous application- systems (Linux or others) at level design challenges as well as • Single executable product that loads chip-level performance or faster traditional real-time embedded tasks. editable data-driven files • Bridged peripheral support between This is where our virtual hardware Editable bootimages host platform and embedded virtual platform provides an additional Peripheral parameters machine resource for managing the design and (e.g., target display screen File system on host machine can debug of your application. parameters) be mapped to embedded virtual Feature/mux configurations on The virtual hardware platform brings machine file system many features found in standard select features (I/Os, UARTs, – Allows rapid testing of board desktop virtual machine environments GPIOs) support/processor support to embedded customers who need EVB memory sizes (editable packages a platform to accelerate software virtual machine configuration development. Unlike traditional files to set EVB memory) – Allows rapid application modeling environments, this tool development (Java™, leverages a fast instruction set model Android™, Linux, MQX™ that runs natively with no code and others) conversion requirements between x86 and ARMV7™.

38 Beyond Bits Vybrid Edition

Diagram of Virtual Hardware Platform

Embedded VM: Laptop Boundary Embedded VM: EVB Boundary Ethernet Laptop Embedded VM: eMPU Boundary VM Bridge Ethernet/Wi-Fi® Ethernet

VM-Cores Serial NAND DDR Flash Flash Network Memory A5 M4 Subsystem File System/ Laptop File System Bridge Display Control Window Virtual Cache li ty SRAM Comm Screen 1 System Windows Laptop LCD Frame Screen Buffer Internal/External Virtual System Visib Comm Ports Window Virtual (UARTs) Screen 2 Frame Trace Data Buffer IDE Tool Config Plug-ins

Ethernet nodes on host machine Serial interface input and capture • Advanced debugging features can be mapped to Ethernet – Configure test files to Industry-leading IDE support nodes on virtual target (Ethernet generate/receive serial allows real-time debug, trace, bridging ability) communications for testing and visibility to internal debug Display controller output to host and validating code data providing enhanced application-level development machine display – Leverage virtualized UARTs in – Leverage GUI development Windows to transmit/receive Debug access available through packages to develop and test live data with model Windows DLL extensions HMI/UI applications, on virtual display controllers. Control one or two screens at the same time

freescale.com/Vybrid 39 Software and Development Tools

Freescale MQX™ Software Solutions Complimentary full-featured RTOS

Freescale Streamlines FreescaleFreescale Comprehensive Comprehensive Solution Solution Embedded Design with a Complimentary RTOS CodeWarrior Development Demo Code Applications Environment Customized and Software Stacks Application (MQX™ OS Applications Application Tasks and Aware) The increasing complexity of Industry-Specific Libraries industrial applications and expanding CodeWarrior functionality of semiconductors Processor Expert Ethernet USB are driving embedded developers MQX RTOS (RTCS) Discrete MQX Design Optional Driver, toward solutions that combine proven and Services Third Enablement File System CAN Development Party Layer hardware and software platforms. To Tools and Freescale help accelerate time to market and Core Services MQX RTOS Third Party: improve application development IAR® ARM®, Keil success, Freescale offers the MQX (MQX OS Aware) RTOS with TCP/IP and USB software BSP/PSP HAL stacks and peripheral drivers to ColdFire, ColdFire+ and Kinetis MCU Open Source BDM and BDM/JTAG MCU Hardware customers at no additional charge. Third Party: Emulator/Probe The combination of Freescale MQX On Device PC Hosted software solutions and our silicon portfolio creates a comprehensive Freescale MQX Software Solutions source for hardware, software, tools and services. Reducing Cost, According to recent research, Accelerating Success development teams spend approximately 60 percent of their By providing complimentary resources on software. Embedded Freescale MQX software solutions projects based on 32-bit devices have with its silicon products, Freescale a greater need for software reuse to helps alleviate much of the initial manage development costs. software investment hurdle faced by embedded developers. Comparable full-featured software offerings may cost developers as much as $95,000 (USD) in licensing fees.

40 Beyond Bits Vybrid Edition

MQX RTOS:MQX CustomizableRTOS: Customizable Component Component Set Set Full Featured, Proven and Scalable The MQX RTOS has been the Name Services backbone of embedded products

Queues Interrupts based on Freescale silicon for more than 15 years. MQX software deployment spans a broad range Partitions Utilities Messages of market segments and leading Task Errors Initialization Task manufacturers worldwide. Events Management Lightweight Core Memory The Freescale MQX RTOS offers Semaphores Services CORE powerful, preemptive real-time Watchdogs Mutexes performance with optimized context Task Queue Automatic Scheduling Task Creation switch and interrupt time, enabling Timers IPCs fast, highly predictable response RR and FIFO times. Its small, configurable size Scheduling Exception Formatted I/O Handling conserves memory space for embedded applications and it can be I/O Subsystems Kernel Log Logs configured to take as little as 6 KB AS-NEEDED of ROM, including kernel, interrupts, semaphores, queues and memory manager.

The Freescale MQX RTOS offers The Freescale MQX RTOS and Freescale MQX is deployed as a straightforward application software stacks address these production-ready source code, programming interface with a modular, developer needs by providing a including communications software component-based architecture that scalable, reusable platform that works stacks and peripheral drivers, at no makes it very scalable. Components across a wide range of Freescale additional cost. Freescale MQX is are linked in only if needed, preventing processor architectures, development provided with a commercial-friendly unused functions from bloating the tools and third-party software software licensing model, enabling memory footprint. Plug-ins, such environments. developers to keep their source as security, industrial protocols and modifications while being able to graphical interfaces from Freescale’s distribute the required binary code. strong network of partners, can also be added.

freescale.com/Vybrid 41 Software and Development Tools

Certifiable to Medical and RTCSTower TCP/IP System Stack Modules Aerospace Standards *SNMP RPC *SSH *XML *SMTP *POP3 HTTP Even if your application does not (v3) require formal certification, the SNMP XDR Telnet FTP TFTP DNS SNTPWeb Server (v1, v2) robustness of MQX provides a trusted platform that has been *SSL proven in thousands of time- critical, sophisticated applications. Sockets BootP DHCP RIP For designs that do have a formal certification process to follow, TCP UDP MQX is an excellent choice. Past ICMP IGMP licensees have certified MQX-based applications to medical specifications NATIP CIDR (CFR 820.30 Part 21, IEC 60601- IP-E IPCP PAP CHAP CCP LCP 1) and the aerospace requirements listed under DO-178b. Safety- ARP PPP critical applications based on MQX include eye surgery equipment, drug injection equipment, radiation Ethernet Serial HDLC dose monitoring equipment, aircraft *Denotes optional products braking systems and aircraft Application Presentation Session Transport Network Data Link Physical navigation equipment.

42 Beyond Bits Vybrid Edition

Freescale MQX Add-on Software

• Network management: Support for SNMP version 1 and 2 is built into RTCS. EAI offers MQX™ Real-Time TCP/IP Communication Suite SNMPv3 (RTCS) Optional Components • XML parsing and framing: The MQX XML component enables your device to accept data in XML, Available from as well as send data packaged in XML Embedded Access Inc. • Email communication: The MQX SMTP module provides your device with outbound email communication and MQX POP3 provides the capability to accept incoming email communication • NanoSSH: Provides privacy, authentication and ensures data integrity between a secure server NanoSSL™ and NanoSSH™ Software by and its clients Mocana Available from freescale.com/ nanossl, freescale.com/nanossh • NanoSSL: Cyptographic protocols that provide security for communications over networks such as the Internet • Portable embedded GUI library designed to provide a professional-quality GUI for embedded PEG + Graphics Library systems applications Available from • Small, fast and easily ported to virtually any hardware configuration capable of supporting freescale.com/peg graphical output SEGGER emWin Graphics Library/GUI • emWin is designed to provide an efficient, LCD controller-independent GUI for any application that operates with a graphical LCD Available from SEGGER Microcontroller • CANopen is a CAN-based higher layer protocol CANOpen Master/Slave for Embedded Devices • Developed as a standardized embedded network with highly flexible configuration capabilities Available from IXXAT, Inc. • Unburdens the developer from dealing with CAN-specific details such as bit-timing and implementation-specific functions • Profinet RT for I/O device • EtherNet/IP for adapter and scanner Industrial Network • Ethernet powerlink for managing and controlled nodes and Field Bus Protocols • EtherCAT for slave nodes Available from IXXAT, Inc. • SERCOS III for slave devices • Precision time protocol IEEE® 1588-2008 (v2) • SFFS is a safe flash file system that can support almost any NOR or NAND flash device • Provides a high degree of reliability and complete protection against unexpected power failure or reset events SFFS Flash File System • Provides wear leveling, bad block handling and ECC K30C algorithms to ensure you get optimal Available from Embedded Access Inc. use out of a flash device • Pre-integrated with the MQX RTOS: allows you to create a robust file system quickly for an embedded device using on-chip or on-board flash devices The complimentary Freescale embedded graphical user interface (eGUI) allows single-chip MCU Freescale eGUI: Graphical LCD Driver systems to implement a graphical user interface and drive the latest generation of color graphics Available from LCD panels with integrated display RAM and simple serial peripheral interface (SPI) or parallel bus freescale.com/egui interface. The uButterfly Browser runs on MQX and browses, parses and renders HTML/CSS content. • Browse HTML 4/CSS 2.1 Web pages MicroBrowsers Available from Motomic Software, Inc. • Enable dynamic HTML, active graphics and media • An optional SDK allows browsing embedded/instanced within C, C++ or Qt apps (available as a separate product) OS Changer is a C/C++ source-level virtualization technology that allows you to easily re-use your software developed for one OS on MQX, while providing real-time performance. Available OS Changer Porting Kits: • VxWorks Porting Kit OS Changer—Reuse Application on MQX • pSOS Porting Kit Available from MapuSoft Technologies • Linux/POSIX Porting Kit • Windows Porting Kit • Nucleus Porting Kit • micro-ITRON Porting Kit freescale.com/Vybrid 43 Software and Development Tools

Freescale Tower System A modular development platform

Overview The Freescale Tower System The Freescale Tower System is a modular development platform for Controller/Processor Primary Elevator 8-, 16- and 32-bit MCUs and MPUs Module (MCU/MPU) • Common serial • Tower MCU/MPU and expansion bus that enables advanced development board signals through rapid prototyping. Featuring • Works stand- • Two 2x80 multiple development boards or alone or in connectors on modules, the Tower System provides Tower System back side for easy signal access and designers with building blocks for entry- • Features side-mounting integrated level to advanced MCU development. board (LCD debugging module) interface for easy Modular and Expandable programming • Power regulation and run control circuitry • Controller modules provide easy- via standard USB cable • Standardized signal to-use, reconfigurable hardware assignments Secondary • Interchangeable peripheral modules • Mounting holes (including communications, Elevator • Additional and Size memory and graphical LCD) make secondary serial • Fully assembled and expansion customization easy Tower System is bus signals • Open-source hardware and approx. • Standardized signal 3.5” H x 3.5” W x standardized specifications assignments 3.5” D promote the development of • Mounting holes Board Connectors additional modules for added and expansion • Four card-edge functionality and customization connectors for side- connectors mounting peripheral • Uses PCI Express® Speeds Development Time connectors Peripheral Module • Open source hardware (x16, 90 mm/ • Adds features and functionality 3.5” long, 164 pins) and software allows quick to your designs development with proven designs • Interchangeable with other peripheral Tower Plug-In (TWRPI) modules and compatible with all • Integrated debugging interface • Designed to attach to modules controller/processor modules that have a TWRPI socket(s) allows for easy programming and • Examples include serial interface, • Adds features and functionality run control via standard USB cable memory, Wi-Fi®, graphical LCD, motor control, audio, Xtrinsic sensing and high • Swappable with other TWRPIs precision analog modules • Examples include accelerometers, key pads, touch pads, sliders and rotary touch pads

44 Beyond Bits Vybrid Edition

Tower System Modules Controller/Processor Modules (8-, 16-, 32-bit) freescale.com/TowerController

Works stand alone or as part of Tower Allows rapid prototyping System

Features open source debugging interface Provides easy programming and run control via standard USB cable Peripheral Modules freescale.com/TowerPeripheral

Can be re-used with all Tower System Eliminates the need to buy/develop redundant controller modules hardware Tower Geeks Online Community Interchangeable peripheral modules: Serial, Enables advanced development and broad memory, graphical LCD, prototyping, sensor functionality TowerGeeks.org is an online design Tower Plug-Ins freescale.com/TWRPI engineer community that allows members to interact, develop designs Designed to attach to any Tower System Adds features and functionality with little module with a TWRPI socket(s) investment and share ideas. Offering a direct path to explore and interact with other Swappable components Allows for design flexibility engineers designing with the Tower Elevator Modules freescale.com/TowerELEV System, TowerGeeks.org is a great way Two 2x80 connectors Provides easy signal access and side- to discuss your projects, post videos of mounting board (i.e. LCD module) your progress, ask questions through Power regulation circuitry Provides power to all boards the forum and upload software. With Standardized signal assignments Allows for customized peripheral module updates through Twitter and Facebook, development it’s easy to get involved. Four card-edge connectors available Allows easy expansion using PCI Express® connectors (x16, 90 mm/3.5” long, 164 pins) Follow Tower Geeks on Twitter twitter.com/towergeeks Cost-Effective Partner Modules Visit Freescale on Facebook • Interchangeable peripheral Tap into a powerful ecosystem of facebook.com/freescale modules can be re-used with all Freescale technology alliances for Tower System controller modules, building smarter, better connected eliminating the need to purchase solutions. Designed to help you redundant hardware for future shorten your design cycle and get designs your products to market faster, these technology alliances provide you with • Enabling technologies like LCD, access to rich design tools, peripherals Wi-Fi®, motor control, serial and and world-class support and training. memory interfacing are offered off- A number of partners have developed the-shelf at a low cost to provide a modules for the Tower System. Some customized enablement solution examples include the i.MX515 ARM Take Your Design Cortex-A8 Tower Computer Module to the Next Level and StackableUSB™ I/O Device Carrier module from Micro/sys, as well as For a complete list of development the rapid prototyping system (RPS) kits and modules offered as part of the AM1 and FM1 modules from iMN Freescale Tower System, please visit MicroControl. freescale.com/Tower.

freescale.com/Vybrid 45 Software and Development Tools

Swell PEG Product Line Any LCD. Anywhere. PEG Software.

Swell Software provides graphical Window Builder Technology user interface solutions for embedded devices. Swell’s PEG Pro, PEG+ and C/PEG product offering includes a GUI library for embedded development that works tightly with real-time operating systems. These development tools allow developers to lay out user interface screens and controls using the PEG library and external resources to generate C or C++ code.

PEG software accelerates GUI design for embedded devices by allowing developers to create prototypes on a Windows or Linux-based PC. It provides a complete visual layout and design tool to enable GUI design to take place in parallel to the embedded PEG Pro PEG+ C/PEG software/hardware development. • Screen transitions • Multiple window updates • Designed for small LCDs The PEG WindowBuilder automatically • Multiple alpha-blended • Alpha-blended images (QVGA) generates C or C++ source code that windows • Run-time image decoders • Low color-depth is ready to be compiled and linked • True anti-aliasing and language resources • Very small footprint • • • into any application, accelerating the Gradient manager Custom widget integration Single window update • Open GL support • Dynamic themes • Multi-language capable deployment of the final product. • Written in C++ • Written in C++ • Written in ANSI C

Swell’s GUI software products work One of the smallest footprints and most efficient code bases available. hand in hand with Freescale customers’ Starting 225 KB Starting at 160 KB Starting at 90 KB real-time operating systems to Typical 225–250 KB Typical 160–175 KB Typical 90–110 KB incorporate LCD screens, display and input interfaces into future products.

GUI Interface Technology real-time operating systems, input • Enables hardware/software devices and LCD controllers by development to happen in parallel Application Layer replacing the underlining driver. • Made available for free evaluation PEG Library For more information visit Input PEG WindowBuilder for Driver LCD Driver freescale.com/peg. RTOS RTOS Rapid Development Driver LCD Driver WindowBuilder allows a designer to lay out each of the screens for a project GUI Interface Technology through a simple-to-use interface. PEG’s modular form enables a • Full WYSIWYG development rapid development process. The • Runs on PC/Linux/X11 to allow core library interfaces to different proof of concept development

46 Beyond Bits Vybrid Edition

Timesys LinuxLink Embedded Linux product development made easy

Timesys helps to eliminate the Timesys LinuxLink learning time, complexity and risk in building and maintaining embedded CHOOSE BUILD DEPLOY Linux devices. As a leader among Linux Kernel and Drivers Support • Latest open-source kernels TimeStorm IDE (Eclipse) • Web-based • ARM® and other architectures • In-person • Application development and debug embedded Linux solution providers, • Extensive SoC/device support • Extensive documentation • Fully integrated with Factory tools Timesys offerings are available for • Compatible with Eclipse ecosystem many Freescale processor families Development Tools/Libraries • Latest version of gcc, glibc, uClibc Your Custom Tools (SDK) including ColdFire, Kinetis, i.MX, • Tested on all supported SoCs • gcc/C library/gdb • Eclipse-based environment ® Factory Distribution Builder • Relevant application libraries Vybrid and Power Architecture based • Interactive UI with intelligent advice • Guides your selection of packages products. • Web (hosted) and desktop versions Your Custom Image (BSP) OS Apps and Middleware • Kernel/drivers • Rich selection of packages • Root file system Timesys offers the award-winning • Networking, industrial, consumer • Pre-built, tested, supported Work Orders Ready to run on LinuxLink embedded development your hardware Updates system, expert Linux support and Boot Loader • Automatic kernel updates • Automatic middleware updates • For supported reference platforms • Web-based and desktop notifications experienced professional services to • Industry-standard U-Boot • Latest open-source code base help development teams bring open source Linux-based products to LinuxLink Software Development Framework market faster and cheaper. semiconductor partners’ suggested relevant to the Linux components used With a LinuxLink subscription for your bootloader, saving time with initial in your software. Freescale processor, you can: board bring up. Unmetered Expert Linux Help • Quickly assemble and boot an initial Factory Distribution Builder As a LinuxLink subscriber, you’ll have embedded Linux image on your Timesys’s Factory Distribution Builder access to responsive technical support Freescale development kit. enables complete customization of from our expert engineers. Intuitive online • Patch/configure/rebuild/update your Linux platform and integration of support enables detailed information your custom Linux platform on your third-party and proprietary software. exchanges and allows you to submit, desktop with a properly installed Also includes innovative “advice” view and update requests, and access and configured development and “recommendation” engines to or reopen resolved requests. environment. minimize mistakes. • Debug/tune the platform with Get Your Free LinuxLink— common open source development TimeStorm IDE Build Your Custom BSP/SDK in Minutes tools and development libraries/ TimeStorm’s powerful suite of Register for a Free LinuxLink account, utilities. application development tools expertly handles embedded chores like cross- and assemble a Linux image that you • Obtain help with common compiling and remote debugging can download and run on your board. development tasks via technical while including support for advanced Register at timesys.com/register. assistance and a rich library of features like profiling, testing and leak Timesys-authored “How To” For more information about Timesys’s detection. And TimeStorm is built on documentation. LinuxLink embedded Linux build the Eclipse IDE foundation, a platform system, visit timesys.com/linuxlink. Key LinuxLink Components: already familiar to developers. Linux Kernel, Toolchain, Software Update Notifications Packages, Bootloader As a LinuxLink user, you’ll only receive All Timesys Linux platforms are built automatic notifications of updates and tested for compatibility with our freescale.com/Vybrid 47 Software and Development Tools

ARM® Development Studio 5 (DS-5) The reference software development tool suite for ARM powered platforms

Overview DS-5 Debugger and DSTREAM The ARM Development Studio 5 (DS-5™) is a complete suite of software development tools for ARM processor-based ASICs and standard devices, including Freescale’s Vybrid family. DS-5 accelerates software development by providing an easy-to-use, integrated and validated toolchain. Key Features and Benefits • Support for all ARM processors • Integration with the industry- standard Eclipse IDE, which provides a large ecosystem of third- party plug-ins • Flexible C/C++ editor and project manager • Powerful C/C++ compilation tools • Debugger supports all phases of development from bootloader to kernel, and user space DS-5 Debugger • Linux kernel and user space debug, • Streamline Performance Analyzer The DS-5 Debugger brings together including context awareness, provides system-wide profiling the convenience and productivity of process, and threads based on performance counters integrated embedded development • Non-intrusive instruction trace • Instant correlation of performance tools with the power and flexibility including summarized profile bottlenecks (cache misses, of open source tools for Linux and • Conditional and scripted interrupts) and software execution Android. breakpoints • Fast simulator for ARM software The DS-5 debugger provides: For expert Linux users, DS-5 includes development on the host computer the traditional GDB command line with typical speeds above 250 MHz • Debug of code generated by ARM and GNU Compile. interface for detailed control of • Support and maintenance contract target interactions and flexibility for one year • Advanced Session Control and System Views control multiple with scripting advanced debugger simultaneous debug sessions, functions. to one or more targets, from one debugger perspective • Run and stop mode debugging of single-core and multicore devices

48 Beyond Bits Vybrid Edition

Streamline: Timeline and Call Paths • Filtering capabilities to restrict the data set used by statistical reports

Timeline view shows process and thread over time and per-process, thread information over time, matched to SoC or call path performance counters. This enables you to spot thread deadlocks and inefficiencies, • Call paths view shows the processor as well as hot spots in time. time spent on each call tree. A flat report is generated for the selected call path, which enables you to focus the analysis of a process or thread • Code View highlights the hot spots within a function by displaying the processor time spent on each line of source code and on each disassembly instruction • Streamline Capture Options dialogue enables you to select the right

Call paths view shows the processor time balance between granularity and spent on each call tree. A flat profiling report is information detail, and intrusiveness generated for the selected call path, which enables you to focus the analysis on a process or thread. ARM C/C++ Compiler The ARM Compiler in DS-5 DSTREAM • Flexible trace clock positioning Professional Edition is the only The ARM DSTREAM™ high (relative to trace data) commercial compiler co-developed performance debug and trace unit • Large 4 GB trace buffer enables with the ARM processors and enables powerful software debug and long-term trace of fast targets specifically designed to optimally optimization on any ARM processor- support the ARM architecture. It is based hardware target. Streamline the industry standard C and C++ Streamline is the Linux and Android compiler for building applications DSTREAM enables the connection of performance analysis tool in DS-5. targeting the ARM, Thumb®, Thumb- DS-5 Debugger to ARM processor- Through a small driver running on the 2, VFP, and NEON™ instruction based devices via JTAG or serial-wire target, Streamline captures the target’s sets found in the newer Cortex™ debug. It uses FPGA acceleration to performance information and displays processor-based devices. deliver high download speeds and it in an easy to understand graphical ARM processors are designed to best fast stepping through code on single interface. Streamline includes: and multi-processor devices and execute code generated by the ARM • Intuitive display of information enables: Compiler. The ARM Compiler enables ranging from system-wide the new features in all the ARM • Run control debug and trace unit performance counters to hot processors. It supports building of supporting all ARM processors spots in the source code, making Symbian OS, ARM Linux, and Android • USB 2.0 and Ethernet interface it easy for developers to identify native applications and libraries, as allows direct and remote performance bottlenecks, multi- well as bare-metal applications and all connections from the host PC threading issues and general major RTOSs. • Code downloads at speeds of inefficient resource usage Learn more at arm.com/ds5. up to 2500 Kbps • Visualization tools to analyze per- • JTAG clocks of up to 60 MHz core performance metrics with provide fast software upload over threads and processes for optimal the existing debug port synchronization and concurrency of target’s resources • 16-bit wide trace capture at 300 MHz DDR (600 Mbit/s per pin) freescale.com/Vybrid 49 Software and Development Tools

IAR Embedded Workbench Powerful, reliable development tools

Continuing a long-standing IAR Embedded Workbench relationship with Freescale Semiconductor, IAR Systems® has announced that their flagship IAR Embedded Workbench® for ARM product supports Freescale’s new Vybrid devices based on the ARM Cortex-A5 and ARM Cortex-M4 cores. IAR Systems supports nearly the entire lineup of Freescale MCUs, including the S08, HCS12, ColdFire (and all its variants), the Kinetis MCUs based on an ARM Cortex-M4 core and now Vybrid devices. IAR Systems is proud to be allied with Freescale in bringing cutting-edge devices and tools to our mutual customers.

IAR Embedded Workbench for ARM is a highly efficient and independent toolchain that supports ARM architectures, including Vybrid devices. The Embedded Workbench for ARM includes IAR’s IDE, C/C++ Compiler, Assembler and Linker to give you unparalleled performance.

50 Beyond Bits Vybrid Edition

• Ease of use. IAR Embedded Developing your Vybrid device • Local support with global Workbench for ARM has over application is never easier than reach. IAR Systems has 10 2,500 example projects to help when you use IAR. offices worldwide (including three you get your project off the ground in the United States) and each • Integration to popular source- quickly. These examples are part one is staffed with capable and code control systems. If you are of the installation and are provided experienced engineers who are using Subversion or a Microsoft free of charge. ready to help you with any issues Visual Source Safe-compliant that arise. No other compiler • Support for all ARM hardware. control system, you can use the vendor can claim to have nearly as IAR Embedded Workbench for Embedded Workbench for ARM much assistance readily available. ARM includes support for the to check code in and out of the floating point DSP unit that is system to speed your development When considering which toolchain to available in many ARM Cortex-M4 process. use in your Vybrid design, consider cores. It also supports the ARM the one that was first to support • Kernel-aware debugging for most Cortex-A5 core and the NEON Kinetis MCUs, first to support Vybrid RTOSs. The C-SPY® debugger is instruction set that is the heart of devices, first in service and first in able to do task-aware debugging the Vybrid architecture. performance: choose IAR Embedded for many popular RTOSs including Workbench for ARM. • Tight code generation. The code MQX, Micrium uC/OS-II and –III, generated is highly optimized SMX, CMX, Quadros, Sciopta, For more information, please and IAR Systems encourages embOS, Express Logic’s ThreadX, email [email protected]. developers to try out one of the free Free/Safe RTOS and others. This versions (32 kB-limited KickStart awareness allows you to see what version or the 30-day evaluation is happening in your RTOS at a version) at iar.com/ewarm to glance. compare it to other compilers. • Power debugging. IAR Systems Prototype your code and see how has a unique power debugging much more efficient IAR is in your feature that allows you to see the design. power being consumed by your • An embedded compiler brings board when the board is powered you full C++. IAR Embedded by a J-Link Ultra. Making your Workbench for ARM brings design power-efficient used to you full desktop C++ (including be the domain of only hardware exception handling, multiple/virtual engineers, but IAR gives the ability inheritance, etc.) to help you cross- to software engineers as well. compile code and use the bevy of test suites available for the PC to validate and verify your design before it goes into the board.

freescale.com/Vybrid 51 Software and Development Tools

Atollic World-class tools for embedded systems development

Atollic tools provide you with powerful True Studio features that reduce your development time and enable you to release a software product with higher quality with less effort. Atollic aims to provide an embedded systems toolset that covers all work- tasks that embedded developers are doing on a day-to-day basis. The Atollic product portfolio not only covers great tools for editing, building and debugging but offers powerful solutions for team collaboration, system and code analysis as well as test automation.

TrueSTUDIO®: The Embedded Systems Development Tool for the Next Decade Atollic TrueSTUDIO is the premier C/C++ development tool for embedded systems development, with its unrivalled feature-set and formal coding standards, and coding TrueANALYZER®: Measure Test unprecedented integration. In addition constructs that are known to be error- Quality with Dynamic Execution to the state-of-the-art editor, the prone are detected automatically. Flow Analysis optimizing C/C++ compiler and Atollic TrueINSPECTOR supports the Atollic TrueANALYZER is a tool for multiprocessor-aware debugger with MISRA®-C:2004 rule standard. in-target measurement of test quality. tracing support, Atollic TrueSTUDIO The product performs system-level TrueVERIFIER™: Get Superior also includes features for team dynamic execution flow analysis and collaboration, graphical modeling Software Quality with Embedded Test Automation provides rigorous code coverage and design, code review and review measurements. Atollic TrueANALYZER Atollic TrueVERIFIER is a tool for meetings. supports many types of code advanced test automation. The coverage analysis up to the level of TrueINSPECTOR®: Improve product performs source code modified condition/decision coverage Software Quality with Static analysis and auto-generate unit-test (MC/DC-level), which is required by Source Code Analysis suites that exercise an extensive RTCA DO-178B (Level A) for flight- Atollic TrueINSPECTOR is a tool set of different execution paths. The control-system software. for professional code analysis. The tool downloads the test cases and product performs static source code runs them in a target board with For more information on Atollic tools, inspection and generates software code coverage monitoring. Finally, visit atollic.com. metrics including code complexity Atollic TrueVERIFIER visualizes the measurements. The source code is test results and the achieved code validated against a database of coverage (MC/DC-level).

52 Beyond Bits Vybrid Edition

Multilink and Cyclone Debug interfaces and production programming

P&E’s line of Multilinks and Cyclones Multilink Universal and Multilink When connected to a PC, the Cyclone are powerful solutions that cover the Universal FX Features can communicate via USB, Ethernet, complete product cycle. • Draws power from USB interface— or serial port, and its operations can no separate power supply required be completely automated. In stand- USB Multilink Debug • Target voltage: 1.6–5.25V alone mode, programming images are Interfaces • Includes a ribbon cable for each first loaded into on-board memory. P&E’s USB Multilinks are affordable, supported architecture An LCD screen and buttons allow development-oriented interfaces that one-touch programming operation • High-speed download (FX version) allow access to the debug interface on as well as configuration. P&E offers • Can provide target power (FX version) a target MCU from the user’s PC. The automation software packages new Multilink Universal and Multilink Supported Architectures allowing many Cyclone units to be Universal FX represent the next step “ganged” together. • Vybrid forward for this very successful line • Kinetis The Cyclone may also be used as a of hardware interfaces. They each hardware interface with many popular combine support, in a single interface, • ColdFire+, ColdFire V1–V4 debuggers, similar to the way a USB for many Freescale architectures, • HCS08, RS08, HC(S)12 Multilink is used, but also including including: Vybrid, Kinetis, HCS08, • DSC support for Ethernet and serial RS08, HC(S)12, ColdFire+/V1, ColdFire Software Support connections. V2-V4, Qorivva MPC55xx/56xx and • CodeWarrior IDE DSC. The FX version also provides Cyclone Features • P&E software (including much higher communications speeds • Stores multiple images for programmers and debuggers) for some architectures (up to a 10x programming speed improvement), and can be used • Software tools from IAR, Keil, • Can be fully automated and to power the target device. These Mentor Graphics, Cosmic, controlled from a PC “universal” Multilinks include ribbon and others. Support varies by • Can be controlled via buttons/ cables to allow connections to all of architecture. Contact vendor to display without a PC the supported architectures. The user determine compatibility. can simply flip open the hinged section • Display for image selection, status, on the Multilink case and install the Cyclone Production and settings appropriate ribbon cable. Programmers • Can provide/switch power to target P&E’s Cyclone products are geared • High-speed programming Multilink and Cyclone towards in-circuit production • Multiple units may be “ganged” for programming, including both parallel programming low-volume, operator-controlled • Support for dynamic data, including programming and high-volume serialization automated programming. The Cyclone • May be used as a debug interface can be used to program both internal with many debuggers memory on a Freescale processor/ MCU as well as external memory connected to the processor’s address/ For more information, visit data bus. The processor can be pemicro.com. mounted on the final printed circuit board before programming and does not need to be pre-programmed. freescale.com/Vybrid 53 Software and Development Tools

SEGGER: J-Link and Flasher Convenient development and production programming

Designed using SEGGER’s industry- SEGGER Debug Probes and Production Flash Programmer leading embedded software, J-Link debug probes offer a wide array of J-Link advanced features and boast support for a broad spectrum of MCUs and Intelligent MPUs, including Freescale’s complete i.MX, Kinetis and ColdFire V2–V4 Debugging via lines. Many popular IDEs such as CodeWarrior, IAR, Keil, Code Sourcery JTAG/SWD V2–V4 and more have built-in support • Robust communication for the J-Link. • Very high performance The J-Link debug line offers a high (download speed up to 1.5 MB)* download speed into RAM* and flash • Unlimited flash breakpoints memory. Each JTAG debugger hardware (license required) model has its own unique attributes and offers a number of available software add-on modules to enhance the J-Link’s RDI, J-Flash and GDB Server, providing Flasher for Production Flash functionality. For more details, visit the optimum debugging solution for the Programming and in the Field segger.com/jlink.html. professional developer. Services The in-circuit programmer (Flasher J-Flash is a comprehensive user J-Link ULTRA for High Performance ARM) is a superset of the J-Link DDL. interface for flash programming. The J-Link ULTRA is based on the highly It contains all of the debug probe flash breakpoint add-on allows for optimized and proven J-Link. It offers features, while being designed for use an unlimited number of breakpoints even higher speed as well as target in a production environment. Different while debugging in flash memory. The power measurement capabilities due to interfaces, like the command line J-Link SDK is a standard Windows the faster CPU, built-in FPGA and High- interface or the optionally available DLL typically used from C. It makes Speed USB interface. This permits you SDK, allow an easy integration into any the entire functionality of the J-Link to take full advantage of the low power production environment. available through the exported features offered by today’s modern functions and allows you to write your cores. J-Link Ultra raises the bar, aiming The Flasher ARM has on-board own program using J-Link. to be the fastest emulator available. memory to store your binary image, permitting simple stand-alone flash Hardware Models J-Trace for Cortex-M for programming. This is particularly useful Post-Mortem Analysis J-Link Pro for Connectivity for support teams that have to upgrade J-Link Pro is an enhanced version of J-Trace for ARM Cortex-M is a JTAG devices out in the field. They only need the J-Link. It incorporates an on-board probe which includes trace (ETM) to carry a small box which is readily Ethernet interface in addition to the support. J-Trace assists the developer configured to perform the update once USB, as well as two LED hardware in analyzing his target system’s it is connected to the target system. status indicators. It comes with licenses behavior. The 4 MB trace memory For more details, visit segger.com/ for all J-Link related SEGGER software provides plenty of space to store the flasherarm.html. products, including flash breakpoints, last executed functions. This allows you to find out how the program arrived at a *The regular J-Link performs with an already high certain position in code, which is either 750 Kbps, J-Link Ultra allows an even faster peak download speed of 1.5 Mbps not expected or wanted. 54 Beyond Bits Vybrid Edition

SEGGER: RTOS, GUI and Middleware Embedded software for the professional developer

SEGGER offers a feature rich, high SEGGER RTOS, GUI and Middleware performance RTOS, GUI, and family of middleware (file system, USB host and device, IP stack), all of which adhere to strict, yet efficient coding and documentation standards. The software is very easy to use and works out of the box. BSPs and projects for popular eval boards and tool chains are available, including BSPs for the popular Freescale based designs. SEGGER offers very flexible license models to meet any size project’s needs. and ROM, as well as high speed and common USB devices are available. It Embedded Graphics versatility. Throughout the development can be used with USB 1.1.or USB 2.0 Package (emWin) process of embOS, the limited Full- and High-Speed devices. emUSB emWin is a professional graphical resources of MCUs have always been supports, among others, the HID, user interface (GUI) for any application kept in mind. The internal structure CDC, MSD, MSD-CDROM, printer and that operates with a graphical LCD. of embOS has been optimized for custom bulk communication classes. For fast user interface development a variety of applications for different emUSB-Host is the counterpart of emWin provides a GUI-Builder software customers, to fit the needs of different emUSB-Device and supports HID, and an extensive widget selection. industries. embOS is fully source- CDC (and FTDI), MSD, printer and emWin is part of SEGGER’s complete compatible on different platforms custom bulk communication classes. middleware solution. Additionally, (8/16/32-bit), making it easy to port emWin is compatible with; polled, applications to different CPUs. Its’ Embedded IP Stack single-task, and multitask environments, highly modular structure ensures that (embOS/IP) with a proprietary operating system only those functions that are needed embOS/IP is a TCP/IP stack that or with any commercial RTOS. It is are linked, keeping the ROM size very provides a small memory footprint shipped as C source code and may small. We took full advantage of our for high-performance embedded be adapted to any size physical and partnership with Freescale by utilizing networking solutions. The stack has virtual display with any LCD controller their expertise and knowledge of their been optimized for use in real-time, and CPU. emWin can be optimized to hardware while adding support for memory-constrained embedded run on very low resources. For more Vybrid devices. This permits you to take systems. It offers RFC-compliant TCP/ details, visit segger.com/emwin.html. full advantage of our software offering IP and a standard socket API. embOS/ while being assured that it has been IP works seamlessly with the embOS RTOS (embOS) developed to the highest standards operating system. Additional higher embOS is a priority-controlled real time and optimized to the fullest. For more level protocols like SMTP, FTP and operating system, designed to be used details, visit segger.com/embos.html. HTTP are also available. On the link as a foundation for the development layer, embOS/IP supports PPP to ease of embedded real-time applications. Embedded USB Stacks the integration of M2M-communication. It is a zero interrupt latency (high (emUSB-Device and For more details, visit segger.com/ priority interrupts are never disabled emUSB-Host) embedded-software.html. by embOS), high-performance RTOS emUSB-Device has been designed to that has been optimized for minimum work on any embedded system with a memory consumption in both RAM USB device controller. Ports for most freescale.com/Vybrid 55 Software and Development Tools

Lauterbach TRACE32® PowerTools

Lauterbach offers the world’s most TRACE32 Debugger advanced and complete debug environment. With more than 30 years of experience, Lauterbach’s TRACE32 product line has accumulated an arsenal of analysis tools suitable for most debug and testing requirements. These tools range from traditional source code debug to statistical analysis, code coverage, charting and profiling of your code execution.

With much experience supporting the various ARM core architectures, including ARM Cortex-A, ARM Cortex-R, ARM Cortex-M, and other Coresight components, Lauterbach is proud to announce support for the latest ARM Cortex-M4/Cortex-A5 TRACE32® Debugger for ARM Cortex™-M or ARM Cortex™-A/R based Freescale Vybrid devices. Offering a 4-bit ETM trace port, the Vybrid part unleashes many of the advanced analysis features offered by the Lauterbach TRACE32 debugger, at a reasonable price point. There are several levels of debugger support, with or without support for the ETM trace. TRACE32 Debugger for ARM Cortex-M or ARM Cortex-A/R Hardware Configuration JTAG Debugger Features The tools for the ARM Cortex-M/ The PowerDebug for the ARM • Supports JTAG, SWD and cJTAG Cortex-A/R processor family Cortex-M processor family consists of: • C and C++ support for all standard are designed as an open debug • A high-speed debug hardware compilers environment that offers sophisticated module features for quick and effective testing • Full and intuitive support of the • A debug cable for the ARM Cortex-M of your embedded design. It now on-chip debug unit or ARM Cortex-A/R devices supports the latest Freescale Vybrid • RTOS awareness for all commonly A USB2.0 or Ethernet interface devices with the ARM Cortex-M4/ available RTOS is provided as host interface to Cortex-A5 core. • Real-time memory access via DAP PC Windows, PC Linux or any • Flash programming support workstation. • Multicore debugging

56 Beyond Bits Vybrid Edition

TRACE32 CombiProbe TRACE32® CombiProbe for ARM Cortex-M for ARM Cortex-M TRACE32 JTAG debuggers can be extended with the CombiProbe which adds 4-bit ETM real time trace capabilities to the debugger, enabling the industry’s finest code analysis and profiling tools.

CombiProbe Hardware Configuration The CombiProbe PowerDebug for ARM Cortex-M processor family consists of: • High-speed debug hardware module TRACE32® PowerTrace for ARM Cortex-A/R or ARM Cortex-M • CombiProbe debug cable for recording the 4-bit ETM v3.x in continuous mode • License for ARM Cortex-M debugging A USB2.0 or Ethernet interface is provided as host interface to PC Windows, PC Linux or any work station. The product also includes CoreSight Single Wire Viewer.

CombiProbe Features

• Up to 128 MB trace entries analysis and profiling tools.This • Trace port rates up to 600 MHz at • Trace port rates up to 200 Mbps configuration supports all modes of 4/8/16/32-bit trace widths • Real-time profiling the ETM trace port. • Real-time profiling • Long-time trace PowerTrace Hardware • Long-time trace • Energy profiling Configuration • Energy profiling • Re-debugging of all sampled The PowerTrace for ARM Cortex-M • Re-debugging of all sampled program steps (CTS) processor family consists of: program steps (CTS) • Trace filter and trigger • High-speed debug hardware • Trace filter and trigger • Run time analysis of functions and module • Run time analysis of functions and tasks • PowerTrace module for recording tasks • Code coverage and variable analysis 4/8/16/32-bit ETM real-time trace • Code coverage and variable analysis • Multicore debugging • Debug cable for Cortex-A/R or • Multicore debugging Cortex-M debugging TRACE32 PowerTrace For more information about TRACE32 A USB2.0 or Ethernet interface is tools, visit lauterbach.com. for ARM Cortex-A/R or provided as host interface to PC ARM Cortex-M Windows, PC Linux or any workstation. TRACE32 JTAG debuggers can be extended with the PowerTrace which PowerTrace Features adds 4/8/16/32-bit ETM real-time • Up to 4 GB trace entries (also, trace capabilities to the debugger, streaming to host for recording enabling the industry’s finest code longer run times) freescale.com/Vybrid 57

For more information, visit freescale.com/Vybrid

Freescale, the Freescale logo, CodeWarrior, ColdFire, Kinetis, PowerQUICC, and Qorivva are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Vybrid, Tower and Xtrinsic are trademarks of Freescale Semiconductor, Inc. ARM is the registered trademark of ARM Limited. ARM9, ARM11, ARM Cortex-A5, ARM Cortex-A9, ARM Cortex-M3, ARM Cortex-M4 and DS-5 are trademarks of ARM Limited. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2012, 2013 Freescale Semiconductor, Inc. Document Number: VYBRIDBYNDBITS REV 1