DOCSLIB.ORG

Safety Standards and WCET Analysis Tools Daniel Kästner, Christian Ferdinand

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Safety Standards and WCET Analysis Tools Daniel Kästner, Christian Ferdinand Safety Standards and WCET Analysis Tools Daniel Kästner, Christian Ferdinand To cite this version: Daniel Kästner, Christian Ferdinand. Safety Standards and WCET Analysis Tools. Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France. hal-02192406 HAL Id: hal-02192406 https://hal.archives-ouvertes.fr/hal-02192406 Submitted on 23 Jul 2019 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Safety Standards and WCET Analysis Tools Daniel Kastner¨ Christian Ferdinand AbsInt GmbH, Science Park 1, D-66123 Saarbrucken,¨ Germany http://www.absint.com Abstract of-the-art techniques for verifying software safety re- quirements have to be applied to make sure that an appli- In automotive, railway, avionics, automation, and cation is working properly. To do so lies in the responsi- healthcare industries more and more functionality is im- bility of the system designers. Ensuring software safety plemented by embedded software. A failure of safety- is one of the goals of safety standards like DO-178B, critical software may cause high costs or even endan- DO-178C, IEC-61508, ISO-26262, or EN-50128. They ger human beings. Also for applications which are not all require to identify functional and non-functional haz- highly safety-critical, a software failure may necessitate ards and to demonstrate that the software does not vio- expensive updates. late the relevant safety goals. Contemporary safety standards – including DO-178B, Classical software validation methods like code review DO-178C, IEC-61508, ISO-26262, and EN-50128 – re- and testing with debugging cannot really guarantee the quire to identify potential functional and non-functional absence of errors. Formal verification methods provide hazards and to demonstrate that the software does not vi- an alternative, in particular for safety-critical applica- olate the relevant safety goals. For ensuring functional tions. One such method is abstract interpretation [2], program properties automatic or model-based testing, which allows to obtain statements that are valid for all and formal techniques like model checking become program runs with all inputs. Such statements may be more and more widely used. For non-functional prop- absence of violations of timing or space constraints, or erties like timing identifying a safe end-of-test crite- absence of runtime errors. Static analysis tools in indus- rion is a hard problem since failures usually occur in trial use can detect stack overflows, violation of timing corner cases and full test coverage cannot be achieved. constraints [20], and can prove the absence of runtime For code-level timing analysis this problem is solved by errors [4]. abstract-interpretation-based static analysis techniques The advantage of static analysis based techniques is that which provide full coverage and yield provably correct they enable full test coverage, but at the same time can results. reduce the test effort. Identifying end-of-test criteria In this article we focus on static analyses of worst- for non-functional program properties like timing, stack case execution time, which are increasingly adopted by size, and runtime errors is an unsolved problem. In con- industry in the validation and certification process for sequence, the required test effort is high, the tests re- safety-critical software. First we will give an overview quire access to the physical hardware and the results are of the most important safety standards with a focus not complete. In contrast, static analyses can be run by on the requirements for non-functional software prop- software developers from their workstation computer, erties. We then explain the methodology of abstract- they can be integrated in the development process, e.g., interpretation-based analysis tools and identify crite- in model-based code generators, and allow developers to ria for their successful application. The integration of detect runtime errors as well as timing and space bugs static analyzers in the development process requires in- in early product stages. terfaces to other development tools, like code genera- From a methodological point of view, static analyses can tors or scheduling tools. Using them for certification re- be seen as equivalent to testing with full coverage and, quires an appropriate tool qualification. We will address as such, are candidates for meeting all testing require- each of these topics and report on industrial experience. ments listed in the above-mentioned standards. Thus, in the areas where validation by static analysis is tech- nically feasible and applied in industry, e.g., for worst- 1 Introduction case execution time analysis, stack size analysis or run- time error analysis, it defines the state-of-the-art testing The use of safety-critical embedded software in the au- technology. tomotive, avionics and healthcare industries is increas- In the following we will give an overview of the most ing rapidly. Failures of such safety-critical embedded important safety standards with a focus on the require- systems may create high costs or even endanger hu- ments for timing. Then we explain the basic methodol- man beings. Also for applications which are not highly ogy of static worst-case execution time (WCET) analy- safety-critical, a software failure may necessitate expen- sis and present the underlying concepts of our aiT tool. sive updates. Therefore, utmost carefulness and state- Industrial experience is summarized in Sec.7. 1 2 Safety Standards cution time. The DO-178C, due to be finalized in 2011, will be a re- Safety standards like DO-178B [18], DO-178C, IEC- vision of DO-178B to bring it up to date with respect 61508 [14], ISO-26262 [15] and EN-50128 [1] require to current software development and verification tech- to identify functional and non-functional hazards and to nologies. It specifically focuses on model-based soft- demonstrate that the software does not violate the rel- ware development, object-oriented software, the use and evant safety goals. These standards mention explicitly qualification of software tools and the use of formal three important non-functional safety-relevant software methods to complement or replace dynamic testing (the- characteristics: Absence of runtime errors, execution orem proving, model checking, and abstract interpreta- time, and memory consumption. In the following, we tion). will focus on execution time. Depending on the critical- ity level of the software the absence of safety hazards 2.2 IEC-61508 Edition 2.0 has to be demonstrated by formal methods or testing with sufficient coverage. In 2010 a new revision of the functional safety stan- In the following, we give a short overview on the as- dard IEC-61508 has been published, called Edition 2.0 sessment of timing properties by the safety standards [14]. It sets out a generic approach for all safety lifecy- for avionics, space, automotive and railway systems, cle activities for systems comprised of electrical and/or for general Electric/Electronic systems, and for medical electronic and/or programmable electronic (E/E/PE) el- software products. ements that are used to perform safety functions. The safety integrity levels are called SIL1 (least critical) to SIL4 (most critical). The timing properties are part of 2.1 DO-178B/DO-178C the software safety requirements specification and list response time and best case and worst-case execution Published in 1992, the DO-178B [18] (“Software Con- time. siderations in Airborne Systems and Equipment Certi- The IEC-61508 states that verification includes test- fication”), is the primary document by which the cer- ing and analysis. In the software verification stage, tification authorities such as FAA, EASA, and Trans- static analysis techniques are recommended for SIL1 port Canada will approve all commercial software-based and highly recommended for SIL2-SIL4. Among these aerospace systems. The purpose of D0-178B is “to pro- techniques, static worst-case execution time analysis is vide guidelines for the production of software for air- recommended in SIL1-4. Among the criteria to be con- borne systems and equipment that performs its intended sidered for selecting specific techniques is the complete- function with a level of confidence in safety that com- ness and repeatability of testing, so where testing is plies with airworthiness requirements.” The criticality used, completeness has to be demonstrated. The results levels defined are Level A (most critical) to Level E of abstract-interpretation-based static analyses are con- (least critical). sidered a mathematical proof; their reliability is rated The DO-178B emphasizes the importance of software maximal (R3). The IEC-61508 also provides require- verification. Verification is defined as a technical as- ments for mixed-criticality systems: “Where the soft- sessment of the results of both the software development ware is to implement safety functions of different safety processes and the software verification process. Sec. 6.0 integrity levels, then all of the software shall be treated of the DO-178B states that “verification is not simply as belonging to the highest safety integrity level, unless testing. Testing, in general, cannot show the absence of adequate independence between the safety functions of errors.” The standard consequently uses the term ”ver- the different safety integrity levels can be shown in the ify” instead of ”test” when the software verification pro- design. It shall be demonstrated either (1) that inde- cess objectives being discussed are typically a combina- pendence is achieved by both in the spatial and tempo- tion of reviews, analyses and test.
Load more

Recommended publications
  • Experiments in Validating Formal Semantics for C
    Experiments in validating formal semantics for C Sandrine Blazy ENSIIE and INRIA Rocquencourt [email protected] Abstract. This paper reports on the design of adequate on-machine formal semantics for a certified C compiler. This compiler is an optimiz- ing compiler, that targets critical embedded software. It is written and formally verified using the Coq proof assistant. The main structure of the compiler is very strongly conditioned by the choice of the languages of the compiler, and also by the kind of semantics of these languages. 1 Introduction C is still widely used in industry, especially for developing embedded software. The main reason is the control by the C programmer of all the resources that are required for program execution (e.g. memory layout, memory allocation) and that affect performance. C programs can therefore be very efficient, but the price to pay is a programming effort. For instance, using C pointer arithmetic may be required in order to compute the address of a memory cell. However, a consequence of this freedom given to the C programmer is the presence of run-time errors such as buffer overflows and dangling pointers. Such errors may be difficult to detect in programs, because of C type casts and more generally because the C type system is unsafe. Many static analysis tools attempt to detect such errors in order to ensure safety properties that may be ensured by more recent languages such as Java. For instance, CCured is a program transformation system that adds memory safety guarantees to C programs by verifying statically that memory errors cannot oc- cur and by inserting run-time checks where static verification is insufficient [1].
    [Show full text]
  • Introduction to Model Checking and Temporal Logic¹
    Formal Verification Lecture 1: Introduction to Model Checking and Temporal Logic¹ Jacques Fleuriot [email protected] ¹Acknowledgement: Adapted from original material by Paul Jackson, including some additions by Bob Atkey. I Describe formally a specification that we desire the model to satisfy I Check the model satisfies the specification I theorem proving (usually interactive but not necessarily) I Model checking Formal Verification (in a nutshell) I Create a formal model of some system of interest I Hardware I Communication protocol I Software, esp. concurrent software I Check the model satisfies the specification I theorem proving (usually interactive but not necessarily) I Model checking Formal Verification (in a nutshell) I Create a formal model of some system of interest I Hardware I Communication protocol I Software, esp. concurrent software I Describe formally a specification that we desire the model to satisfy Formal Verification (in a nutshell) I Create a formal model of some system of interest I Hardware I Communication protocol I Software, esp. concurrent software I Describe formally a specification that we desire the model to satisfy I Check the model satisfies the specification I theorem proving (usually interactive but not necessarily) I Model checking Introduction to Model Checking I Specifications as Formulas, Programs as Models I Programs are abstracted as Finite State Machines I Formulas are in Temporal Logic 1. For a fixed ϕ, is M j= ϕ true for all M? I Validity of ϕ I This can be done via proof in a theorem prover e.g. Isabelle. 2. For a fixed ϕ, is M j= ϕ true for some M? I Satisfiability 3.
    [Show full text]
  • PROGRAM VERIFICATION Robert S. Boyer and J
    PROGRAM VERIFICATION Robert S. Boyer and J Strother Moore To Appear in the Journal of Automated Reasoning The research reported here was supported by National Science Foundation Grant MCS-8202943 and Office of Naval Research Contract N00014-81-K-0634. Institute for Computing Science and Computer Applications The University of Texas at Austin Austin, Texas 78712 1 Computer programs may be regarded as formal mathematical objects whose properties are subject to mathematical proof. Program verification is the use of formal, mathematical techniques to debug software and software specifications. 1. Code Verification How are the properties of computer programs proved? We discuss three approaches in this article: inductive invariants, functional semantics, and explicit semantics. Because the first approach has received by far the most attention, it has produced the most impressive results to date. However, the field is now moving away from the inductive invariant approach. 1.1. Inductive Assertions The so-called Floyd-Hoare inductive assertion method of program verification [25, 33] has its roots in the classic Goldstine and von Neumann reports [53] and handles the usual kind of programming language, of which FORTRAN is perhaps the best example. In this style of verification, the specifier "annotates" certain points in the program with mathematical assertions that are supposed to describe relations that hold between the program variables and the initial input values each time "control" reaches the annotated point. Among these assertions are some that characterize acceptable input and the desired output. By exploring all possible paths from one assertion to the next and analyzing the effects of intervening program statements it is possible to reduce the correctness of the program to the problem of proving certain derived formulas called verification conditions.
    [Show full text]
  • Formal Verification, Model Checking
    Introduction Modeling Specification Algorithms Conclusions Formal Verification, Model Checking Radek Pel´anek Introduction Modeling Specification Algorithms Conclusions Motivation Formal Methods: Motivation examples of what can go wrong { first lecture non-intuitiveness of concurrency (particularly with shared resources) mutual exclusion adding puzzle Introduction Modeling Specification Algorithms Conclusions Motivation Formal Methods Formal Methods `Formal Methods' refers to mathematically rigorous techniques and tools for specification design verification of software and hardware systems. Introduction Modeling Specification Algorithms Conclusions Motivation Formal Verification Formal Verification Formal verification is the act of proving or disproving the correctness of a system with respect to a certain formal specification or property. Introduction Modeling Specification Algorithms Conclusions Motivation Formal Verification vs Testing formal verification testing finding bugs medium good proving correctness good - cost high small Introduction Modeling Specification Algorithms Conclusions Motivation Types of Bugs likely rare harmless testing not important catastrophic testing, FVFV Introduction Modeling Specification Algorithms Conclusions Motivation Formal Verification Techniques manual human tries to produce a proof of correctness semi-automatic theorem proving automatic algorithm takes a model (program) and a property; decides whether the model satisfies the property We focus on automatic techniques. Introduction Modeling Specification Algorithms Conclusions
    [Show full text]
  • Formal Verification of Diagnosability Via Symbolic Model Checking
    Formal Verification of Diagnosability via Symbolic Model Checking Alessandro Cimatti Charles Pecheur Roberto Cavada ITC-irst RIACS/NASA Ames Research Center ITC-irst Povo, Trento, Italy Moffett Field, CA, U.S.A. Povo, Trento, Italy mailto:[email protected] [email protected] [email protected] Abstract observed system. We propose a new, practical approach to the verification of diagnosability, making the following contribu• This paper addresses the formal verification of di• tions. First, we provide a formal characterization of diagnos• agnosis systems. We tackle the problem of diagnos• ability problem, using the idea of context, that explicitly takes ability: given a partially observable dynamic sys• into account the run-time conditions under which it should be tem, and a diagnosis system observing its evolution possible to acquire certain information. over time, we discuss how to verify (at design time) Second, we show that a diagnosability condition for a given if the diagnosis system will be able to infer (at run• plant is violated if and only if a critical pair can be found. A time) the required information on the hidden part of critical pair is a pair of executions that are indistinguishable the dynamic state. We tackle the problem by look• (i.e. share the same inputs and outputs), but hide conditions ing for pairs of scenarios that are observationally that should be distinguished (for instance, to prevent simple indistinguishable, but lead to situations that are re• failures to stay undetected and degenerate into catastrophic quired to be distinguished. We reduce the problem events). We define the coupled twin model of the plant, and to a model checking problem.
    [Show full text]
  • Theorem Proving for Verification
    Theorem Proving for Verification John Harrison Intel Corporation CAV 2008 Princeton 9th July 2008 0 Formal verification Formal verification: mathematically prove the correctness of a design with respect to a mathematical formal specification. Actual requirements 6 Formal specification 6 Design model 6 Actual system 1 Essentials of formal verification The basic steps in formal verification: Formally model the system • Formalize the specification • Prove that the model satisfies the spec • But what formalism should be used? 2 Some typical formalisms Propositional logic, a.k.a. Boolean algebra • Temporal logic (CTL, LTL etc.) • Quantifier-free combinations of first-order arithmetic theories • Full first-order logic • Higher-order logic or first-order logic with arithmetic or set theory • 3 Expressiveness vs. automation There is usually a roughly inverse relationship: The more expressive the formalism, the less the ‘proof’ is amenable to automation. For the simplest formalisms, the proof can be so highly automated that we may not even think of it as ‘theorem proving’ at all. The most expressive formalisms have a decision problem that is not decidable, or even semidecidable. 4 Logical syntax English Formal false ⊥ true ⊤ not p p ¬ p and q p q ∧ p or q p q ∨ p implies q p q ⇒ p iff q p q ⇔ for all x, p x. p ∀ there exists x such that p x. p ∃ 5 Propositional logic Formulas built up from atomic propositions (Boolean variables) and constants , using the propositional connectives , , , and ⊥ ⊤ ¬ ∧ ∨ ⇒ . ⇔ No quantifiers or internal structure to the atomic propositions. 6 Propositional logic Formulas built up from atomic propositions (Boolean variables) and constants , using the propositional connectives , , , and ⊥ ⊤ ¬ ∧ ∨ ⇒ .
    [Show full text]
  • QWIRE Practice: Formal Verification of Quantum Circuits In
    WIRE Practice: Formal Verification of Quantum Circuits in Coq Q Robert Rand Jennifer Paykin Steve Zdancewic [email protected] [email protected] [email protected] University of Pennsylvania We describe an embedding of the QWIRE quantum circuit language in the Coq proof assistant. This allows programmers to write quantum circuits using high-level abstractions and to prove properties of those circuits using Coq’s theorem proving features. The implementation uses higher-order abstract syntax to represent variable binding and provides a type-checking algorithm for linear wire types, ensuring that quantum circuits are well-formed. We formalize a denotational semantics that interprets QWIRE circuits as superoperators on density matrices, and prove the correctness of some simple quantum programs. 1 Introduction The last few years have witnessed the emergence of lightweight, scalable, and expressive quantum cir- cuit languages such as Quipper [10] and LIQUiS⟩ [22]. These languages adopt the QRAM model of quantum computation, in which a classical computer sends instructions to a quantum computer and re- ceives back measurement results. Quipper and LIQUiS⟩ programs classically produce circuits that can be executed on a quantum computer, simulated on a classical computer, or compiled using classical tech- niques to smaller, faster circuits. Since both languages are embedded inside general-purpose classical host languages (Haskell and F#), they can be used to build useful abstractions on top of quantum circuits, allowing for general purpose quantum programming. As is the case with classical programs, however, quantum programs in these languages will invariably have bugs. Since quantum circuits are inherently expensive to run (either simulated or on a real quantum computer) and are difficult or impossible to debug at runtime, numerous techniques have been developed to verify properties of quantum programs.
    [Show full text]
  • Overview on Formal Verification  State of the Art in Formal Verification  Ingredients in Formal Verification  Classification
    Outline Overview on Formal Verification State of the art in Formal Verification Ingredients in Formal Verification Classification P.Camurati G.Cabodi S.Nocco S.Quer Formal Methods Group Department of Computer Engineering Politecnico di Torino Torino, Italy 2 Outline Simulation: The Current Picture State of the art in Formal Verification Ingredients in Formal Verification Classification Hard to generate high quality input stimuli . A lot of user effort . No formal way to identify unexercised aspects No good measure of comprehensiveness of validation . Low bug detection rate is the main criterion . Only means that current method of stimulus generation is not achieving more. 3 Formal Verification: An Alternative to Simulation! Formal Verification is the process of constructing a proof that a target system will behave in accordance with its specification . Use of mathematical reasoning to prove that an implementation satisfies a specification . Like a mathematical proof: correctness of a formally verified hardware design holds regardless of input values . Consideration of all cases is implicit in formal verification Must establish . A formal specification (properties or high-level behavior) . A formal description of the implementation (design at higher level of abstraction — model (observationally) equivalent to implementation or implied by implementation). Formal Verification: Pros Formal Verification: Cons Just because we have proved something correct does not Complete with respect to a given property mean it will work! Correctness
    [Show full text]
  • A Case Study on Formal Verification of the Anaxagoros Hypervisor Paging System with Frama-C Allan Blanchard, N
    A case study on formal verification of the anaxagoros hypervisor paging system with frama-C Allan Blanchard, N. Kosmatov, M. Lemerre, Frédéric Loulergue To cite this version: Allan Blanchard, N. Kosmatov, M. Lemerre, Frédéric Loulergue. A case study on formal verification of the anaxagoros hypervisor paging system with frama-C. FMICS 2015 - Formal Methods for Industrial Critical Systems, Jun 2015, Oslo, Norway. pp.15-30, 10.1007/978-3-319-19458-5_2. cea-01834977 HAL Id: cea-01834977 https://hal-cea.archives-ouvertes.fr/cea-01834977 Submitted on 11 Jul 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. A Case Study on Formal Verification of the Anaxagoros Hypervisor Paging System with Frama-C? Allan Blanchard1;3, Nikolai Kosmatov1, Matthieu Lemerre1, and Fr´ed´ericLoulergue2;3 1 CEA, LIST, Software Reliability Laboratory, PC 174, 91191 Gif-sur-Yvette France [email protected] 2 Inria πr2, PPS, Univ Paris Diderot, CNRS, Paris, France 3 Univ Orl´eans,INSA Centre Val de Loire, LIFO EA 4022, Orl´eans,France [email protected] Abstract. Cloud hypervisors are critical software whose formal verifi- cation can increase our confidence in the reliability and security of the cloud.
    [Show full text]
  • Overview of Formal Methods in Software Engineering
    Overview of formal methods in software engineering IOANA RODHE, MARTIN KARRESAND FOI, Swedish Defence Research Agency, is a mainly assignment-funded agency under the Ministry of Defence. The core activities are research, method and technology development, as well as studies conducted in the interests of Swedish defence and the safety and security of society. The organisation employs approximately 1000 personnel of whom about 800 are scientists. This makes FOI Sweden’s largest research institute. FOI gives its customers access to leading-edge expertise in a large number of fi elds such as security policy studies, defence and security related analyses, the assessment of various types of threat, systems for control and management of crises, protection against and management of hazardous substances, IT security and the potential offered by new sensors. FOI Swedish Defence Research Agency Phone: +46 8 555 030 00 www.foi.se FOI-R--4156--SE SE-164 90 Stockholm Fax: +46 8 555 031 00 ISSN 1650-1942 December 2015 Ioana Rodhe, Martin Karresand Overview of formal methods in software engineering Bild/cover: Martin Karresand FOI-R--4156--SE Titel Översikt över formella metoder i programvaruutveckling Title Overview of formal methods in software engineering Report no FOI-R--4156--SE Month December Year 2015 Pages 50 ISSN ISSN-1650-1942 Customer The Swedish Armed Forces Project no E36077 Approved by Christian Jönsson Division Information- and Aeronautical Systems FOI Research area Armed Forces R&T area Command and control FOI Swedish Defence Research Agency This work is protected under the Act on Copyright in Literary and Artistic Works (SFS 1960:729).
    [Show full text]
  • Reflections on Industrial Use of Frama-C
    Reflections on Industrial Use of Frama-C Joseph R. Kiniry and Daniel M. Zimmerman Sound Static Analysis for Security Workshop NIST — Gaithersburg, Maryland — 28 June 2018 About Galois • established in 1999 to apply functional programming and formal methods to the problem of information assurance • over 40 active projects for numerous clients, both U.S. government (NSA, DARPA, IARPA, Homeland Security, Air Force Research Lab) and commercial (Amazon, LG, others) • over the years, we have substantially broadened our scope to high assurance everything ‹#› © 2018 Galois, Inc. !2 © 2018 Galois, Inc. Galois and Frama-C • Galois has used Frama-C on some projects • DARPA Crowdsourced Formal Verification • WP plugin to generate verification conditions • custom plugins to generate schematic assertions and program traces • DARPA SHAVE • Our clients rarely ask for formal verification in Frama-C’s “sweet spot”‹#› © 2018 Galois, Inc. !3 © 2018 Galois, Inc. SHAVE: Software/Hardware Assurance Verified End-to-End • DARPA MTO seedling for the SSITH program • a bump-in-wire encryption device • single, one-time AES key provisioning • encryption or decryption mutual exclusion • open hardware, firmware, and software • crypto realized as a MMIO RISC-V extension • custom development of a verification system for Bluespec hardware description language ‹#› © 2018 Galois, Inc. !4 © 2018 Galois, Inc. SHAVE Assurance Concept Silicon Verilog Informal Architec- BSV Netlist GDSII Artifacts RTL specs ture spec spec spec spec spec Refinement manual design automatic synthesis and manual design Technology Today's manual inspection, runtime testing, Assurance manual inspection model checking, formal verification Technique SHAVE formal verification that produces independently verifiable claims and proofs Assurance ‹#› © 2018 Galois, Inc.
    [Show full text]
  • A Formally-Verified C Static Analyzer
    A Formally-Verified C Static Analyzer Jacques-Henri Jourdan Vincent Laporte Sandrine Blazy Inria Paris-Rocquencourt IRISA and U. Rennes 1 IRISA and U. Rennes 1 [email protected] [email protected] [email protected] tifact r Comp Xavier Leroy David Pichardie * let * A t e n * te A is W s E * e n l l C o L D C o P * * Inria Paris-Rocquencourt IRISA and ENS Rennes c u e m s O E u e e P n R t v e o d t * y * s E a [email protected] [email protected] a l d u e a t Abstract properties are essential both for safety and security. Among the var- This paper reports on the design and soundness proof, using the ious verification techniques, static analysis is perhaps the one that Coq proof assistant, of Verasco, a static analyzer based on abstract scales best to large existing code bases, with minimal intervention interpretation for most of the ISO C 1999 language (excluding re- from the programmer. cursion and dynamic allocation). Verasco establishes the absence Static analyzers can be used in two different ways: as sophis- of run-time errors in the analyzed programs. It enjoys a modular ticated bug finders, discovering potential programming errors that architecture that supports the extensible combination of multiple are hard to find by testing; or as specialized program verifiers, es- abstract domains, both relational and non-relational. Verasco inte- tablishing that a given safety or security property holds with high grates with the CompCert formally-verified C compiler so that not confidence.
    [Show full text]