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TPS65988DK Dual Port USB Type-C® and USB PD Controller with Integrated Power Switches for USB4 and Thunderbolt 4 Devices

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TPS65988DK Dual Port USB Type-C® and USB PD Controller with Integrated Power Switches for USB4 and Thunderbolt 4 Devices TPS65988DK SLVSFN9A – SEPTEMBER 2020 – REVISED AUGUST 2021 TPS65988DK Dual Port USB Type-C® and USB PD Controller with Integrated Power Switches For USB4 and Thunderbolt 4 Devices 1 Features 2 Applications • This device is certified by the USB-IF for PD3.0 • Docking systems – PD3.0 silicon is required for certification of new • Monitors USB PD designs • USB4 hubs • TID#: 5431 3 Description – Article on PD2.0 vs. PD3.0 • TPS65988DK is a USB4 and Thunderbolt 4 The TPS65988DK is a highly integrated stand-alone (TBT4) device PD3.0 controller Dual Port USB Type-C and Power Delivery (PD) – This PD controller is only intended for use in controller optimized for USB4 & TBT4 Device. The USB4 device designs TPS65988DK integrates fully managed power paths – Refer to Intel Reference Design document with robust protection for a complete USB-C PD number 631605 solution. Upon cable detection, the TPS65988DK – If designing something other than a USB4 communicates on the CC wire using the USB device, please refer to selection guide and PD protocol. When cable detection and USB PD getting started information at www.ti.com/usb-c negotiation are complete, the TPS65988DK enables and E2E guide the appropriate power path and configures alternate • Integrated fully managed power paths: mode settings for external multiplexers. This device is featured on Intel’s Reference Design for USB4 – Integrated two 5-20 V, 5-A, 25-mΩ bidirectional & TBT4 Device end equipments ensuring the PD switches controller has proper system level interaction in these – UL2367 cert #: 20190107-E169910 types of designs. This greatly reduces system design – IEC62368-1 cert #: US-34617-UL complexity and results in reduced time to market. • Integrated robust power path protection – Integrated reverse current protection, Device Information undervoltage protection, overvoltage protection, PART NUMBER PACKAGE(1) BODY SIZE (NOM) and slew rate control for both 20-V/5-A power TPS65988DK QFN (56) 7.00 mm x 7.00 mm paths when configured to sink – Integrated undervoltage protection, overvoltage (1) For all available packages, see the orderable addendum at the end of the data sheet. protection, and current limiting for inrush current protection for both 20-V/5-A power paths when configured to source • USB Type-C® Power Delivery (PD) controller – 13 configurable GPIOs – USB PD 3.0 certified – USB Type-C specification certified – Cable attach and orientation detection – Integrated VCONN switch – Physical layer and policy engine – 3.3-V LDO output for dead battery support – Power supply from 3.3 V or VBUS source – 1 I2C primary or secondary port • 1 I2C primary only port Simplified Schematic • 1 I2C secondary only port An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS65988DK SLVSFN9A – SEPTEMBER 2020 – REVISED AUGUST 2021 www.ti.com Table of Contents 1 Features............................................................................1 9.1 Application Information............................................. 43 2 Applications.....................................................................1 9.2 Typical Applications.................................................. 43 3 Description.......................................................................1 10 Power Supply Recommendations..............................48 4 Revision History.............................................................. 2 10.1 3.3-V Power............................................................ 48 5 Pin Configuration and Functions...................................3 10.2 1.8-V Power............................................................ 48 6 Specifications.................................................................. 7 10.3 Recommended Supply Load Capacitance..............48 6.1 Absolute Maximum Ratings........................................ 7 11 Layout...........................................................................49 6.2 ESD Ratings............................................................... 7 11.1 Layout Guidelines................................................... 49 6.3 Recommended Operating Conditions.........................7 11.2 Layout Example...................................................... 49 6.4 Thermal Information....................................................8 11.3 Stack-up and Design Rules.....................................50 6.5 Power Supply Requirements and Characteristics.......8 11.4 Main Component Placement...................................51 6.6 Power Consumption Characteristics...........................9 11.5 Super Speed Type-C Connectors........................... 51 6.7 Power Switch Characteristics..................................... 9 11.6 Capacitor Placement...............................................52 6.8 Cable Detection Characteristics................................11 11.7 CC1/2 Capacitors & ADCIN1/2 Resistors............... 53 6.9 USB-PD Baseband Signal Requirements and 11.8 CC and SBU Protection Placement........................ 54 Characteristics.............................................................12 11.9 CC Routing..............................................................55 6.10 Thermal Shutdown Characteristics......................... 13 11.10 DRAIN1 and DRAIN2 Pad Pours.......................... 56 6.11 Oscillator Characteristics........................................ 13 11.11 VBUS Routing....................................................... 57 6.12 I/O Characteristics.................................................. 13 11.12 Completed Layout................................................. 58 6.13 I2C Requirements and Characteristics....................14 11.13 Power Dissipation................................................. 59 6.14 SPI Controller Timing Requirements.......................15 12 Device and Documentation Support..........................60 6.15 HPD Timing Requirements..................................... 16 12.1 Device Support....................................................... 60 6.16 Typical Characteristics............................................16 12.2 Documentation Support.......................................... 60 7 Parameter Measurement Information.......................... 17 12.3 Support Resources................................................. 60 8 Detailed Description......................................................18 12.4 Trademarks.............................................................60 8.1 Overview...................................................................18 12.5 Electrostatic Discharge Caution..............................60 8.2 Functional Block Diagram.........................................19 12.6 Glossary..................................................................60 8.3 Feature Description...................................................19 13 Mechanical, Packaging, and Orderable 8.4 Device Functional Modes..........................................40 Information.................................................................... 60 9 Application and Implementation.................................. 43 4 Revision History Changes from Revision * (September 2020) to Revision A (August 2021) Page • Updated the Features list....................................................................................................................................1 • Updated the document title.................................................................................................................................1 • Globally changed instances of legacy terminology to controller and peripheral where SPI is mentioned.......... 1 • Updated the Description section.........................................................................................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TPS65988DK TPS65988DK www.ti.com SLVSFN9A – SEPTEMBER 2020 – REVISED AUGUST 2021 5 Pin Configuration and Functions 43- GPIO15 (PWM) 44- HRESET 45- C2_CC1 46- PP2_CABLE 47- C2_CC247- 48-GPIO16 (PEXT1) 49- (PEXT2) GPIO17 50- C1_USB_P (GPIO18) 51- GND 53- C1_USB_N (GPIO19) 52- DRAIN2 54- C2_USB_P (GPIO20) 55- C2_USB_N (GPIO21) 56- DRAIN2 PP_HV2 -1 42- GPIO14 (PWM) PP_HV2 -2 41- GPIO13 VBUS2 -3 40- GPIO12 57 VBUS2 -4 39- SPI_CS (GPIO11) DRAIN2 VIN_3V3 -5 38- SPI_CLK (GPIO10) ADCIN1 -6 37- SPI_PICO (GPIO9) DRAIN2 -7 59 36- SPI_POCI (GPIO8) DRAIN1 -8 GND 35- LDO_1V8 LDO_3V3 -9 34- I2C2_IRQ ADCIN2 -10 33- I2C2_SDA 58 PP_HV1 -11 DRAIN1 32- I2C2_SCL PP_HV1 -12 31- HPD2 (GPIO4) VBUS1 -13 30- HPD1 (GPIO3) VBUS1 -14 29- I2C1_IRQ 18- GPIO2 19-DRAIN1 16-GPIO0 GPIO1 17- 15-DRAIN1 28- I2C1_SDA 27- I2C1_SCL 25- PP1_CABLE 26-C1_CC2 22- I2C3_SDA (GPIO6) 24- C1_CC124- 21-I2C3_SCL (GPIO5) 23- I2C3_IRQ (GPIO7) 20- GND Figure 5-1. RSH Package 56-Pin QFN Top View Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS65988DK TPS65988DK SLVSFN9A – SEPTEMBER 2020 – REVISED AUGUST 2021 www.ti.com Table 5-1. Pin Functions PIN TYPE(2) RESET STATE(1) DESCRIPTION NAME NO. Boot configuration Input. Connect to resistor ADCIN1 6 I Input divider between LDO_3V3 and GND. I2C address configuration Input. Connect to ADCIN2 10 I Input resistor divider between LDO_3V3 and GND. Output to Type-C CC or VCONN pin for port 1. C1_CC1 24 I/O High-Z Filter noise with capacitor to GND. Output to Type-C CC or VCONN pin for
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