BRNO UNIVERSITY OF TECHNOLOGY VYSOKÉ UČENÍ TECHNICKÉ V BRNĚ

FACULTY OF ELECTRICAL ENGINEERING AND COMMUNICATION FAKULTA ELEKTROTECHNIKY A KOMUNIKAČNÍCH TECHNOLOGIÍ

DEPARTMENT OF TELECOMMUNICATIONS ÚSTAV TELEKOMUNIKACÍ

DEVELOPMENT OF HIGH RESOLUTION RGB VÝVOJ RGB KAMERY S VYSOKÝM ROZLIŠENÍM

MASTER'S THESIS DIPLOMOVÁ PRÁCE

AUTHOR Bc. Jiří Madeja AUTOR PRÁCE

SUPERVISOR Ing. Michal Kubíček, Ph.D. VEDOUCÍ PRÁCE

BRNO 2017 ABSTRACT This thesis deals with a selection of a suitable for an application in a high resolution plant scanning camera and a design of a suitable electronic circuit for connecting the selected sensor (SONY IMX253) with the Avnet MicroZed development board. The thesis discusses various image sensor parameters relevant to the selection of the suitable image sensor. The example of a process of the suitable image sensor selection is demonstrated and the selected sensor parameters are analyzed in detail. The circuit design and printed circuit board design problematics of high-speed circuits and sensitive and specific components such as the image sensor are indicated. A configuration and programming of the Xilinx Zynq SoC is outlined and eventually, a simple theoretical verification of designed module is executed. KEYWORDS image sensor, high resolution, camera, FPGA, Xilinx Zynq, MicroZed, PCB, CMOS, global , SONY IMX253, LVDS

ABSTRAKT Tato práce se zabývá výběrem vhodného obrazového snímače pro použití v kameře sní- mající rostliny ve vysokém rozlišení a návrhem vhodného obvodu pro propojení vybraného snímače (SONY IMX253) s vývojovou deskou Avnet MicroZed. Tato práce pojednává o jednotlivých parametrech obrazových snímačů podle kterých je vybírán vhodný obra- zový snímač. Je vysvětlen proces výběru vhodného obrazového snímače a podrobněji popsány parametry vybraného snímače. Je naznačena problematika návrhu elektroniky a plošných spojů z hlediska požadavků vysokorychlostních obvodů a citlivých a speci- fických součástek jako je obrazový snímač. Je nastíněna konfigurace a programování obvodu Xilinx Zynq a nakonec je provedeno zjednodušené teoretické ověření funkčnosti navrženého modulu. KLÍČOVÁ SLOVA obrazový snímač, vysoké rozlišení, kamera, FPGA, Xilinx Zynq, MicroZed, DPS, CMOS, globální závěrka, SONY IMX253, LVDS

MADEJA, Jiří Development of high resolution RGB camera: master’s thesis. Brno: Brno University of Technology, Faculty of Electrical Engineering and Communication, Depart- ment of Telecommunications, 2017. 93 p. Supervised by Ing. Michal Kubíček, Ph.D. DECLARATION

I declare that I have written my master’s thesis on the theme of “Development of high resolution RGB camera” independently, under the guidance of the master’s thesis supervisor and using the technical literature and other sources of information which are all cited in the thesis and detailed in the list of literature at the end of the thesis. As the author of the master’s thesis I furthermore declare that, as regards the creation of this master’s thesis, I have not infringed any copyright. In particular, I have not unlawfully encroached on anyone’s personal and/or ownership rights and I am fully aware of the consequences in the case of breaking Regulation S 11 and the following of the Copyright Act No 121/2000 Sb. of the Czech Republic, and of the rights related to intellectual property right and changes in some Acts (Intellectual Property Act) and formulated in later regulations, inclusive of the possible consequences resulting from the provisions of Criminal Act No 40/2009 Sb. of the Czech Republic, Section 2, Head VI, Part 4.

Brno ...... author’s signature ACKNOWLEDGEMENT

I would first like to thank my thesis supervisor Ing. Michal Kubíček, Ph.D. ofthe Faculty of Electrical Engineering at Brno University of Technology, whose professional, pedagogical and personal skills helped me through many obstacles during writing this thesis and always went the extra mile to provide very valuable feedback on this thesis.

I would also like to thank my thesis consultant Ing. Tomáš Rataj, who gave me innu- merable expert advices and invaluable knowledge. Ing. Rataj was always very patient and provided very valuable feedback on this thesis.

Brno ...... author’s signature Faculty of Electrical Engineering and Communication Brno University of Technology Technicka 12, CZ-61600 Brno, Czechia http://www.six.feec.vutbr.cz

The research described in this diploma thesis has been done in laboratories supported by Sensor, Information and Communication Systems Research Centre (SIX) project; registration number CZ.1.05/2.1.00/03.0072 Operational Program Research and Development for Innovation (operační program Výzkum a vývoj pro inovace).

LIST OF FIGURES

1.1 Vertical smear (sourced from [59]) ...... 11 1.2 Image with before ...... 13 1.3 Image with Bayer filter after demosaicing ...... 13 1.4 Image with X-Trans filter before demosaicing (sourced by Petr Klempa) 14 1.5 Rolling shutter effect ...... 19 1.6 False when individual components are saturated . . . . . 21 1.7 Sheet of sensors selected for demonstration ...... 25 2.1 High level block scheme of hardware layer ...... 31 2.2 IO Bank connections ...... 32 3.1 Sensor board layout ...... 39 3.2 Detail of decoupling capacitor ...... 40 3.3 Layout of the board connected to the MicroZed ...... 41 3.4 Layout of the switching-mode power supply ...... 42 3.5 Detail of decoupling capacitors placement ...... 42 3.6 Layout of bottom layer of the board connected to the MicroZed . . . 43 3.7 Layout of the analog power supply board ...... 43 4.1 High level block scheme of software layer ...... 44 4.2 Simplified LVDS synchronization flowchart ...... 48 5.1 Image sensor package outline misalignment ...... 51 5.2 Sensor Board clearence errors ...... 52 5.3 Microheader critical errors ...... 53 5.4 Board connected to the MicroZed clearence errors ...... 53 5.5 Power-On sequencer simulation ...... 54 5.6 SPI simulation ...... 55 5.7 SPI simulation 2 - communication interrupted ...... 55 5.8 Timer simulation - normal mode ...... 56 5.9 Timer simulation - external trigger mode ...... 56 5.10 Timer simulation 2 - external trigger mode ...... 57 5.11 96bit to 16x6bit simulation ...... 57 5.12 6bit to 12bit simulation ...... 58 5.13 UserROI simulation ...... 58 B.1 1 - IMX253 ...... 71 B.2 2 - Decoupling ...... 72 B.3 3 - Connectors ...... 73 C.1 1 - Top layer ...... 74 C.2 2 - Power layer ...... 75 C.3 3 - Inner layer 1 ...... 75 C.4 4 - Inner layer 2 ...... 76 C.5 5 - Ground layer ...... 76 C.6 6 - Bottom layer ...... 77 C.7 Assembly top layer ...... 77 D.1 1 - Connectors to the MicroZed ...... 78 D.2 2 - Power sources ...... 79 D.3 3 - Other I/O ...... 80 D.4 4 - Other connectors ...... 81 D.5 5 - Motor control ...... 82 D.6 6 - Construction ...... 83 E.1 1 - Top layer ...... 84 E.2 2 - Power layer ...... 85 E.3 3 - Ground layer ...... 86 E.4 4 - Bottom layer ...... 87 E.5 Assembly silkscreen components composite top ...... 88 E.6 Assembly silkscreen components composite bottom ...... 89 F.1 1 - Power sources ...... 90 G.1 1 - Top layer ...... 91 G.2 2 - Bottom layer ...... 91 LIST OF TABLES

2.1 Power Supply Table ...... 33 2.2 SPI configuration ...... 35 2.3 I2C configuration ...... 35 H.1 Sensor board LVDS length differences ...... 92 I.1 Board connected to the MicroZed LVDS length differences ...... 93 INTRODUCTION

The goal of this thesis is to select a suitable image sensor, design a proper circuit design for the image sensor and to design a printed circuit board of the design. This sensor will be connected to a platform with Xilinx Zynq SoC and digital communi- cation will be configured and programmed. Eventually, a simple design verification will be executed. The image sensor will be selected according to the requirements of the application and of the PSI (Photon Systems Instruments), spol. s r.o. company, for which this module is developed. This image sensor module will be used as a scientific camera. The main function of this camera is to capture images of moving plants (the plants will be placed on a slowly rotating platform) under controlled conditions and these images will be used for a construction of a 3D model and analysis of the plant. It is therefore necessary to design an effective solution that will allow imaging with minimal distortion of the scanned plants. According to the requirements of the PSI, spol. s r.o. company, the module will be compatible with the other systems of the PSI (Photon Systems Instruments), spol. s r.o. company using its proprietary protocols and I2C. The module will have an interface to control a stepper motor used for controlling a filter wheel. The camera will be universal enough to nottobe restricted to this specified application but also will be usable as a typical camera. The module will be connected to the Avnet MicroZed development board. Location of certain connectors and dimensions of the printed circuit boards will be compatible with existing modules for their casing, attachment and connections. The first part of this thesis deals with a selection of the suitable digital sensor. Relevant parameters are mentioned and explained mainly from a practical viewpoint. Also, several sensors are selected, which will serve as a practical demonstration of the sensor selection process and eventually, the properties of the selected sensor are specified. The second part deals with the issue of the electronic circuit design, i.e. especially power supply and data connection between the sensor and the supporting circuits, which are especially in the case of the image sensor, critical. The third part deals with the printed circuit board design, namely the issue of electromagnetic interference, ergonomics and other issues of mechanical and electro- magnetic nature. The fourth part deals with a configuration and programming of the Xilinx Zynq SoC, which controls the whole module. The last part deals with a simple design verification and expands the fourth part of this thesis.

9 1 IMAGE SENSOR

Selection of an image sensor has a significant effect on the final product parameters. Sensors differ in a few intrinsic parameters, either from technological, commercial or practical point of view.

1.1 Sensor Parameters

There is a list of main parameters according to which the suitable image sensor has been selected listed below. Some otherwise important parameters were omitted because of an insufficient specification (and therefore of negligible meaningful value) among the sensors. The parameters definition (or its measurements) differs among manufacturers which specify it. The parameters are either differing wavelengths of light for measured quantum efficiency or differing temperatures of the chip when measuring various noise characteristics. Most of the parameters below are relevant for CMOS sensors only.

1.1.1 Technology

Charge-Coupled Device

The basic principle of CCD technology is as follows: The silicon surface of the sensor is hit by a photon and an electron-hole pair is created by the photoelectric effect. There is a gate over each holding electrons with electric field sothat the electron-hole pair can not recombine. The gate is isolated from the silicon by an insulator through which can light pass but electrons can not, i.e. glass. With the right change of electric field generated by the gate, it is possible to move the electrons across the silicon surface. This effect is used for shifting pixel charges across the sensor to the output amplifier until all the sensor are read out. The same way as an adhesive tape can hold only limited number of grains of sand, the same way pixels of the CCD sensor can hold only a limited number of electrons and exceeding electrons pour over to the nearest pixels, which is called smearing or bleeding. The CCD sensor pixels always expose simultaneously. The output of the CCD sensor is, in principle, analog, usually only consisting of a low amount of channels. The low amount of channels is one of the reasons causing a low speed of data reading from the CCD sensor, this means that high resolution motion capture capabilities are usually very limited. The analog nature of CCD sensors puts additional requirements on the sur- rounding system design because of its susceptibility to noise, whether in terms of

10 signal connections, power supply, grounding and external noise sources. Further- more, usually, there is a need to digitize the signals. The price of CCD sensors is generally higher than the price of CMOS sensors, because CCD requires a specific manufacturing technology. CCD sensors are especially useful for imaging outside of the visible spectrum of light and for applications with specific requirements which can not be met by using the CMOS image sensors.[1, 9, 10, 26, 50]

Fig. 1.1: Vertical smear (sourced from [59])

Complementary Metal–Oxide–Semiconductor

The CMOS technology allows the sensor to have additional circuits on the chip apart from just as with the CCD technology. This gives the CMOS sensor pixels the ability to convert electrons to voltage without the need of shifting them across the chip. Because voltage is transmitted via a metallic wire instead of silicon, this allows the pixels to be interconnected more easily, which, in principle, gives the sensor the ability to random access the pixel voltage. These interconnections and multiple amplifiers give the CMOS sensor the ability to reach higher frame rates than doesthe CCD sensor can. The CMOS technology allows to integrate clocks, A/D converters, digital controllers, image stabilizers, etc. into the chip itself. The CMOS sensors typically expose line by line (rolling shutter), which can cause a variety of image artifacts (the jello effect when fast movement is present inthe scene and half-lit images when or stroboscopic light occurs in the scene when exposing). This problem is not present with the (usually more expensive) global shutter CMOS sensors. The image data signals are digitized in parallel on the chip, the signals are then transmitted simultaneously via several channels with the data in series. This allows a faster data readout from the sensor. Because the signal is in a digital form, the need to digitize the signal in the surrounding system is eliminated and the signals are more resistant to electromagnetic interference right away. The sensor itself usually requires less support of the surrounding system because the CMOS technology allows a better integration of support systems directly on the

11 chip. The CMOS sensors prevail in the visible and near-infrared light imaging, these can be found mainly in commercial digital (ranging from professional to cell phone cameras).[1, 2, 9, 10, 26, 37, 51]

1.1.2 Chromaticity

Most image sensors (particularly the CMOS image sensors) come either in monochrome or color alternatives. Accurate color reproduction is an essential parameter espe- cially for images perceived by humans.

Monochromatic

Each pixel of a monochrome sensor only distinguishes the intensity of light incident upon it. From this perspective, no additional image processing is required for an image presentation. A picture quality (especially spatial resolution) and sensitivity are higher than do the color sensors have.[5, 26]

Color

Bayer The color filter is placed on top of a sensor witheach pixel having either red, green, or blue filter associated to the related photosite by the Bayer configuration. The number of green pixels is the same as red andblue pixels together, this ratio is based on the high sensitivity of human eye to green color. Each photosite thus distinguishes only the intensity of light transmitted by the associated filter. The filter does not transmit one specific wavelength but a range of wavelengths. Ranges of transmitted wavelengths are usually overlapping. The degree of overlap and the characteristic of the transmission wavelength is designed by the manufac- turer and the sensor model. The more the wavelength ranges overlap, the better the sensor resolves spatial details and light intensity. The less the wavelengths overlap, the better the sensor resolves shades of color. In order to reconstruct a complete color image, it is necessary to debayer (de- mosaic) the image, which is a process that calculates an RGB value of a pixel from neighboring pixels. This process adds additional overhead in the post-processing of the image and also reduces the effective sensor resolution, sensitivity, and par- ticularly may cause and moiré in sharp contrasts. The use of an optical low pass filter (AA) suppresses these artifacts, but also reduces the effective spatial resolution of the sensor.[5, 11, 26] The figures 1.2 and 1.3 show the false colors that occur, when the AAfilter is missing or is not properly adapted to the sensor resolution (the effect is not a

12 Fig. 1.2: Image with Bayer filter Fig. 1.3: Image with Bayer filter before demosaicing after demosaicing or other optical phenomenon caused by the lens). Several algorithms are used for debayering, in the figure 1.3, one of the most effective – AMaZe is used. In this case, in the figure 1.2, it is obvious the contrast edge is not gradient, but abruptly varies at the transition between the pixels, this results in the incorrect interpolation and false colors. The vast majority of commercially used color sensors use the Bayer color filter array.

RGBW The RGBW filter is similar to the Bayer color filter array, but instead of one set of green color, there is a pure transparent filter. In the case of the pure filter, the most of light is transmitted to a photosite, rather than being absorbed by the filter, as with red, green and blue filters. This feature increases thesensor sensitivity to the detriment of color resolution.

X-Trans Fuji has developed its own type of filter that aims to eliminate aliasing and moiré. It is inspired by a random placement of silver halide crystals on the analog film. The absence of the necessity for the AA filter allows better rendering of spatial details than with the sensor with a Bayer color filter array of similar resolution. The sample of undemosaiced taken with Fuji T1 is shown in the figure 1.4.[5, 7]

Foveon X3 Foveon has developed the Foveon X3 sensor (it is not a filter), which is taking a different approach – instead of using a color filter, it uses 3stacked sensors. These sensors can recognize color, because a wavelength determines how far can light pass into the sensor, i.e. whether photons are absorbed in the first (blue), second (green) or third sensor (red).

13 Fig. 1.4: Image with X-Trans filter before demosaicing (sourced by Petr Klempa)

The image quality is in the terms of resolution and color fidelity in principle comparable to the image quality of monochromatic sensors, however the Foveon X3 has very low sensitivity when compared to more conventional image sensors.[5, 8]

1.1.3 Resolution

The image sensor resolution is due to the purpose of the camera one of the most important parameters. Apart from the resolution itself, care should be taken also to an aspect ratio – the ratio of the number of horizontal pixels to the number of vertical pixels. Because one of the requirements of the PSI spol. s r.o. company is a possibility of other motion capture applications, it is appropriate for the sensor to have at least 4000 pixels on one side with the minimum of 1,700 pixels on the other side, which is high enough resolution in a satisfactory aspect ratio for most of the usual applications. This could be then marketed as the 4K video camera and would be in the aspect ratio of at least 2.35:1, which is one of the standard aspect ratios used in the movie industry at the moment. For the purpose of plant scanning, however, a lower aspect ratio would be more appropriate. For video applications outside cinema, the 16:9 aspect ratio is used, this aspect ratio would be ideal universal aspect ratio.[12] The aspect ratio is crucial also in the terms of price, because a sensor area is one of the most significant parameters influencing the price – the aspect ratio that isnot optimal can lead to a significant increase in cost for the same or less usable areaof the sensor. Higher aspect ratio further reduces the useful surface while maintaining the same light cone. For the more efficient use of the sensor area in an unfavorable aspect ratio, anamorphic lenses can be used. These, however, when compared to

14 standard lenses, have worse optical properties, are not as available and are much more expensive.[13] If the sensor protrudes from the cone of light thrown by the lens, a larger (and usually more expensive) lens is needed. The ideal (in the terms of the usage of light thrown by the lens) practical sensor should therefore be in the aspect ratio of 1:1. Theoretical ideal sensor (in this sense) would be circular to exactly match the light cone.[14, 15, 26]

1.1.4 Effective Photosensitive Surface Area

Although the parameter is called Effective photosensitive surface area, in the table G.2, it is called Photosensitive surface area equivalent. It is a simplification as the surface itself should be included with a fill factor instead of a quantum efficiency but a QE is in this case more important parameter because concentrate light into pixels and thus increase efficiency of light transmission to the sensor even with lower actual surface area, thus, for the sensitivity of the sensor, the actual photosensitive surface area is not as important as the effective photosensitive surface area, which at least relative to the other sensors, indicates the ability of the sensor to receive light. The effective photosensitive surface area has a major influence onthe number of photons the sensor receives and so it is a parameter that affects the shot noise.[11, 16] Because the shot noise is influenced by the amount of light received by the sensor, it can be affected by several parameters: • The amount of light coming into the lens – it is determined by a duration of and lighting conditions. Long exposure causes motion blur and increases noise from dark current, so it can not be arbitrarily increased. In the movie industry, the rule of 180° (which is based on a mechanical rotational shutter) is used, which means that the length of exposure is 1/(2*FPS) seconds. Lighting conditions can be controlled in a laboratory, therefore this parameter can be usually controlled.[18] • Lens /transmissivity – it is influenced by the optical lens design, ma- terials used, clarity and purity of lenses and usage of anti-reflective coatings. With higher transmissivity of the lens, the price is increasing rapidly. To quantify, the maximum aperture of the lens is defined as f-stop for a theo- retical maximum aperture if parasitic optical properties of lens are neglected and only physical dimensions are considered. For defining the actual measured transmissivity including reflection and absorption of lens, T-stop are used. The largest aperture ends roughly at f/1 (limited by cost, not by physical limi- tations), standard lenses (the ones that are considered to be fast, which means with high transmissivity) range at around f/2, which is 1/4 of the amount

15 of light versus f/1 (half the aperture diameter causes the area of circle which capture photons to be 1/4). This applies to APS-C and FF lenses. Smaller format lenses usually achieve larger (with worse image quality than bigger format lenses, though), but not enough to offset the declining surface area of the sensor, which goes hand in hand with a smaller lens format.[17] • The reflection or absorption of light in applied filters (anti-aliasing filter, IR- cut filter, cover glass) – in the case of many applications, it is a necessity and can not be influenced very well.[19, 20] • Effective photosensitive surface area – strictly speaking, the effective photosen- sitive surface area or the sensor size are irrelevant to the amount of captured photons. The key parameter is the lens aperture diameter (the entrance pupil diameter). The lens aperture diameter is defined as /f number. The same lens on different sensor sizes will have the same light intensity andif photons at the rear end of the lens are projected into proportional areas, both sensors will capture the same amount of photons. However the concentration of light at the rear end is complicated and the increased number of lens elements decreases the transmittivity of the lens and increases its cost and dimensions. Therefore, in order for the smaller size sensors to have the same field of view as the larger size sensors, shorter focal length is used. If the sensor has sides ten times shorter than another sensor, this sensor requires ten times shorter focal length to have the same field of view. This, however, reduces the amount of photons to 1/100th of the larger lens with the same f number (lens aperture diameter = focal length/f number). So while the effective photosensitive sur- face area does not matter in the sense of the light capturing capabilities and the only differences are in used lenses, for any practical means, this parameter can be assumed to be essential.[58]

1.1.5 Shot Noise

A shot noise is caused by the very properties of light, rather than the sensor itself. The shot noise is never stated as a sensor parameter, but it is sometimes included in other measurements, e.g. temporal noise, dynamic range, read noise etc. It is caused by the discrete nature of light – photons. The shot noise is therefore basically a statistical error. The statistical error can by only reduced by increasing of the number of samples – increasing the amount of received photons, e.g. by increasing the photosensitive surface area.[11, 21]

16 1.1.6 Quantum Efficiency

A quantum efficiency indicates what percentage of total incident photons is“con- verted” to electron-hole pairs. The QE is influenced by the ratio of the area of photodiodes to other electronic circuits on the sensor surface. Further, it is influ- enced by the reflection and absorption of the sensor itself and of various surfaces covering it (Bayer color filter array, usually IR-cut filter and AA filter, cover glass to prevent mechanical damage and environmental effects).[22, 26] The QE differs for various wavelengths, most manufacturers specify the valueof the QE for light of wavelength of 550nm. To increase the QE, microlenses are used to redirect light from the photoinsensi- tive chip area onto the photosensitive chip area.[23] Physical coverage (rather than optical) of the photosensitive surface area is called a fill factor. Microlenses are used to increase the QE in the case of the fill factor lower than 100%.

1.1.7 Frame rate

In this case, a maximum number of frames per second is important for the speed of plant image capturing and for a potential usage of the camera in other applications. The most common frame rates include 24 fps for movie and 25 and 30 fps for television purposes. Usage of the camera for other purposes in the future is therefore limited to minimum of 24 or 25 fps, it is therefore good to have a possibility of achieving at least 24 or 25 fps (in 2.35:1 and 19:9 aspect ratio, respectively).[24, 26] It is necessary to consider the possibility of a region of interest function, which would allow to increase the frame rate for the cost of reduced vertical (usually) resolution.[25]

1.1.8 Shutter Technology

Full Frame

Full frame is the simplest technology of the CCD sensors. The full frame CCD sensor has no memory area and charge is moving through pixels at distances up to the height of the sensor. The whole sensor is integrating all the time, so it is traditionally needed to use a mechanical shutter. This type of the CCD sensor technology has the best photosen- sitive surface area coverage, but at the cost of potential smearing and residual charge build up (in the case of front side illuminated sensors), which are dependent on the speed of the sensor readout. The construction of modern CCD sensors dramatically

17 reduces these parasitic effects and enables the sensor to function satisfactorily even without the mechanical shutter.[4, 6] 1

Frame-Transfer

Frame-transfer is the CCD sensor technology in which the sensor has a memory area equivalent in size to the photosensitive area, on which pixel charges are moved at the end of the exposure. Subsequently, pixel charges are moved from the memory area to be transmitted from the sensor while covered away from light. The pixel charges still have to travel up the height of the sensor as with the full frame CCD and therefore the smearing is still present, but because the bottleneck is reading from the sensor, rather than moving the pixel charges, these charges can be moved from photosensitive area more quickly and therefore smearing is reduced. The sensor does not require the mechanical shutter. The photosensitive surface coverage is the same as with the full frame CCD, but because there are memory pixels filling the same area as the photosensitive pixels, the cost of the sensoris significantly higher.[4, 6]

Interline

Interline is the CCD sensor technology in which next to each pixel, there is a pixel memory of the same size, into which the pixel charge is moved immediately after exposure. Because the pixel charge moves straight to the pixel memory and does not need to pass over the silicon surface, the smearing as with the above-mentioned technologies, is greatly reduced and the sensor does not require the mechanical shutter. The disadvantage is a smaller photosensitive surface area (for the same optical format).[4, 6]

Rolling Shutter

Rolling shutter is the most used technology in CMOS sensors. In rolling shutter sensors, exposure is individually controlled line by line, which allows the sensor to be almost permanently exposed (without void intervals in between frames). Between starting or ending of the exposure of each horizontal line, there is a delay, they can not change states simultaneously. Line data are read when the end of exposure of that line, this causes various artifacts whenever there is a change in the scene while exposing, e.g. a movement or

1 Full frame as a CCD sensor technology is not to be confused with the full frame as a sensor format (36x24mm).

18 change of lighting conditions (camera flash). The motion artifact known as the jello effect is shown in the figure 1.5; the image is squeezed because of a rapidmovement of the camera or the object in the scene. In this case, the letters are slanted while in reality they are straight.

Fig. 1.5: Rolling shutter effect

The effects of the rolling shutter can be suppressed with the useofthe mechanical shutter. The amount of the rolling shutter parasitic effects is closely related to the speed of transmitting of pixels from the sensor, which is closely related to the maximum frame rate. General rule of thumb is that the last horizontal line readout is delayed by about 1/frame rate seconds after the first line. Consequently, it makes sense to choose the sensor with the higher maximum frame rate even though it will not be used – higher frame rate means faster shutter.[3, 26]

Global Shutter

Global shutter is the CMOS image sensor technology, in which all the pixels can be controlled at once, therefore there are no shutter artifacts present as with the rolling shutter. The pixel reading, unlike with the rolling shutter, is a process independent of exposure. This brings technological bottlenecks – the charge accumulated at the time of the end of exposure is moved to a pixel memory before its value is retrieved. Due to steps that need to be done in addition compared to the steps needed to be done in the rolling shutter, global shutter sensors usually have significantly worse noise properties. Many global shutter sensors are able to capture in both rolling and global shutter, thus this selection does not become a question of a qualitative compromise, but is rather a matter of the sensor price. [3, 26]

1.1.9 Spectral Sensitivity

The spectral sensitivity defines the efficiency of the sensor to absorb given light spectrum. The sensor must be capable of perceiving selected light spectrum for its application, in this case, the visible spectrum. For further use, especially in the field

19 of scientific analysis, good sensitivity also outside the visible spectrum is abenefit – especially CMOS sensors have negligible sensitivity to UV radiation, so the only difference is in the sensitivity to the infrared spectrum. If no sensitivity toinfrared light is coveted, IR-cut filter can be placed in front of the sensor.[26]

1.1.10 Dynamic Range

The dynamic range indicates what range of light intensity can the sensor capture in a single exposure. It is capped by the pixel full well depth and limited by the noise level at the lower end of the range. When the camera is used in uncontrolled conditions (outdoor photography), the dynamic range is an essential parameter. Apart from the inherent parameters of the sensor, the dynamic range of the sensor can be improved by other means, which some of the sensors offer or by using non-native methods like “dual ISO” (interlacing lines of alternating gains) or bracketing (linking multiple exposures of the same scene into a single image). The CCD sensors usually exhibit higher DR than CMOS sensors in their datasheets, but this can be also influenced by different measurement conditions as that CCD sensors are measured in the most ideal possible system, in practice the surrounding system generates noise, but the surrounding system will not have such a significant impact on the image quality of CMOS sensors. Of course, CCD sensors frequently do have larger DR because of typically larger pixel pitch.[11, 29]

1.1.11 Sensitivity/Responsivity

The sensitivity of the sensor specifies how much is the signal level increased when light is absorbed by the sensor. The sensor with greater sensitivity will have higher signal level than the sensor with lower sensitivity in the same lighting conditions. Higher sensitivity therefore may improve signal to noise ratio. The sensitivity is usually defined as QE/dark noise. Sensitivity is dependent on the wavelength of light and is typically measured at 550nm.[28]

1.1.12 Full Well Charge

The full well charge defines how many electrons can be stored in the pixel with- out it being oversaturated. The FWC is the upper limit of the DR, therefore, it significantly contributes to the DR.[11]

20 The pixel oversaturation is especially critical in the CCD sensors, because this may lead to smearing, which means that a charge of the pixel will spread to neighbor- ing pixels spontaneously (this effect is reduced in many modern CCD sensors).[27] The full well charge is usually directly proportional to the pixel pitch. In the case of high signal levels, it may happen that the pixel of one color component reaches saturation, while the other pixels of other color components not yet. This causes false colors to the image. The parameter reflecting false color production of individual color components and characterizing sensor performance on the edge of oversaturation is also known as the highlight rolloff (in the case of overexposing the image).

Fig. 1.6: False colors when individual color components are saturated

In the figure 1.6, there is a photograph detail of a street lamp illuminated wall. The lamp is on the right (in overexposed portions of the image), and diminishing light intensity with increasing distance from the lamp can be seen on the left. The upper half of the figure 1.6 shows oversaturated pixels (of at least one color channel), marked with black color, the lower half of the figure 1.6 shows the RGB image of the same scene (the image is continued, not repeated). Colored bars show the location on an imaginary X axis (house wall) where the saturation of the color occurs. It is obvious that instead of increased brightness of red/orange hue, hue starts to change to yellow (the ratio of the red component to green and blue drops), after saturation of red pixels and after saturation of green pixels, hue starts to change to white (ratio of red and green component to blue drops until they are all saturated in ratio of 1:1:1).

1.1.13 Dark Noise

A dark noise is the signal generated in the sensor even with zero light intensity, the dark noise is generated by electronics, heat and sensor manufacturing imperfections. The dark noise is closely dependent on the temperature and forms for the entire exposure, so it is negligible for short exposures and the noise level increases with longer exposures. That is why the sensor cooling is important especially in the field

21 of . Because analog films do not have the dark noise, they are superior for long exposures.[26]

1.1.14 Maximum Signal to Noise Ratio

The signal to noise ratio (SNR) is typically maximal at full saturation level of the pixel, this value indicates the ratio of the useful signal (for the given pixel or uniformly exposed image) to noise. For comparison the analog film is lagging behind modern digital sensors inthis parameter, because it has significant noise (grain) in whole signal range, while even lower quality (or cheaper/smaller) digital sensors have, at least near saturation, much higher SNR.[29]

1.1.15 Bit Depth

The bit depth specifies the number of bits representing value of one pixel (one sensor pixel is not equivalent to one pixel of final RGB image in the case of sensors with color filters). Because in most of the cases, the image needs to be converted to 8 bits per color for reproduction, at bit depths higher than 8 the value of the sensor bit depth is important particularly for the purposes of post-processing, e.g. analysis, recon- struction, chroma keying. The insufficient bit depth is visible especially in gradual intensity changes as patches. [11, 29]

1.1.16 Price

Because the price of the image sensor can make up a significant portion of the cost of the camera, it is one of the most important parameters. Most manufacturers and distributors do not disclose the price of their image sensor publicly. Therefore, most sensors require a pricing query to the manufacturer or distributor for a specified number or range of numbers of pieces. Consequently, in the terms of price, in practice, there is only a limited possibility of comparing competing products. It is therefore appropriate to get an idea of how various parameters are reflected in the price of the sensor. The biggest price difference is dependent on the used technology (CMOS/CCD), with the CMOS sensors much cheaper. Furthermore it is dependent on the type of the shutter technology, the rolling shutter sensors are significantly cheaper than the global shutter sensors. And finally, the price rises more than linearly with the photosensitive surface area. The differences between the prices of individual

22 producers generally are usually not as pronounced as the differences in prices by the size of the sensor for given technology.[1]

1.1.17 Features

High Dynamic Range

Some sensors have additional features that allow to increase the dynamic range. All digital sensors have (unlike analog film) a roughly linear transmission characteristic. This affects the capture negatively, especially in natural conditions, which areusu- ally non-linear by nature in illumination (sun, bright skies and reflections, medium intensity, shadows).

Piecewise Linear Response The piecewise linear response can be achieved by partially resetting the pixel charge each time it reaches a threshold. There may be more thresholds, thus piecewise linear response may be partially smoothed. Arti- facts may occur due to the fact that the method works with various pixel exposure times.[31]

Interlacing If the high level signal and the low level signal lines alternate (a pair of rows when the Bayer color filter array is used), the surrounding system can reconstruct the image with higher dynamic range at the expense of effective vertical resolution (1/2 of a native vertical resolution). This can be achieved either by altering gain or exposure time of rows. The rolling shutter sensors are able to do so without requiring a native support for this function, because the exposure time is usually fully controlled by the surrounding system, the sensor only needs to be able to control its gain fast enough if gain alteration is used. A native support for this function is required for the global shutter sensors. There is an increased risk of aliasing (assuming that the AA filter is not adapted to the reduced resolution), due to the reduction of vertical resolution in half of the original.[32]

Multi-Amplifier Some sensors have multiple amplifiers which allow to capture multiple otherwise identical images with different gains.[30] The ambient system can then merge the pictures into one with higher dynamic range. This technique is advantageous because it does not produce artifacts from various exposures and is not reducing vertical resolution. It is also possible to use just individual images and there is no need to merge them unlike with other methods, which may be advantageous in many situations. Response curve does not have to be, as with the other methods continuous, which may be advantageous particularly in situations where the interest is in extremes – range between extremes can be completely omitted. The piecewise

23 linear response does not allow this, interleaving allows discontinuous response curve, but this may introduce strong aliasing.

1.1.18 Correlated Double Sampling

Correlated double sampling is a method of reducing offset levels in sensors. This method is frequently used in image sensors for reducing a fixed-pattern noise, gain offset and other time-independent noises. By subtracting the dark image (void image without incident light) from the actual image, time-independent noise is removed. While some sensors implement this function internally, it has to be done by the surrounding system when the sensor does not support this function. In some cases, e.g. the full frame CCD sensors, it is required to use the mechanical shutter, because it is not possible to obtain the dark image without it (or without other cover). It is especially appropriate to use this method when using the global shutter sensors, because this type of noise is significant in them. When the external CDS is used, the frame rate ishalved because of multiple exposures.

1.1.19 Region of Interest

Most sensors can reduce the number of rows (usually) read and increase the achiev- able FPS proportionally. It is possible to define the exact location to be read (rect- angle of the user defined dimensions and its position), but only number ofrows define increase of frame rate, not the number of columns usually. Therefore, itis important to consider that especially in the case of very high resolution sensors, which generally have a lower frame rate than lower resolution sensors, it would be wrong to exclude such sensors from selection only because they have insufficient frame rate at maximum resolution.[25]

1.1.20 Practical Limitations

Sensors often differ by the communication manner, which transmit the analog data in the case of the CCD sensors (usually), and the digital data in the case of the CMOS sensors (usually), also protocols are different. The image data transmission and transmission of service data are carried out by different means. Fast communi- cation – low-voltage differential signaling in digital output CMOS sensors, is used for transmission of image data, usually. For slow communication, SPI, I2C or pro- prietary protocol is used in CMOS sensors, usually. Also, the sensors have different requirements on the surrounding circuitry, with regards to the analog part, power supply, package connection.

24 Also, they differ in the speed and amount of clock signals. Therefore, itis necessary to consider whether it is practical, to use a sensor and not the other. The CCD sensor parameters may seem better then CMOS sensors from a purely theoretical point of view, but because the CCD sensors usually require additional supporting analog circuits, it can be assumed that additional noise will be introduced in the application (especially when the design is badly executed). The PSI, spol. s r.o. company specifies, that the sensor will communicate with the Avnet MicroZed development board, it is therefore necessary to make sure the development board has available resources the sensor needs for proper function. If the sensor meets the requirements, it is still necessary to assess whether its im- plementation is worthwhile, e.g. the seriousness of possible bad design consequences, time/complexity design requirements or price/availability of used components. The sensor, which may possibly be cheaper than the others, can easily be commercially inappropriate because of the possible higher development cost, i.e. more complicated from either experience demands, price of components or time frame.

1.2 Sensor Selection

Manufacturer CMOSIS TELEDYNE DALSA ONSEMI CMOSIS GPIXEL GPIXEL SONY Model CHR70M FTF9168C VITA25K CMV20000 GMAX0504 GSENSE5130 IMX253 Technology CMOS CCD CMOS CMOS CMOS CMOS CMOS Chroma Bayer Bayer Bayer Bayer Bayer Bayer Bayer Resolution [Mpx] 70 60 25 20 19,5 15 12,4 H. Res. 10000 8959 5120 5120 5144 5120 4096 V. Res. 7096 6708 5120 3840 3800 2968 3000 Aspect ratio 1,409245 1,335569469 1,00 1,33 1,35 1,73 1,37 Format 35mm 53,7x40,3mm APS-H 35mm 38x28,1mm APS-C 1.1" Length of the longest side [mm] 31,00(vypo 53,75 23,04 32,77 38,07 21,76 14,13 Minimum lens format FF Middle format APS-C FF Middle format APS-C m4/3 Surface area 219,98 360,58 117,96 125,83 144,65 64,58 42,39 Photosensitive surface area equivalent 115,39 58,98 - 86,79 38,75 - Pixel pitch [ µm2] 3,1 6 4,5 6,4 7,4 4,25 3,45 Framerate 3 1,4 53 30 25 32 46 Shutter Rolling Full Frame Global, RollingGlobal Global, Rolling Global, Rolling Global Dynamic range [dB] 63 70 56,2 66 72 70 ? Sensitivity [V/lux.s] 0,88 3,4 8,3 - Conversion gain [uV/e-] 64 81,5 110 ? Full well charge [e-] 13000 50000 22000 15000 70000 14400 ? Dark noise [e- (RMS)] 7 34 8 11 5 ? SNR max [dB] 41,1 43,4 41,7 41,9 ? Parasitic light sensitivity 1/900 1/50000 - Dark current [e-/s (25 degC)] 3,2 14 125 130,6 - ? Fixed pattern noise [%] 0,09 0,5 0,2 - ? ADC resolution[bit] 10 12 10 12 12 Quantum efficiency [%] 32 50 - 60 60 ? Price (tentative) - $3 800 $3 330 - - -

Fig. 1.7: Sheet of sensors selected for demonstration

25 The table G.2 shows several sensors selected for demonstration of the selection process. The values shown are extracted from a more comprehensive table with the total of 20 sensors, which were considered for the implementation of the camera. From the table G.2 it is obvious that many sensor parameters are missing. This is mostly because the manufacturers marked the datasheets as confidential. Further- more, some parameters are missing because of several causes: the manufacturer did not measured or defined a parameter, the manufacturer uses a different parameter definition, or the datasheet could not be obtained by practical means. For higher legibility, the cells are colored in a green-yellow-red scale from the best to the worst respectively. The cells are colored either proportionately between the sensors or the sufficient/insufficient value is defined manually. Several parameters in the table are either not mentioned or it would be appro- priate to clarify their meaning:

Chroma All sensors in the table which come in Bayer CFA variant are available in monochromatic variant also.

Format Image format compared to the common commercially used image formats.

Length of the Longest Side The length of the longest side is important for a quick idea of the size of the sensor. This is more straightforward, than the sen- sor size or surface area. The value is calculated from the values provided by the manufacturer.

Minimum Lens Format Because the lenses are manufactured primarily for sen- sors with the aspect ratio roughly 4:3, when more widescreen aspect ratio is used, it may happen that the lens will not be suitable for the selected sensor. Therefore, the corresponding suitable sensor size is stated according to the length of the longest side of the sensor. The minimum lens format is a format of such size that can guar- antee that the light beam covers the entire sensor area. Although, it is possible, that a smaller lens format is also suitable.[33, 15]

Surface Area Surface area is calculated by equation:

푁ℎ * 푁푣 * 푃 106 Where Nh is the number of pixels along horizontal axis, Nv is the number of pixels along vertical axis and P is the pixel pitch in 휇m2.

26 Photosensitive Surface Area Equivalent The photosensitive surface area equiv- alent is calculated as a product of the surface area with the QE. The surface area of the photosensitive part of the sensor is represented by this parameter. The photo- sensitive surface area equivalent is important for appropriate comparisons of sensor ability to receive light.

Pixel Pitch The pixel pitch is a surface area per pixel – this parameter is impor- tant for indicative idea of the full well charge, thus dynamic range.

Price (Tentative) The prices are collected from different sources, i.e. business offer, distributor web, forums; therefore, their credibility and relevance for present time vary considerably. The prices vary in accordance with volume of the offer, thus prices are relevant only to specific volumes.

There is a comparison of selected sensors below – the comparison includes either suitable sensors (favorites in the selection) and sensors inappropriate for required application (for demonstration). The cell colors are defined by all sensors in the initial table (not shown). Because most of the characteristics are confidential, the comparison below does not contain nearly the entire list of important sensor char- acteristics.

1.2.1 Sensor Comparison

CMOSIS CHR70M

Only the rolling shutter mode is supported by this sensor, in conjunction with the maximum of 3 fps, this means that the camera needs to use a mechanical shutter to capture anything moving, otherwise the images are unusable because the last line is delayed by approximately 333ms after the first line in full resolution. Data are output by 8 analog channels from the sensor, the fact that the channels are analog further complicates development. CMOSIS legally restricts use of the sensor for biometric purposes, which limits the possible future use of CHR70M sensor in this field. The relatively small dynamic range (by the standards of the rolling shutter sensors) is mainly due to a small full well charge, probably caused by a small pixel pitch of the sensor. It is worth mentioning the large photosensitive surface area, which is almost double (219.98 vs. 117.96) compared to the CMV20000, which has the same physical dimensions – 35mm format.[34, 39] It is necessary to use at least

27 Full Frame format lenses commonly used by professional photographers, so they are commercially available, albeit range in the more expensive end of commercial lenses.

TELEDYNE DALSA FTF9168

The main disadvantage of this sensor are its design requirements caused by the nature of the CCD technology. Also, the price of this sensor is an order of magnitude higher (the price not shown in the table but taken into account) than the price of some cheaper sensors in the table, which is not commercially justifiable. The maximum frame rate of 1.4 fps in full resolution further limits its potential use in motion picture applications. Large sensor size also prevents reliable compatibility with commercially available APS-C, FF and much less C-mount lenses and have to be used with lenses, of which the vast majority ranges in prices around US$1600 and above in the Czech market (current to 2016/11/1).[36] Apart from the expensive lenses, the size of the sensor is, of course, an advantage, which allows the pixel pitch to be relatively large, and thus obtain good values of the dynamic range. The advantage is the large photosensitive surface area, but this sensor has very low value of the quantum efficiency (compared to the CMOS sensors), so the amount of light the sensor will effectively absorb, will be smaller than one might expect from such large sensor and the size advantage is therefore partially diminished.[35]

ON SEMICONDUTOR VITA25K

Probably the high dark noise causes the low dynamic range. It is also necessary to consider whether a square aspect ratio (1:1) is ideal for plant scanning, this aspect ratio also restricts the universality of the sensor. It is worth mentioning the possibility of the rolling shutter mode, wherein, however, the dynamic range is still low 59.6dB.[38]

CMOSIS CMV20000

This sensor is not very different from the VITA25K. It has a larger surface area in a more convenient aspect ratio. The disadvantage against VITA25K is that CMV20000 does not support a rolling shutter mode, but VITA25K does not have as high dynamic range as CMV20000 even in the rolling shutter mode, so the absence of this feature is not really a problem. The function of increased dynamic range can be used to increase the dynamic range by the piecewise linear response. CMOSIS

28 legally restricts use of the sensor for traffic applications, which limits the possible future use of the CMV20000 sensor in said field.[39]2

GPIXEL GMAX0504

This sensor differs from the previous sensor especially by the possibility ofusing the rolling shutter mode, in which the dynamic range is 77dB. This sensor has two amplifiers, which allow to capture two otherwise identical images with indepen- dently controllable gains and by merging the images, it is possible to create one high dynamic range image. Possible CDS must be done externally by the surround- ing system, which increases the cost of development and may require additional computing capacity of the surrounding system. 80 LVDS in the global shutter mode (40 for the data from one amplifier and 40 for the data from the second amplifier) are used for the image data transfer. Only 48 LVDS channels are available on the Avnet MicroZed development board, which means that only one amplifier is usable. In practice, even this is not achievable due to the compatibility requirements with other systems of the PSI, spol. s r.o. company and the necessity of driving the control signals. As of 2016/12/1, the sensor is in a development stage.[42, 43]

GPIXEL GSENSE5130

GSENSE5130 has a lower resolution than GMAX0504, but this is only at the expense of the vertical resolution and the resulting aspect ratio is close to 16:9, which is currently the most widely used aspect ratio of computer screens, television screens, and of the sources of image data in the form of video cameras and cell phones. Therefore, the loss of these vertical pixels is not a serious drawback. The sensor size corresponds to the most commercially used lens format APS-C, which, due to the volume of the economy, offers the best price/performance ratio. The dynamic range value is specified by the manufacturer only in the HDR mode for both rolling and global shutter modes, in which, the DR is above average for both rolling and global shutter sensors. The manufacturer does not specify the frame rate for 12-bit global shutter mode. Higher frame rate can be achieved at lower bit depths, but they require the use of a higher number of LVDS channels (40 LVDS for 11 bits and 80 LVDS for 10 bits), which, with the MicroZed development board, is not (involving other systems and control signals) feasible. The increase of the frame rate is also

2 On the 2016/11/07 CMOSIS announced that it has developed a global shutter sensor with the resolution of 47,5Mpx, and thus offers the highest resolution on the market (for global shutter CMOS sensors).[40] Approximate price per piece is around US$3,800.[41]

29 possible by reading fewer rows (ROI), but this will increase the aspect ratio to the aspect ratio, that is too widescreen for the application. As of 2016/12/1, the sensor is in a development stage.[44, 45]

SONY IMX253

The important advantage of the IMX253 is the implementation . The sensor requires three different power supplies (for comparison, GSENSE5130 re- quires 13), 11 single-ended channels are used for the operation (for comparison, GSENSE5130 requires 39). Up to 16 LVDS channels are used for the image data transfer. 2 sync signals (XHS, XVS/XTRIG) + 1 clock signal (INCK) are used for the image capture control process. Length of exposure can be set directly in the regis- ter value or by controlling one of the control signals (XTRIG). The sensor has an internal CDS, which eliminates further demands for the development and for the surrounding system computing capacity. The IMX253 supports vertical ROI, which allows increasing the frame rate by reducing the number of readout rows. Sensor size is equivalent to the C-mount lenses in 1” to 4/3” variant. The C- mount lenses are commonly used for scientific, industrial, security and other appli- cations. They are usually small, cheap and high quality for their price. Importance was also given to the reputation of SONY. Most of the parameters in the datasheet are either not mentioned, or to be done. The big advantage of this sensor is a good price compared to the other sensors.[46, 47]

1.2.2 Conclusion

The main favorites were Gpixel GSENSE5130 and SONY IMX253. Both of the sensors have above average parameters overall. Both of the sensors are priced at the lower end of the range of the considered sensors (partially, but not limited to smaller dimensions). Both of the sensors were freshly introduced to a market. The main deal breaker were high requirements from the GSENSE5130 on the number of data channels which prohibited the usage of the sensor to its full potential with the used development board. Other advantage of IMX253 is the good reputation of SONY and previous experiences of the PSI, spol. s r.o. company with SONY image sensors. Therefore, the SONY IMX253 was selected for the further camera development.

30 2 CAMERA CIRCUIT DESIGN

Fig. 2.1: High level block scheme of hardware layer

2.1 Avnet MicroZed Development Board

The essential part of the MicroZed development board is the Xilinx Zynq System on Chip with 1GB DDR3 RAM and 128Mb flash memory on the board. The de- velopment board allows the connection of 1Gb Ethernet, the USB and the microSD card. There are two 100-pin connectors, from which 50 pins of each connector are connected to the FPGA IO ports of the Zynq programmable logic, the remaining pins provide access to power supply, JTAG, processing system PMOD, and other signals. On board, there are also dedicated PMOD connectors that provide access to 8 pins directly connected to the processing part of Zynq.[48]

2.1.1 Xilinx Zynq System on Chip

The most important part of the development board is the Xilinx Zynq SoC, which conveniently groups an FPGA chip (Programmable Logic part) and a dual-core ARM Cortex-A9 processor (Processing System part) to a single chip.[49]

31 2.1.2 Banks and Connectors

100-pin connectors are connected to the bank 34, 35 and 13 of the Zynq. All pins belonging to the bank share its power supply.[48]

Fig. 2.2: IO Bank connections

The pins of the bank 34 are connected to the systems, which do not communicate with the sensor. The voltage of the entire bank has voltage of 3.3V. The LVDS channels communicating with the sensor are connected to the bank 35, the supply voltage of the bank is 2.5V as is specified for the LVDS channels by the IMX253 requirements. The pins of the bank 13 are connected to the sensor other control signal channels, the supply voltage of the bank is 1.8V. The figure 2.2 also shows how the power supply of the MicroZed itself is handled – using altogether nine 5V pins. The pins of the bank 34 and 35 are interlined with ground pins for better signal integrity.

2.2 Power Supply

Several different power supplies are required for the camera (denoted by their volt- age): 3.3V, 1.8V and 1.2V for the sensor; 1.8V is used for communication with the sensor and thus also serve to power supply the bank 13; 2.5V to power the bank 35

32 which drives the LVDS channels and 5V for the MicroZed main power supply.[48] Together, 5V and 3.3V are also required for the external systems (motor control, I2C, proprietary communication). The table of individual power supplies is shown below:

Supply Voltage [V] Max. current [mA] Analog/Digital IMX253 3.3VA 3.3 390 A IMX253 1.8V 1.8 55 D IMX253 1.2VA 1.2 350 A MicroZed 5V 5 1400 D MicroZed 3.3V 3.3 ? D MicroZed 2.5V 2.5 <55 D MicroZed 1.8V 1.8 <55 D Motor 5V 5 ? D

Tab. 2.1: Power Supply Table

The table 2.1 shows that the highest demands are for the MicroZed itself and probably the motor (specifications were not provided). Because the 5V power sup- ply is handled externally, there is no need to place additional components onto the board. Large currents are also present for the sensor analog power supplies. Be- cause this would be 663mW (3.3VA) and 1330mW (1.2VA)1 that linear regulators would emit in the form of heat, the voltage drops are reduced by switching-mode power supplies first and the lowered voltage is stepped-down/stabilized with linear regulators afterwards. Because there is not enough space on the board, the voltage will be reduced by the switching-mode power supply beforehand only for the 1.2VA power supply. The switching-mode power supply from 5V to 1.8V is used for this regulation. This SMPS is used for the 1.8V power supply, which powers the IO bank 13 of the MicroZed. A linear regulator would be sufficient for powering of the bank itself, but because it can be employed for powering the 1.2VA power supply, the SMPS is used. A linear regulator is sufficient for supplying the bank 35 (2.5V), therefore it is used.The bank 34 (3.3V) is used for other systems of the PSI, spol. s r.o. company and may require more power for some applications, therefore a SMPS is used.

13.3VA and 1.2VA are meant as designation of a specific power supply rather than Volt Ampere value, in this case, the VA denomination means Volt/Analog

33 2.2.1 Digital Power Supply

Because digital circuits operate at two levels (low and high), the only requirement from the power supply is to reliably maintain the voltage level with noise low enough to not to exceed the logic threshold levels. This means that the power supply does not have strict demands in terms of noise and voltage characteristics. Therefore, an efficient switching-mode power supply can be used. Because switching-mode power supplies require multiple components that take up more space on the PCB, can generate electromagnetic interference and can be economically inefficient, they are used only where power losses would be toosig- nificant. If the target voltage is only slightly lower than the source voltageand the target circuit requires low power for its function, it is preferable to use a linear regulator.

2.2.2 Analog Power Supply

The analog power supply is a power supply that supplies noise/voltage level sensitive circuits (components), therefore it needs to keep the voltage stable and accurate. In this case, the sensor requires the analog power supply for either the 3.3VA and the 1.2VA pins. It is necessary to use the linear regulators for this power supply, which provide an effective way to achieve a stable and precise voltage. Since these regulators must dissipate the excess energy as heat, it is convenient to step-down the voltage with the switching-mode power supply and then stabilize it by a linear regulator. This is done only with the 1.2VA supply, because of space and economic reasons.

2.2.3 Power Decoupling

One of the most effective ways to eliminate noise (generated by pin coupling) isby using the decoupling capacitors. They are placed as close as possible to the current sink (the pin, into which the current flows), and ensure that the current peaks are carried out of the decoupling capacitor, instead of flowing directly from the high impedance source (the power source and trace impedance). Moreover, because the traces do not have zero impedance and power planes are used for the power distribution, the pin which draws current may influence other pins regardless of the source. The decoupling capacitors should reduce this effect. Most of the decoupling capacitors used in the design are 100nF ceramic capacitors. Bulk capacitors are used to smooth the power supply voltage and hold the con- stant voltage level even with high current peaks. They are placed close to the

34 source. The bulk capacitors used in the design are tantalum capacitors usually with capacitance of 10휇F and 100휇F.

2.2.4 Grounding

The ground is common for all the power supplies, as is recommended by the man- ufacturer and with proper decoupling, there is no need to keep it separate. The ground is realized by a separate ground plane (and copper pours on signal layers). Also, for high speed signals, it is required for the ground plane to be undivided, otherwise, this would cause impedance mismatches and big current loops causing EMI and crosstalk problems. [57]

2.3 SPI

The sensor communicates via SPI and I2C, the SPI and I2C share the same pins, therefore, the appropriate connection needs to be taken into account. The configu- ration is as follows:

PIN Termination [Ω] Connection XCE 10 Signal SCK/SCL 10 Signal SDI/SDA 10 Signal SDO 10 Signal SLAMODE 10k Pulldown

Tab. 2.2: SPI configuration

PIN Termination [Ω] Connection XCE 10k Pullup SCK/SCL 1k Pullup, Signal SDI/SDA 1k Pullup, Signal SDO N/A Not Connected SLAMODE 10 Signal

Tab. 2.3: I2C configuration

The sensor, in this case, is configured in the SPI configuration.

35 2.4 Clock Signals

Because the clock signals are generated continuously and the frequencies of the input clock signal (INCK) are either 37.125MHz, 74.25MHz or 54MHz, requirements for the signal integrity are strict. The signal integrity is achieved by leading the traces as short as possible with the fewest number of transitions between layers. Also, the INCK trace is terminated with a 10Ω resistor. The INCK clock duty have to be in the range of 45–55%. Either low and high (<20% of 1.8V and >80% of 1.8V, respectively) level pulse width of the INCK should not be shorter than 4ns. These requirements can be kept by the Xilinx Zynq.

2.5 Low-voltage differential signaling

Low-voltage differential signaling is a type of signaling in which the signals are transferred by a pair of conductors with opposite polarities. The information is transmitted by a voltage difference between them instead of the absolute voltage level as with the single ended signaling. Because the induced current is inflicting the absolute voltage level on both the conductors, it does not inflict a voltage dif- ference between them, therefore, the LVDS pairs are much more resistant to the electromagnetic interference. The electromagnetic field generated by pulses in the conductors is also reduced by their opposite polarities. The current in these con- ductors needs to flow physically close and in the same time, otherwise the EMIcan not be effectively reduced. The LVDS channels have to be impedance matchedby 100Ω termination resistors, this is provided by the Zynq and needs not to be done separately on the board.[55] The impedance has to be matched over the entire path. This especially means keeping the same capacitance of the path. This is achieved by leading the pairs in the same distance from the ground plane, which should not have any discontinuities. The pairs should also remain in the constant distance between each other over the entire length of the traces. The pair should keep the same width over the entire length of the traces to avoid the impedance mismatch and reflections. The sharp angles of the trace turns can also cause reflections, therefore,° 45 turns are preferred. Because the power of the electromagnetic field drops with the square of distance from the transmitter in free space, a single ended trace can induce current only in one of the traces in the pair if the single ended trace is in close proximity to the LVDS pair. This would not be rejected as a common node noise by the receiver and would affect the signal quality. Because the ground and the power supply planes are neighboring the signal traces and the copper pours are used to spread the ground evenly in signal layers, the LVDS pairs and single ended signal traces can be much

36 closer to each other without significantly affecting the signal quality. Also, the crosstalk can be reduced by reducing the slew rate of the single ended signals. As a rule of thumb, the pair length differences should be no more than 25mm otherwise the phase difference can cause EMI. Considering two connectors inthe path of the LVDS channels in the module and adding a reserve, the length difference tolerance of the PCB traces should be no more than 10mm.[53][54]

2.6 Signal Conditioning

Some signals are low frequency, however, these signals are driven the same way as high frequency signals by the sensor. Since any change in current induces magnetic field, it is appropriate to mitigate these current changes and thereby remove high electromagnetic interference spikes. For signals coming from the Zynq, this can be achieved by decreasing the slew speed rate of the signal. Sensor manufacturer recommends which traces should be terminated with resistors to avoid reflections.

37 3 PRINTED CIRCUIT BOARD DESIGN

Another equally important factor of the camera design is the design of the PCB, i.e. physical connection and placement design. This contributes significantly to the parameters of the camera, the quality of the output image, to the convenience of the camera use, to electromagnetic interference either from the inside and to the outside and also to the overall cost. The overall concept is, for backward compatibility, based on the current design of the other cameras of the PSI, spol. s r.o. company. This will be especially applicable to the location of certain components (the sensor, connectors), dimensions, shape, types and technologies of the boards. The design is based on one board holding the sensor, one board generating the analog power supply and the other board interconnecting most systems, generating the digital power supply and handling the rest.

38 3.1 Sensor Board

Fig. 3.1: Sensor board layout

This is a 6-layer board with dimensions of 64mm x 44mm. The separation of the analog (3.3V) power supply is shown with the white outline in the figure 3.1. The analog power supply is divided near the source (connector) into several branches, the branches avoid the sensor as long as possible. It is important that the least amount of signal traces go across the power planes. The bundle of the LVDS channels can be seen on the right of the sensor as they avoid the power supply planes as they lead to the bottom connector. All LVDS traces pass over the 1.8V power supply plane only, so that the reference voltage remains the same over the entire length of the traces. The figure 3.2 shows the layout of the location of a decoupling capacitor on the other side of the board. Because it is very important that these capacitors are as close as possible to the belonging pads and there are so many of them that they can not be put around the sensor with required conditions met, it is necessary to use blind vias which can be placed the under sensor pads without being electrically connected to them. The sensor requires a connection of certain capacitors to a few specific pads for proper operation. It is critical for the capacitors to be connected by the shortest path possible to the pins. The bad connection, i.e. high impedance trace, may

39 result in image noise. If it is not possible to place the components near enough to the sensor due to lack of space, the components are arranged according to the priority from the most important to the least important: 1. Sensor specific capacitors for certain analog pins 2. Low capacitance capacitors 3. High capacitance capacitors 4. Ferrite beads and inductors 5. Resistors

Fig. 3.2: Detail of decoupling capacitor

In the figure 3.2, the decoupling capacitor is highlighted with a purple rectangle. It is obvious that the capacitor pads are overlapping with vias (blue circle framed within gray circle). For economic reasons, the vias are blind from one side only, therefore, vias can not overlap with the sensor pads (red circles).

40 3.2 Board Connected to the MicroZed

Fig. 3.3: Layout of the board connected to the MicroZed

Because this board does not require as concentrated placement and connections as the sensor board, it is possible to use only 4 layers. Because of the economic and space reasons, the board is automatically fitted only on the top side, the components on the other side are fitted manually, therefore, only connectors are on the bottom side of the board. This board has the largest dimensions (118mm x 84mm), and there are areas that are physically far away from all noise sensitive traces, therefore the switching- mode power supply circuits are placed on this board. The SMPS are located at the bottom of the board to be away from the noise sensitive traces. The component placement of the switched-mode power supply is crucial because there is a close relationship between individual components. Because of the limited space available on the board, the SMPS connection is mostly a compromise. In the figure 3.4, it is shown that the power and ground solder pads of thecom- ponents are connected via the shortest path possible through vias to the respective power or ground layer. The traces avoid the inductor (L4), so it will not cause electromagnetic interference. The most critical paths of the SMPS are implemented using copper pours instead of microstrips. The wiring of the SMPS is based on the IC manufacturer recommendations[52] The demonstration of the power supply wiring of the bank 35 of the Zynq is in the figure 3.5. The power supply is connected via the shortest path possible through

41 Fig. 3.4: Layout of the switching-mode power supply

Fig. 3.5: Detail of decoupling capacitors placement the via from the power layer. Likewise, the decoupling capacitors are connected as close as possible without overlapping with the connector or getting in the way of the LVDS channels. In the figure 3.6, there is a clearly visible bundle of the LVDS lines in thebottom layer of the board. The LVDS pairs lead near each other and with the minimum number of transitions between the layers and other discontinuities, i.e. going over different power planes or at sharp angles. It is important that all the pairs arethe same length within a group (the sensor has two LVDS groups and each group has its own output clock signal, so the groups can have different lengths) and so the signals do not come at different times. It is equally important that the traces are the same length within the pair, as the voltage is to be compared in the differential amplifier of the Zynq.

42 Fig. 3.6: Layout of bottom layer of the board connected to the MicroZed

3.3 Analog Power Supply Board

Fig. 3.7: Layout of the analog power supply board

The analog power supply is on the separate board, making it sufficiently dis- tanced from the electromagnetic interference of the other boards. Only the linear regulators and their associated circuitry are on this board. The board is only double layer and has dimensions of 64mm x 18mm. The source voltage is coming from the board connected to the MicroZed (5V and 1.8V). The analog power supply leads via the connector to the sensor board.

43 4 XILINX ZYNQ CONFIGURATION

Fig. 4.1: High level block scheme of software layer

All the image sensor systems are operated by the Xilinx Zynq SoC. After design- ing the hardware part, the system needs to be programmed to be able to communi- cate with the sensor and store the image data. The development is exercised in the Xilinx Vivado (Programmable Logic) and the Xilinx Software Development Kit (Processing System). In the figure 4.1, the block scheme of the whole system is shown.

44 4.1 Programmable Logic

All functionality of the Xilinx Zynq SoC is in the Vivado implemented with intellec- tual property cores. IP cores are black boxes, which compute a predefined function and the internal implementation is hidden from the user. In this paradigm, even the processing system itself is implemented as an IP core and the processing system (a dual-core ARM Cortex-A9 processor) is initialized by putting the core into the project block design. Various parameters, such as processor periphery, e.g. inter- rupts, SPI, phase-locked loop clock generators and high speed signals are specified in the core configuration form. The IP cores are usually protected by license terms; as s general rule, the Xilinx IP cores are limited for use in belonging model series of its products. The purchase of a license is needed for usage of 3rd party IP cores. The intellectual property is protected by black box behavior of the cores, which hide the source code. However, the user functions are also realized as IP cores, so the whole project is implemented systematically. A user can see and modify the source code of these IP cores. A Vivado tool – the IP Core packager lets the user create the IP cores in its entirety, it is therefore possible to create locked cores (with the source code hidden), configuration forms, so the user can easily modify parameters of the core andsoon. These IP cores are an analogy to the functions in common programming languages or hardware peripheries. A function of certain used/developed cores is clarified below.

4.1.1 IP Cores

Zynq 7 Processing System

A dual-core ARM Cortex-A9 processor is initialized by this core. All the IP cores which communicate with the PS are connected to this core via the ARM AMBA AXI4-lite bus. The AXI4-lite bus provides an address mapped access to IP core registers for the PS of the Zynq. A further description of the processing system from the software point of view is provided in the independent chapter.

Power-On Sequencer

Because the IMX253 is not operation ready immediately after power on, this IP core sets signals to the required levels and counts the clock signal. After the defined intervals (there are 3 interval stages), the core sets new signal levels, enables the other IP cores and enables the main clock signal to the image sensor.

45 SPI

Because the IMX253 allows to communicate only in certain short intervals between frames, the SPI is realized by a dedicated IP core in the programmable logic instead of using an existing SPI in the Zynq 7 Processing System, which can not be precisely synchronized with the control signals. Transferred data are sent from the processor to the IP core via the AXI bus and sent by the core immediately when possible. After a complete SPI transfer, the IP core notifies the processor that the data were sent and the processor can continue to send next data.

Timer

The generation of the synchronization signals of the image sensor is handled by the Timer IP core. It also indicates a transfer of valid image data to the other cores. This is important for a LVDS receiver training. The SPI communication of the SPI IP core is also allowed/prohibited by the Timer.

SelectIO Interface Wizard

This IP core implements serializers/deserializers and delay blocks. The image data are converted from the high-speed LVDS channels coming from the image sensor to a more FPGA friendly form – parallel data at much lower frequency. The data are sent via 16 channels in 12-bit form from the IMX253. Because the data are received via 16 channels, with each having a different delay, this core allows to configure an individual delay for each channel. This delay is configured for sampling of each bit (so the sampling is executed in the middle of the eye diagram) and for a bit position in a 12-bit sequence. Certain important parameters are explained below. • Data Rate Because the image sensor transfers the data on either rising and falling edge of the clock signal, DDR should be selected. • I/O Signaling - Type The transfer is carried out by low-voltage differential signaling at standard 2.5V. • Serialization Factor This core can implement SERDESes only in 4, 6, 8, 10 and 14 bits, therefore it is configured for a 6 bit serialization factor and these data need to be processed in subsequent IP cores. • External Data Width

46 The 16 LVDS channels are used for the data transfer. • Data Delay - Delay Type The option Variable gives the access to run time delay setting.

96bit to 16x6bit

Because the data from the SelectIO Interface Wizard are bit aligned (the zero bit of the 1st channel, the zero bit of the 2nd channel, the zero bit of the 3rd channel...), this core sorts these data by order and their respective channels (the zero bit of the 1st channel, the 1st bit of the 1st channel, the 2nd bit of the 1st channel...).

6bit to 12bit

This core merges a sextuplet of bits to a set of twelve bits at half the frequency. The IP core also expands bit delaying capabilities, because the SelectIO Interface Wizard IP core can bitslip only by maximum of 6 bit.

Delayer

Because the image data come in parallel via 16 LVDS channels and two LVDS clock channels, they need to be synchronized with themselves and with the clock signals. The process is such that the processor sends a command to the image sensor via SPI to output the vertical strip pattern instead of the actual image. Subsequently, the processor notifies the Delayer IP core, that it wants to align bits with theclock signal. The delayer waits for the command from the Timer, which knows (estimates) when the image data are valid, because the Timer generates the control signals, and once the Delayer receives a confirmation, it takes a 12-bit sample from a selected channel. The core then sends this sample to the processor. The processor compares the sample with a reference value – the processor knows that the valid sequence is “010101010101” or “101010101010” (the same sequence shifted by 1 bit). If the sample and the predefined sequence match, then it notes the offset position and sends the instruction to add a delay to the Delayer core. This process is repeated until the processor detects another match. This process is repeated once more until another match is recorded. The position of this third match is recorded and the mean delay is calculated from the first and the third match. This mean delay is the center of the eye diagram and provides the least number of errors. The processor sends the delay command to the Delayer so many times that the delay value returns to the position of this calculated mean delay (the Delayer can increment only by one step at a time). The processor then notifies the Delayer that it wants to align bits within a 12 bit word. Delayer then bitslips (shifts bits within 12-bit words) by

47 one bit each frame until it reads a valid new line sequence (which is a unique bit sequence). The whole process is then executed for the remaining channels. The process is indicated in a simplified flowchart 4.2.

Fig. 4.2: Simplified LVDS synchronization flowchart

UserROI

This IP core controls the data to be stored in memory – it allows to define an image crop and defines various image parts.

48 AXI4-Stream Data FIFO

The AXI4-Stream Data FIFO is used to transition between asynchronous clock domains – the image sensor clock domain (74.25Mhz) and the AXI Stream clock domain (200Mhz). Additionally, it is used to convert the bit width of the data – 192 bits to 24 bits.

AXI Direct Memory Access

The AXI DMA provides a way to direct access the RAM memory without CPU co- operation. The IP core changes the incoming AXI Stream to the memory-mapped data. Because the maximum frequency of this block is 200Mhz with the bit depth of 32 bit, the maximum DMA channel throughput is 6.4Gb/s. Because the maximum of 9.504Gb/s is sent by the IMX253, two DMA channels need to be used. The UserROI IP core switches the channels every new line, so the bandwidth is spread evenly. Certain important IP core parameters: • Enable Scatter Gather Engine In a direct register mode (simple DMA), whenever the DMA wants to write to memory, it sends the interrupt to the processor and expects a pointer to a memory space. This interrupt needs to be transferred whenever the DMA writes a block of data. In a scatter gather mode, the processor creates an address table from which the DMA reads as it writes to memory and does not require further CPU collaboration when the data are stored. This takes up more FPGA resources, therefore, it is possible to save the FPGA logic resources by disabling the SG mode when only low speed transfers are needed (which is not the case with this application). • Enable Multi Channel Support Since the maximum DMA channel bandwidth is 6.4Gb/s and for the full speed data transfer from the IMX253, the bandwidth of 9.504Gb/s is required, it is necessary to use a multi channel support and to use 2 DMA channels with the total bandwidth of 12.8Gb/s. In order to ensure an uniform load and predictable operation, the channels alternate with new image row (this is con- trolled by the UserROI IP core). • Memory Map Data Width A memory map data width represents the bus bit width of the MicroZed. Data width in bits of the AXI MM2S Memory Map Read data bus. Valid values are 32, 64, 128, 256, 512 and 1,024. It is automatically defined as 32 bit by Vivado because MicroZed RAM has a 32 bit port.

49 • Max Burst Size Lower max burst size decreases the bandwidth, but allocates more resources to the other AXI buses. A higher max burst size increases the bandwidth at the expense of the bandwidth of the other AXI buses. Because this IP core transfers by far the largest amount of data, the maximum possible max burst size is selected.

4.2 Processing System

The system runs bare metal and only the basic service of IP cores in the PL part of the Zynq and basic libraries for the processor control and UART communication are implemented in the PS. Within the entire system, the PS part acts as a master and the PL part acts as a slave. The initial initialization of the PS part, the PL part and the image sensor (in- cluding the register setting) is executed as follows: 1. Platform initialization 2. Timer mode setting (the image sensor implements two control modes – using vertical and horizontal synchronization pulses and using horizontal pulses in a combination with a trigger pulse) 3. Timer trigger duration setting 4. Definition of image parts to be stored in memory in the UserROI IP core(start row, end row, start column, end column) 5. SPI IP core interrupt initialization 6. Image sensor register setting 7. Image sensor standby mode disable 8. Timer synchronization pulses enable

50 5 DESIGN VERIFICATION

Because of two critical problems, which were not resolved, the camera is not in a functional state, therefore its testability is limited to theoretical level. The errors are described in their respective chapters.

5.1 Hardware

5.1.1 Sensor Board

One critical problem was made during designing this board – the image sensor PCB decal was designed mirrored. The package outline in the image sensor datasheet is specified from a direct view perspective (the way the outline looks when it is looked upon directly at the pads of the sensor). The image sensor PCB decal was designed from a see through perspective (the way it would look on paper if the sensor would be used as a stamp). This caused the need to redesign the sensor board and caused a delay. The right bottom pad in the figure 5.1 shows the error. In the figure 5.2, three errorsare

Fig. 5.1: Image sensor package outline misalignment highlighted by the design software. Two errors are just text outside the board outline, which is important as an information for the PCB maker, but is not purposefully utilized on the board. The other error is highlighting the connector that sticks out of the board, which also is not actually a problem. The length differences of the LVDS channels are less than 2mm in their group, which is within the specified tolerances. The maximum length differences are spec- ified considering the other board – the board connected to the MicroZed, which

51 Fig. 5.2: Sensor Board clearence errors also has LVDS channels and the combined differences must not exceed the specified tolerances. Because this board has more compact dimensions, the bigger portion of the specified tolerance (10mm) is utilized with this board. It was possible tokeepthe length differences under 2mm.

5.1.2 Board Connected to the MicroZed

One critical problem was made during designing of this board – confusion of type of 100-pin FCI BergStag microheaders leading to the MicroZed. This means that all the connections that are not symmetrical (all signal pins, certain power supply pins) are wrong. Most of signal pins are reconfigurable in the FPGA but pins carrying the clock signal can not be reconfigured, because clock signals use special FPGA inputs and outputs. The LVDS signals also need special inputs, but these are symmetrically connected to the microheaders. The figure 5.3 shows one of the microheaders with critical connections highlighted with red rectangle. These problems are: power supply connected to a signal pin, 2x LVDS clock signals connected to regular LVDS pins, power supply connected to ground and power supply connected to a signal pin. This error caused the need to redesign the board connected to the MicroZed and caused a delay. In the figure 5.4, the errors are highlighted by the design software. Theerrors are highlighting the connectors that stick out of the board, which is not actually a problem.

52 Fig. 5.3: Microheader critical errors

Fig. 5.4: Board connected to the MicroZed clearence errors

The length differences of the LVDS channels are less than 0.2mm in their group, which is within the specified tolerances. The maximum length differences are spec-

53 ified considering the other board – the sensor board, which also has LVDS channels and the combined differences must not exceed the specified tolerances. Because this board has less compact dimensions, it was possible to keep the length differences under 0.2mm.

5.2 Software

5.2.1 Power-On Sequencer

The sequence of signal enabling is shown in the figure 5.5. This sequence corresponds to the requirements stated in the IMX253 datasheet. Because a start up time of the camera is not critical, the initial interval has a reserve time offset.

Fig. 5.5: Power-On sequencer simulation

5.2.2 SPI

The simulation in the figure 5.6 shows a complete data transfer. First, the register data_valid is set to 1, so that the SPI IP core recognizes that the PS part com- pleted its data transfer to the IP core. Consequently, the IP core waits until the signal allowed is set to 1. This signal is generated by the Timer and signalizes that the communication may begin. The communication is initialized by setting the xce signal to 0 and generating the clock signal sck. The chip_id, start_address and data_out, respectively, are transferred and the xce is set to 1, which signalizes the end of communication to the image sensor. The signal communication_ok is then set to 1, which is an acknowledgment (interrupt) for the PS part that the commu- nication was completed. The simulation in the figure 5.7 shows the communication interrupted by the allowed signal set to 0. This causes the communication to stop and the communication_ok signal remains 0.

54 Fig. 5.6: SPI simulation

Fig. 5.7: SPI simulation 2 - communication interrupted

5.2.3 Timer

The simulation in the figure 5.8 shows a synchronization signal generation inthe normal mode – the horizontal (xhs) and the vertical (xvs) signals are used. Also, the communication_allowed has value of 1 for the first 4 line intervals in the frame

55 as is specified in the IMX253 datasheet. The simulation in the figure 5.9showsa

Fig. 5.8: Timer simulation - normal mode synchronization signal generation in the external trigger mode – the horizontal (xhs) and the external trigger (xtrig) signals are used. The trigger in the simulation is set for 2 line intervals exposure. Also, the communication_allowed has value of 1 for the first 2 line intervals in the frame as is specified in the IMX253 datasheet. The

Fig. 5.9: Timer simulation - external trigger mode

56 simulation in the figure 5.10 shows the image_data_valid signal, which has value of 1 when valid image data are generated. In the end and start of every line, there are sequences of non-valid image data.

Fig. 5.10: Timer simulation 2 - external trigger mode

5.2.4 96bit to 6x6bit

The simulation in the figure 5.11 shows a conversion of 96-bit data in data_in signal to 6-bit data in data_out signal. The alternative, more distinct expression of the data_out signal is in the bottom line, where the bits are separated by commas.

Fig. 5.11: 96bit to 16x6bit simulation

5.2.5 6bit to 12bit

The simulation in the figure 5.12 shows a conversion of 6-bit data in data_6bit signal to 12-bit data in data_12-bit signal of half the frequency. The data are in the least

57 significant bit first order in the simulation window for better presentation.

Fig. 5.12: 6bit to 12bit simulation

5.2.6 UserROI

In the simulation in the figure 5.13, the valid signal represents data to be storedin memory. The valid signal has value of 1 for three inck (main clock) cycles. This represents three pixels as is defined by first_column and last_column signals (0– 2). The image_data_valid_from_signal signal defines a valid image signal. The selected_image_data_from_signal defines user defined regions of the valid image data signal. These are depended not on the synchronization pulses as with the Timer IP core, but on the synchronization sequences read from the data_in_vector signal. Changes of this signal can be seen in the simulation window and these changes are a simulated start of valid line, which causes the signals to change and increments counters.

Fig. 5.13: UserROI simulation

58 6 CONCLUSION

The suitable commercially available high resolution RGB image sensor was selected. Relevant image sensor parameters and a selection process are described in this thesis. The selected image sensor is SONY IMX253 CMOS global shutter image sensor with the resolution of 13.3Mpx and the frame rate of 46.4 fps. The IMX253 comes in a color variant with the Bayer color filter array. The optical area of the sensor has dimensions of 14.1mm x 10.6mm. The sensor was chosen with respect to the compatibility with the Avnet MicroZed development board. Subsequently, the electronic circuit design and the printed circuit boards were designed according to the requirements of the image sensor and the PSI (Photon Systems Instruments), spol. s r.o. company. This especially includes the correct signal wiring respecting the requirements of all the components, e.g. the fact that not all the pins of the Zynq PL part are equal, signal conditioning for the integrity preservation, the power supply distribution imperfections elimination with decou- pling and bypass capacitors and the proper high speed signal tracing. The power supplies are designed (and appropriate integrated circuits are chosen) to meet the circuit requirements, as regards to the voltage levels, the output signal stability and the maximum output current. Since the camera is realized using several PCBs, appropriate connections via connectors were designed with respect to the economic aspects, the physical layout of the boards and the integrity of signals going through the connector and on the subsequent boards. The module is formed by 3 printed circuit boards. The first board is a 6-layer board holding the sensor. The board has large density of connections, the components are mounted on the both sides of the board and use of blind vias was required for effective power decoupling. The board is made inthe highest constructional accuracy class of all the boards, this is especially important due (but not limited) to ergonomics, economics and noise sensitivity. The first prototype of this board, however, contained an error and the board needed to be remade. The error was a mismatch between the package outlines of the image sensor and caused most of the connections on the board to be connected mirrored. The second board is the largest, therefore, the most components are placed onto this board and the board connects the whole circuit with the MicroZed development board. This is a 4-layer board, and the components are placed on one side only (the other side of the board is manually fitted with connectors). The board is of lower constructional accuracy class as it is not as densely populated as the sensor board. The first prototype of this board, however, contained an error and the board needed to be remade. The error was a selection of the wrong type of the microheader, which caused connections to be swapped by columns of the microheaders (50x2 pins x2

59 microheaders). The third board is a board with the analog power supplies for the sensor. The board is 2-layer only and is the smallest of them. The analog power supplies have a dedicated board because of space requirements and for reduced electromagnetic interference from other components. Several functions are implemented in the Xilinx Zynq SoC. The developed func- tions (generally carried out by the programmable logic and the processing system parts of the Xilinx Zynq SoC) are image sensor register controlling (via SPI), syn- chronization signals generation, LVDS synchronization, image sensor initialization and data pre-processing. The other implemented functions (developed by 3rd par- ties) include deserialization of the image data and their storage to RAM. Eventually, a simple design verification is executed. Because the designed PCB prototypes contained errors, which caused delays and new PCB prototypes were not made in time until the deadline of this thesis, it was not possible to verify the module functionality practically. Therefore, in the ending of the thesis, the errors are described, a simple PCB verification is executed, a simple verification ofthe Xilinx Zynq SoC configuration design in the form of simulations is executed and the functionality of functional blocks of this configuration is described with the simulations.

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[52] LTC1701/LTC1701B: 1MHz Step-Down DC/DC Converters in SOT-23 [on- line]. [cit. 2016-11-17]. Dostupné z: .

[53] Board Design Guidelines for LVDS Systems [online]. [cit. 2017-05-2]. Dos- tupné z: .

[54] LVDS Owner’s Manual [online]. [cit. 2017-05-2]. Dostupné z: .

[55] 7 Series FPGAs SelectIO Resources [online]. [cit. 2017-05-2]. Dostupné z: .

[56] Zynq-7000 All Programmable SoC [online]. [cit. 2017-03-15]. Dostupné z: .

[57] High-Speed Layout Guidelines [online]. [cit. 2017-02-21]. Dostupné z: .

[58] Digital Cameras: Does Pixel Size Matter? Roger N. Clark [online]. [cit. 2017- 01-05]. Dostupné z: .

[59] Vertical Smear Genetichazzard [online]. [cit. 2017-01-05]. Dostupné z: .

66 LIST OF SYMBOLS, PHYSICAL CONSTANTS AND ABBREVIATIONS

AA Anti Aliasing

APS-C Advanced Photo System type-C

CCD Charge Coupled Device

CDS Correlated Double Sampling

CFA Color Filter Array

CMOS Complementary Metal Oxide Semiconductor

DDR Double Data Rate

DMA Direct Memory Access

DR Dynamic Range

FF Full Frame

FPGA Field Programmable Gate Array

FPS Frames Per Second

FWC Full Well Charge

HDR High Dynamic Range

IC Integrated Circuit

IR Infrared

IR-cut Infrared cut

LVDS Low-Voltage Differential Signalling

PL Programmable Logic

PS Processing System

QE Quantum Efficiency

ROI Region Of Interest

SG Scatter-Gather

67 SMPS Switching-Mode Power Supply

SNR Signal-to-noise Ratio

SoC System on Chip

UV Ultraviolet

68 LIST OF APPENDICES

A Contents of enclosed DVD 70

B Circuit Design of the sensor board 71

C Layout of the sensor board 74

D Circuit Design of the board connected to the MicroZed 78

E Layout of the board connected to the MicroZed 84

F Circuit Design of the Analog Power Supply Board 90

G Layout of the analog power supply board 91

H LVDS Length Differences - Sensor Board 92

I LVDS Length Differences - Board connected to the MicroZed 93

69 A CONTENTS OF ENCLOSED DVD

PCBs Sensor board Sensor board - Layout.pdf Sensor board - Schematics.pdf Board connected to the MicroZed Board connected to the MicroZed - Layout.pdf Board connected to the MicroZed - Schematics.pdf Power supply board Power supply board - Layout.pdf Power supply board - Schematics.pdf Source codes C Main.c Spi.c Timer.c Delayer.c UserROI.c Register_map.c VHDL Power-on_sequencer.vhd Spi.vhd Timer.vhd Delayer.vhd UserROI.vhd 6bit_to_12bit.vhd 96bit_to_16x6bit.vhd Sensors.xls Thesis.pdf...... Master’s Thesis

70

B CIRCUIT DESIGN OF THE SENSOR BOARD D C B A 1 REV: DATE: APPROVED: 1 SHEET: OF DRAWING NO: REVISION RECORD IMX253 ECO NO: LTR SIZE: U1-B IMX253 Sensorboard 2 PSI (Photon Systems Instruments) IMX253 VCP1 VCP2 VRLOFG VRLTRX VRLSEL VBGR VRLTRG CODE: C7 B8 B7 A8 C6 D6 C47 4u7/6V C10 SCALE: COMPANY: TITLE: C42 4u7/6V 7.9.2016 4.10.2016 K VCP2 DATED: DATED: DATED: DATED: C25 220n K VBGR 3 DATASHEET PAGE 91 Rataj Madeja C36 4u7/6V DRAWN: CHECKED: QUALITY CONTROL: RELEASED: C35 4u7/6V K VCP1 TOUT0 TOUT1 TOUT2 4 10R 10R 10R R2 R1 R5 DLCKP1 DLCKM1 DLOPA1 DLOMA1 DLOPB1 DLOMB1 DLOPC1 DLOMC1 DLOPD1 DLOMD1 DLOPE1 DLOME1 DLOPF1 DLOMF1 DLOPG1 DLOMG1 DLOPH1 DLOMH1 DLCKP2 DLCKM2 DLOPA2 DLOMA2 DLOPB2 DLOMB2 DLOPC2 DLOMC2 DLOPD2 DLOMD2 DLOPE2 DLOME2 DLOPF2 DLOMF2 DLOPG2 DLOMG2 DLOPH2 DLOMH2 T5 U5 T12 U12 R3 T3 T4 U4 P4 R4 P5 R5 T6 U6 P6 R6 T7 U7 P7 R7 P10 R10 T10 U10 P11 R11 T11 U11 P12 R12 P13 R13 T13 U13 R14 T14 F1 G3 F2 U1-A TOUT0 TOUT1 TOUT2 DLOPF1 DLOPF2 DLOPE1 DLOPE2 DLOPA1 DLOPB1 DLOPC1 DLOPA2 DLOPB2 DLOPC2 DLOPD1 DLOMF1 DLOPG1 DLOPH1 DLOPD2 DLOMF2 DLOPG2 DLOPH2 DLOME1 DLOME2 DLOMA1 DLOMB1 DLOMC1 DLOMA2 DLOMB2 DLOMC2 DLOMD1 DLOMG1 DLOMH1 DLOMD2 DLOMG2 DLOMH2 DLCKP1 DLCKP2 DLCKM1 DLCKM2 5 IMX253 INCK SDI/SDA XCE SCK/SCL SDO XHS XMASTER SLAMODE XCLR XTRIG XVS J3 L2 L3 L1 K1 K3 N2 N3 N1 M3 U9 SDI XCE SCK XVS XHS

INCK XCLR

XTRIG 10k R3

R6 10R

10k R4 6 SDO DATASHEET PAGE 92 D C B A

Fig. B.1: 1 - IMX253

71

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

SUPPORT DATASHEET PAGE 5

D +1.8V D VDDLSC SUPPORT DATASHEET PAGE 5 +1.2VA +1.2VA C45 C39 C23 C29 C33 C34 +1.2VA +1.2VA +1.2VA 1u/6V 100n 4u7/6V 100n 4u7/6V 100n +1.2VA +1.2VA

+1.2VA

VDDLCN2 L5 VDDLCN3 L12

L1 VDDLCN1 L3 L9 L11

VDDLSC1 VDDLSC2 L7 VDDLSC3 VDDLSC4 MI1210K600R-1 MI1210K600R-1 MI1210K600R-1 MI1210K600R-1 MI1210K600R-1 MI1210K600R-1 MI1210K600R-1

i.B2 Decoupling - 2 B.2: Fig. C11 C10 C5 C7 C6 C57 C62 C8 C9 10u/6V 100n 100n C61 4u7/6V 100n 100n 4u7/6V 100n 4u7/6V C58 C28 100n 100n 100n C C

+1.2VA +1.2VA +1.2VA +1.2VA

72 DATASHEET PAGE 89

+3.3VA +1.2VA PVLM +1.2VA VDDLPA L2 L10 L13 L6 L4 L8 C1 C2 C3 C50 C51 C53 C55 +1.2VA VDDLCB1 VDDLCB2 VDDLCB3 VDDLCB4

22u/6V 22u/6V 100n 100n 100n 100n 100n MI1210K600R-1 MI1210K600R-1 MI1210K600R-1

MI1210K600R-1 MI1210K600R-1 MI1210K600R-1 C22 C16 C18 C27 100n 4u7/6V 4u7/6V 100n C13 C60 C4 C14 C54 1u/6V 100n 100n 100n 100n B VDDHPX1 VDDHPX2 B5 F11 H5 K12 L5 B

+3.3VA +3.3VA +3.3VA +3.3VA

C52 C59 C32 C15 C56 C26 C40 C20 C21 C41 C43 1u/6V 100n 100n 100n 1u/6V 100n 22u/6V 100n 4u7 100n 100n $$$14753

COMPANY: PSI (Photon Systems Instruments) B4 G5

+3.3VA +3.3VA +3.3VA +3.3VA TITLE: +3.3VA +3.3VA IMX253 Sensorboard DRAWN: DATED: Madeja 7.9.2016 C12 C49 C19 C24 C48 C30 C44 C38 C37 C17 C31 C46 A 1u/6V 10u 100n 4u7/6V 100n 100n 100n 10u/6V 100n 100n 10u/6V 10u/6V A CHECKED: DATED: Rataj CODE: SIZE: DRAWING NO: REV: 4.10.2016

QUALITY CONTROL: DATED: PWR 1 F5 F9 F8

RELEASED: DATED: SCALE: SHEET: OF

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

+1.8V

J5 XTRIG 1 2 DLOMH1 3 4 DLOMH2 DLOPH1 5 6 DLOPH2 7 8 +1.8V DLOMG1 9 10 DLOMG2

i.B3 Connectors - 3 B.3: Fig. DLOPG1 11 12 DLOPG2 SDI 13 14 XCLR DLOMF1 15 16 DLOMF2 DLOPF1 17 18 DLOPF2 19 20 +1.8V DLOME1 21 22 DLCKM2 +1.2VA +3.3VA DLOPE1 23 24 DLCKP2 C SDO 25 26 TOUT0 C DLCKM1 27 28 DLOME2 J2 DLCKP1 29 30 DLOPE2 31 32 +1.8V 1 2 DLOMD1 33 34 DLOMD2 3 4 DLOPD1 35 36 DLOPD2 5 6 TOUT1 37 38 +1.8V 7 8 DLOMC1 39 40 DLOMC2

73 41 42 DLOPC1 DLOPC2 HDR-2X4 43 44 +1.8V DLOMB1 45 46 DLOMB2 DLOPB1 47 48 DLOPB2 49 50 GND DLOMA1 51 52 DLOMA2 DLOPA1 53 54 DLOPA2 TOUT2 55 56 XHS INCK 57 58 XVS SCK 59 60 XCE

QTH-030-01-X-D-A QTH-030-01-X-D-A B B

Mounting Holes

J4 R7 COMPANY: 1 R or L PSI (Photon Systems Instruments) MTG_PT

J1 1 TITLE: MTG_PT IMX253 Sensorboard J3 1 DRAWN: DATED: Madeja 7.9.2016 A MTG_PT A J6 R8 1 CHECKED: DATED: R or L Rataj CODE: SIZE: DRAWING NO: REV: 4.10.2016 MTG_PT

QUALITY CONTROL: DATED: IO 1

RELEASED: DATED: SCALE: SHEET: OF C LAYOUT OF THE SENSOR BOARD J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1 L4x2 L5x2 L1L1x1 L1x2 L4x1 L5x1 L3L3x1 L3x2 L4 L5

L2L2x2 L2x1 C7x2 C8x2 C9x2 C10x2 C5x2 C11x2 C6x2 C3x2 C4x2 L7x2 L8x2 L9x2 C7x1 C8x1 C9x1 C10x1 C5x1

C5 C7C8C9C10 C11x1

C6x1 C11

C3x1 C4x1 C6

L6x1 L6x2 C3C4 L6 L7L7x1 L8L8x1 L9L9x1 C14x2 C15x2 C20x2 C12x2 C12x1 C13x1 C13x2 C12 C13 C19x2 C16x1 C16x2 C14x1 C15x1

C20x1 C16 C17x2 C17x1 C18x2 C18x1 C17 C18C19C19x1 C14 C20C15 C23x2 C24x2 C25x2 C27x1 C29x2 C21x2 C21x1 C21 C22C22x2 C22x1 C23x1 C24x1 C25x1 C27x2 C29x1 C26x2 C26x1 C24C25 C26 C27 C28C28x2 C28x1 C23C29 C2x1 C30x2 C30x1 C31x2 C31x1 C32x1 C32x2 C36x1 C30 C33x2 C33x1 C31 C32 C33 C34x1 C34x2 C2C2x2 C34 C35x2 C35x1 C40x1 C37x2 C37x1 C38x1 C38x2 C36x2 C39x2 C39x1 C35 C36C37 C38 C39 C45x1 C41x2 C41x1 C40x2 C42x2 C42x1 C43x1 C43x2 C44x1 C44x2 C40 C41 C42 C45x2 C1x1 C43C44 C45 C46x2 C46x1 C47x2 C47x1

C46C47 C50x1 C1x2 C55x1 C1 C51x1 C52x1 C53x1 C54x1 C49x2 C49x1 C50x2 C55x2 C49C50C51C51x2 C52C52x2 C53C53x2 C54C54x2 C55 C48C48x2 C48x1 C58x2 C58x1 C59x1 C60x1 R1R1x2 R1x1 C57C57x2 C57x1 C58 C61x1 C56C56x2 C56x1 C59x2 C60x2 R2R2x2 R2x1 C59C60 C61x2 L10x1 C61 R3x1 R3x2 R3 R5x1 L11L11x2 L11x1 L10x2

R6x1 L10

R5R5x2 R6R6x2 J5x60 J5x58 J5x56 J5x54 J5x52 J5x50 J5x48 J5x46 J5x44 J5x42 J5x40 J5x38 J5x36 J5x34 J5x32 J5x30 J5x28 J5x26 J5x24 J5x22 J5x20 J5x18 J5x16 J5x14 J5x12 J5x10 J5x8 J5x6 J5x4 J5x2 J5x64 J5x63 J5x62 J5x61 R7x1 R7x2 R7 R8R8x2 R8x1 J4J4x1 J6J6x1 J5J5x59 J5x57 J5x55 J5x53 J5x51 J5x49 J5x47 J5x45 J5x43 J5x41 J5x39 J5x37 J5x35 J5x33 J5x31 J5x29 J5x27 J5x25 J5x23 J5x21 J5x19 J5x17 J5x15 J5x13 J5x11 J5x9 J5x7 J5x5 J5x3 J5x1

Fig. C.1: 1 - Top layer

LAYER 1 (TOP SIDE) L1.PHO

74 J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1

J4J4x1 J6J6x1

Fig. C.2: 2 - Power layer J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1 LAYER 5 (VOLTAGE PLANE) L5.PHO

J4J4x1 J6J6x1

Fig. C.3: 3 - Inner layer 1

75

LAYER 3 (SIGNAL LAYER) L3.PHO J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1

J4J4x1 J6J6x1

Fig. C.4: 4 - Inner layer 2 J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1 LAYER 4 (SIGNAL LAYER) L4.PHO

J4J4x1 J6J6x1

Fig. C.5: 5 - Ground layer

76

LAYER 2 (GROUND PLANE) L2.PHO J2x2 J2x4 J2x6 J2x8

J2J2x1 J2x3 J2x5 J2x7

J1J1x1 J3J3x1 U1x234 U1x231 U1xC16 U1xD16 U1xE16 U1xF16 U1xG16 U1xH16 U1xJ16 U1xK16 U1xL16 U1xM16 U1xN16 U1xP16 U1xR16 U1xA16 U1xC15 U1xD15 U1xE15 U1xF15 U1xG15 U1xH15 U1xJ15 U1xK15 U1xL15 U1xM15 U1xN15 U1xP15 U1xR15 U1xU16 U1xA14 U1xB14 U1xC14 U1xD14 U1xE14 U1xF14 U1xG14 U1xH14 U1xJ14 U1xK14 U1xL14 U1xM14 U1xN14 U1xP14 U1xR14 U1xT14 U1xU14 U1xA13 U1xB13 U1xC13 U1xD13 U1xE13 U1xF13 U1xG13 U1xH13 U1xJ13 U1xK13 U1xL13 U1xM13 U1xN13 U1xP13 U1xR13 U1xT13 U1xU13 U1xA12 U1xB12 U1xC12 U1xD12 U1xE12 U1xF12 U1xG12 U1xH12 U1xJ12 U1xK12 U1xL12 U1xM12 U1xN12 U1xP12 U1xR12 U1xT12 U1xU12 U1xA11 U1xB11 U1xC11 U1xD11 U1xE11 U1xF11 U1xM11 U1xN11 U1xP11 U1xR11 U1xT11 U1xU11 U1xA10 U1xB10 U1xC10 U1xD10 U1xE10 U1xF10 U1xM10 U1xN10 U1xP10 U1xR10 U1xT10 U1xU10 U1xA9 U1xB9 U1xC9 U1xD9 U1xE9 U1xF9 U1xM9 U1xN9 U1xP9 U1xR9 U1xT9 U1xU9 U1xA8 U1xB8 U1xC8 U1xD8 U1xE8 U1xF8 U1xM8 U1xN8 U1xP8 U1xR8 U1xT8 U1xU8 U1xA7 U1xB7 U1xC7 U1xD7 U1xE7 U1xF7 U1xM7 U1xN7 U1xP7 U1xR7 U1xT7 U1xU7 U1xA6 U1xB6 U1xC6 U1xD6 U1xE6 U1xF6 U1xM6 U1xN6 U1xP6 U1xR6 U1xT6 U1xU6 U1xA5 U1xB5 U1xC5 U1xD5 U1xE5 U1xF5 U1xG5 U1xH5 U1xJ5 U1xK5 U1xL5 U1xM5 U1xN5 U1xP5 U1xR5 U1xT5 U1xU5 U1xA4 U1xB4 U1xC4 U1xD4 U1xE4 U1xF4 U1xG4 U1xH4 U1xJ4 U1xK4 U1xL4 U1xM4 U1xN4 U1xP4 U1xR4 U1xT4 U1xU4 U1xA3 U1xB3 U1xC3 U1xD3 U1xE3 U1xF3 U1xG3 U1xH3 U1xJ3 U1xK3 U1xL3 U1xM3 U1xN3 U1xP3 U1xR3 U1xT3 U1xU3 U1xC2 U1xD2 U1xE2 U1xF2 U1xG2 U1xH2 U1xJ2 U1xK2 U1xL2 U1xM2 U1xN2 U1xP2 U1xR2 U1xA1 U1xC1 U1xD1 U1xE1 U1xF1 U1xG1 U1xH1 U1xJ1 U1xK1 U1xL1 U1xM1 U1xN1 U1xP1 U1xR1 U1xU1

U1U1x233 U1x232 C62C62x2 C62x1 L12L12x2 L12x1

L13L13x2 L13x1

J4J4x1 J6J6x1

Fig. C.6: 6 - Bottom layer

J2 J2x2 J2x4 J2x6 J2x8

J1 J2J2x1 J2x3 J2x5 J2x7 J3 L4 L5

J1J1x1 L1 J3J3x1 L1 L3 C9 C10 L4 C8 L5 X REV XXX-XXXX-XXXX P/N: L2 L3 C11 L2 C5 C6 L7 L8 L9 C3 LAYER 6 (BOTTOMC4 C5 C7C8 C9SIDE)C10 L6.PHO L6 C3C4 C6 C7 C11 L6 C19 C14 C20 C15 L7L8L9 C16 C12C12 C13 C13

C23 C16 C17C17 C18 C19C14 C20C15 C21

C21 C22 C24 C25 C23 C29 C26 C27 C24C25 C26 C27 C28 C33 C29 C30 C34

C30 C31 C31 C32 C32 C33 C34 C2 C2 C36 C35

C37 C37 C36 C38 C38 C39 C39 C40 C40C41C41C42 C45 C42 C43C44 C44C45 C46C46 C43

C1 C47 C1 C47 C50 C51 C55

C49 C52 C53 C49C50 C54 C48C48 C51C52C53C54C55 R1 R1 C57 C58 C56 C58

C59 C57 R2 R2C56 C59C60 C60C61C61 R3 R3 L10 L10L11 R5 L11

R5 R6 R6

J4 J6 R7 R8 R7 R8 J4J4x1 J6J6x1 J5 J5

Fig. C.7: Assembly top layer

77

LAYER 1 (TOP SIDE) L1.PHO

D CIRCUIT DESIGN OF THE BOARD CON- NECTED TO THE MICROZED D C B A 1 REV: DATE: APPROVED: 1 C108 100n C76 100n SHEET: OF C102 100n DRAWING NO: REVISION RECORD MICROZED C107 100n ECO NO: C101 100n C75 100n C106 100n C74 100n C100 100n LTR SIZE: C92 100u/6V CAPT C105 100u/6V CAPT C77 10u/6V IMX253 Mainboard PSI (Photon Systems Instruments) 2 +3.3V +1.8V +2.5V CODE: SCALE: COMPANY: TITLE: +5V +2.5V +1.8V +5V 7.9.2016 4.10.2016 DLOPC2 DLOMC2 DLOPD2 DLOMD2 DLOPE2 DLOME2 DLOPF2 DLOMF2 DLOPG2 DLOMG2 DLCKP2 DLCKM2 DLOPH2 DLOMH2 XVS SDO XHS DATED: DATED: DATED: DATED: 3 Rataj Madeja 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J2 1 3 5 7 9 DRAWN: CHECKED: QUALITY CONTROL: RELEASED: 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 BERGSTAK-100 C97 100n SDI TOUT0 TOUT1 TOUT2 DLCKP1 DLOPF1 DLOPE1 DLOPA1 DLOPB1 DLOPC1 DLOPA2 DLOPB2 DLCKM1 DLOPD1 DLOMF1 DLOPG1 DLOPH1 DLOME1 DLOMA1 DLOMB1 DLOMC1 DLOMA2 DLOMB2 DLOMD1 DLOMG1 DLOMH1 C98 100n 4 +5V +2.5V C99 100n +5V +3.3V C96 10u/16V RESET OE-A BIT12 BIT4 BIT13 BIT14 OE-B RX1D TX1D SCL XCLR XTRIG XCE BIT9 BIT1 BIT10 BIT2 C95 100u/6V CAPT MD_IN3 MD_IN2 SCL2 SDA2 5 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C94 100u/6V CAPT J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 BERGSTAK-100 C93 100u/6V CAPT +5V RESET SCK SDA BIT5 BIT6 BIT7 BIT8 BIT0 BIT3 TST0 TST1 TST2 TST3 INCK TX2D RX2D BIT15 BIT11 MD_IN1 MD_IN4 C109 100n +5V 6 +3.3V POSITION_SENSOR D C B A

Fig. D.1: 1 - Connectors to the MicroZed

78

6 5 4 3 2 1

REVISION RECORD +5V +VIN +5V LTR ECO NO: APPROVED: DATE:

R35 J20 +1.8V +5V NC/0R POWER board requires 1.8V a 5V 1 U17 2 J4 J3 ZEN056V130A24LS L2 1 1 1 2 SPOX-2 2 VIN VOUT C39 D 2 D MI1210K600R-1 100u/6V 3 4 GND C62 C63 SPOX-2 10u/16V 100n ? SPOX-4 3

+5V R1 +2.5V 100k +1.8V +5V current draw 350+55mA U20 LTC1701 L1 L3 5 1 U27 VIN SW 4u7 MI1210K600R-1

i.D2 oe sources Power - 2 D.2: Fig. 8 1 VIN VOUT R36 5 2 4 3 ERROR SENSE C122 C3 1M ITH/RUN VFB 56k C121 100n 100u/6V R2 C64 C4 C120 3 6 1M 10n R39 SD VTAP CAPT 10u/16V GND 10u/16V 100n 4 7 C67 C66 C72 GND FB ? 2 100u/6V 2u2/16V 10u/16V 5k6 R37 R38 C 120k CAPT LP2951 C D1 ? DIO_SS16 R3 1M

C65 330p 79

+3.3V

+3.3V +5V

U21 LTC1701 L4 L21 +5V +5VM2 5 1 LED VIN SW 4u7 MI1210K600R-1 D3 L6 R40 4 3 1M ITH/RUN VFB 180k MI1210K600R-1 C68 B R79 B 10u/16V GND R16 C36 C38

C71 C70 C104 100u/6V 100u/6V 330R ? 2 100u/6V 2u2/16V 10u/16V 5k6 R42 R41 120k CAPT D2 DIO_SS16

C69 330p

COMPANY: PSI (Photon Systems Instruments)

TITLE: +3.3V +3.3V +3.3V IMX253 Mainboard DRAWN: DATED: Madeja 7.9.2016 A A C114 C115 C1 C116 CHECKED: DATED: 100n 100n 100n 100n CODE: SIZE: DRAWING NO: REV: Rataj 4.10.2016 QUALITY CONTROL: DATED: PWR 1

RELEASED: DATED: SCALE: SHEET: OF

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE: U24-B 19 OE-A OE 17 3 BIT5 A0 Y0 BIT5OUT 15 5 BIT13 A1 Y1 BIT13OUT 13 7 BIT4 A2 Y2 BIT4OUT 11 9 D BIT12 A3 Y3 BIT12OUT D 74HC244

? BIT1OUT BIT9OUT BIT0OUT BIT8OUT BIT7OUT BIT15OUT BIT6OUT BIT14OUT U25-A 1 OE-B OE 2 18 BIT10 A0 Y0 BIT10OUT 4 16 BIT2 A1 Y1 BIT2OUT 10k 10k BIT11 6 14 BIT11OUT 10k 10k 10k 10k 10k 10k R11-A R11-B R11-C R12-A R12-B R12-C A2 Y2 R11-D R12-D 8 12 BIT3 A3 Y3 BIT3OUT 74HC244 ? U25-B +5V

i.D3 te I/O Other - 3 D.3: Fig. 19 OE-B OE +5V +3.3V +3.3V 17 3 BIT1 A0 Y0 BIT1OUT 15 5 BIT9 A1 Y1 BIT9OUT 13 7 BIT0 A2 Y2 BIT0OUT 11 9 BIT8 A3 Y3 BIT8OUT C117 C BIT5OUT BIT13OUT BIT4OUT BIT12OUT BIT3OUT BIT11OUT BIT2OUT BIT10OUT 100n C 74HC244 ?

R53 4K7 R52 4K7 I2C-EXTERNAL R54 R55 U24-A 330R 330R 10k 10k 10k 10k 10k 10k 10k 10k R13-A R13-B R13-C R14-A R14-B R14-C 1 R13-D R14-D U22 OE-A OE 80 2 18 BIT14 A0 Y0 BIT14OUT 1 SDA TX 3 4 16 SDA I2C_SDA BIT6 A1 Y1 BIT6OUT 6 14 BIT15 A2 Y2 BIT15OUT RX 2 8 12 BIT7 A3 Y3 BIT7OUT 74HC244 ? SCL 7 SCL TY 5 I2C_SCL

RY 6

P82B96 B ? B

RX1/TX1-INTERNAL UART RX2/TX2-EXTERNAL UART

U23 C110 C112 1 2 C1+ V+ 100n 100n 3 C1- COMPANY: C111 C113 4 6 PSI (Photon Systems Instruments) C2+ V- 100n 100n 5 C2- 14 11 TITLE: TX1OUT T1OUT T1IN TX1D 7 10 TX2OUT T2OUT T2IN TX2D IMX253 Mainboard 13 12 RX1IN R1IN R1OUT RX1D DRAWN: DATED: 8 9 Madeja 7.9.2016 RX2IN R2IN R2OUT RX2D

A MAX3232 A ? CHECKED: DATED: Rataj CODE: SIZE: DRAWING NO: REV: 4.10.2016

QUALITY CONTROL: DATED: I/O 1

RELEASED: DATED: SCALE: SHEET: OF

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE: +1.8V

J6 R10 1 2 XTRIG 10R DLOMH1 3 4 DLOMH2 DLOPH1 5 6 DLOPH2 GND 7 8 +1.8V D DLOMG1 9 10 DLOMG2 D DLOPG1 11 12 DLOPG2 R9 R20 13 14 SDI 10R 10R XCLR +VIN +VIN DLOMF1 15 16 DLOMF2 DLOPF1 17 18 DLOPF2 GND 19 20 +1.8V J18 21 22 DLOME1 DLCKM2 1 2 +5VM1 +5V DLOPE1 23 24 DLCKP2 BIT8OUT 3 4 BIT0OUT SDO 25 26 TOUT0 27 28 BIT9OUT 5 6 BIT1OUT J9 DLCKM1 DLOME2 7 8 L5 29 30 BIT10OUT BIT2OUT DLCKP1 DLOPE2 9 10 1 GND 31 32 +1.8V BIT11OUT BIT3OUT BIT12OUT 11 12 BIT4OUT 2 DLOMD1 33 34 DLOMD2 MI1210K600R-1 BIT13OUT 13 14 BIT5OUT 3 SCL2 i.D4 te connectors Other - 4 D.4: Fig. 35 36 DLOPD1 DLOPD2 15 16 4 37 38 BIT14OUT BIT6OUT SDA2 TOUT1 +1.8V +1.8V +1.8V 18 39 40 BIT15OUT 17 BIT7OUT 5 TX2OUT DLOMC1 DLOMC2 19 41 42 20 6 RX2IN DLOPC1 DLOPC2 21 43 44 I2C_SDA 22 I2C_SCL GND +1.8V 23 45 46 RX1IN 24 TX1OUT SPOX-6 DLOMB1 DLOMB2 25 26 DLOPB1 47 48 DLOPB2 49 50 R7

GND GND R5 51 52 MLW-26 DLOMA1 DLOMA2 NC/10k NC/10k DLOPA1 53 54 DLOPA2 55 56 R4 TOUT2 10R XHS C R8 57 58 R6 C INCK 10R 10R XVS R19 59 60 R18 SCK 10R 10R XCE

QSH-030-01-X-D-RA QSH-030-01-X-D-RA 81 GND GND

+VIN +VIN

B J5-A J5-B B 1 14 2 BIT0OUT 15 BIT8OUT 3 BIT1OUT 16 BIT9OUT 4 BIT2OUT 17 BIT10OUT 5 BIT3OUT 18 BIT11OUT 6 BIT4OUT 19 BIT12OUT 7 BIT5OUT 20 BIT13OUT 8 BIT6OUT 21 BIT14OUT 9 BIT7OUT 22 BIT15OUT 10 23 11 I2C_SCL 24 I2C_SDA 12 TX1OUT 25 RX1IN COMPANY: 13 26 PSI (Photon Systems Instruments) MDR-26 MDR-26

TITLE: C2 IMX253 Mainboard DRAWN: DATED: Madeja 7.9.2016 A 4n7 J7 A CHECKED: DATED: R15 TST0 1 CODE: SIZE: DRAWING NO: REV: 2 Rataj 1M TST1 4.10.2016 TST2 3 TST3 4 QUALITY CONTROL: DATED: CONS 1 HDR-1X4 SHLD GND ? RELEASED: DATED: SCALE: SHEET: OF

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D

U7 14 13 INA PI J19 2 8 R32 MD_IN1 IN1 OUT1 10R 1 i.D5 oo control Motor - 5 D.5: Fig. 2 3 1 7 4 MD_IN2 IN2 OUT2 10R

R31 SPOX-4 16 6 MD_IN3 IN3 OUT3 C C 15 5 MD_IN4 IN4 OUT4

LV8413GP 82

+3.3V +3.3V 10k R30 J17 1 2 POSITION_SENSOR B 3 B

SPOX-3 C35 4n7

COMPANY: PSI (Photon Systems Instruments)

TITLE: IMX253 Mainboard DRAWN: DATED: Madeja 7.9.2016 A A CHECKED: DATED: Rataj CODE: SIZE: DRAWING NO: REV: 4.10.2016

QUALITY CONTROL: DATED: MOTOR 1

RELEASED: DATED: SCALE: SHEET: OF

6 5 4 3 2 1

REVISION RECORD

LTR ECO NO: APPROVED: DATE:

D D Mounting Holes

J11 1 MTG_PT

J13 1 MTG_PT

J8 1 MTG_PT

i.D6 Construction - 6 D.6: Fig. J12 1 MTG_PT

C C

Mounting Holes 83 J10 1 MTG_PT

J14 R72 1 R or L MTG_PT

J15 1 MTG_PT

J16 R73 1 R or L B MTG_PT B

Test Points COMPANY: PSI (Photon Systems Instruments) J21 1 TP_500X TITLE:

J22 1 IMX253 Mainboard DRAWN: DATED: TP_500X Madeja 7.9.2016 A A CHECKED: DATED: Rataj CODE: SIZE: DRAWING NO: REV: 4.10.2016

QUALITY CONTROL: DATED: MTGS 1

RELEASED: DATED: SCALE: SHEET: OF E LAYOUT OF THE BOARD CONNECTED TO THE MICROZED J4x1 J4x2 J4x3 J4x4

J4 J6xW3 J6xW1 R16x2 J6x68 J6x67 J6x66 J6x65 J6x64 J6x63 J6x62 J6x61

R16R16x1 J20x1 J20x2 J6xW4 J6xW2

J20 D3x1

D3D3x2 J6 J15J15x1 J8J8x1 C39C39x1 C39x2

R30R30x1 R30x2 J17x1

C35C35x2 C35x1 J17x2 R32x1

J10J10x1 J11J11x1 J17x3

C38x2 J17 J9x6 R32x2 U7x8 U7x7 U7x6 U7x5 U7x9 U7x4 R32 U7x10 U7x3 J9x5 C38x1 U7x11 U7x2

C38 U7x12 U7x1 U7x13 U7x14 U7x15 U7x16 U7 J19x1 J9x4 L6x2 J19x2 C36C36x1 C36x2 J9x3

L6L6x1 J19x3 J9x2 J19x4 J9x1 R31x1 R31x2 R31J19 R20R20x2 R20x1 R18x2 R19x2 R55x2 J22x1 C117x1 J9 U22x8 U22x7 U22x6 U22x5 R18x1 R19x1 J22 R18R19 R55R55x1 C117C117x2 J1x102 J2x102 R54x1 C105x2

C107C107x2 C107x1 R54x2 J1x100 J1x99 J2x100 J2x99 C92x2 R54 U22x1 U22x2 U22x3 U22x4 J1x98 J1x97 J2x98 J2x97 R5x2 R5x1

R8x2 U22 J1x96 J1x95 J2x96 J2x95 R5 C106C106x2 C106x1 R52x1 R53x1 J1x94 J1x93 J2x94 J2x93 R9x1 R9x2

R9 C105x1 R8x1 J1x92 J1x91 J2x92 J2x91 R8 R4R4x2 R4x1 C105 J1x90 J1x89 J2x90 J2x89 R52x2 R53x2 R52R53 C108C108x2 C108x1 J1x88 J1x87 J2x88 J2x87 C92x1 R6x2 R6x1 R10x1 R10x2

C92 J1x86 J1x85 J2x86 J2x85 R10 R6 J1x84 J1x83 J2x84 J2x83 J18x2 J18x1 J1x82 J1x81 J2x82 J2x81 C75x1 C75x2 R7x2 R7x1 C102x2 C102x1 C102 R7 C74x2 C74x1 C75 J1x80 J1x79 C74 J2x80 J2x79 J1x78 J1x77 J2x78 J2x77 U25x10 U25x9 U25x8 U25x7 U25x6 U25x5 U25x4 U25x3 U25x2 U25x1 C77x1 C77x2 C100x2 C100x1 J1x76 J1x75 J2x76 J2x75 J18x4 J18x3 R11x5 R11x4 C100 C76C76x2 C76x1 C77 J1x74 J1x73 J2x74 J2x73 R11x6 R11x3 J1x72 J1x71 J2x72 J2x71 R11x7 R11x2 C114x2 C101x2 C101x1

C101 J1x70 J1x69 J2x70 J2x69 R11x8 R11x1 J18x6 J18x5

J1x68 J1x67 R11 J2x68 J2x67 C114x1 J1x66 J1x65 C114 J2x66 J2x65 L5L5x2 L5x1 J1x64 J1x63 J2x64 J2x63 J18x8 J18x7 U25x11 U25x12 U25x13 U25x14 U25x15 U25x16 U25x17 U25x18 U25x19 U25x20 J1x62 J1x61 J2x62 J2x61 C97C97x2 C97x1

J1x60 J1x59 U25 J2x60 J2x59 C99C99x1 C99x2 J1x58 J1x57 J2x58 J2x57 J18x10 J18x9 C98x2 C98x1

C98 J1x56 J1x55 J2x56 J2x55 J1x54 J1x53 J2x54 J2x53 C94x1 C116x2 C116x1

J1x52 J1x51 C116 J2x52 J2x51 J18x12 J18x11 J1x50 J1x49 J2x50 J2x49 J1x48 J1x47 J2x48 J2x47 J7x4 J1x46 J1x45 J2x46 J2x45 J18x14 J18x13 J1x44 J1x43 J2x44 J2x43 U24x10 U24x9 U24x8 U24x7 U24x6 U24x5 U24x4 U24x3 U24x2 U24x1 J1x42 J1x41 J2x42 J2x41 C94x2 J7x3 J1x40 J1x39 J2x40 J2x39

R14x5 R14x4 C94 J1x38 J1x37 J2x38 J2x37 J18x16 J18x15 R14x6 R14x3 J1x36 J1x35 J2x36 J2x35 R14x7 R14x2 J7x2 J1x34 J1x33 J2x34 J2x33 R14x8 R14x1

J1x32 J1x31 R14 J2x32 J2x31 J18x18 J18x17 J1x30 J1x29 J2x30 J2x29 U24x11 U24x12 U24x13 U24x14 U24x15 U24x16 U24x17 U24x18 U24x19 U24x20 J7x1 J1x28 J1x27 U24 J2x28 J2x27 J1x26 J1x25 J2x26 J2x25 J18x20 J18x19

J7 J1x24 J1x23 J2x24 J2x23 J1x22 J1x21 J2x22 J2x21 C115x1 C1x1 C1x2

J1x20 J1x19 C1 J2x20 J2x19 J18x22 J18x21 C95x1 J1x18 J1x17 J2x18 J2x17 C115C115x2 J1x16 J1x15 J2x16 J2x15 U23x16 U23x15 U23x14 U23x13 U23x12 U23x11 U23x10 U23x9 J1x14 J1x13 J2x14 J2x13 J18x24 J18x23 J1x12 J1x11 J2x12 J2x11 J1x10 J1x9 J2x10 J2x9 C96x1 C112x2 C113x2 J1x8 J1x7 J2x8 J2x7 C95x2 J1x6 J1x5 J2x6 J2x5 J18x26 J18x25

C95 C96x2 C112x1 C113x1 J1x4 J1x3 J2x4 J2x3 C96 C112 C113 C93x1 J1x2 J1x1 J2x2 J2x1 C109x2 C109x1 C109 U23U23x1 U23x2 U23x3 U23x4 U23x5 U23x6 U23x7 U23x8 J1x101 J2x101 C110x2 C110x1 C111x2 C111x1 C110C111 R12x8 R12x7 R12x6 R12x5 R13x8 R13x7 R13x6 R13x5 R72x2 J21x1 C93x2 J18R12x1 R12x2 R12x3 R12x4 R13x1 R13x2 R13x3 R13x4 J21 C93 R12 R13 R72x1 R73x2 R73x1 C65x1 C65x2

R73 J1 J2R37x1 C65R72 R3x1 R2x2 C121x1 D1x2 C120x2 R36x1 C64x2 R37x2

R3x2 R37

C121x2 R2x1 R3 C120x1 C64x1 R36x2 C63C63x1 C63x2 C120 C121R2 C64R36 R1x1 R40x1 R41x1 C69x1 C4x1 U20x5 U20x4 R35x2 R35x1 D1x1 U27x8 U27x7 U27x6 U27x5 C62x2 C62x1 R35

L21x2 C62 R1x2 D1 C69x2 C104x1 R40x2 R41x2 R40R41C69 C4C4x2 R1 U17x1 J16x1 J14x1 C70x2

J16 U20x1 U20x2 U20x3 J14 L1x1 L21L21x1 C104C104x2 J3x2 U20 U21x4 U21x3 C122x2 C68x1 C70x1

U21x2 C70 C72x2 R42x2 L4x3 R79R79x1 R79x2 C122x1 J3x1 U21x5 U21x1 U27x1 U27x2 U27x3 U27x4 C68x2 U17x2 U17x3 L1x4 L1x3 C68U21 C122U27 C66x1 C66x2

U17 C66 C72x1 R42R42x1 C72 L4x1 L4x2 L1x2 L2x1 L2x2 L3x1 L3x2 L2 C3x1 C3x2 C71x1 C71x2 J3 C3 L3 D2x2 D2x1 C71 L1

D2 L4x4

L4 J5x13 J5x11 J5x9 J5x7 J5x5 J5x3 J5x1 C67C67x1 C67x2 R38x1 J5x12 J5x10 J5x8 J5x6 J5x4 J5x2 R38x2 J5x28 J5x27 R39R39x1 R39x2 R38 J5x26 J5x24 J5x22 J5x20 J5x18 J5x16 J5x14 C2x1 C2x2 J5x25 J5x23 J5x21 J5x19 J5x17 J5x15 C2

R15R15x1 R15x2 J12J12x1 J5 J13J13x1 Fig. E.1: 1 - Top layer

LAYER 1 (TOP SIDE) L1.PHO

84 J4x1 J4x2 J4x3 J4x4

J4 J6xW3 J6xW1 J6x68 J6x67 J6x66 J6x65 J6x64 J6x63 J6x62 J6x61 J20x1 J20x2 J20 J6J6xW4 J6xW2 J15J15x1 J8J8x1 J17x1 J17x2

J10J10x1 J11J11x1 J17x3

J17 J9x6 J9x5 J19x1 J9x4 J19x2 J9x3 J19x3 J9x2 J19x4 J19 J9x1

J22x1 J9 J22 J1x102 J2x102 J18x2 J18x1 J18x4 J18x3 J18x6 J18x5 J18x8 J18x7 J18x10 J18x9 J18x12 J18x11 J7x4 J18x14 J18x13 J7x3 J18x16 J18x15 J7x2 J18x18 J18x17 J7x1

J7 J18x20 J18x19 J18x22 J18x21 J18x24 J18x23 J18x26 J18x25 J1x101 J2x101 J1J18 J21J21x1 J2

J16J16x1 J14J14x1 J3x2 J3J3x1 J5x13 J5x11 J5x9 J5x7 J5x5 J5x3 J5x1 J5x12 J5x10 J5x8 J5x6 J5x4 J5x2 J5x28 J5x27 J5x26 J5x24 J5x22 J5x20 J5x18 J5x16 J5x14 J5x25 J5x23 J5x21 J5x19 J5x17 J5x15 J12J12x1 J5 J13J13x1 Fig. E.2: 2 - Power layer

85 J4x1 J4x2 J4x3 J4x4

J4 J6xW3 J6xW1 J6x68 J6x67 J6x66 J6x65 J6x64 J6x63 J6x62 J6x61 J20x1 J20x2 J20 J6J6xW4 J6xW2 J15J15x1 J8J8x1 J17x1 J17x2

J10J10x1 J11J11x1 J17x3

J17 J9x6 J9x5 J19x1 J9x4 J19x2 J9x3 J19x3 J9x2 J19x4 J19 J9x1

J22x1 J9 J22 J1x102 J2x102 J18x2 J18x1 J18x4 J18x3 J18x6 J18x5 J18x8 J18x7 J18x10 J18x9 J18x12 J18x11 J7x4 J18x14 J18x13 J7x3 J18x16 J18x15 J7x2 J18x18 J18x17 J7x1

J7 J18x20 J18x19 J18x22 J18x21 J18x24 J18x23 J18x26 J18x25 J1x101 J2x101 J1J18 J21J21x1 J2

J16J16x1 J14J14x1 J3x2 J3J3x1 J5x13 J5x11 J5x9 J5x7 J5x5 J5x3 J5x1 J5x12 J5x10 J5x8 J5x6 J5x4 J5x2 J5x28 J5x27 J5x26 J5x24 J5x22 J5x20 J5x18 J5x16 J5x14 J5x25 J5x23 J5x21 J5x19 J5x17 J5x15 J12J12x1 J5 J13J13x1 Fig. E.3: 3 - Ground layer

86 L3.PHO J4x1 J4x2 J4x3 J4x4

J4 J6xW3 J6xW1 J6x60 J6x58 J6x56 J6x54 J6x52 J6x50 J6x48 J6x46 J6x44 J6x42 J6x40 J6x38 J6x36 J6x34 J6x32 J6x30 J6x28 J6x26 J6x24 J6x22 J6x20 J6x18 J6x16 J6x14 J6x12 J6x10 J6x8 J6x6 J6x4 J6x2 J6x68 J6x67 J6x66 J6x65 J6x64 J6x63 J6x62 J6x61 J6x59 J6x57 J6x55 J6x53 J6x51 J6x49 J6x47 J6x45 J6x43 J6x41 J6x39 J6x37 J6x35 J6x33 J6x31 J6x29 J6x27 J6x25 J6x23 J6x21 J6x19 J6x17 J6x15 J6x13 J6x11 J6x9 J6x7 J6x5 J6x3 J6x1 J20x1 J20x2 J20 J6J6xW4 J6xW2 J15J15x1 J8J8x1 J17x1 J17x2

J10J10x1 J11J11x1 J17x3

J17 J9x6 J9x5 J19x1 J9x4 J19x2 J9x3 J19x3 J9x2 J19x4 J19 J9x1

J22x1 J9 J22 J1x102 J2x102 J18x2 J18x1 J18x4 J18x3 J18x6 J18x5 J18x8 J18x7 J18x10 J18x9 J18x12 J18x11 J7x4 J18x14 J18x13 J7x3 J18x16 J18x15 J7x2 J18x18 J18x17 J7x1

J7 J18x20 J18x19 J18x22 J18x21 J18x24 J18x23 J18x26 J18x25 J1x101 J2x101 J1J18 J21J21x1 J2

J16J16x1 J14J14x1 J3x2 J3J3x1 J5x13 J5x11 J5x9 J5x7 J5x5 J5x3 J5x1 J5x12 J5x10 J5x8 J5x6 J5x4 J5x2 J5x28 J5x27 J5x26 J5x24 J5x22 J5x20 J5x18 J5x16 J5x14 J5x25 J5x23 J5x21 J5x19 J5x17 J5x15 J12J12x1 J5 J13J13x1 Fig. E.4: 4 - Bottom layer

P/N: XXX-XXXX-XXXX REV X REV XXX-XXXX-XXXX P/N: LAYER 2 (BOTTOM87 SIDE) L2.PHOL4.PHO J4 J4x1 J4x2 J4x3 J4x4 J4 R16 J20 R16 J20x1 J20x2 J15 J20 D3 J15J15x1 J8J8x1 C39 C39 R30 R30 C35 J17x1 C35 J17x2

J10J10x1 J11J11x1 J17x3 R32

J17 J9x6 U7

C38 R32 C38 C36 J9x5 U7 J19x1 J9x4 J19x2 L6 C36 L6 J9x3 R31 J19x3 J9x2

J19x4 R20 J22 R31 R20 J9x1 J19U22 R55

J22x1 J9 U22x8 U22x7 U22x6 U22x5 J22J1 R18 R19 R18R19 R55 J2 C92 C117 R54 C107 C117 R5 C107 J1x100 J1x99 R8 R54 J2x100 J2x99 U22x1 U22x2 U22x3 U22x4 J1x98 J1x97 U22 J2x98 J2x97 J1x96 J1x95 R9 R5 J2x96 J2x95

C106 J1x94 J1x93 R9 R4 J2x94 J2x93 J1x92 J1x91 J2x92 J2x91 C105 R8 R10 R4 J1x90 J1x89 R52R53 R6 C108 J2x90 J2x89 C105 J1x88 J1x87 C108 J2x88 J2x87

C92 J1x86 J1x85 J2x86 J2x85 R52 R10 R6 C75 J1x84 J1x83 R53 J2x84 J2x83 J18x2 J18x1 J1x82 J1x81 J2x82 J2x81

C102 C102 R7 C75 C74 J1x80 J1x79 C74 J2x80 J2x79

J1x78 J1x77 R11 R7 J2x78 J2x77 U25x10 U25x9 U25x8 U25x7 U25x6 U25x5 U25x4 U25x3 U25x2 U25x1 J1x76 J1x75 J2x76 J2x75 J18x4 J18x3 C77 C76 C100 C100 C76 J1x74 J1x73 J2x74 J2x73 C77 J1x72 J1x71 J2x72 J2x71 L5 J1x70 J1x69 J2x70 J2x69

C101 C101 J18x6 J18x5

J1x68 J1x67 R11 J2x68 J2x67

J1x66 J1x65 C114 J2x66 J2x65 L5 J1x64 J1x63 J2x64 J2x63 J18x8 J18x7 C97 U25x11 U25x12 U25x13 U25x14 U25x15 U25x16 U25x17 U25x18 U25x19 U25x20 J1x62 J1x61 J2x62 J2x61 C97 U25 C114

J1x60 J1x59 U25 J2x60 J2x59 C94 C99 J1x58 J1x57 J2x58 J2x57 C98 C116 J18x10 J18x9 C99 C98 J1x56 J1x55 J2x56 J2x55

J7 J1x54 J1x53 J2x54 J2x53

J1x52 J1x51 C116 J2x52 J2x51 J18x12 J18x11 J1x50 J1x49 J2x50 J2x49

J1x48 J1x47 U24 J2x48 J2x47 J7x4 J1x46 J1x45 J2x46 J2x45 J18x14 J18x13 J1x44 J1x43 J2x44 J2x43 U24x10 U24x9 U24x8 U24x7 U24x6 U24x5 U24x4 U24x3 U24x2 U24x1 R14 J1x42 J1x41 J2x42 J2x41 J7x3

J1x40 J1x39 C94 J2x40 J2x39 J1x38 J1x37 J2x38 J2x37 J18x16 J18x15 J1x36 J1x35 J2x36 J2x35 J7x2 J1x34 J1x33 J2x34 J2x33

J1x32 J1x31 R14 J2x32 J2x31 J18x18 J18x17 J1x30 J1x29 J2x30 J2x29 U24x11 U24x12 U24x13 U24x14 U24x15 U24x16 U24x17 U24x18 U24x19 U24x20 J7x1 J1x28 J1x27 U24 J2x28 J2x27

J1x26 J1x25 C115 J2x26 J2x25 C1 J18x20 J18x19

J7 J1x24 J1x23 J2x24 J2x23 J1x22 J1x21 J2x22 J2x21

J1x20 J1x19 C1 U23 J2x20 J2x19 J18x22 J18x21 J1x18 J1x17 C115 J2x18 J2x17 J1x16 J1x15 J2x16 J2x15 U23x16 U23x15 U23x14 U23x13 U23x12 U23x11 U23x10 U23x9 J1x14 J1x13 J2x14 J2x13 C96 J18x24 J18x23 J1x12 J1x11 C112 J2x12 J2x11 J1x10 J1x9 J2x10 J2x9 J1x8 J1x7 J2x8 J2x7 C95 J1x6 J1x5 J2x6 J2x5 C95 J18x26 J18x25 J1x4 J1x3 C112 C113 J2x4 J2x3 C96 J1x2 J1x1 C113 J21 J2x2 J2x1 U23x1 U23x2 U23x3 U23x4 U23x5 U23x6 U23x7 U23x8

C109 U23 R12 R13 C110C111 C65 R73 C110 C111 J21x1 J21 R2 C93 R36R37 J18 R3 R12 R13 R73 J1 J2C64 C65R72 R72

C63 C121

R40 C120 R37 R41 C69 C63 C120 C121R2R3 C64R36 L21 C104 R35 D1 U27x8 U27x7 U27x6 U27x5

R35 R1 C70 C62 D1 R1 L1 R40R41C69 C4 U20 C68J16U21J16x1 J14J14x1 L21 C104 J3x2 U20 C70 C66 R79 U17 J3x1 U27x1 U27x2 U27x3 U27x4 U27 C122 C68U21 R79 R42 U17 C122U27 C66 R42 C72 C72 J3L2 L2 C3C3 L1L3 D2 C71 C67 L3 D2 L4 C71 L4 C67

R38 R38 R39 C2C2 R15R15

J12J12x1 J13J13x1

Fig. E.5: Assembly silkscreen components composite top

LAYER 1 (TOP SIDE)88 L1.PHO J6 J4J4x1 J4x2 J4x3 J4x4

J20J20x1 J20x2 J6 J17 J15J15x1 J8J8x1 J17x1 J17x2

J10J10x1 J11J11x1 J9 J17x3 J19

J17 J9x6 J9x5 J19x1 J9x4 J19x2 J9x3 J19x3 J9x2 J19x4 J19 J9J9x1

J18 J18x2 J18x1 J18x4 J18x3 J18x6 J18x5 J18x8 J18x7 J18x10 J18x9 J18x12 J18x11 J7x4 J18x14 J18x13 J7x3 J18x16 J18x15 J7x2 J18x18 J18x17 J7x1

J7 J18x20 J18x19 J18x22 J18x21 J18x24 J18x23 J18J18x26 J18x25

J3

J16J16x1 J14J14x1 J3x2 J3x1 J5 J3

J12J12x1 J5 J13J13x1 Fig. E.6: Assembly silkscreen components composite bottom

P/N: XXX-XXXX-XXXX REV X REV XXX-XXXX-XXXX P/N: LAYER 2 (BOTTOM89 SIDE) L2.PHOL4.PHO

F CIRCUIT DESIGN OF THE ANALOG POWER SUPPLY BOARD D C B A 1 REV: DATE: APPROVED: 1 SHEET: OF DRAWING NO: POWER REVISION RECORD ECO NO: J3 SPOX-4 1 2 3 4 2 4 6 8 J4 HDR-2X4 LTR 1 3 5 7 +5V SIZE: +1.8V IMX253 Powerboard +3.3VA PSI (Photon Systems Instruments) 2 +1.2VA CODE: SCALE: COMPANY: TITLE: 7.9.2016 4.10.2016 DATED: DATED: DATED: DATED: 3 Rataj Madeja DRAWN: CHECKED: QUALITY CONTROL: RELEASED: C8 100u/6V CAPT 4 C6 100u/6V CAPT +1.2VA +3.3VA C7 100u/6V CAPT C4 100u/6V CAPT R2 R1 R or L R or L C3 10u/6V C5 100n 1 1 J2 J1 2 Mounting Holes MTG_PT MTG_PT 4 5 ? VOUT OUT 3 5 GND

SENSE/ADJ

LT1965 3 VIN GND U2 LF33CD 1 U1 C1 10u/6V IN SHDN 2 1 +5V C2 10u/6V +1.8V 6 D C B A

Fig. F.1: 1 - Power sources

90

G LAYOUT OF THE ANALOG POWER SUP- PLY BOARD R2x2 R2x1 R1x1 R1x2 R1 J4x8 J4x6 J4x4 J4x2 R2 C2x2 J4x7 J4x5 J4x3 J4x1 C2C2x1 J4 U2x3 U1x1 J1x1 J2x1 J1 C7C7x2 C7x1 J2 U1x2 U1x3 C1x2 C1x1 U2x1 U2x2

C1 C6x1 C8x2 C8x1 U2 C8 U1x4 C5x1 U1x5 C3C3x2 C3x1 J3x1 J3x2 J3x3 J3x4 C4x2 C4x1 C5C5x2 U1x6 C4 J3 U1 C6C6x2

Fig. G.1: 1 - Top layer LAYER 1 (TOP SIDE) L1.PHO J4x8 J4x6 J4x4 J4x2

J4J4x7 J4x5 J4x3 J4x1

J1J1x1 J2J2x1

J3J3x1 J3x2 J3x3 J3x4

Fig. G.2: 2 - Bottom layer P/N: XXX-XXXX-XXXX REV X REV XXX-XXXX-XXXX P/N: LAYER 2 (BOTTOM SIDE) L2.PHOL4.PHO

91 H LVDS LENGTH DIFFERENCES - SENSOR BOARD

Signal Length [mm] Length difference [mm] DLCKM2 29.5111 0.10396 DLCKP2 30.21786 0.81072 DLOMA2 29.57786 0.17072 DLOMB2 29.76664 0.3595 DLOMC2 29.77043 0.36329 DLOMD2 30.29685 0.88971 DLOME2 29.75817 0.35103 DLOMF2 29.61332 0.20618 DLOMG2 29.54747 0.14033 DLOMH2 29.70912 0.30198 DLOPA2 29.41412 0.00698 DLOPB2 29.59828 0.19114 DLOPC2 29.59332 0.18618 DLOPD2 30.34359 0.93645 DLOPE2 31.03323 1.62609 DLOPF2 31.3668 1.95966 DLOPG2 29.40714 0 DLOPH2 31.03508 1.62794 DLOMF1 29.02686 0.21588 DLCKM1 29.10887 0.29789 DLCKP1 29.81297 1.00199 DLOMA1 30.10309 1.29211 DLOMB1 29.09139 0.28041 DLOMC1 28.81098 0 DLOMD1 28.95037 0.13939 DLOME1 28.88246 0.07148 DLOMG1 28.86325 0.05227 DLOMH1 29.56855 0.75757 DLOPA1 30.52257 1.71159 DLOPB1 30.70286 1.89188 DLOPC1 29.84793 1.03695 DLOPD1 30.56366 1.75268 DLOPE1 30.24727 1.43629 DLOPF1 30.20031 1.38933 DLOPG1 30.28192 1.47094 DLOPH1 29.93759 1.12661

Tab. H.1: Sensor board LVDS length differences

92 I LVDS LENGTH DIFFERENCES - BOARD CON- NECTED TO THE MICROZED

Signal Length [mm] Length difference [mm] DLCKM2 135,57292 0,02883 DLCKP2 135,56287 0,01878 DLOMA2 135,57292 0,02883 DLOMB2 135,57292 0,02883 DLOMC2 135,55542 0,01133 DLOMD2 135,57292 0,02883 DLOME2 135,57292 0,02883 DLOMF2 135,65826 0,11417 DLOMG2 135,57292 0,02883 DLOMH2 135,57292 0,02883 DLOPA2 135,57292 0,02883 DLOPB2 135,57292 0,02883 DLOPC2 135,54409 0 DLOPD2 135,57292 0,02883 DLOPE2 135,57292 0,02883 DLOPF2 135,65827 0,11418 DLOPG2 135,57292 0,02883 DLOPH2 135,57292 0,02883 DLCKM1 111,2728 0,18095 DLCKP1 111,1171 0,02525 DLOMA1 111,11482 0,02297 DLOMB1 111,13032 0,03847 DLOMC1 111,17174 0,07989 DLOMD1 111,20676 0,11491 DLOME1 111,28994 0,19809 DLOMF1 111,28994 0,19809 DLOMG1 111,28994 0,19809 DLOMH1 111,28994 0,19809 DLOPA1 111,12577 0,03392 DLOPB1 111,13032 0,03847 DLOPC1 111,24331 0,15146 DLOPD1 111,23963 0,14778 DLOPE1 111,28994 0,19809 DLOPF1 111,28994 0,19809 DLOPG1 111,09185 0 DLOPH1 111,28994 0,19809

Tab. I.1: Board connected to the MicroZed LVDS length differences

93