ARM Cortex-A8

Sitara MPU Day

Sitara® MPU Day Updated June 21, 2010 Sitara MPU Day

Sitara™ ARM® Cortex™-A8/ARM9™ Microprocessor Overview & Target Applications Sitara MPU Day TI ARM® investment and innovation

1st single-chip DaVinci™ TMS570 Stellaris digital baseband - MCU MCU DSP/ARM Fixed/ multi-core Floating- Point Introduced DaVinci™ Two ARM TI ® ® ARM9 TI processors for Cortex-R4 Stellaris Stellaris SoC Acquires Licenses digital video cores Fury DustDevil Luminary first – ARM9-based SoCs for Class Class OMAP™ Micro ARM automotive OMAP-L138 core TI *TI first licensee for ARM Licenses Cortex™- A8 Cortex-A9

1993 1995 2002 2005 2006 2007 2008 2009

Stellaris® 1st multi-core Tempest applications Class ® processor, Stellaris DaVinci™ ARM9-based Sandstorm Class TI announces 1st R4F-based OMAP™ 1st ARM 31 new Cortex-A8 floating-point, OMAP1510 Newest DaVinci ARM-based based silicon dual-core auto products solution for MCU OMAP™ and introduces flexible, Sitara™ family OMAP3 HD video TMS570F MCU

TI has shipped over 5 billion ARM-based products and continues to invest in a large portfolio of scalable platforms from $1 to >1GHz

* TI licensed in July 2003, but publicly announced Oct 2005. Sitara MPU Day Embedded processing portfolio TI Embedded Processors

Microcontrollers (MCUs) ARM®-Based Processors Digital Signal Processors (DSPs)

16-bit ultra- 32-bit ARM Ultra 32-bit ARM DSP Multi-core low power real-time Cortex™-M3 Low power Cortex-A8 & DSP+ARM DSP MCUs MCUs MCUs ARM9™ MPUs DSP

C2000™ ™ C6000™ Stellaris® Sitara ™ ™ ™ ™ ARM Cortex-A8 DaVinci™ C6000 C5000 MSP430 Delfino ARM Cortex-M3 ™ & ARM9 video processors Piccolo OMAP™ Up to 40MHz to Up to 375MHz to 300MHz to >1Ghz 24,000 Up to 300 MHz 25 MHz 300 MHz 100 MHz >1GHz +Accelerator MMACS +Accelerator Flash Flash, RAM Flash Cache, Cache Cache Up to 320KB RAM 1 KB to 256 KB 16 KB to 512 KB 8 KB to 256 KB RAM, ROM RAM, ROM RAM, ROM Up to 128KB ROM Analog I/O, ADC PWM, ADC, USB, ENET USB, CAN, SATA, USB, ENET, SRIO, EMAC USB, ADC LCD, USB, RF 2 MAC+PHY CAN, SPI, PCIe, EMAC PCIe, SATA, SPI DMA, PCIe McBSP, SPI, I2C CAN, SPI, I C ADC, PWM, SPI Measurement, Motor Control, Connectivity,Security, Industrial automation, Floating/Fixed Point Telecom test & meas, Audio, Voice Sensing, General Digital Power, Motion Control, HMI, POS & portable Video, Audio, Voice, media gateways, Purpose Lighting, Ren. Energy Industrial Automation data terminals Security, Conferencing base stations Medical, Biometrics $0.25 to $9.00 $1.50 to $20.00 $1.00 to $8.00 $5.00 to $25.00 $5.00 to $200.00 $40.00 to $200.00 $3.00 to $10.00

Software & Dev. Tools MPUs – Microprocessors Sitara MPU Day Sitara™ offers Performance Scalability • 375MHz ARM9™ to > 1GHz Cortex™-A8 • Largest software compatible ARM MCU & devices Embedded MPU portfolio • Industry’s first widely available Cortex-A8 • ARM only to ARM + accelerator functionality devices - 2 DMIPS per MHz while reusing both SW and HW designs • Graphics acceleration for up to 20M polygons/s • Leverage TI’s extensive portfolio of embedded performance for advanced user interface ARM devices to maximize your product’s • High speed DDR2 memory performance changing needs • Fully pin-for-pin and software compatible options to scale from ARM only to ARM + DSP

Connectivity Strength of Software • Ethernet • Free and easy access to software • CAN 2.0 and High speed USB interface • Low cost development tools with reference code • Multiple serial port options per device • Application specific and advanced development • Lowest cost processor with SATA interface kits • Flexible LCD controller for up 720p displays • Aggressive Linux community, Windows moving to 1080p in future devices Embedded CE and RTOS ecosystem of • Industrial peripheral support development partners • Driver software available for most high-level operating systems

5 Sitara MPU Day Sitara™ processors are ideal for

Applications such as Design requirements

• HVAC and building controls • System cost constraints needing high system integration • Network appliances • Network connectivity (Ethernet, Wi- • Industrial automation Fi®) • Point-of-service machines • Multiple connectivity and interface • Test and measurement options (CAN, USB, SDIO, LCD I/F, I2C, SATA, PWM) • Medical instrumentation • Advanced graphical user interfaces • Educational consoles (graphics acceleration) • Industrial low power PCs • Operating system compatibility • … many others (Linux, Windows® Embedded CE, and Others) • Scalability (broad portfolio of product options with code compatible roadmap) • Application software portability (code compatible roadmap) Sitara MPU Day Sitara™ ARM9™ & Cortex™-A8 target markets

Industrial Automation Data Terminals Broad Market

• Industrial control and connectivity • Flexible industrial connectivity • Broad embedded processing interfaces portfolio to allow for optimization • 3D graphics accelerator for on performance, power and cost • Low heat dissipation core (no fan building advanced GUI functions or heat sink) • Flexible integrated peripherals and • High performance core for fast connectivity options • Extended temp range response times • Large ARM® ecosystem and • 3D graphics accelerator for • Power efficient (down to 7mW third-party network simplifies building advanced GUI functions standby, 182mW active) application development • Real-time Linux kernel supported

Long Product Lifecycles with Focus on Reliability and Quality

7 Sitara MPU Day Sitara™ ARM® microprocessors Available Now In Development

ARM9™ ARM Cortex™-A8 ARM Cortex-A8

AM1808 AM3715 “AM38x Next” (2011) AM3703 AM1806 “AM33x Next” (2011) AM3517 AM1707 AM3505 AM1705 OMAP3515 OMAP3503

Low Power ARM9 with High-performance Cortex-A8 Advanced Cortex-A8 with flexible peripherals with system integration performance and value options • Power efficient (down to 7mW • Up to 1GHz (2000 DMIPS) • Greater than 1GHz core standby, 182mW active) • Power efficient (down to 12mW performance • User configurable interfaces through standby, 1W active) • 1080p display support the programmable real-time unit • Integrated graphics for rich user • Enhanced graphics for superior (PRU) interface functions user interface functions • Integrated peripherals, 10/100 • Integrated interfaces to display, USB, • Peripheral integration of 1Gb Ethernet, USB, SATA, CAN, UART 10/100 Ethernet, SD card, Wi-Fi®, Ethernet, PCIe, and many others and many others CAN, and many others Support for Linux & Windows® Embedded CE Sitara MPU Day Sitara™ software and ecosystem

Complementing great processors with great software!

• Production quality Software Development Kit including: − Drivers and kernel port to Linux, Windows Embedded CE and other industry leading operating systems (Android, QNX, etc…) − Development tools for Linux and Windows Embedded CE − Proof-of-concept demonstration and example software • Active open source community accompanied by the world’s largest ecosystem of 3rd party tools and application specific solutions Sitara MPU Day Operating Systems

Linux Android WinCE* Real-Time Operating System

Community/C TI owned Green WR ELogic QNX / Mentor Community Commercial ommercial (with 3P) Hills VxWorks ThreadX RIM Nucleus

AM37x 9

OMAP35x 9 9 9 9 9 9 9 9

AM35x 9 9 Beta available 9

AM17x 9 9 Beta available 9 9 9 9

AM18x 9 9 Beta available 9 9 9

• Production quality Software Development Kit (SDK) including: = TI Driven- No charge ® – Free Drivers and kernel port to Linux, Windows Embedded CE and other = Available industry leading operating systems (Android, QNX, etc…) 9 – Development tools for Linux and Windows® Embedded CE = Planned – Proof-of-concept demonstration and example software D = Date Committed • Active open source community accompanied by the world’s largest rd ecosystem of 3 party tools and application specific solutions * WinCE requires runtime royalties to Microsoft Sitara MPU Day

TI Base SW/Components

Cortex™-A8 software summary TI HW/Libraries ARM® Cortex-A8 + graphics 3rd party/Customer Application Level Software Browser/ User Interface “Applications” Media Players

Application Frameworks – Java, Qt, GStreamer, Flash, Android, DShow, Direct Draw

Board Support Package •Linux – Open Source – TI Developed Video, OpenGL ES 2D •Android – Open Source – TI Funded Imaging, and OpenVG Graphics •Windows Embedded CE – TI Owned, Speech, Library Library Developed by Microsoft Gold Partner Audio On on •Commercial Linux and Android – Many Codecs SGX NEON Partners and •RTOS – QNX, VxWorks, Nucleus, Frameworks Integrity etc. on NEON™

OS Kernel

ARM Cortex-A8 with on chip USB, High End CAN controller (HECC) and Ethernet MAC

Accelerators – SGX 530 and Neon

OMAP35x, AM35x, AM37x Sitara MPU Day AM3715/03 Cortex™- A8 based processors Up to 2000 Dhrystone MIPS: Multi window overlay system • OSs like Linux or WinCE and resizing for hardware • Excellent web experience accelerated user interfaces AM3715/03 Example Applications processors • Smart connected devices ARM® Display Subsystem ™ LCD Video 10 bit DAC • Single board computers 3D Cont- Cortex - Enc Graphics roller 10 bit DAC • Patient monitoring A8 Accelerator (3715) Video • Point of service 12-bit Video Processing Input • Low power PC Front End

L3/L4 Interconnect Benefits • High performance embedded Connectivity Serial Interface Memory Interface computing USB OTG McBSP x5 LPDDR1 • Rich, intuitive user interfaces USB HS Host x3 MCSPI x4 MMC/SD/SDIO x3 • Immersive 3D graphics I2C x3 • High system integration HDQ/ 1-wire Timers • Up to 20M polygons per second UART x3 GP x12 • Hardware based on screen display UART w/ IrDA WDT x2 • Easily create robust GUI’s Sitara MPU Day AM3715/03 Cortex™-A8 based processors

Cores • Up to 1GHz Cortex-A8 with NEON™ coprocessor AM3715/03 • 3D graphics accelerator – up to 20M polygons/s processors • Up to 30% reduction in power ARM® Display Subsystem Memory ™ LCD Video 10 bit DAC 3D Cont- Cortex - Enc • ARM: 32kB I-Cache; 32kB D-Cache; 256kB L2 Graphics roller 10 bit DAC • On Chip: 64kB SRAM A8 Accelerator • External interfaces: LPDDR1 and NAND (3715) Video 12-bit Video Processing Peripherals Input • USB HS Host x3 Front End •USB 2.0 OTG • MMC/SD card interface x3 L3/L4 Interconnect • Display subsystem with LCD controller and dual 10 bit DAC’s Connectivity Serial Interface Memory Interface •1.8V I/O’s USB OTG McBSP x5 LPDDR1 Power • Dynamic Voltage and Frequency Scaling (DVFS) USB HS Host x3 MCSPI x4 MMC/SD/SDIO x3 • Total Power: 735mW (800MHz) • Standby Power: 0.1mW (600MHz) I2C x3 Package • CBP: 12x12mm, 0.4mm pitch, Package On HDQ/ 1-wire Timers Package (POP) • CBC: 14x14, 0.5mm POP UART x3 GP x12 • CUS: 16x16mm 0.65mm pitch. Utilizes Via Channel™ Array technology with 0.8mm pitch UART w/ IrDA WDT x2 plus design rules Sitara MPU Day AM3517/05 Cortex™-A8 based processors Up to 1200 Dhrystone MIPS: Multi window overlay system • OS’s like Linux or WinCE and resizing for hardware • Excellent web experience accelerated user interfaces Example Applications AM3517/05 • Industrial/home automation processors • Point of service ARM® Display Subsystem ™ LCD Video 10 bit DAC • Single board computers 3D Cont- Cortex - Enc • Digital signage Graphics roller 10 bit DAC A8 Accelerator • Portable industrial products (3517) Video 16-bit Video Processing Input • Transportation - Navigation Front End

L3/L4 Interconnect Benefits • High performance embedded Connectivity Serial Interface Memory Interface computing USB OTG w/ PHY McBSP x5 DDR2

• Rich, intuitive user interfaces USB HS Host x2 MCSPI x4 NAND/NOR • Native support for large displays CAN Controller I2C x3 MMC/SD/SDIO x3 • System integration reduces board complexity EMAC HDQ/ 1-wire Timers UART x3 GP x12

• Up to 10M polygons per second UART w/ IrDA WDT x2 • Hardware based on screen display • Easily create robust GUI’s Sitara MPU Day AM3517/05 Cortex™-A8 based processors

Cores • 600MHz Cortex-A8 with NEON™ coprocessor AM3517/05 • 3D graphics accelerator – up to 10M polygons/s processors Memory ® Display Subsystem • ARM: 16kB I-Cache; 16kB D-Cache; 256kB L2 ARM ™ LCD Video 10 bit DAC • On Chip: 64kB SRAM 3D Cont- Cortex - Enc • External Interfaces: DDR2 and NAND/NOR Graphics roller 10 bit DAC A8 Accelerator Peripherals (3517) Video • CAN controller 16-bit Video Processing Input • 10/100 EMAC Front End • USB 2.0 OTG w/ PHY • MMC/SD card interface x3 • Display subsystem with LCD controller L3/L4 Interconnect and dual 10 bit DAC’s • 1.8V or 3.3V I/O’s Connectivity Serial Interface Memory Interface Power USB OTG w/ PHY McBSP x5 DDR2 • Total Power: 700mW • Standby Power: 12mW USB HS Host x2 MCSPI x4 NAND/NOR

Package CAN Controller I2C x3 MMC/SD/SDIO x3 • ZCN – 17x17mm, 0.65mm pitch utilizes Via Channel™ Array technology with 0.8mm pitch plus design rules EMAC HDQ/ 1-wire Timers • ZER – 23x23mm, 1.0mm pitch UART x3 GP x12

UART w/ IrDA WDT x2 Sitara MPU Day

TI Base SW/Components ARM9 software summary TI HW/Libraries 3rd party/Customer Application Level Software Browser/ User Interface “Applications” Media Players

Application Frameworks – Java, Qt, GStreamer, Flash, Android, DShow, Direct Draw

Board Support Package •Linux – Open Source – TI Developed Video, •Windows Embedded CE – TI Owned, Imaging, Developed by Microsoft Gold Partner Speech, •Commercial Linux and Android – Many Audio Partners Codecs •RTOS – QNX, VxWorks, Nucleus, and Integrity etc. Frameworks (ARM9)

OS Kernel

ARM9 with on chip USB, Ethernet, SATA

Accelerators – PRU

AM17x and AM18x Sitara MPU Day AM1808/06 ARM9™ based processors

AM1808/06 Processors Example Applications ARM9™ Display Subsystem • Industrial automation LCD • Home automation PRU Controller • Test & measurement Subsystem Video Video Input x2 • Portable data terminals Port interface Video Output x2

L3/L4 Interconnect

Connectivity Serial Interface Benefits USB OTG w/ PHY McBSP x2 McASP • Multiple connectivity and USB HS w/ PHY SPI x2 UART x3 interface options (1808) I2C x2 • Rich, intuitive user interfaces SATA (1808) • High system integration Memory Interface Timers EMAC (1808) SDRAM WDT x1 • Reduced system cost UHPI LPDDR1/DDR2 GP x3

uPP MMC/SD/SDIO x3 PWM x2

eCAP x3 Sitara MPU Day AM1808/06 ARM9™ based processors

AM1808/06 Cores Processors • Up to 450MHz ARM926EJ-S™ ARM9™ Display Subsystem Memory LCD • ARM: 16kB I-Cache; 16kB D-Cache Controller • On Chip: 128kB SRAM PRU • External interfaces: LPDDR1/DDR2 and SDRAM Subsystem Video Video Input x2 Peripherals Port • PRU flexibility for added peripherals interface Video Output x2 • USB 2.0 OTG w/ PHY • 10/100 EMAC, SATA, uPP L3/L4 Interconnect • MMC/SD card interface x3 • Display subsystem with LCD controller • 1.8V or 3.3V I/O’s Connectivity Serial Interface USB OTG w/ PHY McBSP x2 McASP Power • Total Power: < 182mW USB HS w/ PHY SPI x2 UART x3 • Standby Power: < 7mW (1808) I2C x2 Package SATA (1808) • 13 x 13mm nFBGA (0.65mm), ZCE, 361-balls Memory Interface Timers • 16 x 16mm BGA (0.8mm), ZWT, 361-balls • Extended Temperature Grade Options EMAC (1808) SDRAM WDT x1 − Commercial (0C to 90C) − Industrial (-40C to 105C) UHPI LPDDR1/DDR2 GP x3 • Pin to pin compatible processor: OMAP-L138 uPP MMC/SD/SDIO x3 PWM x2

eCAP x3 Sitara MPU Day AM1707/05 ARM9™ based processors

AM1707/05 Processors Example Applications ARM9™ Display Subsystem • Industrial automation LCD Controller • Test & measurement PRU (1707) • Portable data terminals Subsystem • Power protection systems

L3/L4 Interconnect

Connectivity Serial Interface Benefits USB OTG w/ PHY SPI x2 McASPx3 • Multiple connectivity and USB HS w/ PHY I2C x2 UART x3 interface options (1707) Memory Interface Timers • Rich, intuitive user interfaces EMAC (1707) MMC/SD/SDIO WDT x1 • High system integration UHPI SDRAM GP x1 • Reduced system cost NAND/NOR/ PWM x3 SDRAM eCAP x3

eQEP x2 Sitara MPU Day AM1707/05 ARM9™ based processors

AM1707/05 Cores Processors • Up to 450MHz ARM926EJ-S™ ARM9™ Display Subsystem Memory LCD • ARM: 16kB I-Cache; 16kB D-Cache Controller • On Chip: 128kB SRAM PRU (1707) • External interfaces: SDRAM x2 Subsystem Peripherals • PRU flexibility for added peripherals • USB 2.0 OTG w/ PHY • 10/100 EMAC L3/L4 Interconnect • MMC/SD card interface • Display subsystem with LCD controller • 1.8V or 3.3V I/O’s Connectivity Serial Interface USB OTG w/ PHY SPI x2 McASPx3 Power • Total Power: < 270mW USB HS w/ PHY I2C x2 UART x3 • Standby Power: < 62mW (1707) Memory Interface Timers Package • 17 x 17mm BGA (1.00mm), ZKB , 256-balls EMAC (1707) MMC/SD/SDIO WDT x1 (1707) • 26 x 26mm QFP(0.5mm), PTP, 176-pins (1705) UHPI SDRAM GP x1 • Extended Temperature Grade Options − Commercial (0C to 90C) NAND/NOR/ PWM x3 − Industrial (-40C to 105C) SDRAM − Automotive - not Q100(-40C to 125C) eCAP x3 • Pin to pin compatible processor: OMAP-L137 eQEP x2 Sitara MPU Day Get to market fast with best-in-class tools and development platforms

Development Tools Development Boards On-Demand Support

Various development tool Low cost boards <$200 • Local Support options allow designers of all – Industry’s largest field experience levels to quickly sales / applications team develop applications •WIKI’s – tiexpressdsp.com •Design • E2E Forum • Code and build Hawk - $89 Beagle - $149 – e2e.ti.com • Debug • TI Web/Product Folders • Analyze Full Featured Eval <$2000 – www.ti.com/sitara – www.ti.com/arm • Tune • Linux Community – Beagleboard.org –Hawkboard.org AM35x - $999 OMAP35x - $1495 • Open Source Projects – Designsomething.org Low cost and full featured easy- • Training to-use platforms to enable all – www.ti.com/training developers to get started quickly • Simple App Dev Kits • Fully Featured EVMs • Reference Designs & Demos Sitara MPU Day Evaluation and Development Kits

• Development Kit Contents: – Eval board & G documentation et St arted –BSP Today – Development tools

Tool Part Number Price Availability

AM37x EVM TMDXEVM3715 $1495 TI

AM3517 EVM TMDXEVM3517 $999 TI

AM18x EVM TMDXEVM1808L $1150 TI

AM17x EVM TMDXEVM1707 $845 TI AM18x Experimenter TMDXEXP1808L $445 TI Kit Zoom OMAP35x TMDSMEVM3530-L $995 (subject to change) Logic Development Kit Zoom AM3517 SDK-XAM3517-10-256512R $199 (subject to change) Logic Experimenter Kit Sitara MPU Day Featured community boards & modules

G et St arted • How to access: Today – Contact TI Partners for more information or click link to buy now

Tool Part Number Price Availability

$179 (subject to BeagleBoard-XM Beagle-XM Community (AM37x) change) $149 (subject to Beagle Board Beagle Community (OMAP35x) change) Hawkboard (AM18x / OMAP- ISSPLHawk $89 (subject to change) Community L138)

OMAP35x System OMAP35x SOM-LV $99 (subject to change) Logic on Module Overo OMAP35x $149-$219 Computer on Overo Gumstix (subject to change) Module $139 (subject to KBOC OMAP35x KBOC KwikByte System on Module change) Sitara MPU Day Sitara Cortex A8™ and ARM9 MPU Roadmap

Production Sampling Development AM389x Performance •Cortex-A8 • Maximum Optimized performance • Advanced connectivity

AM37x AM387x AM386x •Cortex-A8 •Cortex-A8 •Cortex-A8 OMAP35x • Up to 1GHz • Increased • Peripheral •Cortex-A8 • 3D Graphics integration enhancements • Up to 720MHz • LPDDR1 • 3D Graphics • LPDDR1

1200 DMIPS) Performance Line (> DMIPS) Value Line (< 1200 AM383x AM35x •Cortex-A8 •Performance •Cortex-A8 AM335x increase • Up to 500MHz •Cortex-A8 • 3D Graphics • Cost optimization AM17x AM18x • 10/100 Enet • Increased features •ARM9 •ARM9 •CAN • Up to 450MHz • Up to 450MHz • DDR2 • 10/100 Enet • 10/100 Enet •PRU •PRU • SDRAM • SATA • LPDDR1/DDR2 Power Optimized

1H10 2H10 1H11 2H11 Speeds shown are for commercial temperature. Dates approximate initial samples. Not all peripherals shown. Sitara MPU Day Why Sitara™ ARM® microprocessors

• TI’s Sitara family of highly-integrated ARM9™ and ARM Cortex™-A8 microprocessor portfolio offers various combinations of high-performance and low power levels providing the ability to create an array of products using a common hardware and software platform

• Reduce system risks and accelerate time to market using standard and comprehensive ARM-based software development tools

• TI is the largest ARM core licensee supporting all major high-level operating systems For more information: – Sitara home page: www.ti.com/sitara – ARM home page: www.ti.com/arm – TI Embedded Processor Wiki: tiexpressdsp.com – Forums: e2e.ti.com – Open Source Software Portal: DesignSomething.org – Training: www.ti.com/training Sitara MPU Day

Sitara™ Technical Overview: AM1x ARM9 Microprocessor Sitara MPU Day AM1x ARM9 MPU Agenda

• ARM9 Core Display Subsystem • Programmable Real-Time Unit ARM9™ LCD (PRU) Subsystem PRU Controller • Peripheral Overview Subsystem Video Video Input x2 Port • Boot Modes interface Video Output x2 • AM18x Runtime Power Management Techniques L3/L4 Interconnect • AM1x Switched Central Connectivity Serial Interface Resource Master Priorities USB OTG w/ PHY McBSP x2 McASP USB HS w/ PHY SPI x2 UART x3 • ARM Interrupts (1808) I2C x2 • System and Pinmux SATA (1808) Configuration Memory Interface Timers EMAC (1808) SDRAM WDT x1 • Package and Electrical Specifications UHPI LPDDR1/DDR2 GP x3 • Development Tools uPP MMC/SD/SDIO x3 PWM x2 eCAP x3 Sitara MPU Day CPU Core – ARM926EJ-S

• 375/450 MHz ARM926EJ-S – Includes MMU 64K • 16K I-Cache ARM926EJ-S Boot ROM • 16K D-Cache 450 MHz 8K • 64K ROM RAM –Boot ROM Vector 16K 16K Table MMU • 8K RAM (Vector Table) I-Cache D-Cache • ARM Interrupt Controller

• 32-inputs SCR • Configurable Priority 128K RAM (shared) Sitara MPU Day

Programmable Real-time Unit (PRU) Subsystem Sitara MPU Day Introduction

1. What is PRU? – Programmable Real-time Unit Subsystem – Dual 32bit RISC processors running at ½ CPU freq. – Local instruction and data RAM. Access to chip-level resources

2. Why PRU? – Full programmability allows adding customer differentiation – Efficient in performing embedded tasks that require manipulation of packed memory mapped data structures – Efficient in handling of system events that have tight real-time constraints. Sitara MPU Day PRU Is/Is-Not

Is Is-Not Dual 32-bit RISC processor specifically In not a H/W accelerator to speed up designed for manipulation of packed algorithm computations. memory mapped data structures and implementing system features that have tight real time constraints Simple RISC ISA Is not a general purpose RISC processor • Approximately 40 instructions • No multiply hardware/instructions, no • Logical, arithmetic, and flow control ops cache, no pipeline all complete in a single cycle • No C programming Simple tooling. Includes Simulator and Assembly tool is integrated into CCS. Assembler Debug for PRU is not. Example code to demonstrate various No SW stack features available. Examples can be used as building blocks Sitara MPU Day PRU Value

1. Extend Connectivity and Peripheral capability – Implement special peripherals and bus interfaces (e.g. UARTs) – Implement smart data movement schemes. Especially useful for Audio algorithms (e.g. Reverb, Room Correction)

2. Reduce System Power Consumption – Allows switching off the ARM clocks – Implement smart power controller by evaluating events before waking up ARM. Maximized power-down time.

3. Accelerate System Performance – Full programmability allows custom interface implementation – Specialized custom data handling to offload ARM for innovative signal processing algorithm implementation Sitara MPU Day PRU Subsystem

• Provides two independent programmable real-time (PRU) cores PRU Subsystem Functional Block Diagram – 32-Bit Load/Store RISC architecture 32 GPO PRU0 Core DRAM0 – 4K Byte instruction RAM (1K 30 GPI (512 Bytes) 32-bit Interconnect SCR 32-bit Interconnect instructions) per core 4KB IRAM – 512 Bytes data RAM per core 32 GPO DRAM1 • PRU operation is little endian PRU1 Core (512 Bytes) 30 GPI • Includes Interrupt Controller for 4KB IRAM system event handling Master I/F • I/O interface Interrupts to (to SCR2) – 30 input pins and 32 output pins ARM INTC Interrupt Controller Events from Slave I/F per PRU core (AM18x) (INTC) Peripherals + (from SCR2) – AM17x does not support PRU I/O PRUs • Power management via single power/sleep controller (PSC) Sitara MPU Day PRU Functional Block Diagram General Purpose Registers • All instructions are performed on Constant Table registers and complete in a single • Ease SW development by cycle providing freq used • Register file appears as linear block constants for all register to memory operations • Peripheral base addresses • Few entries programmable PRU CONST R0 TABLE … … Execution Unit R1 MEM -1 R N-1 • Logical, arithmetic, and flow LD MEM RN 2 R2 MEM control instructions R N … EXECUTION MEM + 1 R N+1 UNIT • Scalar, no Pipeline, Little ST RN MEM 2 MEM + 2 R N+2 R29 Endian … … • Register-to-register data flow 32 GPO R30 • Addressing modes: Ld 30 GPI R31 Instruction Immediate & Ld/St to Mem RAM INTC

Special Registers (R30 and R31) Instruction RAM •R30 • 4KB in size; 1K – Write: 32 GPO Instructions •R31 • Can be updated with PRU – Read: 30 GPI + 2 Host Int status reset – Write: Generate INTC Event Sitara MPU Day PRU Instruction Set

Arithmetic Logic IO Program Flow Operations Operations Operations Control

ADD LSL MOV JAL ADC LSR LDI JMP SUB AND LBBO QBGT SUC OR SBBO QBGE RSB XOR LBCO QBLT RSC NOT SBCO QBLE MIN ZERO QBEQ MAX MVIB QBNE CLR MVIW QBA SET MVID QBBS SCAN QBBC LMBD WBS WBC HALT SLP CALL RET

Pseudo Op-code (Italic) Sitara MPU Day PASM Overview

• PASM is a command-line assembler for the PRU cores – Converts PRU assembly source files to loadable binary data – Output format can be raw binary, C array (default), or hex • The C array can be loaded by host processor (ARM) to kick off PRU – Other debug formats also can be output

• Command line syntax: pasm [-bcmldxz] SourceFile [-Dname=value] [-CArrayname]

• The PASM tool generates a single monolithic binary – No linking, no sections, no memory maps, etc. – Code image begins at start of IRAM (offset 0x0000) Sitara MPU Day Basic Software Package Contents (Today)

• http://focus.ti.com/docs/toolsw/folders/print/sprc940.html

• Bin directory – PASM binary tool

•Doc – Current documentation – Reference to online documentation

•Examples – Collection of CCSv3 DSP projects and associated PRU code

•Host – Common: rCSL, PRU APIs, various helper functions used by examples – DSP: CCSv3 loader examples for C674x DSP core Sitara MPU Day Advanced Software Package (April. 2010)

• Development to be done by Mistral – Free download from TI

• Full soft IP deliverables (CCS based) – Multichannel UART, utilizing McASP (proof of concept demo) – CAN interface – Profibus, RTE – Specialized timers/schedulers – Smartcard IF – DMA framework for specialized audio algorithms

• Companion PRU daughter card Sitara MPU Day

Peripheral Overview Sitara MPU Day Universal Parallel Port (uPP) Extends System Interconnect Options (AM18x only) What is uPP? uPP Peripheral • High Speed parallel data port Config External Pins CPU I/O Registers • Two Bidirectional and Channel Independent 16bit channels A • Internal dedicated DMA to Memory Internal I/O streamline data I/O DMA Channel CPU B • Simple I/O Protocol Interrupt

Value of uPP Configuration Throughput (MB/s) • Efficient Processor to FPGA communication enabled by high 1 Ch, 16-bit 120 speed data I/O 2 Ch, 1 Way, 8-bit 120

• Enable multi-processor system 2 Ch, 1 Way, 16-bit 160 design in various topologies 2 Ch, 2 Way, 16-bit 240 • Interface with high speed ADCs and DACs HPI (16-bit) 50 Sitara MPU Day Serial ATA (SATA) Interface

Benefit: HDD connectivity for large storage applications. SATA is a low pin count, high-speed serial interface.

Features of the SATA include the following: • Supports SATA specification 2.6 • Supports Gen1 (1.5Gbits/Sec) and Gen2 (3.0Gbits/Sec) line speed. • Cold Presence detect allows use of the SATA Connector capability for Hot Plug support • Uses 8b/10b encoding/decoding scheme with a running disparity • Supports AHCI Controller 1.1. • Supports a single HBA port with the capability of scheduling the max supported number of commands, which is 32 commands. • Supports hardware-assisted Native Command Queuing (NCQ) • Has the support for an external Port Multiplier • Supports Partial and Slumber Power-Down modes Sitara MPU Day MMC/SD

Benefit: Multimedia cards (MMC) and Secure Digital (SD) cards connectivity for medium storage applications plus a high speed interface used to achieve WiFi connectivity

Features of the MMC/SD include the following: • Supports a MultiMediaCard (MMC) / Secure Digital Memory Card (8-bit data bus is available for MMC v4.0). • The ability to use the MMC/SD protocol and SDIO protocol. • A programmable frequency of the clock that controls the timing of transfers between the MMC/SD Controller and memory card. • 512 bit Read/Write FIFO to lower system overhead • Signaling to support DMA transfers (slave) • 37.5 MHz maximum clock to SD (spec. V2.0) Sitara MPU Day EMIF A – External Memory Interfaces

Benefit: Interface with external memory devices including SDR-SDRAM, ASRAM, NAND Flash & NOR Flash. Features of the EMIFA include: • Features of SDR-SDRAM interface: – Supports JESD21-C standard compliant SDR SDRAM devices. – 128 MB (AM17x) or 512 MB (AM18x) address range over 1 chip select – 16-bit wide data bus – CAS latencies of 2 & 3 / 1, 2 & 4 internal banks / 256, 512, 1024 & 2048 page sizes – Self-refresh, power-down and ‘mclk’ gating for low power. – Supports sequential burst type. (Interleaved burst type not supported). Burst length = 8 – One CPU interrupt – No support of an EDMA event • Features of Async memory interface: – 32 KB (AM17x) or 64MB (AM18x) address range on each of 4 chip selects. – 8-bit and 16-bit wide data bus – Programmable cycle timings for each chip select – Supports page mode for NOR Flash – Supports Ready input – Supports 1-bit ECC & 4-bit ECC for 8 and 16-bit NAND Flash Sitara MPU Day EMIF B – AM17x ONLY

Benefit: EMIFB is used to interface with external SDR-SDRAM

Features of EMIF B: • Supports JESD21-C standard compliant SDR SDRAM devices. Also supports mobile SDR • 256 MB address range over 1 chip select • Supports 32-bit data bus width • Supports CAS latencies of 2 & 3 • Supports 1, 2 & 4 internal banks • Supports 256, 512, 1024 & 2048 page sizes • Supports ‘Self-Refresh’ and ‘Power Down’ modes for low power. Also supports ‘mclk’ gating for low power • Supports partial array self refresh in mobile SDR SDRAM • Supports sequential burst type. (Interleaved burst type not supported). Burst length = 4 • No event to EDMA supported Sitara MPU Day DDR2/mDDR – AM18x ONLY

Benefit: DDR2/mDDR is used to interface with external DDR2 or mobile DDR memory

Features of DDR2/mDDR: • Supports JESD79D-2A standard compliant DDR2 SDRAM • 150MHz clock rate • 512 MB memory space for DDR2, 256MB memory space for mDDR • Supports 16-bit data bus width • Supports CAS latencies of 2 – 5 (4 & 5 for DDR2 only) • Supports 256, 512, 1024 & 2048 page sizes • Supports ‘Self-Refresh’ and ‘Power Down’ modes for low power. Also supports ‘mclk’ gating for low power • Supports partial array self refresh in mDDR • Supports sequential burst type. (Interleaved burst type not supported). Burst length = 8 • No event to EDMA supported Sitara MPU Day EMAC – Ethernet Media Access Controller

Benefit: The EMAC module provides an efficient interface between the processor and the networked community

Benefit: OTG controller provides a mechanism that complies with the USB2.0 standard for data transfer between USB devices up to 480 Mbps Features of the USB include: • Operating as a host, it complies with USB2.0 standard for high-speed, full-speed and low-speed operation with a peripheral • Operating as a peripheral, it compiles with USB2.0 standard for high-speed and full-speed operation with a host • Supports USB OTG extensions for Session Request (SRP) and Host Negotiation (HNP) • Supports all modes of transfers (control, bulk, interrupt, and isochronous) • Supports 4 simultaneous Transmit (TX) and 4 Receive (RX) endpoints, in addition to endpoint 0 • Includes a DMA controller that supports 4 TX and 4 RX DMA channels with a max single data transfer size up to 4Mbytes • Includes four types of Communications Port Programming Interface (CPPI) 4.1 DMA compliant transfer modes: Transparent, Generic RNDIS, RNDIS, and Linux CDC Sitara MPU Day USB 1.1 Host

Benefit: OHCI controller makes connecting to devices/targets (e.g. Thumb Drive, HDD, Printer, etc) faster and easier up to a maximum speed of 12 Mbits/Sec

Features of the USB 1.1 include: • OHCI Host Controller • Controller generates USB traffic based on data structures and data buffers stored in system memory • Controller accesses the data structures without direct intervention by the processor, which reduces processor software and interrupt overhead. • Full Speed rate of 12 Mbit/s • Low speed rate of 1.5 Mbit/s Sitara MPU Day LCDC

Benefit: The liquid crystal display controller (LCDC) is used to interface to character display panels for text message display or to graphical display panels for image/video display

Features of LCDC include the following: • Supports asynchronous LCD interface (LIDD) to interface to character displays and a synchronous (raster-type) LCD interface to interface to graphical displays for image/video. • LIDD mode supports up to 16-bit parallel data output and two displays using primary and secondary chip selects. • Raster mode supports 1,2,4,8 bits per pixel passive (Super Twisted Nematic) matrix display and 1,2,4,8,16 bits per pixel active matrix (Thin Film Transistor) display. • Raster mode supports up to 1024x1024 display (Frame-rate determined by pixel clock – max 37.5 MHz) • Frame buffer is programmable and can use either internal or external memory Sitara MPU Day Quadrature Encoder Pulse Module (eQEP)

Benefit: The Quadrature Encoder Pulse (eQEP) peripheral is used for direct interface with a linear or rotary incremental encoder to get position, direction & speed information from a rotating machine for use in high performance motion & position control system

Features of the eQEP include: • Input Synchronization • Quadrature Decoder Unit • Position Counter and Control unit for position measurement • Quadrature Edge Capture unit for low speed measurement • Unit Time base for speed/frequency measurement • Watchdog Timer for detecting stalls

* eQEP available on AM17x only Sitara MPU Day Enhanced High Resolution Pulse Width Modulators (eHRPWM) Benefit: The Enhanced High Resolution Pulse Width Modulators (eHRPWM) can effectively generating complex pulse width waveforms with minimal CPU overhead or intervention

Features of the eHRPWM include: • Dedicated 16-bit time-base counter with period and frequency control • Asynchronous override control of PWM signals through software • Programmable phase-control support for lag or lead operation relative to other eHRPWM modules • Dead-band generation with independent rising and falling edge delay control. • Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions. • Programmable event prescaling minimizes CPU interrupt overhead. • High-resolution PWM allows finer time granularity control of edge positioning (~200 ps)

3 on AM1707 2 on AM1808 Sitara MPU Day Enhanced Capture Module (eCAP)

Benefit: The Enhanced Capture Module (ECAP) is essential in systems where accurate timing of external events is important

Features of the eCAP include: • 32-bit time base counter • 4-event time-stamp registers (each 32 bits) • Edge polarity selection for up to four sequenced time-stamp capture events • Interrupt on either of the four events • Single shot capture of up to four event timestamps • Continuous mode capture of timestamps in a four-deep circular buffer • Absolute timestamp capture • Difference (Delta) mode timestamp capture • All above resources dedicated to a single input pin • When not used in capture mode, the eCAP module can be configured as a single channel PWM output Sitara MPU Day Host Port Interface (HPI)

Benefit: The Host Port Interface (HPI) is a parallel port through which a host processor can directly access program and data memory space. The host device functions as a master to the interface, which increases ease of access

Features of the HPI include: • Multiplexed address and data bus • 16-bit data • Both the host and the CPU can access the HPI control register (HPIC) and HPI address register (HPIA) • Multiple strobes and control signals to allow flexible host connection • An external host is capable of accessing most of the on chip memories Sitara MPU Day EDMA 3.0 & SCR–3-Component Architecture

Benefit: Enhanced DMA engine for efficient movement of data between memory and peripherals. Switch Central Resource for high speed, concurrent interconnect

Channel Controller: • Supports flexible 1D,2D and 3D transfers • 2 channel controllers, each with 32 DMA Channels, 8 QDMA Channels • Submits transfer requests (TR) to TC for data transfers between slave peripherals/ memories • Stores/Manages context for multi-frame transfers, ping-pong buffers, circular buffers etc • Manages events (manual, external, chained) − Detects, prioritizes, queues TC0 • Supports transfer chaining and linking External Memory CCn Transfer Controllers (TCs): events TCn Internal • Performs slave-to-slave transfer requests from CC Memory • Responsible for data movement from SRC to DST SCR

Switched Central Resource (SCR): Master Slave Peripheral Peripheral • High Speed , Low Latency Interconnect Data Commands • Enables more concurrency Master Slave Peripheral Peripheral Sitara MPU Day McASP – Multichannel Audio Serial Port

Benefit: The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio applications including time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and inter-component digital audio interface transmission (DIT)

Features of the McASP include: • Two independent clock zones (transmit and receive), each with: − Programmable high frequency and bit clock generators − Programmable frame sync generator • Up to 16 serial data pins, individually assignable as Rx or Tx − TDM streams from 2 to 32, and 384 time slots − Support for slot sizes of 8, 12, 16, 20, 24, 28, and 32 bits − Data formatter for bit manipulation • Supports I2S protocol − I2S is used to transfer serial audio data from chip to chip − Application example: AM17x connected to D/A converter • Integrated digital audio interface transmitter (DIT) supports: − S/PDIF, IEC60958-1, AES-3 formats − Up to 4 transmit pins − Enhanced channel status/user data RAM − DIT is used to transfer digital audio from component to component − Application example: connection from DVD player to A/V receiver • Extensive error checking and recovery Sitara MPU Day McBSP – Multichannel Buffered Serial Port (AM18x) Benefit: The McBSP functions as a general-purpose serial port with programmable behavior to conform to multiple serial interface standards. The MCBSP is well-suited for applications with time-division multiplexed (TDM) data streams

Features of the McBSP include: • Full-duplex communication • 128-channel capability • Programmable word width (8, 12, 16, 20, 32) • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs) and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices • External shift clock or internal, programmable frequency shift for data transfer • Transmit and receive FIFOs allow the McBSP to operate at higher sample rates by making it more tolerant to DMA latency. Sitara MPU Day SPI

Benefit: The SPI is a high-speed synchronous serial input/output port providing an interface to microcontrollers, data converters and serial EEPROMs

Features of SPI include the following: • 16-bit shift register • 2 to 16 bit data width • Receive buffer register (SPIBUF) and Transmit Data Register (SPIDAT0) • 8-bit baud clock generator • Programmable clock frequency, polarity, phase and character length • Multiple SPI modes like 3-pin, 4-pin with Chip select, 4-pin with Enable and 5-pin • Maximum SPI clock rate is 50 MHz

Applications of SPI include the following: • Interface with an external microcontroller • Configure ADCs, DACs, display drivers, shift registers • Interface with an EEPROM Sitara MPU Day UART Benefit: The Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial conversion on data received from the internal busses

Features of the UART include the following: • 16-byte storage space for both the transmitter and receiver FIFOs • 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA • DMA signaling capability for both received and transmitted data • Programmable auto-rts and auto-cts for autoflow control • Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates • Fully prioritized interrupt system controls • Fully programmable serial interface characteristics: − 5, 6, 7, or 8-bit characters − Even, odd, or no parity bit generation and detection − 1, 1.5, or 2 stop bit generation • Line break generation and detection • Loopback controls for communications link fault isolation • 16x or 13x over sampling • Maximum UART baud rate >12 Mbaud Sitara MPU Day I2C – Inter-Integrated Circuit

Benefit: External components attached to the I2C bus serially transmit/receive up to 8-bit data to/from the device through the 2-wire I2C interface

The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (v2.1) • One read EDMA event and one write EDMA event, which can be used by the EDMA controller • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: transmit-data ready, receive- data ready, register-access ready, no-acknowledgement received, arbitration lost • Module enable/disable capability • Free data format mode Sitara MPU Day GPIO – General-Purpose Input/Output

Benefit: The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs

Features of the GPIO include: • When configured as an output, the state driven on the output pin is controlled by writing to an internal register • When configured as an input, the state of the input pin is obtained by reading the state of an internal register • In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event generation modes • GPIOs are programmable on a per-pin basis • Most pins on the device can be used as GPIO if not used for some other function through configuration of the pin muxing controls. Sitara MPU Day Timers Benefit: The device has 64-bit general-purpose timers that can be used to time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the DMA

Features of the timers include: • Each 64-bit timer can be alternately configured as two 32-bit timers. • The timers can be clocked by an internal or an external source • The timers have an input pin and an output pin. The input and output pins (TM64P_IN and TM64P_OUT) can function as timer clock input and clock output. • With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or it can trigger the DMA controller to begin a data transfer. • With an external clock, the timer can count external events and interrupt the CPU after a specified number of events. • Timer1 configurable as a watchdog timer to trigger a system reset • Timer 3 and 4 are available on AM18x only Sitara MPU Day Supported Boot Modes

All Boot modes supported via ROM Boot loader: • NAND Flash boot − 8-bit NAND − 16-bit NAND • NOR Flash boot − NOR Direct boot − NOR Legacy boot − NOR Application Image Script (AIS) boot • HPI Boot • I2C0/I2C1 Boot − Master boot − Slave boot • SPI0/SPI1 Boot − Master boot − Slave boot • UART0/1/2 Boot Sitara MPU Day AM18x Runtime Power Management Techniques

• Clock gating (modules, infrastructure) • CPU idle/sleep modes • Deep Sleep Mode (AM18x only) • Dynamic frequency scaling (PLL) • Dynamic voltage scaling (PMIC) • PHY power down (SATA, USB, DDR) Sitara MPU Day AM1x Master Priorities and Arbitration

• Master Priority Control − Each switched central resource (SCR) performs prioritization based on priority level of the master that sends the read/write requests. − 7 programmable priority levels − Master priority is programmed in the master priority registers (MSTPRI0-3) in the SYSCFG modules. − Application software is expected to modify these values to obtain the desired performance. • Arbitration Scheme − At each priority level, one request from each master is selected in a round robin manner. − The highest priority request is selected. − Arbitration occurs at burst size boundaries (or lower). Sitara MPU Day Interrupts – ARM Interrupt Controller

• Interface between System Interrupts and ARM9 interrupt interface • Supports up to 32 interrupt channels • Multiple interrupts can be mapped to a single channel • Channels 0 and 1 are mapped to FIQ • Channels 2-31 are mapped to IRQ • Each system interrupt can be enabled and disabled • Each host interrupt can be enabled and disabled • Hardware prioritization of interrupts Sitara MPU Day System Config Module System configuration module consists of: • Memory-mapped status registers • Control registers

Supported Features: • Device Identification • Device Configuration − Pin multiplexing control − Device Boot Configuration Status • Master Priority Control − Controls the system priority for all master peripherals (including EDMA3TC) • Emulation Control − Emulation suspend control for peripherals that support the feature • Special Peripheral Status and Control − Locking of PLL control settings − Default burst size configuration for EDMA3 transfer controllers − Event source selection for the eCAP peripheral input capture − McASP AMUTEIN selection and clearing of AMUTE − USB PHY Control − Clock source selection for EMIFA and EMIFB − HPI Control Sitara MPU Day Pin Mux Configuration

• Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module. • Pin multiplexing can be controlled on a pin-by-pin basis. • Each pin that is multiplexed with several different functions has a corresponding 4-bit field in the PINMUXn register • Selects which of several peripheral pin functions controls the pin's IO buffer output data and output enable values only • Note that the input from each pin is always routed to all of the peripherals that share the pin • Pin Mux utility software support: − Allows the pin multiplexing registers of the device to be calculated with ease. − Shows what peripherals can be used together Sitara MPU Day Pin Mux Utility Sitara MPU Day AM1707 Package/Electricals

• Package − 256 pin − 17x17mm BGA − 1.0 mm pitch • Supply voltages − CVDD: 1.2V or 1.3V − DVDD: USB 1.8V, all other 3.3V • Temperature ranges − Commercial: 0 – 90C junction − Industrial: -40 – 90C junction − Extended: -40 – 105C junction − Automotive: -40 – 125C junction Sitara MPU Day AM1705 Package/Electricals

• Package − 176 pin − 26x26mm PowerPAD™ Plastic QFP − 0.5 mm pitch • Supply voltages − CVDD: 1.2V or 1.3V − DVDD: USB 1.8V, all other 3.3V • Temperature ranges − Commercial: 0 – 90C junction − Industrial: -40 – 90C junction − Extended: -40 – 105C junction − Automotive: -40 – 125C junction Sitara MPU Day AM18x Package/Electricals

• ZCE Package − 361 pin − 13x13mm BGA − 0.65 mm pitch • ZWT Package − 361 pin − 16x16mm BGA − 0.8 mm pitch • Supply voltages − CVDD: 1.0V / 1.1V / 1.2V / 1.3V − DVDD: USB/DDR2/SATA 1.8V, all other 1.8/3.3V • Temperature ranges − Commercial: 0 – 90C junction − Industrial: -40 – 90C junction − Extended: -40 – 105C junction Sitara MPU Day Software Overview

• ARM OS Support − MontaVista Linux kernel, drivers, tool chain etc. (for AM17x) − Open source kernel/driver from GIT tree (for AM18x) − Other OS options: WinCE, VxWorks Sitara MPU Day Linux Platform Support Package

• UBOOT − 1.3.3 for AM17x • Utility program to flash ARM UBL, UBOOT and Linux kernel in flash media • LSP user guide explains − LSP installation − How to build kernel/driver/UBOOT − How to setup Linux host (briefly) − Different kernel boot options • Open source kernel (+ drivers) − AM17x: MV 2.6.18 kernel; Will be pushed to open source later − AM18x: Development from the latest kernel in the open source Sitara MPU Day WinCE Overview

• Working with MPCData to port CE to… − AM18x first − AM17x later • Working with a handful of early adopters now to flush out support • Phase 1 – March 2010 − V1.0.0 BETA under testing currently − CE6.0 − Full-EVM from Logic − Available from TI at no charge to the customers − MPC Data available for design services partner − Documentation • Release notes, User Guide, Quick Start Guide, License Agreement Sitara MPU Day

Development Tools & Reference Designs Sitara MPU Day Get to market fast with AM1x development tools AM18x AM17x Hawkboard evaluation module evaluation module

$1150 $845 $89

• Supports AM18x, C674x, • Touch screen LCD • Community board for or OMAP-L138 SOMs • Full peripheral access OMAP-L138 (AM1808/06) • Touch screen LCD • Connector for PRU • Available from • Full peripheral access daughter card • Connector for PRU daughter card • Experimenter kit available for $445 Order entry open now! Sitara MPU Day AM1707 Starter Kit Use for Development on: AM1707, AM1705

• AM1707 ARM Processor • 24-bit stereo CODEC • Four 3.5 millimeter audio jacks • 64Mb SPI Flash memory • 512Mb SDRAM • Ethernet MAC, USB 2.0, USB 1.1, MMC/SD, LCD controller

Hardware • HPI, McASP & I2C interface header emulation • On-board standard JTAG interface • Embedded JTAG support via USB • +5V universal power supply • Expansion ports for plug-in modules

Starter Kit • Monta Vista Linux Pro 5.0 Software support • Fast run-time library available on the web • Quick Start Guide and technical reference Available Now: $845 Software Part Number: TMDXEVM1707 Sitara MPU Day AM1808: Tools for varying customer requirements Use for Development on: AM1808, AM1806

System-on-Module AM1808 EVM • Includes Experimenter board + • AM1808 processor AM1808 SOM and UI board − Full peripheral access: SATA, • 64 or 128MB mDDR uPP, EMAC, USB 2.0/1.1 and • Ethernet PHY MMC/SD, VPIF, LCDC, UPP *Available from Logic for $99 • Software included (depending on volume) • TI supported • LCD display option Small FF *Available from TI for $1150 Confirmed mDDR PN: TMDXOSKL138BET design 2x the memory w/128MB Experimenter board

• AM1808 SOM System-on-Module • 64MB mDDR PN: SOMOMAPL138-10-1502AHCR (64MB mDDR) $99 • Access to key peripherals: PN: SOMOMAPL138-10-1602AHCR (128MB mDDR) − SATA, USB, EMAC, Audio • TPS65070 power management Experimenter Board • CCStudioTM 3.3 & 4.0 TI PN: TMDXEXP1808L $445 *Available from Logic & Authorized Distributors for $445 Evaluation Board Open source TI PN: TMDXEVM1808L $1150 Linux peripheral drivers Sitara MPU Day Hawk Board Ultra low-cost Open Community Platform for OMAP-L138 & AM1808/06 Composite IN VGA

JTAG (ARM-9 and C674x Floating Point DSP)

Expansion SATA •SPI •uPP •PRU Audio Out •VPIF •GPIO Audio IN • MMC/SD •UART 128MB DDR •I2C •PWM UART •eCAP 128MB NAND

USB OTG Ethernet USB Host /Power Power Jack MMC/SD Sitara MPU Day XDS510 and XDS560 • Supports Texas Instruments Processors and Microcontrollers with JTAG interface • Operates off PC/laptop USB port, no internal adapter required • 14-pin JTAG header • USB bus powered, no power supply required • Supports USB 1.x and USB 2.0 (full speed) • Advanced emulation controller provides high performance • Compatible with +3.3V or +5V processors • One LED provides operational status Sitara MPU Day XDS100v2

• Robust and efficient JTAG emulation controller − Plug in and play operation. • Twice as fast as XDS100 version 1 • Available from − Spectrum Digital − Blackhawk − Build your own!

• Additional information: http://tiexpressdsp.com/wiki/index.php?title=XDS100 Sitara MPU Day

Q&A Sitara MPU Day

AM35x Technical Overview Sitara MPU Day AM35x MPU Agenda

• Hardware AM3517/05 – High-level Overview processors – ARM Cortex-A8 ARM® Display Subsystem ™ LCD Video 10 bit DAC – Memory Subsystem 3D Cont- Cortex - Enc Graphics roller 10 bit DAC – Display Subsystem (DSS) A8 Accelerator (3517) Video – Video Processing Front 16-bit Video Processing Input End (VPFE) Front End – Highlighted Peripherals L3/L4 Interconnect – Power Management – Package CAN Timers HDQ / USB HS Host x2 – EVM EMAC GP x12 1-wire USB OTG w/PHY WDT x1 • Software & Tools I2Cx3 – Cortex-A8 Software McBSP x5 UARTx3 DDR2 MMC/SD/ Summary McSPI x4 +1 w/IrDA GPMC SDIO x3 – Linux & WinCE Sitara MPU Day

High-level Overview Sitara MPU Day AM3517/05 Overview

AM3517/05 Core processors • 600 MHz Cortex™A-8 w/ ® Display Subsystem NEON™ SIMD Coprocessor ARM ™ LCD Video 10 bit DAC 3D Cont- Cortex - Enc • 3D/OpenVG Graphics Core Graphics roller 10 bit DAC (10M polygons per second) A8 Accelerator (3517) Video 16-bit Video Processing Input Peripheral Highlights Front End • DDR2 Support L3/L4 Interconnect • USB 2.0 HS Host and OTG w/ PHY Connectivity Serial Interface Memory Interface USB OTG w/ PHY McBSP x5 DDR2 • RMII EMAC controller • HECC – CAN Controller USB HS Host x2 MCSPI x4 NAND/NOR • Native 3.3V IO interfaces CAN Controller I2C x3 MMC/SD/SDIO x3

EMAC HDQ/ 1-wire Timers UART x3 GP x12

UART w/ IrDA WDT x2 Sitara MPU Day AM35x Overview – Platform

Applications Software Shared 3D Graphics Compatibility Peripheral Set Compatibility

AM™ ARM Graphics AM3517 Cortex-A8 Peripherals Open GL ES 600 MHz 2.0

AM™ ARM AM3505 Cortex-A8 Peripherals 600 MHz

Pin-for-pin compatible Availability subject to applicable lead times Sitara MPU Day

ARM Cortex-A8 Sitara MPU Day CORTEX A-8 : Highlights

• First ARMv7 instruction-set architecture • Dual-issue, in-order, superscalar architecture delivers high performance – Advanced dynamic Branch prediction • 256 KB unified L2 cache – Dedicated, low-latency, high-BW interface to L1 cache • Enhanced VFPv3 – Doubles number of double-precision registers – Adds new instructions to convert between fixed and floating point • Efficient Run Time Compilation Target – Jazelle-RCT: Target for Java. Memory footprint reduced up to 3x – Can also target languages such as Microsoft .NET MSIL, Perl, Python Sitara MPU Day Architectural Improvements in Cortex-A8

ARM Cortex-A8 is designed to be a very efficient OS platform

• NEON™: 64/128-bit Hybrid SIMD Engine for Multimedia – Supports Integer and Floating Point SIMD • Thumb-2: performance of ARM code with code size of Thumb – Mixed 16/32-bit instruction set – Simply compile everything with ‘--thumb --cpu cortex-a8’ • Thumb-2EE: “Jazelle-RCT” – For JIT compilation of OO bytecode languages • Physically Indexed, Physically Tagged (PIPT) caches: handles task switching OS cleanly – No ‘page coloring’ workarounds required for 32K D-caches • Thread local storage (new CP15 register) – Each thread in a process is given a unique ID where it can store thread-specific data – Supported by gcc and RVDS armcc – Efficient threading Sitara MPU Day Processor Progression

AM35x Processor ARM926EJ-S™ ARM1136J-S™ Cortex™-A8

Frequency 233+ MHz 330+ MHz 600 MHz

DMIPS 260+ 400+ 1200

Architecture ARMv5TE ARMv6 ARMv7-A with NEON

VFPv3 Floating point Optional VFPv2 Optional VFPv2 (backwards compatible with VFPv2) Thumb-2 No No Yes

Instruction ARM and Thumb ARM and Thumb ARM and Thumb-2 (16/32-bits, requires (16/32 bits, requires (16/32 bits, no mode Set programmer effort) programmer effort) switching needed) Jazelle DBX DBX RCT Sitara MPU Day Processor Progression (cont.)

AM35x

Processor ARM926EJ-S™ ARM1136J-S™ Cortex™-A8 Architecture V5 V6 V7 Version In-order, dual-issue Pipeline type In-order scalar In-order scalar superscalar Pipeline stages 5 8 13 Branch prediction No 128 entry BTB 512 entry BTB ISA Efficiency 1.07 1.18 2.01 (DMIPS/MHz) MMU Yes Yes Yes Core to L1 32 bit 64 bit 64 bit (128 Neon) interface Line length 32B 32B 64B Tightly coupled Yes Yes No memory Sitara MPU Day Neon significant gains NEON improves multimedia performance

• Addition/Subtraction – Dual ALU pipeline for parallel processing of 128 bits of data – 4x potential performance boost over ARM alone • Complex instructions – Implements complex (DSP like) instructions which don’t exist on ARM – They can be processed in a few cycles as opposed to many cycles with ARM • Loop unrolling, data segmentation – Large number of registers to help offload ARM registers allowing for code control and pointers – Large number of registers to more easily unroll loops for interleaving and envisage processing chunks of different data segments in the same loop body. • Memory access – Allows for complex data interleaving and de-interleaving in a way not possible on ARM alone – Improves efficiency of writing to memory – This can be particularly advantageous for image processing. Neon’s packing straight from memory is advantages of a SIMD approach to data processing on the ARM can sometimes be outweighed by the cost of packing the data into registers. Sitara MPU Day

Memory Subsystem Sitara MPU Day AM35x Memory Controller • Two dedicated memory controllers/one internal memory – SDRAM controller (EMIF4) – General purpose memory controller (GPMC) – Internal memory (SRAM) • On Chip Memory [SRAM-64 KB] – Operates at full L3 interconnect clock frequency (166MHz) – One 32-bit access per cycle – By default, only 2K bytes available after reset; however, configuration can then be changed to adapt to application requirement. – Memory range: 0x4020 0000 - 0x4020 FFFF Sitara MPU Day GPMC Controller

• 16-bit external memory controller • GPMC can communicate with many external AM35x devices: − External asynchronous/synchronous 8-bit wide memory/device PsRAM, OneNAND, − External asynchronous/synchronous 16-bit wide Supported NOR/NAND Flash, ASYNC memory/device Logic − External 16-bit non-multiplexed device with limited address range (2 Kbytes) − External 16-bit address/data-multiplexed NOR flash 1GB (128MB per device CS- mux mode) Supported Size − External 8-bit/16-bit NAND flash device 16 KB (2 KB per − External 16-bit pseudo SRAM (pSRAM) device (bits) CS non-mux mode) • Dynamic auto-idle: GPMC internally disables functional clock when no requests pending and no accesses ongoing. Max Clock Speed 100 MHz • Idle request/acknowledge: − Force-idle: On receiving an idle request from PRCM Chip Selects 8 module the GPMC immediately sends an idle request/ acknowledge to let PRCM module correctly cut the 2 KB non mux mode GPMC source clock. Max Address Space − No-idle: GPMC never goes to idle mode. 128 MB mux mode − Smart-idle (strongly recommended): GPMC goes to idle mode when all ongoing transactions are Data Width 16 b complete. Sitara MPU Day SDRAM Controller

AM3517/05 • SDRAM controller has three functional blocks: SDRAM Supported DDR2 − Virtual Rotated Frame Buffer (VRFB) • Rotation engine supporting rotations of 0, Measured 90, 180, 270 810MB/sec ° Throughput − SDRAM memory-access scheduler 16M, 32M, (SMS) Supported Size 64M, 128M, 256M, • Optimizes latency and bandwidth usage (bits) among requestors 512M,1G − SDRAM Controller Max Clock Speed 166MHz • Physical interface to DDR2 or mDDR • Two chip selects Chip Selects 2

OCP – 64b Data Width SDRAM – 16/32b Sitara MPU Day

Display Subsystem Sitara MPU Day Display Subsystem (DSS) Sitara MPU Day

Video Processing Front End (VPFE) Sitara MPU Day Video Processing Front End

Camera clock and synchronization signal Parallel camera

AM35x

VPFE Timing control

processing sub module

C C D C

VPBE

PREVIEW

L3 MMU REGISTERS L4 Sitara MPU Day Video Processing Front End

• Input − RAW (CCD or CMOS sensor - Bayer pattern) − YUV 4:2:2 (camera)

• Interface (Parallel) − Sync (RAW/RGB) – 8, 10, 11, or 12 bit interface − ITU-R BT 656 (YUV422) − YCbCr 422 – 8 or 16 bit

• Image Processing Module − CCDC • Physical Interface for camera/image sensors • Optical Clamp, Optical Black Clamp

− Image-Pipe: • A-Law decompression Sitara MPU Day

Highlighted Peripherals Sitara MPU Day Controller Area Network (CAN)

Ideal for noisy and harsh environments

• Serial multi-master communication supporting up to 1MBps • AM35x supports Standard CAN controller (SCC) and High End CAN controller (HECC) for complex applications. Sitara MPU Day EMAC – Ethernet Media Access Controller

The EMAC module provides an efficient interface between the processor and the networked community

The basic feature set of the EMAC module is: • The EMAC supports both 10Base-T (10 Mbits/sec) and 100BaseTX (100 Mbits/sec), • Half or Full duplex • Hardware flow control and quality-of-service (QoS) support • EMAC acts as DMA master to either internal or external memory space • Standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) to physical layer device (PHY) • Includes MDIO module to communicate with PHY • Eight receive channels with VLAN tag discrimination for receive quality of service (QoS) support • Eight transmit channels with round-robin or fixed priority for transmit quality of service (QoS) support • Ether-Stats and 802.3-Stats statistics gathering • Transmit CRC generation selectable on a per channel basis Sitara MPU Day USB Subsystem • Two USB Controllers: − Single Port USB 2.0 OTG Controller with built in Phy (Port0): • Host (Low/Full/High Speed), Peripheral (Full/High Speed), OTG Support − Multiport (3) USB Host Controller (Port 1, 2, 3) • Host only • All 3 ports operate in either HS or FS mode (determined by selected PHY connection) • HS Mode − 480M bit/s − Available Port – 1 & 2 − PHY interface ULPI • FS Mode − 12M bit/s − Available Port – 1, 2, and 3 − PHY interface Serial Asynchronous Sitara MPU Day MMC/SD/SDIO

• 3 High Speed MMC/SD/SDIO Ports: − MMC1: 1.8/3.3V support 8bit (has integrated transceiver) − MMC2: 1.8/3.3V support 8bit w/o transceiver 4bit w/ external transceiver − MMC3 1.8/3.3V support 8bit w/o transceiver • Support: − 1-bit or 4-bit transfer mode specifications for SD and SDIO cards − 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards Sitara MPU Day AM35x Peripherals • System DMA − Transfers data between memories and peripherals with minimum CPU overhead. − Solid color fill & transparent color fill for image processing. − 96 Hardware synchronized transfer for data transfer from slower peripheral to memory or vise versa. − Chained multiple channel transfer − Endianism support. • Universal Asynchronous Receiver Transmitters (UART) − UART mode only (UART1, UART2, and UART4) − UART3: UART, IrDA (SIR, MIR, FIR) and CIR mode. − Supports baud rate up-to 3.6M bits/s. • Multi-Channel Buffered Serial Port (McBSP) − Data clock (up to 48MHz) − Each FIFO is 512 Byte (128 x 32-bit ) - McBSP 1, 3, 4, and 5 − Each FIFO is 5KB (1024 + 256) x 32-bit - McBSP 2 − I2S, PCM, TDM − SIDETONE core support: Audio loopback capability (McBSP2 & 3 only) Sitara MPU Day AM35x Peripherals • 12 GP Timers & 1 watchdog timer − Free-running 32-bit upward counter. Runs off 32KHz or 12, 13, 19.2, 26, or 38.4 MHz system clock. − WDT: MPU Watchdog (runs of 32KHz system clock) •I2C − 3 I2C ports compliant with Philips I2C specification version 2.1 − Support for standard (up to 100K bits/s) and fast (up to 400K bits/s) modes and HS mode for transfer up to 3.4 Mbits/s • General-Purpose I/O (GPIO) Interface − Synchronous interrupt requests in active mode from each channel are processed by interrupt generation submodule by the microprocessor unit (MPU) subsystems. − Asynchronous wake-up request • Multichannel Serial Port Interface − Data Clock 11.7 Kbps to 48 Mbps − Full duplex/half duplex − Power management through wakeup capability • 1 HDQ / 1-Wire Sitara MPU Day

Power Management Sitara MPU Day Power Management • AM35x power management features: − Single voltage and power domain − Multiple clock domains − 4 DPLLs − Single Operating Voltage and Frequency − Low power mode (standby) • Power, Reset and Clock Management (PRCM) module controls power management • AM35x does not support voltage and power domains. • One voltage supply to device processors and peripherals. • No support for switching power on or off to individual power domains. • Supports dynamic clock gating for power management through clock domains. − A clock domain is a group of modules or subsections of device that share a common clock − By gating the clock to each domain, it is possible to cut a clock to a group of inactive modules to lower their active power consumption. Sitara MPU Day Power Supply Characteristics

REGULATO VOLTAGE PARAMETER DESCRIPTION R TYPE RANGE VDD_CORE Core and oscillator macros power supply Ext. SMPS 1.2 V

VDD_SRAM_MPU MPU SLDO analog power supply Int. LDO 1.8 V Core SLDO and VDDA of BandGap analog VDDS_SRAM_CORE_BG Int. LDO 1.8 V power supply MPUSS DPLL and USBHOST DPLL analog VDDS_DPLL_MPU_USBHOST Int. LDO 1.8 V power supply DPLL and HSDIVIDER/ CORE and VDDS_DPLL_PER_CORE Int. LDO 1.8 V HSDIVIDER analog power supply VDDS 1.8V power supply. Ext. SMPS 1.8V VDDSHV 1.8/3.3V power supply. Ext. SMPS 1.8/3.3 V VDDA1P8V_USBPHY 1.8V USB transceiver power supply Ext. SMPS 1.8 V VDDA3P3V_USBPHY 3.3V USB transceiver analog power supply Ext. LDO 3.3 V VDDAC DAC analog power supply. Ext. LDO 1.8V Sitara MPU Day Operating & Standby Conditions

• AM35x supports Single Operating Voltage and Frequency

MPU Freq L3 Freq Voltage (V) (MHz) (MHz) 1.2 600 166

• AM35x also supports single standby mode. Conditions are: − All modules have clocks properly gated − DDR in self-refresh − Optimized IO config (Required for each board design) − DDR PHY in standby − USB PHY in standby Sitara MPU Day AM35x Power Measurement

Power Ambient Use case Measured Process Note Rails Temp

Dhrystone 472.6 mW VDD_CORE 25°C Strong MPU_CLK = 600 MHz

3D Graphics 407.8 mW VDD_CORE 25°C Strong Game Scene

DSS BW 318 MB/s, DMA BW 304 MB/s, Stress Test 488.2 mW VDD_CORE 25 C Strong ° USBOTG 10 MB/s

ARM is continuously executing a while loop ARM writes to 363.5 mW VDD_CORE 25 C Nominal in which it writes DDR2 locations one 32-bit DDR2 ° word at a time.

212.0 mW Other Rails

STDBY 1.8V IO 11.59 mW ALL 25°C Nominal VDDSHV = 1.8 V

STDBY 3.3V IO 15.45 mW ALL 25°C Nominal VDDSHV = 3.3 V Sitara MPU Day AM35x Power Options

TPS650732

Touchscreen Interface TPS65910

10-bit ADC 4 inputs

Integrated AC & USB RTC 32kHz Integration Battery Charger w/ DPPM

25mA wLED 10mA LED Drivers Driver Driver TPS65023

3 DCDC 3 DCDC Power 1x 5V Boost 3 DCDC 2 LDO 9 LDO 2 LDO

I2C 1 I2C 2 HS I2C 1 I2C Interface Sitara MPU Day

Package Sitara MPU Day Sitara MPU Day

Evaluation Module Sitara MPU Day Start development immediately with AM3517 evaluation module for $999 Hardware Software Connectivity TMDXEVM3517 includes • AM3517 Linux SDK • EMAC, USB PHY, USB • Touch screen LCD − Kernel 2.6.31 OTG & Host, CAN, SDIO, − U-boot I2C, JTAG, Keypad • Applications Board • Windows® Embedded CE • SD/MMC (2) • Base Board in 3Q10 • DVID/HDMI • AM3517 SOM • Multiple RTOS available −256MB DDR2 • Video input −512MB NAND • Bluetooth, WLAN

Base board + application board + LCD = TMDXEVM3517 Sitara MPU Day Processor Module

Wireless Module Power

AM35x

256MB DDR2 (64MBx32) • Ethernet Phy (Bottom) • Touch controller • Wireless 802.11 & Bluetooth • USB 2.0 HS Phy (Bottom)

512 MB NAND (256MBx16) Sitara MPU Day Experimenter Baseboard

A – SD/MMC card slot (on bottom of board) B – HDMI video port C – 60-pin header for integrated LCD, touch, backlight, connector power D – USB Type B port (serial debug) E – Three 100-pin board-to-board (BTB) socket connectors for SOM-M2 F – Three BTB expansion connectors for Application Board G – S-Video out port H – RJ45 Ethernet jack with magnetics I – USB On-the-Go mini-AB port J – USB host Type A port K – Boot mode / HDMI enable / IO voltage select DIP switches (S7) L – General purpose user DIP switches (S2) M– System reset button N – System user button O – Power on/off switch P – Power-in from 5 volt regulated power supply Q – DB9 serial debug port Sitara MPU Day Application Board Sitara MPU Day

Software & Tools Sitara MPU Day AM35x Software and Ecosystem

ARM Microprocessors

• Production quality Software Development Kit including: – Base port to multiple industry leading Operating Systems – Full peripheral driver library – Development kits for Linux and Windows® Embedded CE • Active Open Source community accompanied by the world’s largest ecosystem of 3rd Party tools and application specific solutions Sitara MPU Day Linux Stack

Customer Applications

Qt Embedded GStreamer QGLWidget QWidget

Customer Communication Protocols

FFMPEG, VisualOn, Ittiam Provided by OSS, 3P or OSS, 3P by Provided

OpenGL ES FBDEV V4L2 ALSA VISA McSPI Touch Ethernet screen

2DA (Neon) TVout CAN I2C Timers USB McBSP MMC/SD UART

DSS2

System on Chip Provided by TI Provided by

Target Board Sitara MPU Day 3rd Party ARM Codecs

Vendor Speech Codecs Audio Codecs

AAC-LC(E/D), AAC-HE(E/D), MP3(E/D), BSAC(D), FLAC(D), OGG VORBIS (D), WMA(E/D), Dolby-AC3 G.711 (E/D), G.726 (E/D), GSM- 5.1(E/D), WMA-Lossless (D),WMA-Pro LBR (D), MP2- Ittiam AMR NB (E/D) 5.1 (D),AAC-LC5.1 (E/D), WMA Pro 5.1 (E/D), Enhance AAC+ 5.1 (E/D) http://www.ittiam.com/pages/products/products.htm

AAC-LC(E/D), AAC-HE(E/D), MP3(E/D), BSAC(D), FLAC(D), OGG VORBIS (D), WMA(E/D), Dolby- Ingenient G.726(E/D), GSM-AMR WB+ (E/D) AC3(E/D) More Information: http://www.ingenient.com/multimedia_compression.html G.711 (E/D), G.722.1 (E/D), G.723.1A (E/D), G.726 (E/D), MP3 (D) CouthIT G.728 (E/D), G.729 AM (E/D), http://www.couthit.com/codecs.asp GSM-AMR NB, WB and WB+ (E/D), EVRC (E/D), ILBC (E/D) Sitara MPU Day 3rd parties ARM codec List

ARM Cortex A8 Video and Image Codecs

Vendor Video Codecs Image

DivX (D), H.263 Baseline (D), H.264 BP (E/D), H.264 MP (D), H.264 HP (D), Ittiam MPEG4 ASP (D), MPEG4 BP (E/D), JPEG (E/D) WMV9/VC1 BP/MP (D), MPEG2 (on request)

H.263 Baseline (D), H.264 BP (D), H.264 MP (D), MPEG4 SP/ASP (D), DivX,/xVID JPEG (E/D) (D), WMV SP/MP(D),MPEG2 (D), More Information: Visual ON SORENSON (D), ON2 (D), Real (D) http://www.visualon.com/english/Products/Visual Visual ON ALSO Support Audio/Speech Onsoftwarecodecs.htm decoders: AAC, AMR, WMA and MP3

• Check with each vendor to verify frameworks support. (e.g., TI Codec Engine, GStreamer, Direct Show, Open Core etc.) Sitara MPU Day Linux SW Dev Tool: CODESourcery Sourcery G++ • Complete software development environment based on the open-source Linux GNU Toolchain for ARM code development with broad adoption in the Linux community. • Includes the GNU C and C++ compilers and run-time libraries, a source- and assembly-level debugger Debugger, the Eclipse IDE, and many more tools designed for ARM platforms and Linux application development. Important Note • Sourcery G++ will be included in EVM Kits by TI and • Link will be provided to Code Sourcery web site from TI.com; Customers to choose Sourcery G++ SW Edition of choice.

Sourcery G++ Software Editions Lite Personal Professional 30-day Installation Support No Yes Yes Unlimited Support No No Yes Priority Defect Correction No No Yes Access to Updates, Knowledge Base No Yes Yes Big Endian, Neon support No No Yes GNU/Linux Application Simulator No Yes Yes GNU C/C++ Compiler Yes Yes Yes

GNU Debugger (GDB) Yes Yes Yes CONTACT: Eclipse IDE No Yes Yes Brian Barrera Annual Subscription Price per Host Free $399 $2799 [email protected] • Professional Edition: Designed for enterprise software development; including Extra run-time libraries • Personal Edition: Designed for individuals and small development teams; including access to updates and knowledge base • Lite Edition: Free, command line-only tools Sitara MPU Day More Linux Tool Support Options

Other Features and Tool Debug Compile link

TI Code Low Level DSP and Low-level ARM (ARMv7) and Power Aware Debug Composer Studio ARM DSP (NEON roadmap)

Application-level ARM (ARMv7, http://www.arm.com/produ ARM Real View Low Level ARM NEON) cts/DevTools/

Low Level and User Trace Green Hills level ARM debug and Low Level ARM http://www.ghs.com/produ DSP cts/arm_development.html

Low Level and User Extensive Trace support Lauterbach level ARM debug and None http://www.lauterbach.com DSP /frames.html Sitara MPU Day Commercial Linux Vendors

Vendor Capabilities Supported Contact Platforms Linux build tool with support for multiple kernel versions and OMAP3530, DM355, Charlie Ashton TimeSys middleware packages that enables OMAP-L137, DM6446, [email protected] users to easily customize OMAP-L138, AM 3517 distribution. Lower cost than MV and WRS MVL Pro 4 and 5 are distributions Scott Mullarkey based on frozen version of Linux OMAP3530, DM355, [email protected] kernel. MVL 6 is based on ‘GIT DM365, DM6446, Montavista Linux’ released by TI. Customized DM6467, OMAP-L137, distributions (mobilinux, carrier OMAP-L138, AM3517 grade) targeted at vertical (Montavista is now part of segments. Cavium Network)

Distributions based on frozen Michael Ling version of Linux kernel. ‘Frozen’ OMAP3530, DM355, [email protected] WindRiver kernel is updated every two years OMAP-L137, OMAP-L138, to later release. Customized AM 3517 distributions targeted at vertical segments (mobile, networking) (Windriver is now part of Intel) Sitara MPU Day Windows® Embedded CE SW Strategy Customers can obtain CE 6.0 • Download BSP from TI TI CE 6.0 BSP • Drivers, Application Framework, & Graphics Package (Where ever applicable) Applications from End Equipment Makers • Does NOT include any 3P ARM -based codecs Development Tools: Visual Studio 2005 and Platform Builder Support: Partners for BSP (some Hours FREE BSP support), Fee based Extended support. For Graphics and Multimedia development - TI Forums & Community Microsoft Framework Cost: BSP Download is Free*

TI Board Support Package (BSP) For Production Release *Microsoft Runtime Licenses for Commercial Shipments Once a customer is ready to bring an embedded system to market, they must acquire a runtime licenses and certificate of authenticity from a Microsoft Authorized Embedded Distributor • Applies to all silicon platforms • Cost of license will vary, based on volume of licenses Sitara MPU Day Windows Embedded CE - High-Level Working Model

OMAP35x-Now AM 3505/17 Plan

Windows CE WinCE 6.x R3 WinCE 6.x R3 Version

Development Tool Visual Studio 2005 Visual Studio 2005

Multimedia TI (DVSDK) 3P MM on Neon Development

Graphics TI Graphics SDK (for TI Graphics SDK Development AM3517)

V.6.13 (Beta is done) Software Schedule Beta – May 2010 V.6.14 – April 2010 Sitara MPU Day Windows Embedded CE System Integrators / Consulting

Vendor Contact Region Expertise/Services

Michael Tidwell TI Partner for BSP Development for OMAP35x. Supports BSQUARE Americas system integration needs for customers. Specific solution [email protected] are available for SD/MMC, Adobe Flash etc.

Michael Erickson US based embedded hardware and SW design company. Logic PD Americas Familiar with TI devices. Working with many OMAP35x [email protected] customers for WinCE system integration.

WinCE training, application and driver development. Based Europe Adeneo Yannick Chammmings in France. Working with many OMAP35x for system [email protected] Americas integration around WinCE. Have very good experience with mass market WinCE support (training and enablement).

Europe MPC Data Frank Breeze TI partner for WinCE BSP development for OMAP-L [email protected] Americas products. Have good knowledge about TI products.

Srinivas Panapakam India-based embedded HW and SW design company. [email protected] Familiar with TI devices, WinCE, and TI multimedia stack Mistral WW components. Developed WinCE 5.0 for TI on DM644x. Also developed WinCE 6.0 on DM644x and Support. Sitara MPU Day RTOS - Summary

• Available for purchase from commercial suppliers • Sales and Support is provided by the RTOS Supplier • TI works with RTOS supplier to enable their OS on TI platforms

Vendor OS Description Link Contact

Micro kernel based operating http://www.qnx.com/products Kroy Zeviar QNX Neutrino system. Support for different /neutrino_rtos/ product segments. [email protected]

Designed for reliability and Integrity http://www.ghs.com/products Joe Fabbre Green Hills security. Leader in security .html VelOSity applications. [email protected]

Established RTOS vendor. Part http://www.windriver.com/pro Lepine, Emery A (Joe) Wind River VxWorks of Intel now. ducts/vxworks/ [email protected] Nucleus is popular in wireless Mentor http://www.mentor.com/prod Nucleus handsets. Extending the same to Hank Andray Gaphics ucts/embedded_software/ [email protected] other markets also.

Express RTOS targeted at deeply John Carbone ThreadX http://www.rtos.com/ Logic embedded applications [email protected] Sitara MPU Day Where to get help

• TI E2E forums – http://e2e.ti.com – • Embedded Processor Wiki page: – http://wiki.omap.com/index.php/Main_Page

• Self Serve Collateral – http://ap-fpdsp-swapps.dal.design.ti.com/index.php/Self_serve_collateral

• OMAP Developer Series Videos (5 Parts) – http://focus.ti.com/docs/prod/folders/print/omap3530.html (or on YouTube)

• Online TrainingÆ www.ti.com/onlinetraining Sitara MPU Day Getting started with your AM3517 Experimenter Board • Start at TI Public Wiki – http://processors.wiki.ti.com/index.php/Main_Page

• AM35x Getting Started Guide: – http://processors.wiki.ti.com/index.php/AM35x_Getting_Started_Guide • AM35x Software Setup – http://processors.wiki.ti.com/index.php/GSG:_AM35x_EVM_Software_Setup • AM35x Hardware Setup – http://processors.wiki.ti.com/index.php/GSG:_AM35x_EVM_Hardware_Setup • AM3517 Online Workshop – http://processors.wiki.ti.com/index.php/AM3517_On-line_Workshop • Rotating Cube Demo: – http://processors.wiki.ti.com/index.php/AM3517_On-line_Workshop (Lab 4 p.0-25 specifies how to re-flash to cube demo)

• Workshops – 4-Day workshop • http://processors.wiki.ti.com/index.php/Hands- On_Training_for_TI_Embedded_Processors#OMAP.E2.84.A2.2FDaVinci.E2.84.A2.2FSitara.E2.84.A2_ System_Integration_using_Linux_Workshop – 1-Day Workshop • http://processors.wiki.ti.com/index.php/Hands- On_Training_for_TI_Embedded_Processors#Sitara.E2.84.A2_AM3517_One-Day_Workshop

• Displays – If customers want various displays from Logic, they can buy them through Arrow: • Logic PD 4.3” WQVGA Display Kit (LCD-4.3-WQVGA-10R): http://www.logicpd.com/products/display- kits/43-wqvga-display-kit • Other display options: http://www.logicpd.com/downloads/37/ Sitara MPU Day Why Sitara™ ARM® microprocessors

• Reduce system risks and accelerate time to market using standard and comprehensive ARM-based software development tools

Q&A Sitara MPU Day

Backup Featured AM18x Analog Attach *Please visit ti.com/processorpower for COMPLETESitara powerMPU solutionsDay

Best Performance Low Power Performance Value

DRV135 • Audio Balanced Driver DRV602 • 2 Vrms Line Driver with Adjustable Gain • SOIC • Low distortion of 0.0005% at • TSSOP Line Drivers f = 1kHz • DIRECTPATH™ Eliminates Pops and Output DC-Blocking Capacitors • 15V/μs Slew Rate • Low Noise and THD: SNR > 102dB

• Low Power Codec TLV320AIC3254 • Ultra Low Power Codec TLV320AIC36 TLV320AIC3107 • Single ended or fully • Mini-DSP w/ PowerTune™ • Mini-DSP w/ PowerTune™ Stereo Audio • QFN • QFN differential configuration • VFBGA • Adjustable Power vs. SNR . • Adjustable Power vs. SNR . Codecs • 97-dBa SNR DAC • 100DBa SNR Stereo DAC • DAC: 90dB @ 7.7mW -> 100dB @ 9.2mW • Sample rate of 8-96 kHz • 92dBa SNR Stereo ADC • ADC: 86dB @ 8.4mW -> 93dB @ 14.2mW • 2 Channel ADC PCM4222 • 2 channel ADC PCM1870A TLV320ADC3101 • 90 dB SNR • 2 Channel ADC • 124dBA SNR • HTQFP • DSBGA • 16-bit, 192kHz • VQFN • 92-dBA SNR Audio ADC • 24-bit, 216kHz • Pwr. Disp = 13mW • 16-bit, 8-96 kHz sampling rate • Av. Pwr @48kHz 305mW • Multiple Programmable • 17-mW Stereo Record @ 48kHz Functions TPA3123D2 TPA3100D2 TPA2016D2 • 25W Stereo ClassD Amp • 20W Stereo ClassD Amp Stereo Audio • HTSSOP • Operates 10V to 30V • HTQFP • Operates 10V to 26V • DSBGA • 1.7W Stereo ClassD Amplifier • 25-W/ch into 4-Ω load from • QFN • 92% Effncy. Eliminates • Sply. Current-3.5mA a 24-V Supply Need for Heat Sinks • 2.5 – 5.5V Power Supply Range • Precision Clock Generator CDCM7005-SP • LVPECL & LVCMOS PLL CDCM61004 CDCV304 • General Purpose Clock Buffer Clock Synthesizer • Low Jitter <1.5ps •Low Skew <100ps Clocking Devices • QFN • 1.8-V and 3.3-V Outputs • QFN • Input Xstal bypass mode • TSSOP • 4 Outputs up to 200MHz • 10LVPECL or 5 LVCMOS • Integrated PLL Loop • Output Enable Outputs • 43.75 --625MHz Output Freq. • Two Ref. Clock Inputs PCM1792 PCM1754 TLV320DAC32 • 132 dB SNR St. DAC • 106 dB SNR St. DAC • 95 dBA SNR St. DAC • SSOP • SSOP • 24 bit, 192 kHz • QFN Audio DAC • 24-bit, 192 kHz • 18-mW Stereo 48-kHz • Sampling Frequency of 10 • QSOP • Sampling Frequency of 5 • Playback 3.3-V Supply kHz to 200 kHz kHz to 200 kHz • 8 kHz to 96 kHz

REF50xx • Low Temperature Drift REF33xx (3ppm/°C (max)) • Low Supply Current: 3.9uA (typ) High Output Current: ±5mA • SOIC Voltage Ref • SOIC • High Acc: .05% max • Low Temperature Drift: 30ppm/°C (max) • MSOP • MSOP • High Initial Accuracy: ±0.15% (max) Featured AM18x Analog Attach *Please visit ti.com/processorpower for COMPLSitaraETE poMPUwer soluDaytions

Best Performance Low Power Performance Value

PGA2500 INA217 • Digitally Controlled • Low Noise, Low-Distortion, Instrumentation Amplifier Microphone • SSOP Microphone Pre-Amp • SOIC • Low THD+N: 0.004%@1kHz, G = 100; Low Noise:1.3nV/√Hz@1kHz Pre-Amp • Gain Range: 10 dB through • PDIP • Wide Bandwidth: 800kHz at G = 100; HIGH CMR: > 100dB 65 dB, 1dB Incm. • Gain Set with External Resistor

SRC4392 • 2 Channel SRC SRC4184 • 4 Channel SRC Sample Rate • Dynamic Range w/ -60dB Input (A-Weighted): 144 dB Typical • Dynamic Range -128dB • TQFP • TQFP Converter • Digital Audio Interface Transmitter w/ Sampling Rates up to 216 kHz • 1.8 or 3.3V Supply • Digital Audio Interface Receiver w. Sampling Rates up to 216 kHz • THD+N: −125dB

INA2137 INA134 • +/- 6dB Line Receiver • Single Channel Audio Differential Line Receivers • PDIP • PDIP Line Receivers • High Slew Rate: 14V/us • Low Distortion: 0.0005% at f = 1kHz: High Slew Rate: 14V/us • SOIC • SOIC • Settl.Time:3ms to 0.01% • Fast Settling Time: 3us to 0.01%: Low Quiescent Current: 2.9mA max

TPD4E001 TPD2E001 • 4-Channel ESD Protection • 2-Channel ESD Protection ESD Protection • DRY • SOT • Low 1.5-pF Input • Low 1-nA (MAX) Leakage Current ±15-kV Array Capacitance • DRL • 0.9-V to 5.5-V Supply-Voltage Range • QFN CC2525 CC2500 Low Power RF • Low Current (13.3 mA in • Wide Supply Range (2.0V – 3.8V) RX, 250 kBaud) 2.4 GHz RF • QFN • QFN • Low Current Consumption (27 mA in RX, 31 mA in TX @ 0 dBm) • Programmable data rate Transceiver • -87 dBm sensitivity (at 2 Mbps) from 1.2 to 500 kBaud

TPA6130A2 TPA6120A2 TPA6102A2 • 38mW Headphone Amp • Slew Rate -1300 V/μs • 50-mW Stereo Output Headphone • QFN • Pwr. Sply.Rnge 2.5-5.5V • DWP • 80 mW into 600 Ω From • SOIC • .75mA Supply Current a ±12-V Supply at • 50nA Shutdown Current Amplifiers • DSBGA • High PSRR - > 100 dB 0.00014% THD + N • MSOP • Fixed Gain (14 dB) • ESD Protection of 8 kV • 120 dB SNR

TMP102 Digital Temp • Low Quiescent Current – 10 uA (MAX) 12-bit Resolution Sensor • SOT • 10 uA (MAX) shutdown current Supply Range: 1.4V to 3.6V • Accuracy: 0.5°C (–25°C to +85°C Featured AM18x Analog Attach *Please visit ti.com/processorpower for COMPLSitaraETE poMPUwer soluDaytions

Best Performance Low Power Performance Value

ADS62P24 ADS901 ADS6123 • 125MSPS Dual ADC • 20 MSPS 10Bit ADC • 80MSPS Low Power ADC • 95dB Crosstalk • 318mW ADC • QFN • SSOP • Low Power 48mW • QFN • Digital Processing Block • Adjustable Full Scale • 12 Bit Resolution • 12 Bit Resolution Range with External Ref. • Parallel CMOS & DDR LVDS

THS7353 THS7313 • 3 Channel Video Amp • 3 Channel Low Power Video Amp, 16.6mA @ 3.3V Video • TSSOP • 5th Order Butterworth • TSSOP • Selectable Input Modes Rail to Rail Out Amplifier • External Gain Control • 5th Order Butterworth Filter • I2C Control • I2C Control

TVP5147 • Decoder with Macrovision TVP5150AM1 • Ultra Low Power Decoder TVP5146 • 4x10 Bit 30 MSPS ADCs • I2C Host Port Interface • Fully Differential Channels Analog Video • HTQFP • QFN • Macrovision • 2 30MSPS ADC • TQFP • Macrovision Codecs • Power Down Control • Programmable Gain Amp. • Cross-Chrominannce Noise Reduction • I2C Host Port Interface • Supports NTSC PAL, and • Locks to weak, noisy, or unstable signal more

TRS3243E • Multichannel RS-232 TRSF3232E • 2-Channel RS-232 TRSF3221E • Single Channel RS-232 • QFN • Single Chip Interface • 1Mbit /s • 1Mbit/s RS-232 Line • SOIC • TSSOP • Hardware Flow Control and • Exceeds 100mA/JESD 78, • Auto-Powerdown Driver/Receiver • SOIC Modem Control Capabilities • TSSOP Class II • TSSOP • Accepts 5V Logic Input with • Always Active Non Inverting • SSOP • Hardware Flow Control only a 3.3V Supply • SSOP Receiver Output Capabilities

DAC2904 • 125MSP 14 Dual DAC DAC2932 • 40MSPS Dual 12 Bit DAC THS5661A • 125MSPS 12 Bit DAC • Low Power 310mW • Ultra Low Power @ 29mW • Low Power @ 175mW • TQFP • TQFP • SOIC Low Glitch: 2pVs • High SFDR at 75dB • Internal Reference DAC • TSSOP • Internal Reference • Internal Reference • Differential Scalable Current Outputs

There is usually an FPGA or other form of digital isolation between the High Speed A/D converter and the processor. Sitara MPU Day Power Options for AM18x *Please visit ti.com/processorpower for COMPLETE power solutions

Simplest Solution High Vin High Efficiency 5V High Efficiency

DC/DC Integrated Power Discrete DC/DC Discrete DC/DC Converter Solution Converter and LDO and LDO Power Solution Power Solution

TPS62353 VIN: 5V VIN: 3.3V VIN: 4.5V- 17V TPS62111 800mA 1.5A 3.3V @ 115mA DCDC Converter 1.2V @ 600mA with I2C TPS74801 1.2V @ 600mA DCDC Converter PG 2 1.5A LDO EN I C EN PG VIN: 3.3V

EN SYNC EN TPS62353 EN 1.2V @ 600mA TPS62232 800mA With I2C 800mA 1.2V @ 251mA DCDC Converter DCDC Converter TPS74701 2 1.2V @ 251mA I C 500mA LDO PG

EN EN TPS62232 EN 1.8V @ 230mA 500mA 1.2V @ 251mA TPS71718 TPS62231 150mA LDO DCDC Converter 500mA 1.8V @ 230mA DCDC Converter

EN PG EN TPS62231 1.8V @ 230mA TPS74801 3.3V @ 115mA 500mA EN 1.5A LDO DCDC Converter TPS71733 3.3V @ 115mA 150mA LDO

• Highly customizable PCB layout and • Offers flexibility of layout • 3.3V Input device placement • 2.25MHz for Small Inductors • No Inductors Required! • 2.25MHz for Small Inductors • Small SON & SOT-23 packaging • Chip-scale packaging available for • Chip-scale packaging available for TPS62353 TPS62353

Full Design Document: SLVA342 Full Design Document: SLVA339 Full Design Document: SLVA341 Sitara MPU Day Power Options for AM18x *Please visit ti.com/processorpower for COMPLETE power solutions

Medium Integration High Integration Highest Integration

Dual DCDC Converter & DC/DC and LDO Integrated DC/DC and LDO Integrated LDO Power Solution Power Solution Power Solution

RESET VIN:1.3V or 3.3V DC_OUT1 TPS3805 VIN: 3.3V 1.2V @ 600mA Voltage Detector TPS62420 1.2V @ 251mA DC_OUT3 Dual 600mA 1.2V @ 251mA DCDC Converter DC_OUT2 1.2V @ 600mA 1.8V @ 230mA OUT2 VIN: 5.0V LDO_EN EN2 3.3V OUT1 1.8V @ 230mA DC_OUT1 DC_OUT2 3.3V or 1.8V DC_OUT3 1.2V TPS65023 EN1-DCDC Three Step-Down Converters USB EN Two 200 mA LDO TPS65070 VIN: 2.8V – 6.3V TPS71733 3.3V @ 115mA 800mA 150mA LDO Single Chip Solution DCDC Converter & LDO DCDC-EN1 I2C DCDC-EN2 LDO_OUT1 3.3V @ 115mA PG DCDC-EN3 LDO_OUT2 I2C EN2-DCDC LDO_OUT1 1.8V EN3-DCDC LDO_OUT2 1.2V

• Dual Output reduces board space • 5 Outputs: 2 LDOs & 3 Converters • 5 Outputs: 3 Converters & 2 LDOs • Battery Charging Capabilities using USB • Power Safe mode for Light Load • Light Load Capabilities Efficiency • 2.25MHz for Small Inductors • 2.25MHz for Small Inductors • I2C Interface for PWM Control • 2.25MHz for Small Inductors • I2C Interface for PWM Control • Light Load Capabilities

Full Design Document: SLVA343 Full Design Document: SLVA340 Full Design Document: TBA Sitara MPU Day

Best Performance Low Power Performance Value

PGA2500 INA217 • Low Noise, Low-Distortion, Instrumentation Amplifier • SSOP • Digitally Controlled • SOIC Microphone Microphone Pre-Amp • Low THD+N: 0.004%@1kHz, G = 100; Low Noise:1.3nV/√Hz@1kHz Amplifier • Gain Range: 10 dB through • PDIP • Wide Bandwidth: 800kHz at G = 100; HIGH CMR: > 100dB 65 dB, 1dB Incm. • Gain Set with External Resistor

SRC4392 • 2 Channel SRC SRC4184 • 4 Channel SRC • Dynamic Range w/ -60dB Input (A-Weighted): 144 dB Typical • Dynamic Range -128dB Sample Rate • TQFP • TQFP Converter • Digital Audio Interface Transmitter w/ Sampling Rates up to 216 kHz • 1.8 or 3.3V Supply • Digital Audio Interface Receiver w. Sampling Rates up to 216 kHz • THD+N: −125dB

INA2137 INA134 • +/- 6dB Line Receiver • Single Channel Audio Differential Line Receivers • PDIP • PDIP Line • High Slew Rate: 14V/us • Low Distortion: 0.0005% at f = 1kHz: High Slew Rate: 14V/us • SOIC • SOIC Receivers • Settl.Time:3ms to 0.01% • Fast Settling Time: 3us to 0.01%: Low Quiescent Current: 2.9mA max

TPD4E001 TPD2E001 • 2-Channel ESD Protection ESD Protection • 4-Channel ESD Protection • DRY • SOT • Low 1-nA (MAX) Leakage Current ±15-kV Array • Low 1.5-pF Input Capacitance • DRL • 0.9-V to 5.5-V Supply-Voltage Range • QFN CC2525 CC2500 Low Power RF • Wide Supply Range (2.0V – 3.8V) • Low Current (13.3 mA in RX, 2.4 GHz RF • QFN • Low Current Consumption (27 mA in RX, 31 mA in TX @ 0 dBm) • QFN 250 kBaud) • -87 dBm sensitivity (at 2 Mbps) • Programmable data rate from Transceiver 1.2 to 500 kBaud

TPA6130A2 TPA6120A2 TPA6102A2 • 138mW Headphone Amp • Slew Rate -1300 V/μs • 50-mW Stero Output Headphone • QFN • Pwr. Sply.Rnge 2.5-5.5V • DWP • 80 mW into 600 Ω From a • SOIC • .75mA Supply Current • High PSRR - > 100 dB ±12-V Supply at 0.00014% • 50nA Shutdown Current Amplifier • DSBGA THD + N • MSOP • ESD Protection of 8 kV • Fixed Gain (14 dB) • 120 dB SNR

TMP102 Digital Temp • Low Quiescent Current – 10 uA (MAX) 12-bit Resolution • SOT Sensor • 1 uA (MAX) shutdown current Supply Range: 1.4V to 3.6V Accuracy: 0.5°C (–25°C to +85°C Sitara MPU Day Power Options for AM17x *Please visit ti.com/processorpower for COMPLETE power solutions

Simplest Solution Highest Flexibility LDO Power Solution Discrete DCDC + LDO

• 3.6V – 5.5V Input • Highly customizable PCB layout and device • No Inductors Required placement • Small SON & SOT-23 • 3MHz for Small Inductors packaging • Chip-scale packaging available for TPS62353

Full Design Document: Full Design Document: SLVR343 SLUA491

High Efficiency, Highest Integration Low Part Count PMIC + LDO Dual DCDC + LDO

• Dual Output reduces board • 3 DCDC + 2 LDO’s allows space flexibility and small board space • Power Safe mode for Light Load Efficiency • Up to 95% efficiency • 2.25MHz for Small Inductors • PFM mode for Light Load Efficiency

Full Design Document: Full Design Document: SLVR344 LINK