MAX9777/MAX9778 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input

19-0509; Rev 0; 4/06

Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

General Description Features MAX9777/MAX9778 The MAX9777/MAX9778 combine a stereo 3W bridge- ♦ Industry-Leading, Ultra-High 100dB PSRR tied load (BTL) audio power amplifier, stereo single- ♦ 3W BTL Stereo Speaker Amplifier ended (SE) headphone amplifier, headphone sensing, ♦ 200mW Stereo Headphone Amplifier and a 2:1 input multiplexer all in a tiny 28-pin thin QFN package. These devices operate from a single 4.5V to ♦ Low 0.002% THD+N 5.5V supply and feature an industry-leading 100dB ♦ Click-and-Pop Suppression PSRR, allowing these devices to operate from noisy ♦ ESD-Protected Outputs supplies without the addition of a linear regulator. An ♦ ultra-low 0.002% THD+N ensures clean, low-distortion Low Quiescent Current: 13mA amplification of the audio signal. Click-and-pop sup- ♦ Low-Power Shutdown Mode: 10µA pression minimizes audible transients on power and ♦ MUTE Function shutdown cycles. Power-saving features include low ♦ Headphone Sense Input 4mV V (minimizes DC current drain through the OS ♦ speakers), low 13mA supply current, and a 10µA shut- Stereo 2:1 Input Multiplexer down mode. A MUTE function allows the outputs to be ♦ Optional 2-Wire, I2C-Compatible or Parallel quickly enabled or disabled. Interface A headphone sense input detects the presence of a ♦ Tiny 28-Pin Thin QFN (5mm x 5mm x 0.8mm) headphone jack and automatically configures the Package amplifiers for either speaker or headphone mode. In speaker mode, the amplifiers can deliver up to 3W of Ordering Information continuous average power into a 3 load. In head- Ω CONTROL PIN- PKG phone mode, the amplifier can deliver up to 200mW of PART INTERFACE PACKAGE C OD E continuous average power into a 16Ω load. The gain of the amplifiers is externally set, allowing maximum flexi- MAX9777ETI+ I2C Compatible 28 Thin QFN- EP * T2855-6 bility in optimizing output levels for a given load. The MAX9778ETI+ Parallel 28 Thi n QFN -E P * T2855-6 amplifiers also feature a 2:1 input multiplexer, allowing Note: All devices are specified over the -40°C to +85°C operat- multiple audio sources to be selected. The multiplexer ing temperature range. can also be used to compensate for limitations in the +Denotes lead-free package. frequency response of the loud speakers by selecting *EP = Exposed paddle. an external equalizer network. The various functions are 2 Pin Configurations and Functional Diagrams appear at end controlled by either an I C-compatible (MAX9777) or of data sheet. simple parallel control interface (MAX9778). The MAX9777/MAX9778 are available in a thermally Simplified Block Diagram efficient 28-pin thin QFN package (5mm x 5mm x 0.8mm). These devices have thermal-overload protec- SINGLE SUPPLY 4.5V TO 5.5V tion (OVP) and are specified over the extended -40°C to +85°C temperature range.

LEFT IN1

Applications LEFT IN2

Notebooks PC Audio Peripherals SE/ BTL Portable DVD Players Camcorders RIGHT IN1 Tablet PCs Multimedia Monitor RIGHT IN2

CONTROL I2C- COMPATIBLE

MAX9777

______Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

ABSOLUTE MAXIMUM RATINGS VDD to GND ...... +6V Continuous Power Dissipation (TA = +70°C) PVDD to VDD ...... ±0.3V 28-Pin TQFN, Multilayer Board PGND to GND...... ±0.3V (derate 34.5mW/°C above +70°C)...... 2758.6mW All Other Pins to GND...... -0.3V to (VDD + 0.3V) Operating Temperature Range ...... -40°C to +85°C Continuous Input Current (into any pin except power-supply Storage Temperature Range ...... -65°C to +150°C and output pins) ...... ±20mA Junction Temperature...... +150°C OUT__ Short Circuit to GND, VDD ...... 10s Lead Temperature (soldering, 10s) ...... +300°C Short Circuit Between OUT_+ and OUT_- ...... Continuous

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MAX9777/MAX9778 Supply Voltage Range VDD/PVDD Inferred from PSRR test 4.5 5.5 V Quiescent Supply Current BTL mode, HPS = 0V, MAX9777/MAX9778 13 32 IDD mA (IVDD + IPVDD) Single-ended mode, HPS = VDD 718

Shutdown Current I SHDN SHDN = GND 10 50 µA Switching Time tSW Gain or input switching 10 µs CBIAS = 1µF 300 Turn-On Time tON ms CBIAS = 0.1µF 30 Thermal Shutdown Threshold +160 oC Thermal Shutdown Hysteresis 15 oC OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)

Output Offset Voltage VOS OUT_+ - OUT_-, AV = 1V/V ±4 ±32 mV VDD = 4.5V to 5.5V 75 100 Power-Supply Rejection Ratio PSRR f = 1kHz, V = 200mV 82 dB (Note 2) RIPPLE P-P f = 20kHz, VRIPPLE = 200mVP-P 70 Ω fIN = 1kHz, RL = 8 1.4 Output Power POUT THD+N < 1%, RL = 4Ω 2.6 W TA = +25°C RL = 3Ω 3 Total Harmonic Distortion Plus f = 1kHz, BW = POUT = 1W, RL = 8Ω 0.005 THD+N IN % Noise 22Hz to 22kHz POUT = 2W, RL = 4Ω 0.01 Signal-to-Noise Ratio SNR RL = 8Ω, POUT = 1W, BW = 22Hz to 22kHz 95 dB Slew Rate SR 1.6 V/µs

Maximum Capacitive Load Drive CL No sustained oscillations 1 nF Crosstalk fIN = 10kHz 73 dB Peak voltage, A-weighted, Into shutdown -50 Click/Pop Level KCP 32 samples per second dBV (Notes 2, 6) Out of shutdown -65

2 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

ELECTRICAL CHARACTERISTICS (continued) MAX9777/MAX9778 (VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = VDD) VDD = 4.5V to 5.5V 75 106 Power-Supply Rejection Ratio PSRR f = 1kHz, V = 200mV 88 dB (Note 2) RIPPLE P-P f = 20kHz, VRIPPLE = 200mVP-P 76 Ω fIN = 1kHz, THD+N < RL = 32 88 Output Power POUT mW 1%, TA = +25°C RL = 16Ω 200

POUT = 60mW, Ω 0.002 Total Harmonic Distortion Plus f = 1kHz, RL = 32 THD+N IN % Noise BW = 22Hz to 22kHz P = 125mW, OUT 0.002 RL = 16Ω R = 32Ω, BW = 22Hz to 22kHz, Signal-to-Noise Ratio SNR L 92 dB VOUT = 1VRMS Slew Rate SR 1.8 V/µs Maximum Capacitive Load Drive CL No sustained oscillations 2 nF Crosstalk fIN = 10kHz 78 dB BIAS VOLTAGE (BIAS)

BIAS Voltage VBIAS 2.35 2.5 2.65 V Output Resistance RBIAS 50 kΩ DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN1/2) Input-Voltage High VIH 2V Input-Voltage Low VIL 0.8 V Input Leakage Current IIN ±1µA HEADPHONE SENSE INPUT (HPS) 0.9 x Input-Voltage High VIH V VDD 0.7 x Input-Voltage Low VIL V VDD

Input Leakage Current IIN ±1µA Peak voltage, A-weighted, Into shutdown -70 Click/Pop Level KCP 32 samples per second dBV (Notes 2, 4) Out of shutdown -52

______3 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

ELECTRICAL CHARACTERISTICS (continued) (VDD = PVDD = 5.0V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, RIN = RF = 15kΩ, RL = ∞. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9777) Input-Voltage High VIH 2.6 V Input-Voltage Low VIL 0.8 V Input Hysteresis 0.2 V

Input High Leakage Current IIH VIN = 5V ±1µA Input Low Leakage Current IIL VIN = 0V ±1µA Input Capacitance CIN 10 pF Output-Voltage Low VOL IOL = 3mA 0.4 V Output Current High IOH VOH = 5V 1 µA TIMING CHARACTERISTICS (MAX9777)

Serial Clock Frequency fSCL 400 kHz MAX9777/MAX9778 Bus Free Time Between STOP t 1.3 µs and START Conditions BUF

START Condition Hold Time tHD:STA 0.6 µs START Condition Setup Time tSU:STA 0.6 µs Clock Period Low tLOW 1.3 µs Clock Period High tHIGH 0.6 µs Data Setup Time tSU:DAT 100 ns Data Hold Time tHD:DAT (Note 3) 0 0.9 µs 20 + Receive SCL/SDA Rise Time tr (Note 4) 300 ns 0.1CB 20 + Receive SCL/SDA Fall Time tf (Note 4) 300 ns 0.1CB 20 + Transmit SDA Fall Time tf (Note 4) 250 ns 0.1CB Pulse Width of Suppressed tSP (Note 5) 50 ns Spike

Note 1: All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design. Note 2: Inputs AC-coupled to GND. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling edge. Note 4: CB = total capacitance of one of the bus lines in picofarads. Device tested with CB = 400pF. 1kΩ pullup resistors connected from SDA/SCL to VDD. Note 5: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns. Note 6: Headphone mode testing performed with 32Ω resistive load connected to GND. Speaker mode testing performed with 8Ω resistive load connected to GND. Mode transitions are controlled by SHDN. KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1VRMS]. Units are expressed in dBV.

4 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics MAX9777/MAX9778 (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) vs. FREQUENCY (SPEAKER MODE) vs. FREQUENCY (SPEAKER MODE) 1 1 1 RL = 3Ω RL = 4Ω RL = 3Ω AV = 4V/V AV = 2V/V AV = 2V/V MAX9777/78 toc03 MAX9777/78 toc02 MAX9777/78 toc01

0.1 0.1 0.1 POUT = 500mW POUT = 1W POUT = 500mW POUT = 1W P = 250mW OUT POUT = 500mW THD+N (%) THD+N (%) THD+N (%) 0.01 0.01 0.01 P = 2.5W P = 2W OUT POUT = 2W POUT = 2.5W OUT P = 2W POUT = 1W OUT

0.001 0.001 0.001 10100 1k 10k 100k 10100 1k 10k 100k 10100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (SPEAKER MODE) vs. FREQUENCY (SPEAKER MODE) vs. FREQUENCY (SPEAKER MODE) 1 1 1 RL = 4Ω RL = 8Ω RL = 8Ω AV = 4V/V AV = 2V/V AV = 4V/V MAX9777/78 toc05 MAX9777/78 toc06 MAX9777/78 toc04

0.1 0.1 0.1

POUT = 250mW POUT = 500mW POUT = 250mW POUT = 500mW POUT = 250mW THD+N (%) THD+N (%) THD+N (%) POUT = 500mW 0.01 0.01 0.01

POUT = 2W POUT = 1W POUT = 1.2W P = 1.2W POUT = 1W POUT = 1W OUT 0.001 0.001 0.001 10100 1k 10k 100k 10100 1k 10k 100k 10100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) vs. OUTPUT POWER (SPEAKER MODE) vs. OUTPUT POWER (SPEAKER MODE) 100 100 100 AV = 2V/V AV = 4V/V AV = 2V/V Ω RL = 3Ω RL = 3 RL = 4Ω 10 10 10 MAX9777/78 toc09 MAX9777/78 toc07 MAX9777/78 toc08

1 1 f = 10kHz 1 f = 1kHz

f = 10kHz THD+N (%) THD+N (%) 0.1 THD+N (%) 0.1 0.1 f = 10kHz f = 20Hz f = 1kHz

0.01 0.01 0.01 f = 1kHz f = 20Hz f = 20Hz

0.001 0.001 0.001 041 2 3 041 2 3 00.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W)

______5 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics (continued) (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (SPEAKER MODE) vs. OUTPUT POWER (SPEAKER MODE) vs. OUTPUT POWER (SPEAKER MODE) 100 100 100 AV = 4V/V AV = 2V/V AV = 4V/V Ω Ω RL = 4 RL = 8 RL = 8Ω 10 10 10 MAX9777/78 toc10 MAX9777/78 toc11 MAX9777/78 toc12

f = 10kHz 1 1 1 f = 10kHz f = 1kHz f = 10kHz THD+N (%) THD+N (%) 0.1 0.1 THD+N (%) 0.1 f = 1kHz f = 1kHz 0.01 0.01 0.01 f = 20Hz f = 20Hz f = 20Hz 0.001 0.001 0.001 00.5 1.0 1.5 2.0 2.5 3.0 3.5 00.5 1.0 1.5 2.0 00.5 1.0 1.5 2.0 MAX9777/MAX9778 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W)

OUTPUT POWER vs. AMBIENT TEMPERATURE OUTPUT POWER vs. AMBIENT TEMPERATURE OUTPUT POWER vs. AMBIENT TEMPERATURE (SPEAKER MODE) (SPEAKER MODE) (SPEAKER MODE) 4 4 2.0 THD+N = 10% THD+N = 10%

THD+N = 10% MAX9777/78 toc14 MAX9777/78 toc15 3 MAX9777/78 toc13 3 1.5 THD+N = 1% THD+N = 1% THD+N = 1% 2 2 1.0 OUTPUT POWER (W) OUTPUT POWER (W) OUTPUT POWER (W) 1 1 0.5 f = 1kHz f = 1kHz f = 1kHz Ω RL = 3Ω RL = 4 RL = 8Ω 0 0 0 -40-15 10 35 60 85 -40-15 10 35 60 85 -40-15 10 35 60 85 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)

OUTPUT POWER vs. LOAD RESISTANCE POWER DISSIPATION vs. OUTPUT POWER (SPEAKER MODE) (SPEAKER MODE) 5 1.6 f = 1kHz 1.4 4 THD+N = 10% MAX9777/78 toc17 MAX9777/78 toc16 1.2

1.0 3 0.8 THD+N = 1% 2 0.6 OUTPUT POWER (W)

POWER DISSIPATION (W) 0.4 1 0.2 RL = 4Ω f = 1kHz 0 0 110 100 1k 10k 100k 0 0.5 1.0 1.5 2.0 2.5 LOAD RESISTANCE (Ω) OUTPUT POWER (W)

6 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics (continued) MAX9777/MAX9778 (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

POWER-SUPPLY REJECTION RATIO CROSSTALK vs. FREQUENCY vs. FREQUENCY (SPEAKER MODE) (SPEAKER MODE) 40 -40 VRIPPLE = 200mVP-P VIN = 200mVP-P -50 RL = 8Ω 50 MAX9777/78 toc18 -60 MAX9777/78 toc19 60 -70 RIGHT TO LEFT 70 -80 PSRR (dB) -90 80 CROSSTALK (dB) -100 90 LEFT TO RIGHT -110

100 -120 10100 1k 10k 100k 10100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz)

ENTERING SHUTDOWN (SPEAKER MODE) EXITING SHUTDOWN (SPEAKER MODE) MAX9777/78 toc20 MAX9777/78 toc21

VDD SHDN 2V/div 2V/div

OUT_+ AND OUT_- OUT_+ AND OUT_- 1V/div 1V/div

OUT_+ - OUT_- 200mV/div OUT_+ - OUT_- 500mV/div

400ms/div 100ms/div

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) vs. FREQUENCY (HEADPHONE MODE) 1 1 RL = 16Ω RL = 16Ω AV = 1V/V AV = 2V/V MAX9777/78 toc23 0.1 MAX9777/78 toc22 0.1

POUT = 25mW POUT = 50mW POUT = 25mW 0.01 POUT = 50mW 0.01 THD+N (%) THD+N (%)

0.001 0.001 POUT = 100mW POUT = 150mW POUT = 100mW POUT = 150mW

0.0001 0.0001 10100 1k 10k 100k 10100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz)

______7 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics (continued) (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (HEADPHONE MODE) vs. FREQUENCY (HEADPHONE MODE) vs. OUTPUT POWER (HEADPHONE MODE) 1 1 100 Ω RL = 32Ω RL = 32 AV = 1V/V A = 2V/V R = 16Ω AV = 1V/V V 10 L MAX9777/78 toc26 MAX9777/78 toc24 0.1 0.1 MAX9777/78 toc25 1 POUT = 25mW POUT = 50mW P = 25mW f = 20Hz OUT P = 50mW f = 10kHz 0.01 OUT 0.01 0.1 THD+N (%) THD+N (%) THD+N (%) 0.01 0.001 0.001 POUT = 100mW POUT = 150mW POUT = 100mW 0.001 POUT = 150mW f = 1kHz 0.0001 0.0001 0.0001 10100 1k 10k 100k 10100 1k 10k 100k 050 100 150 200 250 300 MAX9777/MAX9778 FREQUENCY (Hz) FREQUENCY (Hz) OUTPUT POWER (mW)

TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (HEADPHONE MODE) vs. OUTPUT POWER (HEADPHONE MODE) vs. OUTPUT POWER (HEADPHONE MODE) 100 100 100 AV = 2V/V AV = 1V/V AV = 2V/V R = 16Ω RL = 32Ω RL = 32Ω 10 L 10 10 MAX9777/78 toc29 MAX9777/78 toc27 MAX9777/78 toc28 f = 1kHz 1 1 1 f = 10kHz f = 10kHz f = 10kHz 0.1 0.1 0.1 f = 20Hz f = 20Hz THD+N (%) THD+N (%) THD+N (%) f = 20Hz 0.01 0.01 0.01

0.001 f = 1kHz 0.001 0.001

f = 1kHz 0.0001 0.0001 0.0001 050 100 150 200 250 300 025 50 75 100 125 025 50 75 100 125 OUTPUT POWER (mW) OUTPUT POWER (mW) OUTPUT POWER (mW)

OUTPUT POWER vs. AMBIENT TEMPERATURE OUTPUT POWER vs. AMBIENT TEMPERATURE OUTPUT POWER vs. LOAD RESISTANCE (HEADPHONE MODE) (HEADPHONE MODE) (HEADPHONE MODE) 300 150 600 f = 1kHz THD+N = 10% 250 125 THD+N = 10% 500 MAX9777/78 toc32 MAX9777/78 toc30 MAX9777/78 toc331 200 100 400 THD+N = 10% THD+N = 1% THD+N = 1% 150 75 300

100 50 200 THD+N = 1% OUTPUT POWER (mW) OUTPUT POWER (mW) OUTPUT POWER (mW)

25 100 50 f = 1kHz f = 1kHz Ω RL = 16Ω RL = 32 0 0 0 -40-15 10 35 60 85 -40-15 10 35 60 85 110 100 1k 10k AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) LOAD RESISTANCE (Ω)

8 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics (continued) MAX9777/MAX9778 (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

POWER DISSIPATION vs. OUTPUT POWER POWER DISSIPATION vs. OUTPUT POWER POWER-SUPPLY REJECTION RATIO (HEADPHONE MODE) (HEADPHONE MODE) vs. FREQUENCY (HEADPHONE MODE) 120 70 40 VRIPPLE = 200mVP-P 60 100 50 MAX9777/78 toc34 MAX9777/78 toc35 MAX9777/78 toc33 50 80 60 40 60 70

30 PSRR (dB) 40 80 20 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 90 20 10 R = 32Ω RL = 16Ω L f = 1kHz f = 1kHz 0 0 100 0 50 100 150 200 0 20 40 60 80 100 10100 1k 10k 100k OUTPUT POWER (mW) OUTPUT POWER (mW) FREQUENCY (Hz)

CROSSTALK vs. FREQUENCY (HEADPHONE MODE) EXITING SHUTDOWN (HEADPHONE MODE) -40 MAX9777/78 toc37 VIN = 200mVP-P -50 RL = 16Ω SHDN -60 MAX9777/78 toc36 2V/div

-70

-80 RIGHT TO LEFT OUT_+ -90 CROSSTALK (dB) 1V/div -100

-110 LEFT TO RIGHT HP JACK 200mV/div -120 10100 1k 10k 100k 100ms/div RL = 16Ω FREQUENCY (Hz) INPUT AC-COUPLED TO GND

SUPPLY CURRENT vs. SUPPLY VOLTAGE ENTERING SHUTDOWN (HEADPHONE MODE) (SPEAKER MODE) MAX9777/78 toc38 25

TA = +85°C SHDN 20 2V/div MAX9777/78 toc39

15 TA = +25°C

OUT_+ 1V/div 10

SUPPLY CURRENT (mA) TA = -40°C 5 HP JACK 100mV/div 0 100ms/div 4.504.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V)

______9 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Operating Characteristics (continued) (VDD = PVDD = 5V, GND = PGND = 0V, VSHDN = 5V, CBIAS = 1µF, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE (HEADPHONE MODE) (HEADPHONE MODE) 12 12

10 10 MAX9777/78 toc40 ° MAX9777/78 toc40 TA = +85 C TA = +85°C 8 8

6 6 ° TA = +25 C TA = +25°C 4 4 SUPPLY CURRENT (mA) ° SUPPLY CURRENT (mA) TA = -40 C TA = -40°C 2 2

MAX9777/MAX9778 0 0 4.504.75 5.00 5.25 5.50 4.504.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

POWER DISSIPATION vs. OUTPUT POWER EXITING POWER-DOWN (SPEAKER MODE) (SPEAKER MODE) 0.8 MAX9777/78 toc43

0.7 VDD 0.6 MAX9777/78 toc42 2V/div

0.5

0.4 OUT_+ AND OUT_- 0.3 1V/div

POWER DISSIPATION (W) 0.2 Ω 0.1 RL = 8 OUT_+ - OUT_- f = 1kHz 1V/div 0 0 0.25 0.50 0.75 1.00 1.25 1.50 100ms/div OUTPUT POWER (W)

10 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Pin Description MAX9777/MAX9778

PIN NAME FUNCTION MAX9777 MAX9778 1 — SDA Serial Data I/O 2—INT Interrupt Output

3, 4 3, 4 VDD Power-Supply Input 5 5 INL1 Left-Channel Input 1 6 6 INL2 Left-Channel Input 2 7 7 GAINLA Left-Channel Gain Set A 8 8 GAINLB Left-Channel Gain Set B 9, 13, 23, 27 9, 13, 23, 27 PGND Power Ground. Connect to GND. Left-Channel Bridged Amplifier Positive Output. OUTL+ also serves as the 10 10 OUTL+ left-channel headphone amplifier output.

11, 25 11, 25 PVDD Output Amplifier Power Supply 12 12 OUTL- Left-Channel Bridged Amplifier Negative Output

14 14 SHDN Active-Low Shutdown Input. Connect SHDN to VDD for normal operation. Address Select. A logic-high sets the address LSB to 1, a logic-low sets the 15 — ADD address LSB to zero. Headphone Sense Input. A logic-high configures the device as a single- 16 16 HPS ended headphone amp. A logic-low configures the device as a BTL speaker amp. DC Bias Bypass Terminal. See the BIAS Capacitor section for capacitor 17 17 BIAS selection. Connect CBIAS from BIAS to GND. 18 18 GND Ground. Connect to PGND. 19 19 INR1 Right-Channel Input 1 20 20 INR2 Right-Channel Input 2 21 21 GAINRA Right-Channel Gain Set A 22 22 GAINRB Right-Channel Gain Set B Right-Channel Bridged Amplifier Positive Output. OUTR+ also serves as the 24 24 OUTR+ right-channel headphone amplifier output.

26 26 OUTR- Right-Channel Bridged Amplifier Negative Output 28 — SCL Serial Clock Line — 1 MUTE Active-High Mute Input Headphone Enable. A logic-high enables HPS. A logic-low disables HPS — 2 HPS_EN and the device is always configured as a BTL speaker amplifier. Gain Select. A logic-low selects the gain set by GAIN_A. A logic-high — 15 GAINA/B selects the gain set by GAIN_B. Input Select. A logic-low selects amplifier input 1. A logic-high selects —28IN1/2 amplifier input 2. EP EP EP Exposed Paddle. Connect to GND.

______11 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Detailed Description Input Multiplexer Each amplifier features a 2:1 input multiplexer, allowing The MAX9777/MAX9778 feature 3W BTL speaker input selection between two stereo sources. Both multi- amplifiers, 200mW headphone amplifiers, input multi- plexers are controlled by bit 1 in the control register plexers, headphone sensing, and comprehensive click- (MAX9777) or by the IN1/2 pin (MAX9778). A logic-low and-pop suppression. The MAX9777/MAX9778 are selects input IN_1 and a logic-high selects input IN_2. stereo BTL/headphone amplifiers. The MAX9777 is controlled through an I2C-compatible, 2-wire serial The input multiplexer can also be used to further interface. The MAX9778 is controlled through five logic expand the number of gain options available from the inputs: MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2 MAX9777/MAX9778 family. Connecting the audio (see the Selector Guide). The MAX9777/MAX97778 fea- source to the device through two different input resis- ture exceptional PSRR (100dB at 1kHz), allowing these tors (Figure 1) increases the number of gain options devices to operate from noisy digital supplies without from two to four. Additionally, the input multiplexer the need for a linear regulator. allows a speaker equalization network to be switched into the speaker signal path. This is typically useful in The speaker amplifiers use a BTL configuration. The optimizing acoustic response from speakers with small signal path is composed of an input amplifier and an physical dimensions. output amplifier. Resistor RIN sets the input amplifier’s gain, and resistor RF sets the output amplifier’s gain. Headphone Sense Enable The output of these two amplifiers serves as the input to MAX9777/MAX9778 The HPS input is enabled by HPS_EN (MAX9778) or the a slave amplifier configured as an inverting unity-gain HPS_D bit (MAX9777). HPS_D or HPS_EN determines follower. This results in two outputs, identical in magni- whether the device is in automatic detection mode or tude, but 180° out of phase. The overall gain of the fixed-mode operation (see Tables 1a and 1b). speaker amplifiers is twice the product of the two amplifier gains (see the Gain-Setting Resistors section). A feature of this architecture is that there is no phase inversion from input to output. MAX9777 When configured as a headphone (single-ended) ampli- 15kΩ MAX9778 fier, the slave amplifier is disabled, muting the speaker IN_1 and the main amplifier drives the headphone. The AUDIO MAX9777/MAX9778 can deliver 3W of continuous power INPUT 30kΩ into a 3Ω load with less than 1% THD+N in speaker IN_2 mode, and 200mW of continuous average power into a 16Ω load with less than 1% THD+N in headphone mode. These devices also feature thermal-overload protection. Figure 1. Using the Input Multiplexer for Gain Setting BIAS These devices operate from a single 5V supply, and feature an internally generated, power-supply independent, Table 1a. MAX9777 HPS Setting common-mode bias voltage of 2.5V referenced to GND. BIAS provides both click-and-pop suppression and sets INPUTS GAIN the DC bias level for the audio outputs. BIAS is internally HPS_D SPKR/HP MODE HPS PATH* connected to the noninverting input of each speaker BIT BIT amplifier (see the Typical Application Circuits and 0 0 X BTL A Functional Diagrams). Choose the value of the bypass capacitor as described in the BIAS Capacitor section. 01XSEB No external load should be applied to BIAS. Any load 1 X 0 BTL A or B lowers the BIAS voltage, affecting the overall perfor- 1 X 1 SE A or B mance of the device. *Note: A—GAINA path selected B—GAINB path selected A or B—Gain path selected by GAINAB control bit in register 02h

12 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Table 1b. MAX9778 HPS Setting MAX9777/MAX9778 VDD INPUTS MODE GAIN PATH* R1 680kΩ HPS_EN HPS MAX9777 R3 Ω 0 X BTL A or B MAX9778 47k HPS 1 0 BTL A or B 1 1 SE A or B OUTL+ *Note: OUTR+ A or B—Gain path selected by external GAINAB R2 R2 10kΩ 10kΩ Headphone Sense Input (HPS) With headphone sense enabled, a voltage on HPS less than 0.7 x V sets the device to speaker mode. A volt- DD Figure 2. HPS Configuration Circuit age greater than 0.9 x VDD disables the inverting bridge amplifier (OUT_-), which mutes the speaker device. The digital section of the MAX9777 remains amplifier and sets the device into headphone mode. active when the device is shut down through the inter- For automatic headphone detection, enable headphone face. All devices feature a logic-low on the SHDN input. sense and connect HPS to the control pin of a 3-wire headphone jack as shown in Figure 2. With no head- MUTE phone present, the resistive voltage-divider created by The MAX9777/MAX9778 feature a mute mode. When R1 and R2 sets the voltage on HPS to be less than 0.7 x the device is muted, the input is disconnected from the VDD, setting the device to speaker mode and the gain amplifiers. MUTE does not shut down the device. setting defaults to GAINA (MAX9777). When a headphone plug is inserted into the jack, the control pin is dis- MAX9777 MUTE The MAX9777 MUTE mode is selected by writing to the connected from the tip contact, and HPS is pulled to VDD through R1, setting the device into headphone mode and MUTE register (see the Mute Register section). The left the gain-setting defaults to GAINB (MAX9777) (see the and right channels can be independently muted. Gain Select section). Place a resistor in series with the MAX9778 MUTE control pin and HPS (R3) to prevent any audio signal from The MAX9778 features an active-high MUTE input that coupling into HPS when the device is in speaker mode. mutes all channels. Shutdown Click-and-Pop Suppression The MAX9777/MAX9778 feature a 10µA, low-power The MAX9777/MAX9778 feature Maxim’s comprehen- shutdown mode that reduces quiescent current con- sive click-and-pop suppression. When entering or exit- sumption and extends battery life. The drive amplifiers ing shutdown, the common-mode bias voltage of the and bias circuitry are disabled, the amplifier outputs amplifiers is slowly ramped to and from the DC bias (OUT_) go high impedance, and BIAS is driven to point using an S-shaped waveform. In headphone GND. Driving SHDN low places the devices into shut- mode, this waveform shapes the frequency spectrum, 2 down mode, disables the interface, and resets the I C minimizing the amount of audible components present registers to a default state. A logic-high on SHDN at the headphone. In speaker mode, the BTL amplifiers enables the devices. start up in the same fashion as in headphone mode. MAX9777 Software Shutdown When entering shutdown, both amplifier outputs ramp A logic-high on bit 0 of the SHDN register places the to GND quickly and simultaneously. To maximize click- MAX9777 in shutdown mode. A logic-low enables the and-pop suppression, drive SHDN to 0V before power- up or power-down transitions.

______13 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Digital Interface devices from high-voltage spikes on the bus lines, and The MAX9777 features an I2C/SMBus™-compatible 2- minimize crosstalk and undershoot of the bus signals. wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facili- Bit Transfer tate bidirectional communication between the One data bit is transferred during each SCL clock MAX9777 and the master at clock rates up to 400kHz. cycle. The data on SDA must remain stable during the Figure 3 shows the 2-wire interface timing diagram. The high period of the SCL clock pulse. Changes in SDA MAX9777 is a transmit/receive slave-only device, rely- while SCL is high are control signals (see the START ing upon a master to generate a clock signal. The mas- and STOP Conditions section). SDA and SCL idle high 2 ter (typically a microcontroller) initiates data transfer on when the I C bus is not busy. the bus and generates SCL to permit that transfer. START and STOP Conditions A master device communicates to the MAX9777 by When the serial interface is inactive, SDA and SCL idle transmitting the proper address followed by a com- high. A master device initiates communication by issu- mand and/or data words. Each transmit sequence is ing a START condition. A START condition is a high-to- framed by a START (S) or REPEATED START (Sr) con- low transition on SDA with SCL high. A STOP condition dition and a STOP (P) condition. Each word transmitted is a low-to-high transition on SDA while SCL is high over the bus is 8 bits long and is always followed by an (Figure 4). A START condition from the master signals acknowledge clock pulse. the beginning of a transmission to the MAX9777. The MAX9777/MAX9778 SDA and SCL are open-drain outputs requiring a pullup master terminates transmission by issuing the STOP resistor (500Ω or greater) to generate a logic-high volt- condition; this frees the bus. If a REPEATED START age. Series resistors in line with SDA and SCL are option- condition is generated instead of a STOP condition, the al. These series resistors protect the input stages of the bus remains active. SMBus is a trademark of Intel Corp.

SDA

tBUF tSU, DAT tHD, STA tHD, STA tSP tSU, STO tLOW tHD, DAT

SCL

tHIGH tHD, STA tR tF

START REPEATED STOP START CONDITION START CONDITION CONDITION CONDITION

Figure 3. 2-Wire Serial-Interface Timing Diagram

SSr P

SCL

SDA

Figure 4. START/STOP Conditions

14 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Early STOP Conditions Acknowledge Bit (ACK) MAX9777/MAX9778 The MAX9777 recognizes a STOP condition at any The acknowledge bit (ACK) is the ninth bit attached to point during the transmission except if a STOP condi- any 8-bit data word. The receiving device always gen- tion occurs in the same high pulse as a START condi- erates ACK. The MAX9777 generates an ACK when tion (Figure 5). This condition is not a legal I2C format; receiving an address or data by pulling SDA low during at least one clock pulse must separate any START and the night clock period. When transmitting data, the STOP condition. MAX9777 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuc- REPEATED START Conditions cessful data transfers. An unsuccessful data transfer A REPEATED START (Sr) condition may indicate a occurs if a receiving device is busy or if a system fault change of data direction on the bus. Such a change has occurred. In the event of an unsuccessful data occurs when a command word is required to initiate a transfer, the bus master should reattempt communica- read operation. Sr may also be used when the bus tion at a later time. master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX9777 ser- Slave Address ial interface supports continuous write operations with The bus master initiates communication with a slave or without an Sr condition separating them. Continuous device by issuing a START condition followed by a 7-bit read operations require Sr conditions because of the slave address (Figure 6). When idle, the MAX9777 change in direction of data flow. waits for a START condition followed by its slave address. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX9777 (R/W = 0 SCL selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX9777 issues an ACK by pulling SDA low for one clock cycle. SDA The MAX9777 has a factory-/user-programmed address. Address bits A6–A2 are preset, while A0 and A1 is set by ADD. Connect ADD to either VDD, GND, STOP START SCL, or SDA to change the last 2 bits of the slave LEGAL STOP CONDITION address (Table 2).

SCL S A6A5A4A3A2A1A0R/W

Figure 6. Slave Address Byte Definition

SDA Table 2. MAX9777 I2C Slave Addresses START ILLEGAL ADD CONNECTION I2C ADDRESS STOP GND 100 1000 ILLEGAL EARLY STOP CONDITION VDD 100 1001 Figure 5. Early STOP Condition SDA 100 1010 SCL 100 1011

______15 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Write Data Format in bit 0 of the SHDN register shuts down the device; a There are three registers that configure the MAX9777: logic-low turns on the device. A logic-high is required in the MUTE register, SHDN register, and control register. bits 2 to 7 to reset all registers to their default settings. In write data mode (R/W = 0), the register address and data byte follow the device address (Figure 7). Control Register The control register (03hex) is a read/write register that MUTE Register determines the device configuration. Bit 1 (IN1/IN2) con- The MUTE register (01hex) is a read/write register that trols the input multiplexer, a logic-high selects input 1; a sets the MUTE status of the device. Bit 3 (MUTEL) of logic-low selects input 2. Bit 2 (HPS_D) controls the the MUTE register controls the left channel; bit 4 headphone sensing. A logic-low configures the device in (MUTER) controls the right channel. A logic-high mutes automatic headphone detection mode. A logic-high dis- the respective channel; a logic-low brings the channel ables the HPS input. Bit 3 (GAINA/B) controls the gain- out of mute. select multiplexer. A logic-low selects GAINA. A logic- high selects GAINB. GAINA/B is ignored when HPS_D = SHDN Register 0. Bit 4 (SPKR/HP) selects the amplifier operating mode The SHDN register (02hex) is a read/write register that when HPS_D = 1. A logic-high selects speaker mode, controls the power-up state of the device. A logic-high and a logic-low selects headphone mode.

S ADDRESS WR ACK COMMAND ACK DATA ACK P MAX9777/MAX9778 7 BITS 8 BITS 8 BITS 1 I2C SLAVE ADDRESS. REGISTER ADDRESS. REGISTER DATA SELECTS DEVICE. SELECTS REGISTER TO BE WRITTEN TO.

S ADDRESS WR ACK COMMAND ACKS ADDRESS WR ACK DATA P 7 BITS 8 BITS7 BITS 8 BITS 1 I2C SLAVE ADDRESS. REGISTER ADDRESS. I2C SLAVE ADDRESS. DATA FROM SELECTS DEVICE. SELECTS REGISTER SELECTS DEVICE. SELECTED REGISTER TO BE READ.

Figure 7. Write/Read Data Format Example Table 3. MAX9777 MUTE Register Format Table 4. MAX9777 SHDN Register Format REGISTER REGISTER ADDRESS 0000 0010 0000 0001 ADDRESS BIT NAME VALUE DESCRIPTION BIT NAME VALUE DESCRIPTION 0* — 7 RESET 7 X Don’t Care — 1 Reset device 0* — 6 X Don’t Care — 6 RESET 1 Reset device 5 X Don’t Care — 0* — 0* Unmute right channel 5 RESET 4 MUTER 1 Reset device 1 Mute right channel 0* — 0* Unmute left channel 4 RESET 3 MUTEL 1 Reset device 1 Mute left channel 0* — 3 RESET 2 X Don’t Care — 1 Reset device 1 X Don’t Care — 0* — 2 RESET 0 X Don’t Care — 1 Reset device *Default state. 1 X Don’t Care — 0* Normal operation 0 SHDN 1 Shutdown *Default state.

16 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Table 5. MAX9777 Control Register Format Read Data Format MAX9777/MAX9778 In read mode (R/W = 1), the MAX9777 writes the con- REGISTER ADDRESS 0000 0011 tents of the selected register to the bus. The direction of BIT NAME VALUE DESCRIPTION the data flow reverses following the address acknowl- 7 X Don’t Care — edge by the MAX9777. The master device reads the contents of all registers, including the read-only status 6 X Don’t Care — register. Table 6 shows the status register format. 5 X Don’t Care — 0* Speaker mode selected Interrupt Output (INT) The MAX9777 includes an interrupt output (INT) that 4 SPKR/HP Headphone mode 1 can indicate to a master device that an event has selected occurred. INT is triggered when the state of HPS 0* Gain-setting A selected changes. During normal operation, INT idles high. If a 3 GAINA/B 1 Gain-setting B selected headphone is inserted/removed from the jack and that action is detected by HPS, INT pulls the line low. INT Automatic headphone 0* remains low until a read data operation is executed. detection enabled I2C Compatibility 2 HPS_D Automatic headphone The MAX9777 is compatible with existing I2C systems. 1 detection disabled SCL and SDA are high-impedance inputs; SDA has an (HPS ignored) open drain that pulls the data line low during the ninth 0* Input 1 selected clock pulse. The communication protocol supports the 1 IN1/IN2 1 Input 2 selected standard I2C 8-bit communications. The general call 0 X Don’t Care — address is ignored. The MAX9777 slave addresses are compatible with the 7-bit I2C addressing protocol only. *Default

Table 6. MAX9777 Status Register Format

REGISTER ADDRESS 0000 0000 BIT NAME VALUE DESCRIPTION 0 Device temperature below thermal limit 7 THRM 1 Device temperature exceeding thermal limit 0 OUTR- current below current limit 6 AMPR- 1 OUTR- current exceeding current limit 0 OUTR+ current below current limit 5 AMPR+ 1 OUTR+ current exceeding current limit 0 OUTL- current below current limit 4 AMPL- 1 OUTL- current exceeding current limit 0 OUTL+ current below current limit 3 AMPL+ 1 OUTL+ current exceeding current limit 0 Device in speaker mode 2 HPSTS 1 Device in headphone mode 1 X Don’t Care — 0 X Don’t Care —

______17 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Applications Information Single-Ended Headphone Amplifier The MAX9777/MAX9778 can be configured as single- BTL Speaker Amplifiers ended headphone amplifiers through software or by The MAX9777/MAX9778 feature speaker amplifiers sensing the presence of a headphone plug (HPS). In designed to drive a load differentially, a configuration headphone mode, the inverting output of the BTL referred to as bridge-tied load (BTL). The BTL configu- amplifier is disabled, muting the speaker. The gain is ration (Figure 8) offers advantages over the single- 1/2 that of the device in speaker mode, and the output ended configuration, where one side of the load is power is reduced by a factor of 4. connected to ground. Driving the load differentially In headphone mode, the load must be capacitively doubles the output voltage compared to a single- coupled to the device, blocking the DC bias voltage ended amplifier under similar conditions. Thus, the from the load (see the Typical Application Circuits). devices’ differential gain is twice the closed-loop gain of the input amplifier. The effective gain is given by: Power Dissipation and Heat Sinking Under normal operating conditions, the MAX9777/ R A =×2 F MAX9778 can dissipate a significant amount of power. VD The maximum power dissipation for each package is RIN given in the Absolute Maximum Ratings section under Substituting 2 x VOUT(P-P) for VOUT(P-P) into the follow- Continuous Power Dissipation or can be calculated by

MAX9777/MAX9778 ing equations yields four times the output power due to the following equation: doubling of the output voltage: TTJ() MAX− A PDISSPKG() MAX = VOUT() P− P θJA VRMS = 22 where TJ(MAX) is +150°C, TA is the ambient tempera- 2 VRMS ture, and θJA is the reciprocal of the derating factor in POUT = RL °C/W as specified in the Absolute Maximum Ratings section. For example, θJA of the TQFN package is Since the differential outputs are biased at midsupply, +29°C/W. there is no net DC voltage across the load. This elimi- The increase in power delivered by the BTL configura- nates the need for DC-blocking capacitors required for tion directly results in an increase in internal power dis- single-ended amplifiers. These capacitors can be large sipation over the single-ended configuration. The and expensive, consume board space, and degrade maximum power dissipation for a given V and load is low-frequency performance. DD given by the following equation: When the MAX9777 is configured to automatically detect the presence of a headphone jack, the device defaults to 2V 2 gain setting A when the device is in speaker mode. P = DD DISS() MAX 2 π RL If the power dissipation for a given application exceeds the maximum allowed for a given package, either reduce VDD, increase load impedance, decrease the ambient +1 VOUT(P-P) temperature, or add heatsinking to the device. Large output, supply, and ground PC board traces improve the maximum power dissipation in the package. 2 x VOUT(P-P) Thermal-overload protection limits total power dissipation in these devices. When the junction temperature exceeds +160°C, the thermal-protection circuitry dis- -1 VOUT(P-P) ables the amplifier output stage. The amplifiers are enabled once the junction temperature cools by 15°C. This results in a pulsing output under continuous thermal-overload conditions as the device heats and cools. Figure 8. Bridge-Tied Load Configuration

18 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Component Selection the load impedance form a highpass filter with a -3dB MAX9777/MAX9778 Gain-Setting Resistors point determined by: External feedback components set the gain of the 1 f− = MAX9777/MAX9778. Resistor RIN sets the gain of the 3dB π 2 RCL OUT input amplifier (AVIN), and resistor RF sets the gain of the second stage amplifier (AVOUT): As with the input capacitor, choose COUT such that f-3dB is well below the lowest frequency of interest. ⎛10kΩ⎞ ⎛ R ⎞ Setting f too high affects the amplifier‘s low-fre- A =−⎜ ⎟, A =−⎜ F ⎟ -3dB VIN ⎝ R ⎠ VOUT ⎝10kΩ⎠ quency response. IN Load impedance is a concern when choosing COUT. Combining AVIN and AVOUT, RIN and RF set the single- Load impedance can vary, changing the -3dB point of ended gain of the device as follows: the output filter. A lower impedance increases the cor- ner frequency, degrading low-frequency response. ⎛10kΩ⎞ ⎛ R ⎞ ⎛ R ⎞ AA=× A =− ×− ⎜ FF⎟ =+ Select COUT such that the worst-case load/COUT com- V VIN VOUT ⎜ ⎟ ⎝ ⎠ ⎜ ⎟ ⎝ RIN ⎠ 10kΩ ⎝ RIN ⎠ bination yields an adequate response. Select capacitors with low ESR to minimize resistive losses and As shown, the two-stage amplifier architecture results optimize power transfer to the load. in a noninverting gain configuration, preserving If layout constraints require a physically smaller output- absolute phase through the MAX9777/MAX9778. The coupling capacitor, decrease the value of COUT and add gain of the device in BTL mode is twice that of the sin- series resistance to the output of the MAX9777/MAX9778 gle-ended mode. Choose RIN between 10kΩ and 15kΩ (see Figure 9). With the added series resistance at the and RF between 15kΩ and 100kΩ. output, the cutoff frequency of the highpass filter is: Input Filter = 1 f−3dB The input capacitor (C ), in conjunction with R , forms 2π()RR+ C IN IN L SERIES OUT a highpass filter that removes the DC bias from an incoming signal. The AC-coupling capacitor allows the Since the cutoff frequency of the output highpass filter amplifier to bias the signal to an optimum DC level. is inversely proportional to the product of the total load Assuming zero-source impedance, the -3dB point of resistance seen by the outputs (RL + RSERIES) and the highpass filter is given by: COUT, increase the total resistance seen by the MAX9777/MAX9778 outputs by the same amount COUT = 1 f−3dB is decreased to maintain low-frequency performance. 2πRC IN IN Since the added series resistance forms a voltage- divider with the headphone speaker resistance for fre- Choose R according to the Gain-Setting Resistors sec- IN quencies within the passband of the highpass filter, tion. Choose the C such that f is well below the IN -3dB there is a loss in voltage gain. To compensate for this lowest frequency of interest. Setting f too high affects -3dB loss, increase the voltage gain setting by an amount the amplifier’s low-frequency response. Use capacitors equal to the attenuation due to the added series resis- whose dielectrics have low-voltage coefficients, such as tance. Use the following equation to approximate the tantalum or aluminum electrolytic. Capacitors with high- required voltage gain compensation: voltage coefficients, such as ceramics, may result in an increased distortion at low frequencies. ⎛ RR+ ⎞ Other considerations when designing the input filter A = 20log⎜ L SERIES ⎟ V_ COMP ⎝ R ⎠ include the constraints of the overall system, L the actual frequency band of interest, and click-and- pop suppression. COUT RSERIES OUT_+ Output-Coupling Capacitor The MAX9777/MAX9778 require output-coupling RL capacitors to operate in single-ended (headphone) mode. The output-coupling capacitor blocks the DC component of the amplifier output, preventing DC current from flowing to the load. The output capacitor and Figure 9. Reducing COUT by Adding RSERIES

______19 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

BIAS Capacitor where the impedance, CF, begins to decrease, and at BIAS is the output of the internally generated 2.5VDC high frequencies, the CF is a short circuit. Here the bias voltage. The BIAS bypass capacitor, CBIAS, impedance of the feedback loop is: improves PSRR and THD+N by reducing power supply and other noise sources at the common-mode bias RR × R = FF12 node, and also generates the clickless/popless, start- F() EFF RRFF12 + up/shutdown DC bias waveforms for the speaker amplifiers. Bypass BIAS with a 1µF capacitor to GND. Assuming RF1 = RF2, then RF(EFF) at low frequencies is twice that of R at high frequencies (Figure 11). Supply Bypassing F(EFF) Thus, the amplifier has more gain at lower frequencies, Proper power-supply bypassing ensures low-noise, low- boosting the system’s bass response. Set the gain roll- distortion performance. Place a 0.1µF ceramic capacitor off frequency based upon the response of the speaker from V to GND. Add additional bulk capacitance as DD and enclosure. required by the application, typically 100µF. Bypass PVDD with a 100µF capacitor to GND. Locate bypass To minimize distortion at low frequencies, use capaci- capacitors as close to the device as possible. tors with low-voltage coefficient dielectrics when selecting CF. Film or C0G dielectric capacitors are good Gain Select choices for CF. Capacitors with high-voltage coeffi- The MAX9777/MAX9778 feature multiple gain settings on cients, such as ceramics (non-C0G dielectrics), can MAX9777/MAX9778 each channel, making available different gain and feed- result in increased distortion at low frequencies. back configurations. The gain-setting resistor (RF) is connected between the amplifier output (OUT_+) and the Layout and Grounding gain set point (GAIN_). An internal multiplexer switches Good PC board layout is essential for optimizing perfor- between the different feedback resistors depending on mance. Use large traces for the power-supply inputs the status of the gain control input. The stereo and amplifier outputs to minimize losses due to para- MAX9777/MAX9778 feature two gain options per chan- sitic trace resistance, as well as route heat away from nel. See Tables 1a and 1b for the gain-setting options. the device. Good grounding improves audio performance, minimizes crosstalk between channels, and Bass Boost Circuit prevents any digital switching noise from coupling into Headphones typically have a poor low-frequency the audio signal. If digital signal lines must cross over response due to speaker and enclosure size limitations. or under audio signal lines, ensure that they cross per- A bass boost circuit compensates the poor low-frequen- pendicular to each other. cy response (Figure 10). At low frequencies, the capaci- The MAX9777/MAX9778 TQFN package features an tor CF is an open circuit, and the effective impedance in exposed thermal pad. This pad lowers the package’s the feedback loop (RF(EFF)) is RF(EFF) = RF1. thermal resistance by providing a direct heat conduc- At the frequency: tion path from the die to the PC board. Connect the pad 1 to signal ground (0V) by using a large pad or multiple π vias to the ground plane. 2 RCFF2

GAIN C RF1 F RF2 RIN

RF1

RIN

RF1 RF2 RIN FREQUENCY 1 VBIAS 2π RF2 CF

Figure 10. Bass Boost Circuit Figure 11. Bass Boost Response

20 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Application Circuits MAX9777/MAX9778

4.5V TO 5.5V

0.1µF 100µF 3, 4 11, 25

VDD PVDD 17 µ BIAS 0.047 F 27.4kΩ 1µF 33.2kΩ 8 GAINLB 220µF 15kΩ 10kΩ 7 GAINLA

15kΩ 10 5 OUTL+ INL1 0.68µF 12 µ OUTL- 0.68 F 15kΩ 6 HPF INL2

CODEC µ MAX9777 0.68 F Ω 15k 19 INR1

26 µ OUTR- 0.68 F 15kΩ 20 HPF INR2 24 4.5V TO 5.5V OUTR+ 15kΩ 220µF 21 GAINRA 4.5V TO 5.5V 33.2kΩ 22 1kΩ 1kΩ 10kΩ GAINRB 10kΩ 680kΩ 27.4kΩ 28 SCL 1 0.047µF SDA 47kΩ 15 16 MICROCONTROLLER ADD HPS 2 INT 14 SHDN

GND PGND 18 9, 13, 23, 27

______21 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Typical Application Circuits (continued)

4.5V TO 5.5V

0.1µF 100µF 3, 4 11, 25

VDD PVDD 17 µ BIAS 0.047 F 27.4kΩ 1µF 33.2kΩ 8 GAINLB 220µF 15kΩ 10kΩ 7 GAINLA

15kΩ 10 5 OUTL+ INL1 0.68µF 12 MAX9777/MAX9778 µ OUTL- 0.68 F 15kΩ 6 HPF INL2

CODEC µ MAX9778 0.68 F Ω 15k 19 INR1

26 µ OUTR- 0.68 F 15kΩ 20 HPF INR2 24 OUTR+ 15kΩ 220µF 21 GAINRA 4.5V TO 5.5V 33.2kΩ 22 GAINRB 10kΩ 680kΩ 27.4kΩ 28 IN1/2 1 0.047µF MUTE 47kΩ 15 16 MICROCONTROLLER GAINA/B HPS 2 HPS_EN 14 SHDN

GND PGND 18 9, 13, 23, 27

22 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Functional Diagrams MAX9777/MAX9778

4.5V TO 5.5V

100µF 0.1µF

11, 25 3, 4

PVDD VDD GAINLB 8 GAIN 10kΩ SET GAINLA 7 0.047µF 0.68µF 15kΩ MUX AUDIO 33.2kΩ 5 INL1 2:1 27.4kΩ INPUT 10kΩ 15kΩ INPUT AUDIO 6 INL2 10kΩ MUX OUTL+ 10 INPUT 0.68µF 15kΩ 220µF

10kΩ 17 BIAS BIAS Ω 1µF 10k OUTL- 12

GAINRB 22 GAIN 10kΩ SET 0.047µF MUX GAINRA 21 0.68µF 15kΩ Ω AUDIO 33.2k 19 INR1 2:1 27.4kΩ INPUT 10kΩ 15kΩ INPUT AUDIO 20 INR2 10kΩ MUX OUTR+ 24 INPUT 0.68µF 15kΩ 220µF 4.5V TO 5.5V 10kΩ

10kΩ 1kΩ 1kΩ 10kΩ 14 SHDN OUTR- 26 28 SCL TO 1 SDA LOGIC µCONTROLLER 15 ADD 2 INT HPS 16 HPS

MAX9777 GND PGND 18 9, 13, 23, 27

______23 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Functional Diagrams (continued)

4.5V TO 5.5V

100µF 0.1µF

11, 25 3, 4

PVDD VDD GAINLB 8 GAIN 10kΩ SET GAINLA 7 0.047µF 0.68µF 15kΩ MUX AUDIO 33.2kΩ 5 INL1 2:1 27.4kΩ INPUT 10kΩ 15kΩ INPUT AUDIO 6 INL2 10kΩ MUX OUTL+ 10 INPUT 0.68µF 15kΩ 220µF

10kΩ 17 BIAS BIAS 10kΩ MAX9777/MAX9778 1µF OUTL- 12

10kΩ 1kΩ 1kΩ 10kΩ 14 SHDN OUTR- 26 28 IN1/2 TO 1 MUTE LOGIC µCONTROLLER 15 GAINA/B 2 HPS_EN HPS 16 HPS

MAX9778 GND PGND 18 9, 13, 23, 27

24 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Pin Configurations MAX9777/MAX9778

TOP VIEW TOP VIEW GAINRA INR2 GND BIAS HPS ADD INR1 INR1 GAINRA INR2 GND BIAS HPS GAINA/B

2120 1918 17 16 15 2120 1918 17 16 15

GAINRB 22 14 SHDN GAINRB 22 14 SHDN

PGND 23 13 PGND PGND 23 13 PGND

OUTR+ 24 12 OUTL- OUTR+ 24 12 OUTL-

PVDD 25 MAX9777 11 PVDD PVDD 25 MAX9778 11 PVDD OUTR- 26 10 OUTL+ OUTR- 26 10 OUTL+

PGND 27 9 PGND PGND 27 9 PGND + + SCL 28 8 GAINLB IN1/2 28 8 GAINLB

123 4567 123 4567 DD DD DD DD INT V V V V SDA INL1 INL2 INL1 INL2 MUTE GAINLA GAINLA THIN QFN HPS_EN THIN QFN

______25 Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS

MAX9777/MAX9778

26 ______Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux

Package Information (continued) MAX9777/MAX9778 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______27