“ATE Open System Platform” IEEE-P1552 Structured Architecture for Test Systems (SATS) Working Group Cochairmen Michael J. Stora ; Modular Integration Technologies, Boonton, NJ; [email protected] David Droste; PEI Electronics Inc., Huntsville, AL; [email protected]

Abstract- The IEEE-P1552 Structured Architecture for Test Systems (SATS) Standards effort, is a multidimensional ATE “Open System Platform” packaging specification. The Standard defines data/signal/power interconnect mechanical/electrical mating connector requirements and common hardware packaging form factors. Addressed are plug&play wiring panels, switchable instrument/power mezzanine (IPM) modules, high speed serial control, and test bus matrix functionality, that permit subelement interchangeability and interoperability. The standard’s functional performance requirements are limited to mechanical engagement, connector styles/footprints, electrical pin characteristics, and pin mapping defi- nitions. As a higher order plug&play architecture SATS supports legacy VXIbus and PXIbus architectures as hybrid subsystem integrations.

I. INTRODUCTION In conjunction with the SSC20 Liaison Standards Subcommittee of the Institute of Electrical, Electronic Engineers (IEEE) Stan- dards Organization [1], a new multidimensional ATE “Open Sys- tem Platform” packaging standard has been initiated under IEEE- P1552 Structured Architecture for Test Systems (SATS). An ar- chitecture that will have profound impact on current test com- puter-busboard systems in reducing costs and size, while improv- ing performance and supportability.

The key to ATS Integration and Test Program Set (TPS) cost re- duction/avoidance requires us to reduce variations of the soft- ware /hardware interfaces between ATS. Standardization func- tionally defines and provides guidelines for developing the inter- faces within a ATS. Applying these standards with Commercial Off The Shelf (COTS) modular compatible pluggable modules, the ATS structure becomes more homogenous in its integration and supportability. This open architecture approach avoids unique government requirements and associated nonrecurring costs, en- Figure 1. SATS Multi-Dimensional Plug&Play Interconnectivity hances product availability/performance, and benefits from in- dustry investment/technology. A preliminary set of specifications has been developed and is undergoing refinement under the IEEE Standards Organization SATS replaces/extends the current two dimensional process. Meetings are planned for IEEE, NEPCON, and AS- computer-based architecture of VMEbus [2], VXIbus [3], PCI- SEMBLY TECHNOLOGY trade shows to broaden participation. bus [4], PXIbus [5], and several other standards into a multidi- mensional integrated hardware architecture, as conveyed by Fig- II. TECHNICAL PROBLEM ure 1. Under the SATS Frameworks, Instrument/Power Mezza- The technical problem of this Standard was first addressed by nine (IPM) Carrier Modules and Serial/Test Bus Integration, the Department of Defense memorandum OSD (A&T) - 29Apr94, current 2-D backplane is reconfigured into 3-D matrix wiring DOD Policy for Automatic Test Systems, by direction of Noel panels supporting control, power, and signal interconnectivity. Longuemare. The following memo caption reflects on the in- tent of Mr. Longuemare’s directive and serves to lead our ef- Legacy VMEbus, VXIbus, PCIbus, PXIbus Standards are sup- forts; “ATS capabilities shall be defined through control of criti- ported through a hybrid process that integrates respective back- cal hardware and software elements and interfaces to ensure DOD plane standard characteristics with SATS wiring panel specifica- family tester and COTS tester and component interoperability, tions. Legacy standards can choose to integrate current front and to meet future DOD test needs”. connectors to SATS wiring panels, or convert to the SATS com- mon CompactPCI [6] connector family. SATS reduces dissimi- A joint government/industry Critical Interface Working Group lar front panel connector proliferation and eliminates wire be- (CIWG) effort furthered this ATS interface standardization pro- tween chassis systems. This has the potential of reducing Auto- cess. It was conducted under the auspices of the military Joint matic Test Systems (ATS) material costs, labor, test time, and Service Automatic Test Systems Research and Development Inte- support by 40%. grated Product Team (ARI), by a combined government and in- dustry Critical Interfaces Working Group[7]. The CIWG objec- specifications through fabrication of multivendor/multifunction tives were to identify the critical ATS interfaces that impacted prototype modules that would be integrated into working SATS interoperability/interchangeability of system hardware and test architecture. The (third) objective is achieving Users and Inte- program set transportability. Although the results established grators recognition and acceptance of the Standard(s), that in turn clear definitions of the critical interfaces, very few could relate will drive vendor/supplier requirements. This represents a de- to commercial interface standards, beyond existing VXI, com- parture from previous Test Standards that were established by puter data interfaces and government specifications. supplier/vendor motives, and therein reasons for their respective limitations. The remaining issues of the technical problem are those critical packaging and interconnect hardware interfaces not addressed Success will be measured by SATS ability to: (a) align with COTS by current industry standards. Hardware interfaces relate pri- - Commercial Off The Shelf products, that are designed to exist- marily to packaging and data/signal/power interconnect standards. ing commercial standards, i.e. IEEE, Eurocard, VXI, VME; (b) These standards typically define mainframe and subelement (mod- reduce costs by exploiting commercial investment, limited non- ule) mechanical/electrical mating specifications, that should per- recurring integration development, and competitive pressures; (c) mit subelements to be interchanged without impact to subele- improve availability and interoperability through common archi- ment interoperability. The functional performance of the stan- tectures and multivendor product offerings; (d) improve test pro- dard is normally limited to mechanical engagement, connector gram set transportability; (e) increase ATS supportability through styles/footprints, electrical pin characteristics, and pin mapping standard acceptance, available technical/spares third-party sup- definitions. This permits various vendor products (subelement/ port tools and resources; and (f) assure longer product life by module) to interoperate (plug & play) with no or minimum modi- structuring the architecture for future commercial subelement pre- fication by the integrator or user. Functional performance speci- planned product improvements and ATS technical insertion. fications of unique subelement capabilities, that exceed interop- erability requirements are typically relegated to the integrator/ IV. SATS GENERIC INTERFACE ARCHITECTURE user to define. The following diagram, Figure 2, illustrates the traditional VXI based ATS hardware/electrical connector interface elements em- III. OBJECTIVES OF THE SATS STANDARD EFFORT ployed: (a) Rack/Chassis Mechanical Integration Structure; (b) The mission of this Standard effort are threefold: (first) to estab- Computer Control Interface; (c) VXI/IEEE-488 Instruments; lish ballot ready specifications for the Structured Architecture (d) Power Distribution; (e) Cabling/Signal Interconnects; and for Test Systems (SATS) Standards; and (second) validate those (f) Receiver Fixture Interface Subsystem. Figure 2. Traditional VXI/IEEE based ATS hardware/electrical generic interfaces V. RELATED STANDARDS ACTIVITIES ity/technical insertion and general reuse more effectively. By The SATS Program minimized its specification development pro- distributing the Switch Matrix Bus Architecture from the Carrier cess by embracing current or planned Standards efforts. The fol- Module (functional access port), to the RFI System (UUT access lowing represents many of those being implemented under SATS: port), in a scalable and software selectable manner, I/O (a) IEEE SSC20 Technical Committee for the IEEE P1226.X, VXI selectability instrument sharing, fault tolerance, and system di- Instrument Control [8]; (b) IEEE I&M Technical Committee for agnostics are enhanced. the IEEE 488, VXI Instrument Control [9]; (c) IEEE P1505 I& M Technical Committee for the Receiver Fixture Interface [10]; As the next generation to the current VXI/VME instrument/mod- (d) VXI Consortium for the VXI Hardware Specification 1.4[11]; ule control standards, the SATS Frameworks “open” mechani- (e) VXIplug&play Operating Systems and Instrument Drivers, cal and electrical packaging specification implements: VPP-3/4[12]; (f) EIA Standard, RS-310-C, Racks, Panels and 1) Mechanical Integration Structure (MIS) modular/scal- Associated Equipment [13]; (g) ANSI, VME/VME-64 Hardware able plug&play, cableless, environmental sealed, mainframe ar- Standard [14]; (h) IEC 917 (DIN 43355) / IEC 603-2 (DIN 41612) chitecture, utilizing EIA Electronic Rack Specifications [17], Eu- Connector Specifications [15] and (i) M-Module Mezzanine rocard Mechanical Packaging and DIN 43355 Connectors Stan- Specification VITA 12[16]. Other Standards and related Organi- dards; zations may be consulted for electrical and packaging specifica- 2) Plug-on Instrument/Power Mezzanine (IPM) Card pro- tions. visioning functionality at the lowest cost/technical impact and Common Carrier Module with 3U/6U/9U scaleability; VI. SATS STANDARD TECHNICAL APPROACH 3) Computer Control Distribution (CCD) high speed serial The SATS Standard defines and implements a scalable/modular/ bus control for instrument/functional operation, test signal/power cableless ATE “Open System Platform” packaging specifica- switch matrix distribution system management (see Figure 4); tion, conceptually shown in Figure 3, through an IEEE/IEC in- 4) Integrated scalable test/power distributed switch matrix dustry standardization process. The SATS architecture frame- for multi-asset selection/sharing; work and respective seven (7) interfaces are intended to mini- 5) IEEE-P1505 Receiver Interface with I/O switchable and mize design development by reducing complex functionality to scalable from 4 slot cable/PCB connector interface to 29 slot the level of a plug-on mezzanine card (IPM). This minimizes multi-OTPS Fixture engagement; and impact to the integrated Carrier Module, Wiring Panel, and RFI 6) Support for legacy VME/VXI/PCI/PXI test standards. structure, thereby accommodating reconfigurability, upgradeabil-

¥ Integrated Receiver Fixture Interface (RFI)

¥ SATS-RFI Integration Printed Wiring Panel

¥ Modular/Scaleable Plug&Play Composite Environmental Sealed Chassis

¥ Modular/Scaleable Plug&Play 3U/6U/9U IPM Module Implementation (configuration shown supports 12 Slots, 3-9U high, B Size depth Modules w/72 IPM Cards)

¥ SATS-IPM Module Integration Printed Wiring Panel

¥ External Heat Exchanger with Sealed Internal Pressurized Cooling System

Figure 3. SATS Typical Multi-Framework ATE “Open System Platform” VII. ELECTRICAL SYSTEM INTEGRATION FRAMEWORKS board transmission lines designs permit signals to reach 18GHz A. ESI Overview bandwidths. ATE signal integrity and repeatability under The Electrical System Integration (ESI) Specification defines plug&play PCB construction, also dramatically improves pro- the overall SATS Frameworks electrical interconnect system, con- ducibility, as well as reduce integration and test acceptance times nectorization, switching network, and electrical bus pathways for by 40%. A greater gain is achieved by through lower mainte- power, control and stimulus/measurement test signals. The dia- nance support costs (40%), and product technology insertion/evo- gram (Figure 4), correlates to the atypical configuration shown lution costs (60%). in Figure 3, reflecting general interfaces and related elements of the electrical frameworks and their respective relationships. When The ESI specification supports/embeds three distribution sub- implemented under a plug&play architecture, that utilizes ad- systems within the plug& play board/wiring panel fabric. They vanced high speed digital/RF printed circuit board technology, are: (a) the Computer Control Distribution (CCD) Subsystem; considerable benefits accrue. Specifically, it embeds and directly (b) the Power Switching/Distribution Bus (PDB) Subsystem; couples control, power and test signal bus pathways between the and (c) the Test Signal Switching/Distribution Bus (TSD) Sub- test system controller, instrument/power resource, and the UUT system. The Eurocard DIN 43355 Connector serves as common interface. The advancement of embedded RF printed circuit interconnect between board/wiring subelements.

Figure 4. Electrical System Frameworks Integration Overview

System Serial Signal/Low RF Test Bus High RF Test Bus Power Test Bus

IEEE488//Serial Bus

Instr/Power Instr/Power Instr/Power External Resource Bay Mezzanine Mezzanine Mezzanine External Instrument/Power for VME Chassis (IPM) Card(s) (IPM) Card(s) (IPM) Card(s) Rack Mount Resource and & 3U Carrier & 3U Carrier & 3U Carrier Instrument B-Size (6U) Module or Module or Module or Modules Custom 3U Custom 3U Custom 3U Module Module Module

Envirmt/Diag Cntrl Embedded/External/Multi- Power Distr Control Computer Timing& Synch Subsystem(s) System Interrupt System Serial Bus

IEEE488/Ethernet ATE Host CPU Instrument/Power Instr/Power Mezzanine (IPM) Mezzanine (IPM) Card(s) Operator Interface Card(s) & Carrier and Display 6U Module & 3U Carrier - or - Module or Custom 6U Module Custom 3U Module

External Resource Bay S S i i for VXI/PXI Chassis g g Switch/ n Recvr a n Fixture and Instrument Routing Frame- l a Frame- Circuit, work l work/ C-Size (6U) Modules Signal and Enclo- Unit Conditng, Mech P sure Under Active P o Test Drive o and Instr/or Assy w w Plug-in/ (UUT) Personlty e e Direct Instrument/Power Mezzanine (IPM) PCB r r Mount Card(s) & Carrier 9U Module Module Assy R - or - R F F Custom 9U Module

Wiring Panel Bus Interconnect Subsystem Receiver Fixture Interface Subsystem Fixture Plug-in Circuits/ Modules B. Computer Control Distribution (CCD) Subsystem Spec C. Power Switching/Distribution Bus (PDB) Subsystem Spec Use of an advanced computer serial bus network embraces com- Power Switching/Distribution Subsystem (see Figure 7), com- puter industry trends as reflected in Figure 5. This distribution bines distributed primary 48 Volts Direct Current (VDC) Bus with subsystem (see Figure 6 illustrating Rapid I/O implementation), DC-DC Fixed/Programmable Instrument and Power Mezzanine incorporates physical electrical pathways that will host any num- (IPM) Submodules. Outputs from these DC-DC IPM’s are swit- ber of advanced Computer Standards, such as Infiniband[18], chable to the System Power Distribution Bus Matrix which feed Rapid I/O [19], or PCI Express [20]. system resources or Unit-Under-Test (UUT) power requirements. Figure 5. Serial Bus Network and Distribution Subsystem Spec The power switch matrix design incorporates a: (a) 30 amp [30A] High Current Primary 48VDC Feed and Multi-Return/Ground Device Device Lines; (b) 16 wire - 8 output scalable System Power Distribution P • Packet Switched Very Bus Matrix; and (c) Power Bus Entry Level Switching at the IPM e • Point-to-Point Switch Fabric High S r • Frequency and In-line Receiver Fixture Interface (RFI) Power Switching. y f Figure 7 Power Switching/Distribution Subsystem Spec s o Device Device 120/240 48VDC t r Power Entry VAC Primary Bridged Hierarchy AC/DC e m Device Device Input Power Module Broadcast <133MHz Power Feed/ m a Source Power Examples: PCI, PXI, Source Return n Device Switch R Bridge Device Device VME, VXI Module c Power Mezzanine e F DC/DC Card i e Fix/ProgmDC c U Resource/UUT Power e x Single Segment Broadcast <33MHz Power IPM Control U Power Output Switch i t Examples: CompactPCI, VME, VXI Switch Carrier Module Module T v u r Device Device Device Device Device Device Power Mezzanine e DC/DC Card Fix/ProgmDC Power r e Resource/UUT Switch Device Device Device Device Device Device Power IPM Control Power Output Module Switch Carrier Module

Fix/ProgmDC This distributed network fabric will incorporate advanced trans- Custom Power Resource/UUT w/Control &Switch Power Output 2x8 Scalable mission line technology facilitating network speeds to 12G Bytes Module Power Distribution Matrix Bus performance. Employing parallel-multi-serial lines interface fabric, distributed multi-task control, and segregated node con- D. Test Signal Switching/Distr Bus (TSB) Subsystem Spec trol points, the test system control can achieve both speeds and SATS defines an advanced distributed test signal switching fab- technology evolution without impact. ric, as shown in Figure 4 and 8, that routes resource signals to a Figure 6. Serial Bus Network and Distribution Subsystem Spec wide matrix of pin map contacts at the UUT interface. It in- cludes: (a) Resource-to-Bus Entry Switching at the Instrument Figure 8. Test Signal Switching/Distribution Subsystem Spec Inside the Box Box to Box

Serial Rapid I/O UUT Embedded Parallel Rapid I/O Fixture PCI Express Receiver Hyper- Transport .. Embedded Panel N x 32 wire Receiver Receiver Receiver PC/Server Proprietary PCI Scalable Test Signal Distribution Matrix Bus 1x4 Switch 1x4 Switch 1x4 Switch Bus PCI-X Module Module Module Processor Local ...... Bus I/O Bus Backplane SAN LAN .. .. Logical Specification Part I Part II Part V Information necessary for the end point to process the transaction, .. 1x8 Switch 1x8 Switch (ie. transaction type, size, physical I/O System Message Passing Globally Shared Future Mezzanine Card Mezzanine Card .. address) .. VXI/PXI Instr IPM Cntrl/ Instr IPM Cntrl/ Instrument Part III Module Switch Carrier Switch Carrier Transport Specification Information to transport packet from end to end in the system, (i.e. routing Common address) Instrument Instrument VXI/PXI .. Mezzanine Card Mezzanine Card Instrument Part IV Part VI .. Module Physical Specification .. Information necessary to move Instr IPM Cntrl/ Instr IPM Cntrl/ packet between two physical device, 8/16 LP=LVDS 1x/4x LP Serial Future Physical Switch Carrier Switch Carrier

Custom Instr Custom Instr Other Inter-Operability w/Cntrl & w/Cntrl & ATE Switch Module Switch Module Resources

Compliance Checklist Embedded Panel N x 16 Wire Scalable Test Signal Distribution Matrix Bus and Power Mezzanine (IPM) Card level (located on the IPM Car- F. EUROCARD DIN 43355 CONNECTORS rier Module; (b) In-line Bus Matrix Switching as dedicated re- The SATS electrical/pin map specifications builds upon the source modules (IPM Module); and (c) Receiver-to-Bus Matrix “open” design of the IEC 917 (DIN 43355) Connector style, Switching, that directs bus signals to specific Receiver Fixture shown in Figure 10. SATS will benefit from the well-defined Interface (RFI) contacts. Combined with system control soft- and established connector design, to characterize physical inter- ware, the distributed switching architecture provides consider- mateability properties of the interface. Utilizing predefined as- able signal routing flexibility, wire length and pin count reduc- pects of VME, VXI, PCI, PXI, and M-Module electrical bus/pin tion, while simultaneously enhancing system diagnostics and fault definitions further reinforces SATS implementation of the IEC tolerance. 917/DIN 43355 electrical pin functionality. Figure 10. Eurocard DIN 43355 Connectors E. Scalable High Performance Test Signal Bus Matrix Pin Map Scalability of the embedded test signal matrix begins with 4 x 8 wire (16 transmission line signal connectivity-TLC), that can be multiplied by the integrator to serve their respective requirements. Pin Map shown in Figure 9, for a 9U high carrier module and wiring panel interconnectivity can accommodate up to 64 TLC test signal matrix, that can be in turn duplicated within the wiring panel for a number of carrier modules. Figure 9. Test Signal Switching/Distribution Subsystem Pin Map

ZA BCD EF 22 GND TBP6+ TBS87 GND TBS88 TBP6- GND 21 GND TBS83 TBS84 GND TBS85 TBS86 GND 20 GND TBP5+ TBS81 GND TBS82 TBP5- GND 19 GND TBS77 TBS78 GND TBS79 TBS80 GND 18 GND TBP4+ TBS75 GND TBS76 TBP4- GND 17 GND TBS71 TBS72 GND TBS73 TBS74 GND 16 GND TBS68 TBS69 GND TBS70 TBS71 GND 15 GND 3.3V TBS66 GND TBS67 3.3V GND 14 GND TBS62 TBS63 GND TBS64 TBS65 GND 13 GND 5V TBS60 GND TBS61 5V GND 12 GND TBS56 TBS57 GND TBS58 TBS59 GND P2 11 GND 3.3V TBS54 GND TBS55 3.3V GND 10 GND TBS50 TBS51 GND TBS52 TBS53 GND 9 GND 5 V RES GND RES 5 V GND 8 GND TBS46 TBS47 GND TBS48 TBS49 GND 7 GND TBS42 TBS43 GND TBS44 TBS45 GND 6 GND TBS38 TBS39 GND TBS40 TBS41 GND 5 GND TBP3+ TBS36 GND TBS37 TBP3- GND 4 GND TBS32 TBS33 GND TBS34 TBS35 GND 3 GND TBP2+ TBS30 GND TBS31 TBP2- GND 2 GND TBS27 TBS28 GND TBS29 TBS30 GND 1 GND TBP1+ TBS25 GND TBS26 TBP1- GND 25 GND 5 V GND 5 V GND 24 GND TBS23 TBS24 GND GND 23 GND 3.3V TBS21 GND TBS22 3.3V GND 22 GND TBS17 TBS18 GND TBS19 TBS20 GND 21 GND 5V TBS15 GND TBS16 5V GND 20 GND TBS11 TBS12 GND TBS13 TBS14 GND 19 GND 3.3V TBS9 GND TBS10 3.3V GND 18 GND TBS5 TBS6 GND TBS7 TBS8 GND 17 GND 5 V RES GND RES 5 V GND 16 GND TBS1 TBS2 GND TBS3 TBS4 GND 15 GND 3.3V RES GND RES 3.3V GND 14 13 KEY P1 12 11 GND 3.3V RST# GND EALTHY# 3.3V GND 10 GND TCK T M S GND T D I T D I GND 9 GND 5V INTC# GND INTD# 5V GND 8 GND INTA# TRG7 GND TRG8 INTB# GND 7 GND -12V TRG5 GND TRG6 +12V GND 6 GND TRG1 TRG2 GND TRG3 TRG4 GND 5 GND 3.3V CLK+ GND CLK- 3.3V GND 4 GND +T4x -T4x GND +R4x -R4x GND 3 GND +T3x -T3x GND +R3x -R3x GND 2 GND +T2x -T2x GND +R2x -R2x GND 1 GND +T1x -T1x GND +R1x -R1x GND VIII. SATS MECHANICAL FRAMEWORKS lows unique solutions under the Standard as competitive incen- The SATS Frameworks Mechanical System Integration (MSI) tive to suppliers. Definition is however provided to assure com- specification describes elements related to the: (a) mainframe and patible at module interface and direct mainframe pluggable inte- engagement assembly; (b) printed wiring panels, CPCI connec- gration levels. Many of these interfaces are related to connectors tor family and bus matrix; and (c) instrument/power mezzanine applied to the module and mating wiring panel. These are criti- card and carrier module packaging. The SATS Frameworks is cal to the overall objectives in reducing or eliminating the need based upon VMEbus: IEC 297-3[21], IEEE 1014[22]; and VXI- for wire and related costs and space. The chassis engagement bus IEEE 1155 Eurocard Mechanical Packaging[23] and con- mechanism and test interface may be built upon the same distrib- nector engagement/interoperability between the instrument, uted architecture used/proven in the IEEE P1505 Receiver Fix- power, switch/matrix and cooling module. ture Interface (RFI) System.

A. SATS Mainframe C. SATS Wiring Panel/IPM Architecture The SATS Mainframe specification adopts a modular/scalable SATS architecture has been developed as a scalable, distributed Eurocard Packaging Standard design, that can be implemented asset structure that can be employed independently, or in con- for either a suitcase or high end ATE system application. Al- cert, and matriced to a variety of Receiver Fixture Interface (RFI) though, the mainframe specification permits smaller footprints, I/O pins, or with other RFI Ports. The unique High Speed Serial typical implementations would build upon the standard B-size Bus design (Infiniband, Rapid I/O, or PCI Express being consid- depth, 3U/6U/9U VME/PCI or SATS I/PM carriers modules, ered), permits multi-tasking control at a rate as high as 13 Giga scaled to 9U chassis height and to 12 slots at 1.2 inch spacings Bytes/Sec. By reducing the functional stimulus/measurement, (see Figure 11). When fully integrated with cooling, engage- power, and signal conditioning elements to mezzanine cards, the ment mechanisms, and wiring panels total height can reach 14U lowest level of integration and I/O Control (TTL Interconnect) (24.5 inches) and 17.5 inch width. Multi-mainframes may be can be implemented as was illustrated in Figure 12. At this level, integrated horizontally front-to-back, side-to side, and vertical to development costs are marginalized to card functionality, with meet various needs as illustrated in Figure 3. minimum or no costs expended for packaging, control, and ex- Figure 11. SATS Base Mainframe Design ternal I/O. Instrument vendors who have developed products previously for the M-Module Mezzanine Specification -VITA ¥ Push-pull, temp controlled, ¥ Molded composite/extrusion high pressure cooling sub- material framework with built- 12[16] will see direct similarities with enhanced I/O performance, system. in engagement mechanism; density, scaleability and common packaging.

Figure 12. SATS Plug&Play IPM/Carrier Module and Wiring Panel Design

¥ SATS Implementaton Example Using Three (3) “B Size” SATS ¥ Carrier Modules Mainframes and multiples of 3U, 6U, and 9U Instrument/Power mechanical support/ alignment/shielding, Mezzanine (IPM) Cards and Carrier Modules and front mount and rear printed wiring panel interconnect ¥ Implementaton is scaleable in three dimensions using options of multiple layers of mainframes, and various configurations of 3U, 6U, and 9U high IPM Modules.

¥ B-Size, 1.2 inch increment, 9U high, Eurocard specifications

¥ Carrier Modules scaleable vertically 3U, 6U, and 9U high, and horizontal in 1.2 inch increments wide; ¥ A single 19” SATS Mainframe with thirteen (13) 1.2 slots can integrate up to thirty-nine (39) 3U high IPM Carrier Modules, which could support seventy-eight (78) IPM Cards. B. SATS Specification Mechanical Interfaces An alignment/engagement mechanism necessary to integrate ¥ A configuration of three (3) SATS Mainfranes supports 117 IPM Carrier Modules and 234 IPM Cards multi-mainframes is not defined under the Specification and al- D. Instr/Power Mezzanine Card/Carrier Module Spec connectorization to minimize signal path loss. A 3U module can The fundamental element of the SATS Standard describes the support two 1.5U IPM Cards, while a 6U module supports four packaging/interconnect definition of the Instrument/Power Mez- cards, and 9U six cards. SATS Specification permits vendors to zanine (IPM) Card and Carrier Module Specification. Serv- construct 3U, 6U, and /or 9U size IPM cards to optimize func- ing as a stable modular/reconfigurable 3U/6U/9U structure, IPM/ tional component/circuit requirements. Custom combined card/ Carrier Modules (shown in Figure 12), can be developed, inte- carrier modules may be supplied by vendors, as long as the me- grated and upgraded with minimum efforts. Packaging standards chanical/electrical interface specifications remain compatible implemented under VMEbus: IEC 297-3[21], Eurocard Mechani- where the module/wiring panel integrates. cal Packaging [17] and IEC 917/DIN 43355 [15] connector, de- fine the mechanical/electrical interconnects between instruments, Figure 14. SATS 6U Instr/Power Mezzanine Card/Carrier Module power, switch/matrix and Receiver Fixture Interface elements. As shown in Figure 13, the 3U IPM/Carrier Modules structure supports a scaleable 1.5U/3U Instrument/Power Mezzanine Card that is plugged on to a 3U Carrier Module. This IPM/Carrier SEE 3U FOR TOP VIEW DIMENSIONS structure supports a broad range of applications in which func- tionality can be packaged on the smallest 1.5U IPM card foot- BACK PLANE FRONT PLANE print, to a custom combined 9U card/carrier module footprint, 6.2992 FRONT PANEL BACK PANEL capable of supporting a vector analyzer capability. The 0.1181 plug&play design also permits easy reconfigurability, 2.1803 expandability, and upgradeability without modification each time functional change is dictated. 0.6811

0.1000 Figure 13. SATS 3U Instr/Power Mezzanine Card /Carrier Module

Adjacent Rear Chassis IPM Carrier Module Adjacent Forward Instrument/Power Wiring Panel Rear/ 3U High Supporting Chassis Wiring Panel Mezzanine (IPM) Card Front PCI Connector Two IPM Cards Rear/Front PCI Connector

0.0350 0.0777 0.0500 0.0500 10.3091

0.1120 0.5906 5.8039 1.5743 1.5447 1.1960 1.2000 0.5900 1.2 in Center Line BACK PLANE FRONT 0.2306 1.6717

0.0500 2.2000 0.1181 BACK PANEL 0.0500 FRONT PANEL 0.5900

5.8039

1.6717 0.1000

2.2000

5.0591

3.9370 2.1803 0.1000 0.1000 0.4811

0.1000

0.1000 0.1100

1.4717 1.5585 1.6609 6.2992 0.3000 0.3000 6.0039

UNLESS OTHERWISE SPECIFIED 1. DIMENSIONS ARE IN INCHES. INTERPRET DIMENSIONING PER ANSI Y14.5M - 1994 2. FOR DIMENSIONS IN INCHES TOLERANCES ARE: 1.0610 0.1100 `0.010 FOR ALL 2 PLACE DECIMALS Modular Integratio `0.005 CarrierFOR ALL 3 PLACE DECIMALS Module `0.0005 FOR ALL 4 PLACE DECIMALS The Complete Source for Your E `1/2~ALL ANGLES `1/64'' ALL FRACTIONS 315A W OOTTON ST R EET 1.7717 1.4717 TITLE: DRAFTSMANConnectorAdministrator 10/4/2002 Side

CHECKER XX 0.1500 PRJ. ENG. ComponentXX IPM Back Side SIZE: DWG 3U-Daught MFG. APRVL.MountingXX AreasB NO: NEXT HIGHER ASSY: SCALE: ENG. RE E. Wiring Panel /Backplane Specification Component XXX XXX X:X REF XX Mounting Areas IPM Connector Side Component Mounting Areas The SATS Wiring Panel/Backplane construction is a scalable structured interconnect bus design that can be hybridized/cus- Common carrier modules can support any number of functional tomized to meet unique test system requirements. It is the most I/PM Cards through standard engagement/interoperability con- flexible aspect of any SATS implementation serving primarily nectorization. The Carrier Module also provides the embedded as the substitution for wire in current ATE configurations. Serial Interface Control, Switch Matrix, and Test/Power Bus in- terface. Standardization of IEC 917 (DIN 43355) / IEC 603-2 Digital I/O, Measurement and Stimulus Instrument/Power Mod- (DIN 41612) Connector Specification at the dual interface points ules (IPM) will apply current VXI Consortium and VXIplug&play of the Carrier Module and mating Wiring Panels points (see Fig- Specifications. SATS extends these specifications by applying ure 9). Combined, those features create a stable structural integ- the DIN 43355 Connector to a transition device that converts rity and interchangeability framework for the overall test system current VXI/PXI front panels to common SATS Carrier Module architecture. I/O Specifications. The DIN Connector, shown in Figure 59, provides direct signal interfacing direct to Expansion Bay Printed As described in Figures 13 and 14, the respective 3U and 6U I/ Wiring Panel eliminating wiring while maintaining consistent PM Card and Carrier Module Specification, IPM Cards are opti- matched impedance/signal loss pathways to and from the Instru- mized for double side board population and center short wire ment. Within the Expansion Bay Printed Wiring Panel (EBPWP), SATS is defining a Common Instrument Signal Bus (CISB) that X VXI/VME/PXI LEGACY SUPPORT can be matriced to other instruments through physical pin map- A. Technology Transition ping and/or switching. Through common output ports (pin maps SATS recognizes that solutions of the magnitude discussed will of instrument front panels), categories of instruments having com- not occur overnight and transitional support must be implemented mon pin maps can be interchanged, reconfigured/routed through into the design of SATS to grandfather existing systems into the CISB access to any number of points defined by the system inte- architecture. This will permit integrators and users to apply ex- grator without dramatic modification of the hardware. isting VXI instruments and cabling where direct interfaces do not exist. Transition extensions (translators) of the SATS archi- This Instrument Signal Bus architecture can be iterated between tecture allows existing VXI/PXI front panels or cabling to couple each chassis, as shown in Figure 4 thereby extending/expanding with follow-on standard printed wiring panels connectors. When the routing possibilities to either the UUT or other instrumenta- direct integration is possible (VXI/PXI front panels evolve to stan- tion. This layering process provides multiple benefits in reduced dard SATS), transition assemblies can be eliminated and the me- footprints of the hardware, elimination of costly/performance chanical structure directly coupled with its mating module inter- degrading wiring, and tremendous savings in producing main- face. The Augmentation bay, shown in Figure 16, reflects inte- taining and upgrading the product. Instrument selection, place- gration of translator modules with VXI, PXI Modules standards ment, and functionality become more transparent to the system (conversion to cableless interconnect). controller and/or Test Program Set (TPS) software operation, that in turn makes it more migratable between test systems. Figure 16. Hybrid Legacy/SATS Configuration

Hybrid SATSPower/ Connector Transistion Hybrid VME/PXI/SATS VXI Chassis Module B-Size/9U Bay Chassis IX. TEST SYSTEM INTERFACE TO THE UNIT-UNDER-TEST The IEEE P1505 Receiver Fixture Interface (RFI) Standard, Operator SATS Power Module Display shown in Figure 15, has been selected for the SATS Standard. It PXI/ Interface provides a common mechanical quick disconnect for connecting VME/ large numbers of electrical signals (digital, analog, RF, power, SATS IPM etc.), between source and recipient of those connections. (a.k.a. VXI Controller/ Modules Instrument General Purpose Interface, Mass Connect Interface, Test Inter- Module face System, Test Adapter, Interface Device, Interface Test RFI Receiver Adapter). The associated Fixture is thought of as the “buffer” Subsystem between the Unit-Under-Test (UUT) and Test System RFI Re- ceiver. Its UUT-specific role being to translate standard I/O sig- nal routing for as many as 5,600 pins offered at the Receiver to a Cooling Module Cooling Module wiring interface that directly connects to the UUT. These UUT interfaces can represent cable connectors, direct plug-in (printed circuit board edge connectors), sensor monitoring, or manual feed- B. Hybrid SATS Standard Implementation back from the test technician. Hybrid SATS Standard implementation will apply current VXI Consortium and VXIplug&play Specifications into SATS wiring Figure 15. IEEE P1505 Receiver Fixture Interface (RFI) Design panels and module packaging integration. The non-defined front 16 Slot Receiver panels are resolved by applying the DIN 43355 Connector to a transition device that converts current VXI/PXI front panels to Receiver Connector Modules and Contacts common SATS Carrier Module I/O Specifications. Power may be alternatively distributed from the Power Module front panel Four Slot Fixture with interfaces via the Augmentation Bay printed wiring panel, to ei- Cable/Strain Relief ther the Augmentation Bay, RFI system or UUT. These options Enclosure permit more efficient use of the available power and support as backup in event module failure. Suppliers are expected to apply features that reconfigure or program outputs to meet multi-appli- cations without augmenting resources. In standardizing on the IEC 917 DIN 43355 Connector, illustrated in Figure 5, through- Receiver Engagement out the SATS internal interfaces, common footprints and pin char- Mechanism Operator”s Handle acteristics can be defined. Fixture Connector Modules and Contacts Twelve Slot Fixture with Enclosure XI. SATS ATE APPLICATION AUTHORS BIOGRAPHY The Structured Architecture Test System (SATS) is the culmina- Michael J. Stora is President and CEO of Modular Integration Tech- tion of several years of study by both the government and indus- nologies, Inc. of Boonton NJ, (973)299-8321/ E-Mail: try to define a more structured approach to integrating VXI, PXI [email protected]. A member of the IEEE, VXIplug&play, VXIbus VME, IEC, RFI subset standards into a cohesive system solu- Consortium, current Chairman of the IEEE P1505, Receiver Fixture Interface Standards effort, past chairman of the IEEE 1149 Test Bus tion. This is done primarily to preserve test program rehostabil- Standard, and past chairman functions of the AUTOTESTCON efforts. ity, equipment reconfigurability, and technology evolution require- A Business Manager by education and past positions with Emerson ments. It further reduces customization/ augmentation, test pro- Electric, Raytheon, Harris, GenRad, and MAC Panel, Mike has been gram development, and interface costs, while increasing compe- directly involved with test technology for 25 years, a holder of four tition. patents, and developer of several industry test products.

Fundamental design is being developed through industry partici- David Droste is a BSEE graduate of the University of Evansville with pation to assure product viability and long-term commitments to 27 year career in military testing projects. In his twelve year tenure the standard. Several current government ATE programs such with the Government David led a team which produced over 100 AN/ USM-465 test program sets. At Harris for 11 years, he was responsible as RTCASS, ARGCS, JSF, and B1-B could benefit from the for the development of F/A-18 TPSs and MIL-STD-2165 testability standard’s process. SATS implementation, as illustrated in Fig- design efforts supporting Boeing on the P-3 ASW aircraft. Dave cur- ure 17, offers a fault-tolerant test system structure, that shares rently leads a team at PEI Electronics Inc., Huntsville Alabama, on the 35% of the assets, matrices test signal/power bus I/O to dual multi- Re-Entry System Test Set (RSTS) Program for the Minuteman III, port RFI, and reduces overall costs, build process and footprint MK12/12A Re-Entry Systems. Mr. Droste also serves as Co-Chair for by 50% of current ATE VXI/PXI/19” instrument hybrid system the IEEE-P1552, Structured Architecture for Test Systems (SATS) and solutions. The SATS program is actively seeking integrators Secretary for IEEE’s SCC20 Test and Diagnosis for Electronic Sys- and instrument suppliers to refine and implement the specifica- tems Standards Committee. tion. Figure 17. SATS RTCASS, ARGCS, B1-B Implementation REFERENCES [1] Electrical, Electronic Engineers (IEEE) Standards Organization; Piscat- away, NJ; URL:http://standards.ieee.org. ¥ Modular/Scaleable Plug&Play Composite [2] VMEbus; VITA-Scottsdale, AZ; URL:http://vita.com; ANSI- Washington, EnvironmentalSealed Chassis for Rugged Transportability/Easy Integration; DC; URL:http://ansi.org. [3] VXIbus; San Diego, CA; URL:http://vxi.org [4] PCIbus; Wakefield, MA; URL:http://picmg.com [5] PXIbus; Austin, TX; URL:http://vxipnp.org. [6] CompactPCI; Wakefield, MA; URL:http://picmg.com [7] Joint Service Automatic Test Systems Research and Development Inte- grated Product Team (ARI), govt/industry Critical Interfaces Working Group; USAF-CIWG Contract Report;, Washington, DC, 6/1/98. [8] IEEE SSC20 Technical Committee for the IEEE P1226.X, VXI Instru- ment Control; Piscataway, NJ; URL:http://standards.ieee.org. [9] IEEE I& M Technical Committee for the IEEE 488, VXI Instrument Con- trol; Piscataway, NJ; URL:http://standards.ieee.org. [10] IEEE P1505 I& M Technical Committee for the Receiver Fixture Inter- face; Piscataway, NJ; URL:http://standards.ieee.org. [11] VXI Consortium-VXI Hardware Specification 1.4; San Diego, CA; URL:http://vxi.org. [12] VXIplug&play Operating Systems and Instrument Drivers, VPP-3/4; Aus- tin TX; URL:http://vxipnp.org. [13] EIA Standard, RS-310-C, Racks, Panels and Associated Equipment; EIA- Arlington, VA; URL:http://eia.org [14] ANSI, VME/VME-64 Hardware Standard; VITA-Scottsdale, AZ; URL:http:/ /vita.com; ANSI- Washington, DC; URL:http://ansi.org. [15] IEC 917 (DIN 43355) / IEC 603-2 (DIN 41612) Connector Spec; IEC- Chicago, IL; URL:http://iec.org; DIN-Berlin Germany; URL:http:// ¥ External Heat Exchanger with Sealed Internal Pressurized Cooling SystemProtects Against en.din.de. Environment Quiet Ops; [16] M-Module Mezzanine Spec-VITA 12; Scottsdale, AZ; URL:http://vita.com. [17] Eurocard VME/VXI/PCI/PXI Packaging; EIA Standard, 60796-3, 15 Feb ¥ Cableless Modular/Scaleable Plug&Play 3U/6U/9U IPM Module and Wiring Panel Con- 1990, Racks, Panels and Assoc Equipment; EIA-Arlington, VA; URL:http:/ struction Offers Easy Mftrg, Maintenance, and Technology Insertion; /eia.org [18] Infiniband Trade Assoc; URL:http://infinibandta.org ¥ Switched Matrixed Bus Integration Supports Shared Assets and Multi-Port Test Interface Access; [19] Rapid I/O Trade Assoc; URL:http://rapidio.org [20] PCI Express Trade Assoc; URL:http://pcisig.com ¥ High Speed Serial Bus Control Supports Point-to-Point Control at a 12GHz Rate; [21] VMEbus: IEC 297-3; IEC-Chicago, IL; URL:http://iec.org [22] IEEE 1014; Piscataway, NJ; URL:http://standards.ieee.org. ¥ Open High Performance Receiver Fixture Interface Offers 2.0 GHz High Speed Digital,Fiber [23] VXIbus IEEE 1155 Eurocard Mechanical Packaging; VXIbus-San Diego, Optics, 60GHz Distributed Pin Map, and Direct Cable Access. CA; URL:http://vxi.org; Piscataway, NJ; URL:http://standards.ieee.org.