“ATE Open System Platform” IEEE-P1552 Structured Architecture for Test Systems (SATS) Working Group Cochairmen Michael J. Stora ; Modular Integration Technologies, Boonton, NJ; [email protected] David Droste; PEI Electronics Inc., Huntsville, AL; [email protected]
Abstract- The IEEE-P1552 Structured Architecture for Test Systems (SATS) Standards effort, is a multidimensional ATE “Open System Platform” packaging specification. The Standard defines data/signal/power interconnect mechanical/electrical mating connector requirements and common hardware packaging form factors. Addressed are plug&play wiring panels, switchable instrument/power mezzanine (IPM) modules, high speed serial bus control, and test bus matrix functionality, that permit subelement interchangeability and interoperability. The standard’s functional performance requirements are limited to mechanical engagement, connector styles/footprints, electrical pin characteristics, and pin mapping defi- nitions. As a higher order plug&play architecture SATS supports legacy VXIbus and PXIbus architectures as hybrid subsystem integrations.
I. INTRODUCTION In conjunction with the SSC20 Liaison Standards Subcommittee of the Institute of Electrical, Electronic Engineers (IEEE) Stan- dards Organization [1], a new multidimensional ATE “Open Sys- tem Platform” packaging standard has been initiated under IEEE- P1552 Structured Architecture for Test Systems (SATS). An ar- chitecture that will have profound impact on current test com- puter-busboard systems in reducing costs and size, while improv- ing performance and supportability.
The key to ATS Integration and Test Program Set (TPS) cost re- duction/avoidance requires us to reduce variations of the soft- ware /hardware interfaces between ATS. Standardization func- tionally defines and provides guidelines for developing the inter- faces within a ATS. Applying these standards with Commercial Off The Shelf (COTS) modular compatible pluggable modules, the ATS structure becomes more homogenous in its integration and supportability. This open architecture approach avoids unique government requirements and associated nonrecurring costs, en- Figure 1. SATS Multi-Dimensional Plug&Play Interconnectivity hances product availability/performance, and benefits from in- dustry investment/technology. A preliminary set of specifications has been developed and is undergoing refinement under the IEEE Standards Organization SATS replaces/extends the current two dimensional plug and play process. Meetings are planned for IEEE, NEPCON, and AS- computer-based architecture of VMEbus [2], VXIbus [3], PCI- SEMBLY TECHNOLOGY trade shows to broaden participation. bus [4], PXIbus [5], and several other standards into a multidi- mensional integrated hardware architecture, as conveyed by Fig- II. TECHNICAL PROBLEM ure 1. Under the SATS Frameworks, Instrument/Power Mezza- The technical problem of this Standard was first addressed by nine (IPM) Carrier Modules and Serial/Test Bus Integration, the Department of Defense memorandum OSD (A&T) - 29Apr94, current 2-D backplane is reconfigured into 3-D matrix wiring DOD Policy for Automatic Test Systems, by direction of Noel panels supporting control, power, and signal interconnectivity. Longuemare. The following memo caption reflects on the in- tent of Mr. Longuemare’s directive and serves to lead our ef- Legacy VMEbus, VXIbus, PCIbus, PXIbus Standards are sup- forts; “ATS capabilities shall be defined through control of criti- ported through a hybrid process that integrates respective back- cal hardware and software elements and interfaces to ensure DOD plane standard characteristics with SATS wiring panel specifica- family tester and COTS tester and component interoperability, tions. Legacy standards can choose to integrate current front and to meet future DOD test needs”. connectors to SATS wiring panels, or convert to the SATS com- mon CompactPCI [6] connector family. SATS reduces dissimi- A joint government/industry Critical Interface Working Group lar front panel connector proliferation and eliminates wire be- (CIWG) effort furthered this ATS interface standardization pro- tween chassis systems. This has the potential of reducing Auto- cess. It was conducted under the auspices of the military Joint matic Test Systems (ATS) material costs, labor, test time, and Service Automatic Test Systems Research and Development Inte- support by 40%. grated Product Team (ARI), by a combined government and in- dustry Critical Interfaces Working Group[7]. The CIWG objec- specifications through fabrication of multivendor/multifunction tives were to identify the critical ATS interfaces that impacted prototype modules that would be integrated into working SATS interoperability/interchangeability of system hardware and test architecture. The (third) objective is achieving Users and Inte- program set transportability. Although the results established grators recognition and acceptance of the Standard(s), that in turn clear definitions of the critical interfaces, very few could relate will drive vendor/supplier requirements. This represents a de- to commercial interface standards, beyond existing VXI, com- parture from previous Test Standards that were established by puter data interfaces and government specifications. supplier/vendor motives, and therein reasons for their respective limitations. The remaining issues of the technical problem are those critical packaging and interconnect hardware interfaces not addressed Success will be measured by SATS ability to: (a) align with COTS by current industry standards. Hardware interfaces relate pri- - Commercial Off The Shelf products, that are designed to exist- marily to packaging and data/signal/power interconnect standards. ing commercial standards, i.e. IEEE, Eurocard, VXI, VME; (b) These standards typically define mainframe and subelement (mod- reduce costs by exploiting commercial investment, limited non- ule) mechanical/electrical mating specifications, that should per- recurring integration development, and competitive pressures; (c) mit subelements to be interchanged without impact to subele- improve availability and interoperability through common archi- ment interoperability. The functional performance of the stan- tectures and multivendor product offerings; (d) improve test pro- dard is normally limited to mechanical engagement, connector gram set transportability; (e) increase ATS supportability through styles/footprints, electrical pin characteristics, and pin mapping standard acceptance, available technical/spares third-party sup- definitions. This permits various vendor products (subelement/ port tools and resources; and (f) assure longer product life by module) to interoperate (plug & play) with no or minimum modi- structuring the architecture for future commercial subelement pre- fication by the integrator or user. Functional performance speci- planned product improvements and ATS technical insertion. fications of unique subelement capabilities, that exceed interop- erability requirements are typically relegated to the integrator/ IV. SATS GENERIC INTERFACE ARCHITECTURE user to define. The following diagram, Figure 2, illustrates the traditional VXI based ATS hardware/electrical connector interface elements em- III. OBJECTIVES OF THE SATS STANDARD EFFORT ployed: (a) Rack/Chassis Mechanical Integration Structure; (b) The mission of this Standard effort are threefold: (first) to estab- Computer Control Interface; (c) VXI/IEEE-488 Instruments; lish ballot ready specifications for the Structured Architecture (d) Power Distribution; (e) Cabling/Signal Interconnects; and for Test Systems (SATS) Standards; and (second) validate those (f) Receiver Fixture Interface Subsystem. Figure 2. Traditional VXI/IEEE based ATS hardware/electrical generic interfaces V. RELATED STANDARDS ACTIVITIES ity/technical insertion and general reuse more effectively. By The SATS Program minimized its specification development pro- distributing the Switch Matrix Bus Architecture from the Carrier cess by embracing current or planned Standards efforts. The fol- Module (functional access port), to the RFI System (UUT access lowing represents many of those being implemented under SATS: port), in a scalable and software selectable manner, I/O (a) IEEE SSC20 Technical Committee for the IEEE P1226.X, VXI selectability instrument sharing, fault tolerance, and system di- Instrument Control [8]; (b) IEEE I&M Technical Committee for agnostics are enhanced. the IEEE 488, VXI Instrument Control [9]; (c) IEEE P1505 I& M Technical Committee for the Receiver Fixture Interface [10]; As the next generation to the current VXI/VME instrument/mod- (d) VXI Consortium for the VXI Hardware Specification 1.4[11]; ule control standards, the SATS Frameworks “open” mechani- (e) VXIplug&play Operating Systems and Instrument Drivers, cal and electrical packaging specification implements: VPP-3/4[12]; (f) EIA Standard, RS-310-C, Racks, Panels and 1) Mechanical Integration Structure (MIS) modular/scal- Associated Equipment [13]; (g) ANSI, VME/VME-64 Hardware able plug&play, cableless, environmental sealed, mainframe ar- Standard [14]; (h) IEC 917 (DIN 43355) / IEC 603-2 (DIN 41612) chitecture, utilizing EIA Electronic Rack Specifications [17], Eu- Connector Specifications [15] and (i) M-Module Mezzanine rocard Mechanical Packaging and DIN 43355 Connectors Stan- Specification VITA 12[16]. Other Standards and related Organi- dards; zations may be consulted for electrical and packaging specifica- 2) Plug-on Instrument/Power Mezzanine (IPM) Card pro- tions. visioning functionality at the lowest cost/technical impact and Common Carrier Module with 3U/6U/9U scaleability; VI. SATS STANDARD TECHNICAL APPROACH 3) Computer Control Distribution (CCD) high speed serial The SATS Standard defines and implements a scalable/modular/ bus control for instrument/functional operation, test signal/power cableless ATE “Open System Platform” packaging specifica- switch matrix distribution system management (see Figure 4); tion, conceptually shown in Figure 3, through an IEEE/IEC in- 4) Integrated scalable test/power distributed switch matrix dustry standardization process. The SATS architecture frame- for multi-asset selection/sharing; work and respective seven (7) interfaces are intended to mini- 5) IEEE-P1505 Receiver Interface with I/O switchable and mize design development by reducing complex functionality to scalable from 4 slot cable/PCB connector interface to 29 slot the level of a plug-on mezzanine card (IPM). This minimizes multi-OTPS Fixture engagement; and impact to the integrated Carrier Module, Wiring Panel, and RFI 6) Support for legacy VME/VXI/PCI/PXI test standards. structure, thereby accommodating reconfigurability, upgradeabil-
¥ Integrated Receiver Fixture Interface (RFI)
¥ SATS-RFI Integration Printed Wiring Panel
¥ Modular/Scaleable Plug&Play Composite Environmental Sealed Chassis
¥ Modular/Scaleable Plug&Play 3U/6U/9U IPM Module Implementation (configuration shown supports 12 Slots, 3-9U high, B Size depth Modules w/72 IPM Cards)
¥ SATS-IPM Module Integration Printed Wiring Panel
¥ External Heat Exchanger with Sealed Internal Pressurized Cooling System
Figure 3. SATS Typical Multi-Framework ATE “Open System Platform” VII. ELECTRICAL SYSTEM INTEGRATION FRAMEWORKS board transmission lines designs permit signals to reach 18GHz A. ESI Overview bandwidths. ATE signal integrity and repeatability under The Electrical System Integration (ESI) Specification defines plug&play PCB construction, also dramatically improves pro- the overall SATS Frameworks electrical interconnect system, con- ducibility, as well as reduce integration and test acceptance times nectorization, switching network, and electrical bus pathways for by 40%. A greater gain is achieved by through lower mainte- power, control and stimulus/measurement test signals. The dia- nance support costs (40%), and product technology insertion/evo- gram (Figure 4), correlates to the atypical configuration shown lution costs (60%). in Figure 3, reflecting general interfaces and related elements of the electrical frameworks and their respective relationships. When The ESI specification supports/embeds three distribution sub- implemented under a plug&play architecture, that utilizes ad- systems within the plug& play board/wiring panel fabric. They vanced high speed digital/RF printed circuit board technology, are: (a) the Computer Control Distribution (CCD) Subsystem; considerable benefits accrue. Specifically, it embeds and directly (b) the Power Switching/Distribution Bus (PDB) Subsystem; couples control, power and test signal bus pathways between the and (c) the Test Signal Switching/Distribution Bus (TSD) Sub- test system controller, instrument/power resource, and the UUT system. The Eurocard DIN 43355 Connector serves as common interface. The advancement of embedded RF printed circuit interconnect between board/wiring subelements.
Figure 4. Electrical System Frameworks Integration Overview
System Serial Control Bus Signal/Low RF Test Bus High RF Test Bus Power Test Bus
IEEE488/Ethernet/Serial Bus
Instr/Power Instr/Power Instr/Power External Resource Bay Mezzanine Mezzanine Mezzanine External Instrument/Power for VME Chassis (IPM) Card(s) (IPM) Card(s) (IPM) Card(s) Rack Mount Resource and & 3U Carrier & 3U Carrier & 3U Carrier Instrument B-Size (6U) Module or Module or Module or Modules Custom 3U Custom 3U Custom 3U Module Module Module
Envirmt/Diag Cntrl Embedded/External/Multi- Power Distr Control Computer Timing& Synch Subsystem(s) System Interrupt System Serial Bus
IEEE488/Ethernet ATE Host CPU Instrument/Power Instr/Power Mezzanine (IPM) Mezzanine (IPM) Card(s) Operator Interface Card(s) & Carrier and Display 6U Module & 3U Carrier - or - Module or Custom 6U Module Custom 3U Module
External Resource Bay S S i i for VXI/PXI Chassis g g Switch/ n Recvr a n Fixture and Instrument Routing Frame- l a Frame- Circuit, work l work/ C-Size (6U) Modules Signal and Enclo- Unit Conditng, Mech P sure Under Active P o Test Drive o and Instr/or Assy w w Plug-in/ (UUT) Personlty e e Direct Instrument/Power Mezzanine (IPM) PCB r r Mount Card(s) & Carrier 9U Module Module Assy R - or - R F F Custom 9U Module
Wiring Panel Bus Interconnect Subsystem Receiver Fixture Interface Subsystem Fixture Plug-in Circuits/ Modules B. Computer Control Distribution (CCD) Subsystem Spec C. Power Switching/Distribution Bus (PDB) Subsystem Spec Use of an advanced computer serial bus network embraces com- Power Switching/Distribution Subsystem (see Figure 7), com- puter industry trends as reflected in Figure 5. This distribution bines distributed primary 48 Volts Direct Current (VDC) Bus with subsystem (see Figure 6 illustrating Rapid I/O implementation), DC-DC Fixed/Programmable Instrument and Power Mezzanine incorporates physical electrical pathways that will host any num- (IPM) Submodules. Outputs from these DC-DC IPM’s are swit- ber of advanced Computer Standards, such as Infiniband[18], chable to the System Power Distribution Bus Matrix which feed Rapid I/O [19], or PCI Express [20]. system resources or Unit-Under-Test (UUT) power requirements. Figure 5. Serial Bus Network and Distribution Subsystem Spec The power switch matrix design incorporates a: (a) 30 amp [30A] High Current Primary 48VDC Feed and Multi-Return/Ground Device Device Lines; (b) 16 wire - 8 output scalable System Power Distribution P • Packet Switched Very Bus Matrix; and (c) Power Bus Entry Level Switching at the IPM e • Point-to-Point Switch Fabric High S r • Low Pin Count Frequency and In-line Receiver Fixture Interface (RFI) Power Switching. y f Figure 7 Power Switching/Distribution Subsystem Spec s o Device Device 120/240 48VDC t r Power Entry VAC Primary Bridged Hierarchy AC/DC e m Device Device Input Power Module Broadcast <133MHz Power Feed/ m a Source Power Examples: PCI, PXI, Source Return n Device Switch R Bridge Device Device VME, VXI Module c Power Mezzanine e F DC/DC Card i e Fix/ProgmDC c U Resource/UUT Power e x Single Segment Broadcast <33MHz Power IPM Control U Power Output Switch i t Examples: CompactPCI, VME, VXI Switch Carrier Module Module T v u r Device Device Device Device Device Device Power Mezzanine e DC/DC Card Fix/ProgmDC Power r e Resource/UUT Switch Device Device Device Device Device Device Power IPM Control Power Output Module Switch Carrier Module
Fix/ProgmDC This distributed network fabric will incorporate advanced trans- Custom Power Resource/UUT w/Control &Switch Power Output 2x8 Scalable mission line technology facilitating network speeds to 12G Bytes Module Power Distribution Matrix Bus performance. Employing parallel-multi-serial lines interface fabric, distributed multi-task control, and segregated node con- D. Test Signal Switching/Distr Bus (TSB) Subsystem Spec trol points, the test system control can achieve both speeds and SATS defines an advanced distributed test signal switching fab- technology evolution without impact. ric, as shown in Figure 4 and 8, that routes resource signals to a Figure 6. Serial Bus Network and Distribution Subsystem Spec wide matrix of pin map contacts at the UUT interface. It in- cludes: (a) Resource-to-Bus Entry Switching at the Instrument Figure 8. Test Signal Switching/Distribution Subsystem Spec Inside the Box Box to Box