3 ASIC HIGHLIGHTS

INTRODUCTION

The term ASIC (application specific ) has been a misnomer from its first use. ASICs are really customer specific ICs; a gate array or IC that is specifically made for one customer. ASIC, if taken literally, would mean the IC is created for one particular type of system, such as a disk-drive, even if this IC is sold to numerous customers or is put in an IC man- ufacturer’s catalog. An IC type that is sold to more than one user, even if it is produced using ASIC technology, is considered a standard IC.

The nomenclature guidelines presented in Figure 3-1 help to clarify this confusion that surrounds the use of the term ASIC.

ASIC: An application specific IC is produced for only one customer. PLDs are included as ASICs because the customer programs them for its needs only.

CSIC: Customer specific ICs are what ASICs should have been called initially. Some companies differentiate an ASIC from a CSIC by who completes or is responsible for the majority of the IC design effort. If it is the IC producer, the part is labeled a CSIC; if it is the end-user, the device is called an ASIC. Unfortunately, this term is not used often in the IC industry.

ASSP: Application specific standard product ICs target specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques), but will ultimately be sold as a standard IC to numerous users (i.e., put into a product catolog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the IC before it is made available to competitors.

CSP: Customizable standard products are 70 to 90 percent standard with 10 to 30 percent of the chip available for user-specified logic, memory, or peripheral functions. A CSP can be an ASIC device if it is sold to only one customer.

Source: ICE 19181D

Figure 3-1. ASIC Terminology

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One problem many IC producers have run into while producing application specific standard product ICs (ASSPs) is that to provide the optimum part, the IC producer must understand the system application as well as the end-user. Because this system-level expertise is not easy to acquire, most ASSP suppliers have formed close relationships or partnerships with end-users. In this way, the IC supplier and user work closely together early in the system design cycle to prop- erly define the needed ASSPs.

In general, as standard ICs take aim at ever finer segments of the IC market, they ultimately evolve into ASSPs. In other words, at some point in time there could be very few standard ICs; most ICs produced would be aimed at specific system needs. For example, certain DRAMs are architec- turally optimized for hand-held telecommunications systems, laptop personal computers (PCs), or high definition television (HDTV) sets. This is precisely the direction the IC industry is heading.

As IC producers customize their products for specific system needs, the list of ICs labeled as ASSPs continues to expand. In 1997, Alcatel-Mietec introduced an ARM core-based ISDN chip- set (Figure 3-2). The chip set is produced using a 3V 0.5µm CMOS mixed-signal process. It doesn’t take too much imagination to visualize a one-chip ASSP solution sometime in the near future. As was mentioned earlier, 20 years from now there may be few standard ICs produced.

AGND Analog Proprietary (DSP) JTAG Support Filter Engine TAP

Interface ROM

D/A Logic RAM ARM7TDMI Core A/D Serial

Port

Pulse Shaper S-Interface GCI Logic Logic Detector

Source: Alcatel-Mietec/EET 22707A

Figure 3-2. Network-Termination IC Borrows ARM CPU

A few years ago, Motorola introduced the concept of customizable standard products (CSPs, Figure 3-3). A CSP allows a small portion of user-specific logic to be introduced into a standard product design. The customized logic can be complex function blocks (CFBs), for example, an ATM cell , or other circuitry from Motorola’s standard cell or gate array libraries.

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ASSP Application MC92xxx Specific Standard CFB Product CSP Customizable Platform Diffused Memory Customizable Architectures Standard Standard Product User-Specific Logic

CFB-Library CFBs- CSP Elements Application Customizable Driven Standard USL Product

Source: Integrated System Design/Motorola 21034

Figure 3-3. Motorola’s CSP Design Flow

Basically, ASSP circuitry is entirely designed by the IC producer. On the other hand, a CSP IC always contains some of the end users’ unique circuit design or circuit interconnection.

A CSP IC is usually classified as an ASIC because it is sold only to the customer that defined the unique circuitry portion. Moreover, like an ASIC, Motorola’s CSP program has non-reoccurring engineering costs starting at $100,000 and design cycle times that are typically 90 days.

Although the 1996 ASIC market was about $17.6 billion, including full custom, ASSP products, which are part of the special purpose metal-oxide-semiconductor (MOS) logic category, are taking away some of the ASIC market momentum (Figure 3-4). Overall, the ASIC market is forecast to follow total IC industry growth rates closely.

Does the proliferation of ASSPs and more customer-specific standard products mean an end to the ASIC market? No. This is because most of the pros and cons of ASICs versus ASSPs or standard products still exist.

The primary advantage of ASSPs or standard products is the ability to immediately (most of the time) purchase the ICs and get a system to market quickly. However, ASICs allow the system pro- ducer to differentiate its product from competition. The result is that many times the system man- ufacturer is able to gain market share and better profit margins.

In some cases standard products and ASICs are merging in an attempt to offer the benefits of both approaches. In 1993, Texas Instruments (TI) announced that it was merging an enhanced version of its standard fixed-point TMS320C25 (DSP) and 15,000 usable and cus- tomizable 0.8µm CMOS gate-array gates on one IC. Thus, the user is able to take advantage of well-characterized high-performance DSP circuitry while adding unique features to give its system a differential advantage over competitors. About 35 percent of TI’s total DSP IC sales in 1996 were in a customizable version. This percentage is expected to rise to over 50 percent in 2001.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-3 ASIC Highlights

8 7.39

7 Ð13% 24% 6.41 Ð6% 5.98 6.15 6 26%

5 4.74

26% 4 3.75

3 Billions of Dollars

2

1

0 1992 1993 1994 1995 1996 1997 (EST) Year

Source: ICE 20204E

Figure 3-4. Special Purpose MOS Logic Market (1992-1997)

In another example that confuses definitions, Cirrus Logic takes one of its ASSPs and customizes a portion of it for one of its customers. Typically only about 5 to 10 percent of the new design is customized for the end-user. This special IC is still normally classified as an ASSP since the major- ity of the circuitry is still ASSP-based.

There is no question that the IC industry will continue to evolve toward products that are specif- ically suited for customers’ needs. ICE believes that various versions of ASICs and ASSPs will co- exist to help serve those needs in the most economical and efficient manner possible.

ASIC Definitions

Formal definitions for ASICs and ASSPS are given in Figure 3-5. According to ICE’s definition, ASICs include gate arrays, standard cells (sometimes called cell-based), full custom, and pro- grammable logic devices (PLDs).

ICE does not include ASSPs in its ASIC market figures. An example of an ASSP part that is not classified as an ASIC by ICE is Hitachi’s H8/300H Series of . Although the H8/300H user is able to customize this using an extensive Hitachi cell library, the finished ICs are almost always allowed to be sold to other Hitachi customers after a certain period of time. Motorola has a similar program using its 68HC05 microcontrollers.

3-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

I. ASIC Semicustom IC - A monolithic circuit that has one or more customized mask layers, but does not have all mask layers customized, and is sold to only one customer.

Gate Array - A monolithic IC usually composed of columns and rows of , organized in blocks of gates. One or more layers of metal interconnect are used to customize the chip. Sometimes called an uncommitted logic array (ULA).

Linear Array - An array of transistors and resistors that performs the functions of several linear ICs and discrete devices.

II. ASIC Custom IC - A monolithic circuit that is customized on all mask layers and is sold to only one customer. "System-on-a-chip" devices are typically custom ICs.

Standard Cell IC - A monolithic IC that is customized on all mask levels using a cell library that embodies pre-characterized circuit structures. ICs that are designed with a silicon compiler are included in this category. Most embedded arrays are included in this category because all mask layers are customized.

Full Custom IC - A monolithic IC that is at least partially handcrafted. Handcrafting refers to custom layout and connection work that is accomplished without the aid of a silicon compiler or standard cells.

III. ASIC Programmable Logic Device (PLD) - A monolithic circuit with fuse, antifuse, or memory cell-based circuitry that may be programmed (customized), and in some cases, reprogrammed by the user in-system or prototype form.

Simple PLD (SPLD) - Usually a PAL or PLA, typically contains less than 750 logic gates.

Complex PLD (CPLD) - A hierarchical arrangement of multiple PAL-like blocks.

Field Programmable Gate Array (FPGA) - A PLD that offers fully flexible interconnects, fully flexible logic arrays, and requires functional placement and routing.

Electrically Programmable Analog Circuit (EPAC) - A PLD that allows the user to program and reprogram basic analog functions.

IV. ASSP - Application specific standard product ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques), but will ultimately be sold as a standard IC to numerous users (i.e., put into a product catalog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the IC before it is made available to competitors.

Source: ICE 13660J

Figure 3-5. ASIC and ASSP Definitions

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Motorola also has a so-called FlexCore program that allows an end-user to use its 32-bit micro- processors as cores in cell-based designs. This program is significantly different from its, and Hitachi’s, microcontroller ASSP offerings in that the finished ICs will most likely stay proprietary to the original customer. Thus, these ICs are considered to be standard cell ASICs.

The FlexCore and CSP-type ASIC programs are prime examples of why ASSPs will not eliminate the market for ASICs. As was mentioned earlier, ASSPs will still hold an advantage in time-to- market, but they will never be able to compete with the product differentiation capabilities of robust ASIC offerings such as FlexCore and CSP.

Another ASIC segment that needs additional clarification and discussion is the programmable logic device (PLD) category. ICE includes under the generic term PLD simple bipolar fuse-programma- ble array logic (PAL) ICs produced by Advanced Micro Devices (AMD) and TI, complex program- mable logic devices (CPLDs) that typically have configurable macrocells, multiple feedback paths, and are usually MOS-memory cell-based, and field programmable gate arrays (FPGAs).

The FPGAs are produced using MOS memory cells, which makes them usually reprogrammable, or antifuse technology. The physical line lengths and electrical characteristics of the interconnects are unknown before programming, just like a gate array.

As was shown, the PLD classification now encompasses a broad range of products and most experts in the IC industry are aware that the term PLD is no longer synonymous with the obso- lete bipolar fuse-programmable PAL.

Another definition clarification is in the standard cell category. In many of the standard cell designs, ASIC suppliers use a combination of pre-characterized and hand-crafted circuit struc- tures. ICE categorizes an ASIC that has 50 percent or more of its circuitry composed of cells as a standard cell IC. If less than 50 percent of the circuitry is from pre-characterized cells, with the majority of the design being hand crafted, the IC is considered a full custom ASIC.

Another IC that deserves further discussion is the embedded array ASIC. When designing with this IC, the customer first identifies any mega-cell functions that will be needed. The ASIC pro- ducer optimizes the layout of the cell-based design and then begins producing base wafers. While the base wafers are being fabricated, the customer is finishing design work for the uncommitted random logic area, the gate array portion, that was set aside in the initial design. After base wafers are fabricated, the gate array area of the ICs is metallized.

The ultimate goal of the parallel random logic design and cell-based wafer fabrication efforts of the embedded array approach is to shorten the turnaround time encountered with standard cell ICs. Many embedded array producers are achieving turnaround times very close to those of gate arrays.

3-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Although both standard cell and gate array design and fabrication techniques are used on an embedded array, because all of the mask layers of the IC are customized for the user, ICE classi- fies embedded array ASICs (e.g., VLSI Technology’s Flex-Arrays) as standard cells.

In Status 1998 ICE uses terms such as available, total, raw, and usable when referring to gate den- sities. Figure 3-6 shows gate count definitions used by ICE. Typical usable gate counts for vari- ous ASICs are shown in Figure 3-7.

AVAILABLE, TOTAL OR RAW GATES The number of unconnected gates on an IC.

USABLE OR WIREABLE GATES The number of gates that can typically be interconnected implementing an average design. Usable gate count will always be less than the number of available, total, or raw gates.

Source: ICE 16779B

Figure 3-6. Gate Count Definitions

ASIC Type Usable Gate Percentage

Double-Level Metal MOS PLD 30 - 50

Triple-Level Metal MOS PLD 60 - 70

Double-Level Metal Channelled Gate Array 85 - 95

Double-Level Metal Channelless Gate Array 40 - 50

Triple-Level Metal Channelless Gate Array 60 - 70

Four-Layer Metal Channelless Gate Array 40 - 60*

Five-Layer Metal Channelless Gate Array 60 - 70*

Standard Cell 85 - 95

Full Custom 100

*For devices with more than one million total gates

Source: ICE 16780C

Figure 3-7. Sampling of Usable Gate Counts

As total gate densities have increased, IC manufacturers have had to go to a greater number of metal interconnect levels to keep size and usable gate count percentages reasonable. This has been especially evident with the new triple-level metal PLDs. The new PLD technologies are help- ing reduce PLD die size dramatically, and in turn, significantly reduce manufacturing costs.

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The move to a greater number of metal layers comes with cost and complexity problems. With an increasing number of ASIC designs being pad limited, where die size is dictated by the number of input-output (I/O) pads rather than the area, the move to more layers of metal has pro- ceeded very slowly in the ASIC user base.

ASIC PRODUCT LIFECYCLE

Figure 3-8 shows the 1997 location of each major ASIC family on a product lifecycle curve. It is interesting to note that most of the classifications still reside near the growth side of this curve. As the ASIC market matures, the majority of ASIC products will be in or approaching the maturity stage of their lifecycles in the late 1990s.

Low density gate arrays (i.e., less than 20,000 gates) are considered to be in the saturation to declining stage. Currently, many gate array suppliers do not encourage accepting designs for low gate count arrays. As veteran IC buyers know, once products enter the latter stages of their life- cycles, price becomes a secondary concern to availability. Likewise, bipolar -transistor logic (TTL) PLDs are quickly losing market share and are now entirely in the declining stage. As shown, replacement products for the bipolar TTL PLD and low-density gate array, such as MOS PLDs, are currently in the introduction or growth and maturity stages.

THE LOGIC MARKET

Similar to the total IC market, the use of MOS logic, including ASICs, has increased significantly in the computer and communications segments (Figure 3-9). ICE believes that this trend will con- tinue for the rest of the decade as system-on-a-chip standard cell ICs become more prevalent in the ASIC industry.

An analysis of the logic market provides a good background to study the ASIC market since a vast majority of ASICs perform some basic logic function within a system. Figure 3-10 shows the logic trends by technology. The most obvious trend shown on the graph is the tremendous growth of complementary MOS (CMOS) logic. In the time span shown, CMOS technology has grown from a minority process to the dominant process used in making logic ICs.

On the other hand, older technologies such as n-channel MOS (NMOS) and bipolar have been phased out. Also, emitter-coupled logic (ECL) technology, after maintaining about eight percent of the logic market share for several years, is forecast to account for less than one percent of the logic market by 2002. Many excellent performance characteristics of ECL and other older tech- nologies have been replicated in CMOS and combined bipolar and CMOS (BiCMOS) technologies in recent years. These two technologies will dominate not only the logic market, but all digital IC production in the foreseeable future.

3-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights s e l a S

Introduction Growth Maturity Saturation Decline and Obsolescence

PLD W/Memory Bipolar PLDs EPLD EPAC EEPLD Flash-PLD SRAM-PLD Antifuse PLD Full CMOS Gate Array CMOS Gate Array Custom (≥500,000 Gates) (≥100,000 and <500,000 Gates) CMOS Gate Array (≥20,000 and <100,000 Embedded-DRAM Gates) Mixed CMOS Gate Array Standard Cell Analog/Digital (<20,000 Gates) Standard Cell Digital Standard Cell

Embedded Arrays ECL Gate Arrays

GaAs Gate Array BiCMOS Analog Gate Array Arrays GaAs Standard Cell

Source: ICE 11642V

Figure 3-8. ASIC Products Lifecycle: 1997

Displayed in Figure 3-11 is the average selling price (ASP) for logic ICs during the past several years. The TTL SSI and MSI (small scale and medium scale integration) segments of logic ICs have remained essentially flat since the late-1980s. Meanwhile, MOS logic ASPs swelled in the mid- 1980s, stayed flat for several years, then rose again beginning in 1994 due to increased sophistica- tion and greater implementation of logic products in systems. The declining ASPs for the total logic market in 1996 and 1997 reflect inventory adjustment and overcapacity in the IC industry.

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Auto Military Auto Military 4% 3% Industrial 3% 1% Industrial 9% 9%

Communications 21% Computer Computer 1991 34% Consumer 1996 38% $10.0B 21% $22.5B

Consumer Communication 29% 28%

Source: WSTS 21718B

Figure 3-9. MOS Logic Use by System Type

100

90 23%

80 t

e 55%

k 70 18% r a 88%* M CMOS c i 60 NMOS g 90%* o 8% L

l

a 50 93%* t o

T ECL

51% f o 40 10% t n e c r 8% e 30 P 4% 20 27% TTL and Other Bipolar 2% 10 6% 4% <1% BiCMOS <1% 3% 5% 0 4% <1% 1982 1987 1996 2002 $3.3B $11.6B $24.3B $62.4B (FCST) 1997 $25.6B *Includes 1% for GaAs (EST) Source: ICE 12875S

Figure 3-10. Total Logic IC Market Trends by Technology

As shown in Figure 3-12, ASICs are typically high ASP ICs. Considering that the average IC ASP in 1997 is estimated to have been $2.22, the overall ASIC ASP is expected to be almost four times as much at $8.39.

3-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

2.00

1.80 TTL SSI/MSI MOS Logic 1.60 Total Logic

1.40

1.20

1.00 ASP ($)

0.80

0.60

0.40

0.20

0.00 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997

Year Source: WSTS 20197E

Figure 3-11. Average Selling Prices for Logic ICs

12.00 11.00 10.00 10.10 10.00 9.00 8.00 7.00 6.75

) 7.00 $

( 6.20

P 6.00 S

A 5.00 5.00 4.00 3.00

2.00 1.40 1.00 0 Bipolar Linear Bipolar MOS MOS Full MOS PLD Arrays Gate Array PLD Gate Array* Custom* Std. Cell* and Std. Cell* ASIC Product Category * Not including NRE charges Source: ICE 21742B

Figure 3-12. 1997 ASIC ASPs

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While the ASIC market in dollars represents about 15 percent of the total IC industry, ASIC unit volume shipments are estimated to have been only four percent of the estimated 57 billion IC units sold in 1997.

ASIC MARKET FORECAST

ICE segments the ASIC market into three areas—semicustom including MOS and bipolar gate arrays and linear arrays, custom including MOS and bipolar cell-base and full custom ICs, and programmable logic including FPGAs.

ICE’s tabulation of the ASIC market trend and its forecast is shown in Figure 3-13. ICE estimates that in 1997, the ASIC market grew 11 percent. The catalyst for ASIC growth continues to be strong MOS PLD and MOS standard cell sales. By 2002, ICE forecasts that the MOS PLD market will be larger than the MOS gate array market. In fact, 1996 was the first year MOS standard cell sales surpassed MOS gate array sales. Figure 3-14 shows that the actual crossover occurred in late summer of 1996.

1992 1996 1997 1997/1996 2002 1992-2002 Market Segment ($M) ($M) (EST, $M) % Change (FCST, $M) CAGR MOS Standard Cell 2,280 6,700 8,845 32 34,110 31% MOS Gate Array 2,915 5,475 4,790 Ð13 7,320 10% MOS PLD 665 1,795 2,300 28 7,890 28% Bipolar Gate Array 970 510 460 Ð10 245 Ð13% and Standard Cell Bipolar PLD 275 65 40 Ð38 10 Ð28% Linear Arrays 185 240 245 2 295 5% Full Custom 2,650 2,800 2,850 2 3,150 2% Total ASIC 9,940 17,585 19,530 11 53,020 18%

Source: ICE 22708A

Figure 3-13. ASIC Market Trend and Forecast

As is evident, the mainstream IC market has moved away from bipolar-based ICs toward MOS- based technology. As a result, bipolar gate arrays, bipolar standard cells, and bipolar PLDs are forecast to be the poorest performing of all ASIC segments.

Even with the forecast calling for sustained growth, the ASIC market will represent 15 percent of the worldwide IC market in 2002. Fast growth in other IC segments such as DRAMs and microproces- sors will mirror the growth in the ASIC market in the long run. Therefore, even as the ASIC market increases, its percentage of the overall IC market will remain essentially unchanged from 1996.

3-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

625 600 575 550

) 525 M $ (

s 500 e l

a 475 S Gate e 450 g

a Array r

e 425 v A 400 h t n

o 375 M -

3 350 Standard Cell 325 300 275 250 April May June July Aug. Sep. Oct. Nov. Dec. Jan. Feb. Mar. April May June July Aug. 1996 1997

Source: WSTS 21724C

Figure 3-14. 1996 and 1997 Worldwide MOS Gate Array Versus MOS Standard Cell Sales

The forecasted cumulative-average annual growth rates (CAGRs) of specific ASIC product seg- ments are shown in Figure 3-15. Here, the high growth market segments, such as MOS PLDs and MOS standard cells, are exposed. The demise of bipolar ASICs is evident as well.

1992-1997 1998-2002 Product CAGR (%) CAGR (%)

MOS Standard Cell 31 31 MOS PLDs 29 28 Total ASIC 13 20 MOS Gate Arrays 18 5 Linear Arrays 7 4 Full Custom 2 3 Bipolar Gate Array and Std. Cell Ð15 Ð12 Bipolar PLDs Ð30 Ð26

Source: ICE 20195F

Figure 3-15. ASIC Product CAGRs

In 1986, full custom products accounted for more than half of the ASIC market share. Now, though this segment is growing ever so slightly in terms of dollars, it is continuing to lose market share to ICs such as standard cells (Figure 3-16). Full custom ASICs are forecast to represent only

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six percent of the total ASIC market share in 2002. Supercomputer manufacturers and the mili- tary are the best examples of full custom users. Since overall military spending is down and with supercomputer power available in desktop systems, it stands to reason that there will be less demand for full custom ICs. Meanwhile, standard cell ICs, which held a 38 percent ASIC market share in 1996, are forecast to account for 64 percent in 2002.

PLDs PLDs 10% 12% Standard Gate and Full Custom Standard Cell Cell 23% 1992 Linear Arrays 15% 1997 (EST) 45% $9.9B 40% Gate and $19.5B Full Custom Linear Arrays 27% 28%

Full Custom 6% Gate and Linear Arrays 15%

2002 (FCST) Standard Cell PLDs $53.0B 64% 15%

Source: ICE 16278P

Figure 3-16. ASIC Product Market Shares

Figure 3-17 forecasts the market for several logic technologies. By the size of the various markets shown in the graphs, it is evident that most designers and users have made the switch to MOS technologies to achieve the desired performance from their ASICs. The only IC category listed estimated to have shown significant growth in 1997 is the MOS standard cell.

Quarterly market size for the MOS gate array, MOS standard cell, MOS PLD, and bipolar PLD seg- ments are displayed in the next several charts:

In Figure 3-18 the MOS gate array market is shown peaking in late 1995. A moderate nine percent CAGR is forecast for this segment from 1998 through 2002 as the ASIC market moves more to using cell-based designs.

The MOS standard cell market is shown on a quarterly basis in Figure 3-19. While the market for MOS standard cells dipped in the first quarters of 1995 and 1997, overall it has been characterized by tremendous growth during the past few years. Besides being used in a broad range of appli- cations, the sizable market increase for standard cells might be explained by the fact that in recent years, many companies have reclassified their full custom ICs as standard cell products.

3-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

1,000 2,000 1,000 905 1,730 1,630 Ð10% s

s 1,575 790 r r 1,505 Ð6% 800 1,455 a Ð13% a Ð3% l l 1,500 19% l l

Ð3% o 635 650 o D D Ð20% 2%

1,080 f 600 f

Ð31% o o

1,000 435

845 s s Ð33% 390 n

n Ð22% 400 o o i i l l l l i Ð10% i 500 M

M 200

0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST) (EST) Year Year TTL/Other Standard Logic Market Bipolar Gate Array Market

400 100 90 335 85

s Ð6% s r

r 80 75 75 a l a 300 275 20% Ð12% 70 l l

l 65 Ð18% o Ð7%

o 15%

230 D

D 60 55 f Ð16% f 18% o

o 200

s

s 155 n

n Ð33% 40 o i o

110 l i l l i l Ð29% i 100

65 M

M 20 Ð41% 40 Ð38% 0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST) (EST) Year Year Bipolar PLD Market Bipolar Standard Cell Market 8,845

7,000 8,000 7,000 6,700 s 6,000 5,510 5,475 s r r

a Ð1% a l 4,790 l 6,000 32% l 5,000 4,480 l o Ð13% o 23% 4,860 D D 5,000

38% f 4,000 3,555 f o o 26% 4,000 3,585 s 3,000 2,845 2,915 s 36% n 22% n 2,745

o 2% o 3,000 i i 2,280 31% l l 2,065 l l

i 2,000 i 20% 2,000 10% M M 1,000 1,000 0 0 1991 1992 1993 1994 1995 1996 1997 1991 1992 1993 1994 1995 1996 1997 (EST) (EST) Year Year MOS* Gate Array Market MOS* Standard Cell Market *Includes BiCMOS and GaAs Source: ICE 18928H

Figure 3-17. Selected 1991-1997 Logic IC Markets

Figure 3-20 portrays the rise in quarterly MOS PLD sales dating back to 1991. Flexibility and quick time-to-market—two key issues for systems designers—have helped propel the MOS PLD market. In 1996, the MOS PLD market was not immune to inventory corrections by systems man- ufacturers. However, the forth quarter of 1996 began another upward trend for the MOS PLD market that extended throughout 1997.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-15 ASIC Highlights

1,400

1,300

1,200

) 1,100 s n o i l

l 1,000 i M (

s

r 900 a l l o

D 800

700

600

500 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1991 1992 1993 1994 1995 1996 1997 Year Source: WSTS 17778N

Figure 3-18. Quarterly MOS Gate Array Market (1991-1997)

1,950 1,850 1,750 1,650 1,550 1,450

) 1,350 s n

o 1,250 i l l i 1,150 M ( 1,050 s r a

l 950 l

o 850 D 750 650 550 450 350 250 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST)

1992 1993 1994 1995 1996 1997

Source: WSTS Year 18930J

Figure 3-19. Quarterly MOS Standard Cell Market (1992-1997)

3-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

650

600

550

500

450 )

s 400 n o i l l

i 350 M (

s

r 300 a l l o 250 D

200

150

100

50

0 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1991 1992 1993 1994 1995 1996 1997 Year

Source: WSTS 18929J

Figure 3-20. Quarterly MOS PLD Market (1991-1997)

The trend for bipolar PLDs is shown in Figure 3-21. Since 1991, the bipolar PLD market has dropped steeply. This market shows a tendency to rebound slightly in various quarters of each year, but overall, the trend is still down.

ASIC SALES

ICE’s ASIC sales figures do not include standard products designed from standard cell libraries or with silicon compilers. Only gate and linear arrays, full custom, and standard cell ICs sold to only one customer, as well as PLDs, are considered ASICs.

Figure 3-22 provides a list of the top 10 ASIC suppliers, not including full custom, for 1996. With total ASIC sales of about $1.7 billion, NEC extended its lead as the number one supplier of ASICs. In doing so, it captured 10 percent of the total ASIC market, again, not including full custom.

LSI Logic, the number two supplier in 1996, has been the preeminent North American gate array supplier for many years. However, it is now a world leader in sales of standard cell ICs as well. 1996 was the first year that LSI Logic’s cell-based ASIC sales were greater than its gate array sales.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-17 ASIC Highlights

100

90

80

70

60

50

40 Dollars (Millions) 30

20

10

0 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1991 1992 1993 1994 1995 1996 1997 Year Source: WSTS 17777P

Figure 3-21. Quarterly Bipolar PLD Market (1991-1997)

Total Standard Percent 1996 Gate Array Linear Array PLD** Sales Company ASIC Sales Cell Sales of ASIC Rank Sales ($M) Sales ($M) ($M) ($M) ($M) Market

1 NEC 1,680 920 35 725 — 11.4

2 LSI Logic 1,175 530 — 645 — 7.9

3 Lucent 1,060 20 — 965 75 7.2

4 Fujitsu 1,046 597 — 449 — 7.1

5 TI 1,024 533 — 475 16 6.9

6 IBM 950 300 — 650 — 6.4

7 Toshiba 845 590 — 255 — 5.7

8 Hitachi 580 450 — 130 — 3.9

9 566 — — — 566 3.8

10 Altera 497 — — — 497 3.4

Top Ten Total 9,423 3,940 35 4,294 1,154 —

Other Suppliers 5,362 1,970 205 2,481 706 —

Total Market* 14,785 5,910 240 6,775 1,860 —

*Not including full custom **Includes FPGA Sales Source: ICE 20194E

Figure 3-22. 1996 Top Ten ASIC* Leaders

3-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Lucent and IBM were members of the top ten list because of their strong sales of standard cell ICs; they are number one and three, respectively, in worldwide sales of standard cells. Xilinx, the lead- ing supplier of PLDs, was at the number nine position for total ASIC sales in 1996 while Altera captured the number ten spot. Overall, the top ten ASIC suppliers had sales that accounted for 56 percent of the total ASIC market in 1996.

PLD Suppliers

The top suppliers in the 1996 PLD market and their sales are shown in Figure 3-23. There are sev- eral small-to-medium size companies that vigorously compete for PLD market share. Firms such as Xilinx, which took over the leadership position in 1994, Altera, Lattice, and Actel have all dis- played leadership in this fast growing market.

1996 1996 1995 1996 COMPANY PERCENT RANK MOS BIPOLAR TOTAL MOS BIPOLAR TOTAL MARKETSHARE

1 Xilinx 520 — 520 566 — 566 30 2 Altera 402 — 402 497 — 497 27 3 Vantis 198 58 256 210 38 248 13 4 Lattice 185 — 185 195 — 195 10 5 Actel 109 — 109 125 — 125 7 6 Lucent 55 — 55 75 — 75 4 7 Cypress 55 — 55 55 — 55 3 8 Philips 5 18 23 12 13 25 2 9 Atmel 20 — 20 25 — 25 2 10 Quicklogic 15 — 15 20 — 20 1 Other 91 34 125 15 14 29 1 Total 1,655 110 1,765 1,795 65 1,860 100 *Includes software and development system sales.

Source: ICE 13601T

Figure 3-23. 1996 Top Ten PLD Sales Leaders*

One of the major benefits driving PLD use continues to be fast time-to-market. Of three prof- itability factors—rapid time-to-market, production costs, and development-cost overrun—time- to-market is often the most critical in the electronics industry where market windows seem to be continuously shrinking.

Lively competition in the PLD market has resulted in several marginal suppliers exiting the market in recent years: National Semiconductor announced that it stopped taking new orders for programmable logic. Intel sold its programmable logic business to Altera for $50 million in cash and stock. Actel declared that it purchased the FPGA business of its second-source partner, Texas

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-19 ASIC Highlights

Instruments. IBM announced late in 1996 it would not enter the PLD market with its own line of SRAM-based FPGAs. And, although they have no plans to exit the PLD market, AMD and Philips turned their respective PLD divisions into wholly-owned subsidiaries to keep up with changes in the fast-paced PLD market.

Complex PLDs (CPLDs) and FPGAs will contribute the most to the expected growth of the pro- grammable logic sector. CPLDs and FPGAs often target the same applications, including data communications and telecommunications equipment, PC peripherals and add-in cards, and elec- tronic games.

CPLDs are being turned to more often because of their low cost, compared with less-dense simple PLDs. For essentially no added expense, designers can consolidate several simple PLD designs into one complex PLD.

PLD market share for 1996 is displayed in Figure 3-24. Xilinx, which took over as the leading PLD supplier in 1994, kept its PLD market share at 29 percent in 1996. Xilinx’s number one ranking is due to its aggressive market introduction of many, very well accepted new products. However, Altera gained three percentage points of market share in 1996 to gain ground on Xilinx.

Cypress 3% Lucent 4% Other 8% Actel 8% Xilinx 29%

Lattice $1,955M 10%

Vantis Altera 13% 25% Cypress 3% Lucent Other 4% TOTAL PLD 7% MARKET Actel Philips 8% Xilinx 20% 30%

$1,890M $65M Lattice Vantis TI 11% 58% 22% Vantis Altera 11% 26%

CMOS BIPOLAR *Includes software and development system sales Source: ICE 13602T

Figure 3-24. 1996 PLD Market Shares*

3-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Vantis, which was formerly AMD, held 46 percent of the total PLD market share in 1988, but has dropped to only 13 percent in 1996. Its grip on the PLD market loosened quickly due to aggres- sive competition from many smaller, but very aggressive suppliers. In addition, up until around 1990, AMD emphasized bipolar PLDs. In fact, 1993 was the first year AMD produced a greater percentage of CMOS PLDs than bipolar PLDs. Vantis is still the leading bipolar PLD supplier, but that market segment is dwindling. Vantis now vigorously pursues CMOS technology. Its CMOS- based complex PLDs, fast low-voltage PLDs, and PLDs characterized for the so-called green com- puter environment have been successful.

REGIONAL ASIC MARKETS

The estimated 1997 gate array market by region is shown in Figure 3-25. Japan continues to lead as the largest consuming region of both bipolar and MOS gate arrays. For 1997, ICE estimates that Japan will have captured 43 percent of the total gate array market, while the North American region estimate is 33 percent of the market, down two points from 1996.

ROW 3%

Europe 13% Japan $390M North 44% America 40%

Bipolar Gate Array Market

ROW ROW Europe 7% Europe 7% 18% 17%

North $4,790M Japan North $5,180M Japan America 43% America 43% 32% 33%

MOS Gate Array Market Total Gate Array Market

Source: ICE 8881AB

Figure 3-25. Estimated 1997 Worldwide Digital Gate Array Market by Region

ICE expects that the North American portion of the gate array market will continue to shrink in the future. Because the North American market is typically at the leading-edge of technology, many new system designs in the U.S. are migrating to more complex, but versatile standard cell ASIC methodology.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-21 ASIC Highlights

The worldwide standard cell market estimate for 1997 by region is displayed in Figure 3-26. As expected the North American segment is the largest of the four major regions. ICE estimates that the North American share in 1997 will show an increase of six percentage points from 1996. In fact almost all the surge in the standard cell market since 1995 is attributable to significant increases in North American and European cell-based ASIC consumption.

ROW ROW 9% Japan 10% Japan 25% 21% North 1997 North 2002 America (EST) America Europe 44% Europe 46% 23% 22%

Total Market = $8.9B Total Market = $34.2B Source: ICE 10403AB

Figure 3-26. Worldwide Standard Cell Market by Region

It is interesting to note that only 18 percent of PLD consumption is estimated to have come from the combined regions of Japan and the ROW (Figure 3-27). In general, the Japanese and ROW regions have been slow to adopt PLDs into system designs because of their emphasis on high- volume consumer electronics. Most of the current use of PLDs in these regions is for prototyping eventual gate array and standard cell designs.

ASIC TECHNOLOGY TRENDS

Overview

It is becoming increasingly difficult to distinguish between each of the ASIC product categories. Until recently, the ASIC industry could be divided into three well-defined product groups: semi- custom ICs including gate arrays and linear arrays, custom ICs including standard cells and full custom, and programmable logic ICs including simple and complex PLDs, FPGAs, and EPACs. However, the lines separating these categories are blurring. The best features of products from one category are increasingly showing up in products of other categories.

For example, embedded arrays are based on a gate array structure, but have large mega-cells such as compiled memories or cores embedded in them (Figure 3-28). These cores pro- vide a higher level of integration than a pure gate-array structure, but can lead to longer proto- type lead times, though, still shorter than the lead times for pure cell-based ASICs.

3-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

ROW 6%

Japan 12% North Europe $2,300M America 21% 61%

ROW MOS PLD Market ROW Japan 4% 6% 4%

Japan Europe 12% 19% North $40M North Europe $2,340M America America 21% 61% 73%

Bipolar PLD Market Total PLD Market Source: ICE 19513F

Figure 3-27. Estimated 1997 PLD Markets by Region

RAM ROM

Sea of Gates Array

Special Function Serial I/O

Source: EDN 19190B

Figure 3-28. Typical Embedded Array ASIC

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-23 ASIC Highlights

Another example of the convergence of ASIC technologies is Actel’s and Synopsys’ co-developed system-programmable gate array (SPGA) that was announced late in 1996 (Figure 3-29).

(a) (b)

Field - Field - Programmable Programmable Logic Logic

66MHz Mask PCI Core Programmable ASIC

Datacom Computer Instrumentation ¥ Router ¥ DMA ¥¥¥ ¥ Data Acquisition ¥ Bridge ¥ Graphics ¥ Image Processing

An SPGA could either be standard Ð an FPGA with widely used cells on chip (a) or customer specific Ð a combination FPGA and gate array (b). Source: Electronic Products 21735

Figure 3-29. Actel’s System-Programmable Gate Array (SPGA)

Figure 3-30 describes two approaches to increasing PLD functionality. The increase in functional- ity of ASICs has been realized by the industry’s quick migration to deep-submicron process tech- nologies. The rapid advancement in ASIC technology, however, has not come without challenges or compromises.

The Embedded Core Approach (Actel, Lucent)

FPGA Embedded Area Area Interface

The Fast Bus Approach (Xilinx)

High-Speed Scalable Bus Core FPGA Chip

Note: The embedded core may have a faster interface, but the fast bus lets the FPGA remain a standard product.

Source: OEM Magazine 22716A

Figure 3-30. Two Approaches for FPGAs

3-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Design Productivity Issues

One of the most significant challenges facing the ASIC industry is design productivity. Although great strides have been made in ASIC software design tools and design productivity (Figure 3-31), the improvements have not been able to keep pace with the increases in gate density (Figure 3-32). Figure 3-33 shows how far design productivity has lagged IC density since 1981.

5,000 5,000

4,500

4,000

3,500 3,000 3,000

2,500

2,000 1,500 Gates/Person/Month 1,500

1,000 750 500 500 150 0 Early 1980's Mid 1980's Late 1980's Early 1990's Mid 1990's Year 2000

Source: ICE 17667C

Figure 3-31. Increasing Design Productivity

Overall, CAD tools are going to be a key issue in producing high-density sub-0.35µm ASICs. The move to using core cells such as DSPs and microcontrollers in an ASIC design is one way to help offset the lag in design productivity.

ASIC Process Technology Issues

In the mid-1980s, ASICs were typically using process technology that was two to three years behind high-volume memory process technology (Figure 3-34). Today, however, processes rival- ing the technological advancement of state-of-the-art memory ICs are being developed specifi- cally for ASICs (Figure 3-35). Figures 3-36 through 3-40 describe the state-of-the-art ASIC process technologies offered by LSI Logic and VLSI Technology. As shown, LSI Logic’s G10 and newest G11 processes are primarily targeting the cell-based ASIC market segment. In fact, both the G10 and G11 technologies describe the availability of DRAM cells for additional system-on- a-chip capability.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-25 ASIC Highlights

100M

10M

Memory Density MPU Density (Bits) (Transistors) 1M

ASIC Density (Usable Gates) 100K

10K 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 Year Source: ICE 21019A

Figure 3-32. IC Density Increases

Memory Density (Bits) 250x

ASICs (Usable Gates) 100x

MPUs (Transistors) 75x

Design Productivity* 20x

*(Gates/Person/Month)

Source: ICE 21020A

Figure 3-33. 1981-1996 IC Industry Improvements

3-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

10.0

5.0 4.0 1.67 MOS Gate Array 3.0 64K 1.5 2.0

m) 256K µ 1.33

1.0 DRAM 1M 1.25

4M

Feature Size ( 1.00 0.5 0.4 16M 1.00

0.3 64M

0.2

0.1 '83 '84 '85 '86 '87 '88 '89 '90 '91 '92 '93 '94 '95 '96 '97 Year = Gate Array/DRAM Feature Size Ratio Source: ICE 18531A

Figure 3-34. ASICs Narrow Technology Gap

Volume Process Generation Gate Density Manufacturing (Drawn, µm) (Gates/mm2) Start 2.0 100 to 200 1986 1.2 300 to 500 1989 0.7 1,250 to 1,500 1992 0.5 5,000 to 6,000 1994 0.35 15,000 to 20,000 1996 0.25 30,000 to 40,000 1998 0.18 45,000 to 60,000 2001

Source: SGS-Thomson 21734

Figure 3-35. Road Map: CMOS Logic Technology Platforms for ASICs

VLSI Technology and Hitachi have worked together to develop a leading-edge ASIC process that VLSI labels VSC9 and VSC10. As shown, the VSC10 process offers 0.15µm channel lengths and gate oxide thickness of only 40Å.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-27 ASIC Highlights

LSI Logic G11ª Family G10ª Family 500K CMOS Process Effective 0.18µ 0.25µ 0.38µ Drawn 0.25µ 0.35µ 0.5µ Architectures Cell Based Cell Based Cell Based Embedded Array Gate Array Metal Interconnect 3,4,5, and 6 Layer 2,3,4, and 5 Layer 2,3, and 4 Layer Operating Voltages 2.5 and 1.8 Volts 3.3 and 2.5 Volts 3.3 Volts

Gate Capacities

Usable (Max) 8,100,000 5,000,000 1,500,000 Max. Typical (Used) 100K to 3,500K 100K to 2,500K 60 to 500K Power Dissipation 0.03-0.25µW/Gate/MHz 0.4-0.7µW/Gate/MHz 1.0µW/Gate/MHz

Source: LSI Logic 22710

Figure 3-36. LSI Logic ASIC Technology Products

Product Comparison

G10ª G11ª Introduced 1995 1997 MAXIMUMS 0.25µ Leff/0.35µ Drawn 0.18µ Leff/0.25µ Drawn Random Logic 5,000,000 Gates 8,100,000 Gates SRAM Memory 6,500,000 Bits 8,000,000 Bits (50% of Die) (50% of Die) 3-Transistor Cell 10,800,000 Bits 12,000,000 Bits DRAM Memory (50% of Die) (50% of Die) 49,500,000 64,000,000 (Logic 50% and SRAM (Logic 50% and SRAM 50% of Die) 50% of Die)

Theoretical Comparisons (Assuming No Interconnect Or Power Limitations)

MIPS RISC Microprocessor R10000 - 64bit CPU = 5,600,000-transistors (LSI Logic could put the equivalent of over eleven MIPS R10000 processors onto a single G11 chip) INTEL P6 CPU Die = 5,500,000-transistors SRAM Die = 16,000,000-transistors Total P6 Multi Chip Module = 21,500,000-transistors (LSI Logic could put the equivalent of over eleven Intel P6 processors or three complete P6 modules onto a single G11 chip)

Source: LSI Logic 22709

Figure 3-37. LSI Logic 0.18µm Process Statistics (Drawn Channel Length = 0.25µm)

3-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

VSC9 VSC10 Drawn Gate Length 0.25µ 0.20µ Effective Channel Length 0.18µ 0.15µ Supply Voltage 2.5V 1.8V Max I/O Voltage 3.3V 3.3V Gate Oxide Thickness 55Å 40Å Isolation Trench Trench Metal Layers Six Six Stacked Vias Yes (CMP) Yes (CMP) Plug Material Tungsten Tungsten M1 Contacted Pitch 0.85µ 0.85µ M2 Contacted Pitch 0.90µ 0.90µ M3 Contacted Pitch 0.90µ 0.90µ M4 Contacted Pitch 1.4µ 1.4µ M5 Contacted Pitch 1.4µ 1.4µ M6 Flip Chip Layer Flip Chip Layer SRAM Cell Size (6T Cell) 10.5µ2 10.5µ2 Power (µW/MHz/Gate) 0.04 0.02 Minimum Inverter Stage Delay @ Vcc 35ps @ 2.5Vdd 35ps @ 1.8Vdd Logic Gates/22 x 22mm Die 18,000,000 18,000,000 Pad Pitch 42µ 42µ 100% Utilization (Gates/mm2) 40K 40K

Source: VLSI Technology 22713

Figure 3-38. VLSI Technology’s ASIC Process Overview

14,000,000

12,000,000

VSC9 and VSC10 Process, 0.85µ Metal Pitch, 10,000,000 18,000,000 Max Gates at 4.84cm2

8,000,000

6,000,000 Max Usable Gates 4,000,000

2,000,000 VLSI 0.35µ Process, 1.4µ Metal Pitch, 6,200,000 Max Gates at 4.84cm2 0 0.5 1.0 2.0 4.0 Die Area in cm2

Source: VLSI Technology 22711

Figure 3-39. What VSC9 and VSC10 Give You

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-29 ASIC Highlights

Metal Pitch: 1.4µ 0.85/0.90µ Voltage: 0.35µ VSC8 3.3V w 5V tox = 80Å 0.30µLeff Signaling

2.5V w 3.3V tox = 55Å 0.25µ VSC9 Signaling 0.18µLeff 1.8V w 3.3V Process Signaling 0.20µ VSC10 µ tox = 40Å 0.15 Leff

1.0X 2.4X Density 1995 1997

Source: VLSI Technology 22714

Figure 3-40. Technology Transitions

A key aspect of VLSI Technology’s processing is the use of trench isolation (Figure 3-41). Trench isolation allows greater packing density of transistors and thus a small die size.

FIELD TRENCH OXIDE OXIDE

LOCOS Isolation Trench Isolation

Photos by ICE 22712

Figure 3-41. Trench Versus LOCOS Isolation

It should be noted that both the G11 and VSC10 processes are slated for 1998 high volume ASIC production; in 1998 these technologies will represent two of the best ASIC processes available.

While deep-submicron integration has allowed for unprecedented performance and economies of scale, it has also brought with it a new set of design challenges. With larger geometry chips, cir- cuit timing is limited primarily by gate delays. However, as geometries shrink, delay from the resistance and capacitance of the wiring interconnect between transistors begins to dominate (Figure 3-42). Interconnect delays have increased, as a percent of total delay, from 15 to 30 percent at the 1.0µm level to 50 to 75 percent at the 0.35µm level.

3-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Typical Gate Delay

1 Delay (nsec) 0.1

Average Wiring Delay

Feature Size: 1.5µm 1.2µm 1.0µm 0.8µm 0.5µm 0.3µm Circuit Size: 20 30 60 150 500 1,000 (thousands of gates) Source: OKI Semiconductor 20407B

Figure 3-42. Wiring (Interconnect) Delay Versus Gate Delay

In battling the effects of increased resistance and capacitance associated with increasingly thinner, narrower, and more closely spaced interconnects, ASIC designers are having to use more design iterations identifying and solving timing errors; or else, settle for a design that does not use its full speed potential just to get a functional IC.

Other challenges intensified by shrinking circuit geometries include limiting crosstalk between interlayers and adjacent wires, managing I/O issues like simultaneously switched outputs, and minimizing clock skews.

Business Issues

The ASIC and ASSP segments of semiconductor manufacturing are not only challenged by tech- nical issues, including processing, packaging, design, and test, but also by business considera- tions. One such consideration is ASIC industry standards. In general, the high-density ASIC and ASSP market will continue to expand regardless of whether a framework of standards exists or not. However, some type of open-industry organization could help facilitate a less cumbersome path for companies to follow into the future.

In response to the surge toward system-on-a-chip ICs, the Virtual Socket Interface (VSI) alliance was formed in 1996. As of mid-1997 VSI had brought together over 130 companies (Figure 3-43) including EDA companies, intellectual-property (IP) companies, semiconductor producers, and systems manufacturers.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-31 ASIC Highlights

¥ Actel ¥ General Instrument ¥ Phoenix Technologies ¥ Adaptec ¥ GigaLex ¥ Pioneer Electronic ¥ Advancel Logic ¥ Hitachi ¥ PrairieComm ¥ Advantest ¥ Hyundai Electronics ¥ Quickturn Design Systems ¥ Advanced Hardware Industries ¥ Richard Watts Associates Architectures (AHA) ¥ IK Technology ¥ Rockwell Semiconductor ¥ Alcatel Mietec ¥ Ikos Systems ¥ ROHM ¥ Altera ¥ In Chip Systems ¥ Samsung Electronics ¥ AMI ¥ Indus ¥ SandCraft ¥ Ando Electric ¥ International Computers ¥ Sand Microelectronics ¥ Apix ¥ Integrated Silicon Systems ¥ Sanyo Electric ¥ Aristo Technology ¥ iReady ¥ Schlumberger ¥ Artisan Components ¥ Innovative ¥ Sebring Systems ¥ Advanced Risc Machines Semiconductors ¥ Seiko Instruments ¥ Asahi Kasei Microsystems ¥ Kawasaki Steel ¥ Seiko Epson ¥ ASPEC Technology ¥ LG Semicon ¥ SIDSA ¥ Beijing Intelligent ¥ LightSpeed ¥ SGS-Thomson Electronics ¥ Lockheed ¥ Sharp ¥ Cadence Design Systems ¥ Logic Research ¥ SICAN ¥ CAD Framework Initiative ¥ Logic Vision ¥ Siemens ¥ CAE Plus ¥ LSI System ¥ Sierra Research & ¥ Caesium ¥ LTX Technology ¥ Cast ¥ Matsushita ¥ Silicon & Software Systems ¥ Chip Express ¥ Mentor Graphics ¥ SIS Microelectronics ¥ Chronology ¥ MIPS Technologies ¥ Smartech Oy ¥ Cirrus Logic ¥ Mitsubishi Electric ¥ Sonics ¥ Cisco Systems ¥ National Semiconductor ¥ Sony ¥ COMPASS Design ¥ NEC ¥ Spinnaker Systems Automation ¥ NeoParadigm Labs ¥ Summit Design ¥ CompCore Multimedia ¥ Neuw Intellectual Property ¥ Symbios Logic ¥ CoWare ¥ Nexwave Design ¥ Synchronicity ¥ Cygnus Solutions Automation ¥ Synopsys ¥ Cypress Semiconductor ¥ Nippon Telegraph and ¥ Technical Data Freeway ¥ Diagonal Systems Telephone ¥ Thine Microsystems ¥ DSP Group ¥ NKK ¥ Texas Instruments ¥ Duet Technologies ¥ Nordic ¥ Toshiba ¥ Easics NV ¥ Nortel Semiconductors ¥ Tower Semiconductor ¥ ECSI (Eropean CAD ¥ Oki Electric ¥ Trimble Navigation Standards Initiative) ¥ Oki Telecommunications ¥ Tseng Labs ¥ Hewlett-Packard/ Group ¥ TSMC HPEEsof Div. ¥ Olympus Optical ¥ Vantis ¥ Escalade ¥ The Open Microprocessor ¥ Victor of Japan ¥ Excellent Design Systems Initiative ¥ Viewlogic Systems ¥ Exemplar Logic ¥ Management Office ¥ VLSI Technology ¥ Fuji Facom ¥ Packet Engines ¥ Western Design Center ¥ Fujitsu ¥ Palmchip ¥ Xilinx ¥ GEC Plessey ¥ Philips Semiconductors ¥ Yokogawa Electric ¥ Zycad Source: VSI Alliance 22746A

Figure 3-43. VLSI Alliance Member List

The goal of VSI is to allow a chip designer to use IP information (e.g., core cells of an ASIC) sourced from numerous companies to create an IC design that could be produced by any one of a number of semiconductor manufacturers. Of course for this to happen, IC design and process compatibility standards must be created by VSI; version 1.0 of the VSI standard was released March 19, 1997. Licensing and royalty issues of IP must also be addressed.

3-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

Embedded-DRAM ASICs

One of the hottest ASIC segments is the embedded-DRAM cell-based market. Although the embedded-DRAM ASIC market is estimated to have been only about $1.0 billion in 1997, Toshiba expects this market to surge near $6 billion in 2002. Figure 3-44 shows some of the companies offering embedded-DRAM technology.

Company Comments Chartered Semiconductor Licensed technology from Toshiba Hitachi Plans to begin offering embedded-DRAM ASICs in October 1997 LSI Logic/Micron* Joint effort to embed 1M-2M bytes of DRAM in ASICs Mitsubishi In March 1996 combined 2M bytes of DRAM with a 32-bit RISC CPU Motorola Acquired rights to Mitsubishi technology NEC Developing embedded-DRAM ASICs Oki Developed embedded-DRAM graphics controller with Silicon Magic Samsung Began offering embedded-DRAM ASICs in late 1996 SGS-Thomson Developing MPU/DRAM devices Toshiba Targeting ASIC marketplace TSMC Will offer foundry customers a 0.35µm embedded-DRAM process in 2H97 VLSI Technology Plans to begin offering embedded-DRAM technology in 1998 * Micron will fab base wafers while LSI Logic will add final metal layers. Source: ICE 22743

Figure 3-44. Sampling of Embedded-DRAM Offerings

As is shown in Figure 3-45, the initial applications for embedded-DRAM ASICs were for graphics and desktop imaging. In these systems only 1M or 2M of DRAM was required. In 1998, embed- ded-DRAM 0.25µm ASICs with up to 128M of DRAM are expected to be available from Toshiba.

Although large blocks of DRAM will most likely be available from ASIC suppliers in the future, the system needs for such large amounts of on-chip DRAM are not obvious. The cost and benefit of on-chip DRAM becomes less clear above 24M to 32M. Many of the current embedded-DRAM ASIC producers have already voiced concern over the current lack of clear customer roadmaps for systems needing large blocks of on-chip DRAM.

PLDs and FPGAs

The first field programmable logic devices were introduced almost 25 years ago. Basically, the benefits of using programmable logic have been shortening the time to market and risk reduction. This has been true for over 20 years and will continue to be true in the foreseeable future.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-33 ASIC Highlights

Set-Top Box 3D/2D Graphics TBD DVD PC Peripheral 0.18 micron Network Computer Alpha CPU ~32Mbits Printer Arm 7 Family Wireless Communication OakDSPCore 400K 0.25 micron Video Encoder/Decoder 24Mbits JAVA 80C52 0.35 micron Z-80 Gate Count CDG A/D, D/A CDP PCI Video CD MPEG 100K Digital Camera CODEC 300MHz RAMDAC/PLL Sound Systems Mass Storage

60K 1Mbit

0.5 micron 1996 1997 1998 1999 Source: Samsung 22719A

Figure 3-45. Optimization of Cell-Based Logic, DRAM and Analog for System-on-a-Chip Solutions

Over the 20 years of programmable logic offerings, the term PLD has evolved to encompass more than just low-density bipolar products. The PLD industry has gone from using strictly bipolar technology and simple architecture to using CMOS EPROM, EEPROM, SRAM, flash, and antifuse processing with very elaborate circuit designs.

In an industry as dynamic as the IC industry, the natural trend has been toward high-density and high-performance technologies. In the PLD market this is very obvious as simple bipolar PLDs are now steadily losing market share to the more flexible and higher density CMOS PLD technologies.

As was previously mentioned, ASSPs are taking away some of the market served by traditional ASICs. Along these same lines, there are an increasing number of PLDs being tailored for specific applications. In fact, nearly every major PLD and FPGA supplier has recently announced the availability of a library of system-level cores and megacells that can be embedded in their IC designs, thereby allowing PLDs to be used as system-level ICs (Figure 3-46).

Overall, PLDs are moving away from being used only as peripheral logic and more toward core logic at the heart of the system.

3-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Highlights

¥ ARM M16450 Universal Asynchronous Receiver/Transceiver ¥ ARM M16550A Universal Asynchronous Receiver/Transceiver with FIFOs ¥ ARM M8254 Programmable Timer ¥ ARM M8255 Programmable Peripheral Interface ¥ Memec FX-TWSI two-wire serial interface ¥ Memec XF8250 Universal Asynchronous Receiver/Transceiver ¥ Memec XF8255 Peripheral Interface Adapter ¥ ISS Reed Solomon encoder

Source: ICE 22742

Figure 3-46. New FPGA Cores Announced by Xilinx in 2Q97

In general, the MOS PLD market will continue to be one of the most dynamic in the entire IC industry. As PLD technology and capabilities increase, ICE expects the PLD logic segment to be a cornerstone of the ASIC industry. Some key PLD developments to watch for include:

• Implementation of 0.35µm and 0.30µm feature size technology (Figure 3-47). • Aggressive PLD price reductions (Figure 3-48). • Increased offerings of high-gate-count ICs. • Further offerings of specialized core cells for PLDs. • Additional development of in-system programmable (ISP) and dynamically reconfigurable hardware and software infrastructures.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-35 ASIC Highlights

ALTERA: Product Family: EPF10K130V Feature Size: 0.35µm Total Gates: 130K; 32K RAM Operating Voltage: 3.3V Pricing: 2Q97 at $895/100 599-PGA 4Q97 at $275/5,000 600-BGA Other: 250K-gate device expected by the end of 1997.

LUCENT: Product Family: OR2TxxA Feature Size: 0.3µm Metal Layers: 3 Operating Voltage: 3.3V Pricing: 1Q98 at $49.80/10,000 with 15K usable gates Other: Plans to sample 0.25µm FPGAs in 4Q97.

XILINX: Product Family: XC4000XL Feature Size: 0.35µm Total Gates: 85K Operating Voltage: 3.3V Metal Layers: 3 Pricing: 2Q97 at $1,530/100 Other: Plans a 0.25µm 5-layer metal 125K-gate family operating a 2.5V by the end of 1997.

Source: ICE 22741

Figure 3-47. Leading-Edge PLD Technologies

4Q 1995 $995

2Q 1996 $350

1Q 1997 $195

4Q <$65 1997

0 200 400 600 800 1,000 100-Unit List Price (Dollars) Source: Altera 22740

Figure 3-48. PLD Prices Keep Decreasing (50,000-Gate EPF10K50)

3-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION