Introduction to CMOS VLSI Design
Lecture 14: Circuit Families David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh
Outline q Pseudo-nMOS Logic q Dynamic Logic q Pass Transistor Logic
9: Circuit Families CMOS VLSI Design Slide 2 Introduction q What makes a circuit fast?
– I = C dV/dt -> tpd ∝ (C/I) ΔV – low capacitance – high current – small swing B 4 A 4 q Logical effort is proportional to C/I Y q pMOS are the enemy! 1 1 – High capacitance for a given current q Can we take the pMOS capacitance off the input? q Various circuit families try to do this…
9: Circuit Families CMOS VLSI Design Slide 3 Pseudo-nMOS q In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON q In CMOS, use a pMOS that is always ON – Ratio issue – Make pMOS about ¼ effective strength of pulldown network 1.8 load 1.5 P/2 1.2 P = 24 V Ids out 0.9
Vout 0.6 P = 14 16/2 0.3 P = 4 Vin 0 0 0.3 0.6 0.9 1.2 1.5 1.8
Vin
9: Circuit Families CMOS VLSI Design Slide 4 Pseudo-nMOS Gates q Design for unit current on output
to compare with unit inverter. Y q pMOS fights nMOS inputs f
Inverter NAND2 NOR2
gu = gu = gu = g = g = g = d Y d d g = g = g = avg A avg avg Y pu = pu = Y pu = A pd = B pd = A B pd = pavg = pavg = pavg =
9: Circuit Families CMOS VLSI Design Slide 5 Pseudo-nMOS Gates q Design for unit current on output
to compare with unit inverter. Y q pMOS fights nMOS inputs f
Inverter NAND2 NOR2
gu = gu = gu = g = 2/3 g = g = d Y d d g = g = 2/3 g = 2/3 avg A 8/3 avg avg Y pu = pu = Y pu = A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd = pavg = pavg = pavg =
9: Circuit Families CMOS VLSI Design Slide 6 Pseudo-nMOS Gates q Design for unit current on output
to compare with unit inverter. Y q pMOS fights nMOS inputs f
Inverter NAND2 NOR2
gu = 4/3 gu = 8/3 gu = 4/3 g = 4/9 2/3 g = 8/9 g = 4/9 d Y d d g = 8/9 g = 16/9 2/3 g = 8/9 2/3 avg A 8/3 avg avg Y pu = pu = Y pu = A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd = pavg = pavg = pavg =
9: Circuit Families CMOS VLSI Design Slide 7 Pseudo-nMOS Gates q Design for unit current on output
to compare with unit inverter. Y q pMOS fights nMOS inputs f
Inverter NAND2 NOR2
gu = 4/3 gu = 8/3 gu = 4/3 g = 4/9 2/3 g = 8/9 g = 4/9 d Y d d g = 8/9 g = 16/9 2/3 g = 8/9 2/3 avg A 8/3 avg avg Y pu = 6/3 pu = 10/3 Y pu = 10/3 A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9 pavg = 12/9 pavg = 20/9 pavg = 20/9
9: Circuit Families CMOS VLSI Design Slide 8 Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS In q G = 1 1 Y q F = H In 1 q P = k q N = q D =
9: Circuit Families CMOS VLSI Design Slide 9 Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS In q G = 1 * 8/9 = 8/9 1 1 Y q F = GBH = 8H/9 H In 1 q P = 1 + (4+8k)/9 = (8k+13)/9 k q N = 2 4 2Hk 8+ 13 q D = NF1/N + P = + 39
9: Circuit Families CMOS VLSI Design Slide 10 Pseudo-nMOS Power q Pseudo-nMOS draws power whenever Y = 0
– Called static power P = I•VDD – A few mA / gate * 1M gates would be a problem – This is why nMOS went extinct! q Use pseudo-nMOS sparingly for wide NORs q Turn off pMOS when not in use
en Y A B C
9: Circuit Families CMOS VLSI Design Slide 11 Dynamic Logic q Dynamic gates uses a clocked pMOS pullup q Two modes: precharge and evaluate
2 2/3 φ 1 A Y Y Y 1 A 4/3 A 1
Static Pseudo-nMOS Dynamic
φ Precharge Evaluate Precharge
Y
9: Circuit Families CMOS VLSI Design Slide 12 The Foot q What if pulldown network is ON during precharge? q Use series evaluation transistor to prevent fight.
precharge transistor φ φ φ Y Y Y inputs inputs A f f foot
footed unfooted
9: Circuit Families CMOS VLSI Design Slide 13 Logical Effort
Inverter NAND2 NOR2
φ 1 Y 1 φ 1 A 2 φ unfooted Y Y A 1 B 2 A 1 B 1 gd = gd = gd = pd = pd = pd =
φ 1 Y 1 φ 1 A 3 φ Y Y footed A 2 B 3 A 2 B 2 g = g = g = 2 d 3 d 2 d pd = pd = pd =
9: Circuit Families CMOS VLSI Design Slide 14 Logical Effort
Inverter NAND2 NOR2
φ 1 Y 1 φ 1 A 2 φ unfooted Y Y A 1 B 2 A 1 B 1 gd = 1/3 gd = 2/3 gd = 1/3 pd = 2/3 pd = 3/3 pd = 3/3
φ 1 Y 1 φ 1 A 3 φ Y Y footed A 2 B 3 A 2 B 2 g = 2/3 g = 3/3 g = 2/3 2 d 3 d 2 d pd = 3/3 pd = 4/3 pd = 5/3
9: Circuit Families CMOS VLSI Design Slide 15 Monotonicity q Dynamic gates require monotonically rising inputs during evaluation – 0 -> 0 φ – 0 -> 1 A – 1 -> 1 violates monotonicity – But not 1 -> 0 during evaluation A
φ Precharge Evaluate Precharge
Y
Output should rise but does not
9: Circuit Families CMOS VLSI Design Slide 16 Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!
A = 1
φ φ Precharge Evaluate Precharge Y X A X
Y
9: Circuit Families CMOS VLSI Design Slide 17 Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another!
A = 1
φ φ Precharge Evaluate Precharge Y X A X X monotonically falls during evaluation Y Y should rise but cannot
9: Circuit Families CMOS VLSI Design Slide 18 Domino Gates q Follow dynamic stage with inverting static gate – Dynamic / static pair is called domino gate – Produces monotonic outputs
φ Precharge Evaluate Precharge domino AND W
W X Y Z X A B C Y φ Z dynamic static φ φ NAND inverter φ φ A W X A X H Y B H Z = B Z C C
9: Circuit Families CMOS VLSI Design Slide 19 Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HI-skewed static stages can perform logic
φ
S0 S1 S2 S3 D0 D1 D2 D3 Y H φ
S4 S5 S6 S7 D4 D5 D6 D7
9: Circuit Families CMOS VLSI Design Slide 20 Dual-Rail Domino q Domino only performs noninverting functions: – AND, OR but not NAND, NOR, or XOR q Dual-rail domino solves this problem – Takes true and complementary inputs – Produces true and complementary outputs
sig_h sig_l Meaning 0 0 Precharged Y_l φ Y_h inputs 0 1 ‘0’ f f
1 0 ‘1’ φ 1 1 invalid
9: Circuit Families CMOS VLSI Design Slide 21 Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B)
9: Circuit Families CMOS VLSI Design Slide 22 Example: AND/NAND q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B) q Pulldown networks are conduction complements
Y_l φ Y_h = A*B A_h = A*B A_l B_l B_h
φ
9: Circuit Families CMOS VLSI Design Slide 23 Example: XOR/XNOR q Sometimes possible to share transistors
Y_l φ Y_h = A xnor B A_h A_l A_l A_h = A xor B B_l B_h
φ
9: Circuit Families CMOS VLSI Design Slide 24 Leakage q Dynamic node floats high during evaluation
– Transistors are leaky (IOFF ≠ 0) – Dynamic value will leak away over time – Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node – Must be weak enough not to fight evaluation weak keeper φ 1 k X H Y A 2 2
9: Circuit Families CMOS VLSI Design Slide 25 Charge Sharing q Dynamic gates suffer from charge sharing
φ φ Y A A x CY Y B = 0 Cx
x
9: Circuit Families CMOS VLSI Design Slide 26 Charge Sharing q Dynamic gates suffer from charge sharing
φ φ Y A A x CY Y B = 0 Cx Charge sharing noise
x
VVxY==
9: Circuit Families CMOS VLSI Design Slide 27 Charge Sharing q Dynamic gates suffer from charge sharing
φ φ Y A A x CY Y B = 0 Cx Charge sharing noise
x
CY VVx== Y V DD CCxY+
9: Circuit Families CMOS VLSI Design Slide 28 Secondary Precharge q Solution: add secondary precharge transistors – Typically need to precharge every other node q Big load capacitance CY helps as well
secondary φ precharge Y transistor A x B
9: Circuit Families CMOS VLSI Design Slide 29 Noise Sensitivity q Dynamic gates are very sensitive to noise
– Inputs: VIH ≈ Vtn – Outputs: floating output susceptible noise q Noise sources – Capacitive crosstalk – Charge sharing – Power supply noise – Feedthrough noise – And more!
9: Circuit Families CMOS VLSI Design Slide 30 Domino Summary q Domino logic is attractive for high-speed circuits – 1.5 – 2x faster than static CMOS – But many challenges: • Monotonicity • Leakage • Charge sharing • Noise q Widely used in high-performance microprocessors
9: Circuit Families CMOS VLSI Design Slide 31 Pass Transistor Circuits q Use pass transistors like switches to do logic q Inputs drive diffusion terminals as well as gates q CMOS + Transmission Gates: – 2-input multiplexer – Gates should be restoring S S
A A S Y S Y B B
S S
9: Circuit Families CMOS VLSI Design Slide 32 LEAP q LEAn integration with Pass transistors q Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint
S A S L Y B
9: Circuit Families CMOS VLSI Design Slide 33 CPL q Complementary Pass-transistor Logic – Dual-rail form of pass transistor logic – Avoids need for ratioed feedback – Optional cross-coupling for rail-to-rail swing
S A S L Y B S A S L Y B
9: Circuit Families CMOS VLSI Design Slide 34