Appendix a Addresses of Standards Organizations

Appendix A Addresses of Standards Organizations

Following are the addresses of the IPC and EIA, as well as other sources for standards documents.

Electronic Industries Association (EIA) 2001 Pennsylvania Avenue, NW Washington, DC 20006-1813

Institute for Interconnecting and Packaging Electronic Circuits (IPC) 7380 North Lincoln Avenue Lincolnwood, IL 60646

Military documents are available from: Standardization Documents Order Desk, Building 4D 700 Robbins Avenue Philadelphia, PA 19111-5094

Central office of the IEC: International Electrotechnical Commission (lEC) 3 Rue de Varembe 1211 Geneva 20, Switzerland

IEC documents are available from: American National Standards Institute (ANSI) 11 West 42nd Street New York, NY 10036

319 AppendixB Summary of SMT Semiconductor Outlines from JEDEC Publication 95

320 luenenc uescription Rel!lstralton Number SOT-23 TO-236AA-AB SOT-89 TO-243AA-AB SOT-143 TO-2S3AA DPAK TO-2S2AA SMT Header Family TO-263AA-AB MELF Diode DO-213AA-AB SOIC-3.7S mm Body MS-O 12AA-AC (Standard) SOIC-7.S mm Body MS-O 13AA-AF (Standard) SOIC-11.2 mm (0.440·) Body MO-099AA-AB SOP. Gullwin~ Leads MO-tI7 SOJ-0.300· Body MO-06SAA-AB SOJ-0.300· Body MO-088AA-AF SOJ-0.300" Body MO-077AA-AC SOJ-0.300" Body SOJ-03S0" Body MO-09IAA-BA SOJ-26/20-0.3S0" Body MO-063 SOJ-32128-0.400· Body MO-06J SOJ-0.300· Body MO-119 SOJ-O.3S0· Body MO-120 SOJ-O.330· Body MO-121 SOJ-12 mm Body MO-I23 SOJ-12.7 mm Body MO-124 TSOJ-O.300· Body MO-IOS SSOP-O.300· Body MO-118 PLCC-SQuare-O.OSO· Lead Soacin~ MO-047AA-AH PLCC-Reetangular-Q.OSO" Liad Spacin~ MO-O 16AA-AE (Standard) PLCC-Rectan~ular-O.OSO· Lead Spacing MO MO-OS2AA-AE PLCC-SQuare. Ceramic-O.OSO· Lead Soacing••J" Lead MO-087 LCC~O.OSO· Lead Soacin\! MS-002 thru MS-OOS (Slandard) Leaded Socket O.OSO" Lead Soacin\! MS-009. MS-OI4 (Standard) Plastic Quad Flat Pack-0.02S" Lead Spacing MS-069AA-AH Plastic Quad Flat Pack-0.02S· Lead Spacing. Bumoered. Thin Lead Family (Gullwin~) MO-069AA-AH Plaslic Quad Flat Pack-0.02S· Lead Spacing. Bumpered. Thin Lead Family (Gullwing) MO-071 AA-BB

321 Ivenenc VescriptlOn RegIstration Number Plastic Quad Flat Pack-0.02S" Lead Spacing. Bumpered. Low Profile (Gullwing) MO-086AA-AH Plastic Quad Flat Pack-O.OSO" Lead Spacing. Bumpered (Gullwingl MO-089 TaoePak/Molded Carrier Ring MO-094AA-BD TapePak/Molded Carrier Ring. Fine Pitch MO-109 Tape Ouad Flat Pack MO-102AA-CD Metric Quad Flat Pack (Body +3.2) MO-J08AA·FA Metric Quad Flat Pack (Body + 3.9) MO-112AA-FA TAB - En!!:lish Dimension UO-017 TAB - Metric Dimension UO-118 Ceramic Quad Flat Pack. 0.020" Lead Spacin!!:. 256 Leads MO-IOOAA Ceramic Quad Flat Pack. 0.025" Lead Soacing MO-082AA-AF Ceramic Quad Flat Pack. 0.025" Lead Spacing. Guard Ring. 132 Leads MO-104AA Ceramic Quad Flat Pack. 0.015" Lead Spacing MO-090AA-AF Ceramic Quad Flat Pack. 0.050" Lead Spacin!!: MO-084AA-AF Ceramic Leaded ChiD Carrier MO-107AA-AE Ceramic Chip Carrier. "r Lead. 0.050" Lead Spacin!!: MO-087AA-AE Ceramic Round Lead. "r Lead. 0.050" Lead Spacing MO-110 Ceramic Round Lead. "Gull" Lead. 0.050" Lead Spacin!!: MO-III Ceramic Quad Flat Pack, w/Tie Bar MO-113 CerQuad Family w/Gullwin!!: Leads MO-114 Ceramic Ouad Flat Pack. 132 Lead MO-060 Ceramic Quad Flat Pack, 196 Lead MO-f2S 6.35 mm Cerpak Leaded Flat Pack MO-092AA-AD Braze Lead Flat Pack MO-098AA-AD Top Brazed 48 Pin Flat Pack MO-IOIAA-AB Flat Pack Family. 0.535" Lon!!:. 0.303" Pitch MO-\06AA-AC Flat Pack. 32 Lead MO-IIS Lateral (Leadless) Ceramic Chip Carrier. 0.025" Spacing MO-OS6AA-HC Lateral (Leadless) Ceramic Chip Carrier. 0.020" Spacin!!: MO-OS7AA-JC

322 Appendix C Summary of Important Component, Material, Process and Design Standards

The following documents center on surface mount technology. These documents have been developed by standards organizations in the U.S. and internationally. The letters of each document indicate the organization that has responsibility for the document:

• EIA represents documents prepared by the Electronic Industries Association • JEDEC represents documents of the Joint Electron Devices Engineering Council of the EIA • IPC represents documents prepared by the Institute for Intercormecting and Packaging Electronic Circuits • MIL represents documents prepared by the Military • DoD represents documents prepared by the Department of Defense

Components, General

EIA-481-A Taping of Surface Mount Components for Automatic Placement EIA-481-1 8 mm and 2 mm Taping of Surface Mount Components for Automatic Handling EIA-481-2 16 mm and 24 mm Embossed Carrier Taping of Surface Mount Components for Automated Handling EIA-481-3 32 mrn, 44 mm, and 56 mm Embossed Carrier Taping of Surface Components for Automated Handling EIA/IS-47 Contact Termination Finish Standard for Surface Mount Devices EIA-PDP-lOO Registered and Standard Mechanical Outlines for Electronic Parts EIA-JEP-95 JEDEC Registered and Standard Mechanical Outlines for Semiconductor Devices 323 324 Fine Pitch Surface Mount Technology

Components, Passive Capacitors EIA-469-B Standard Test Method for Destructive Physical Analysis of High Reliability Ceramic Monolithic Capacitors EIA-CB-II Guidelines for the Surface Mounting ofMultilayer Ceramic Chip Capacitors EIA/IS-28 Fixed Tantalum Chip Capacitor Style 1 Protected Standard Capacitance Range EIA/IS-29 Fixed Tantalum Chip Capacitor Style I Protected Extended Capacitance Range EIA/IS-36 Chip Capacitors, Multi-Layer (Ceramic Dielectric) EIA/IS-37 Multiple Layer High Voltage Capacitors (Radial Lead Chip Capacitors) IEC-384-3 Sectional Specification, Fixed Multilayer Ceramic Chip Capacitors IEC-384-10 Sectional Specification. Fixed Multilayer Ceramic Chip Capacitors IECQ Draft Blank Detail Specification, Fixed Multilayer Ceramic Chip Capacitors IECQ-PQC-31 Sectional Specification, Fixed Tantalum Chip Capacitors with Solid Electrolyte IECQ-PQC-32 Blank Detail Specification, Fixed Tantalum Chip Capacitor

Resistors

EIA-575 Resistors, Rectangular, Surface Mount, General Purpose EIA-576 Resistors, Rectangular, Surface Mount, Precision EIA/IS-34 Leaded Surface Mount Resistor Networks Fixed Film

Components, Active

EIA-JEP-95 JEDEC Registered and Standard Outlines for Semiconductor Devices EIA-JESD21-C Configurations for Solid State Memories EIA-JESD22-B Test Methods and Procedures for Solid State Devices Used in TransportationfAutomotive Applications EIA-JESD-II Chip Carrier Pinouts Standardized for CMOS 4000, HC, and HCT Series ofLogic Circuits

Components, Electromechanical Connectors

EIA-506 Dimensional and Functional Characteristics Defining Sockets for Leadless Type A Chip Carriers (.050 Spacing) EIA-507 Dimensional Characteristics Defining Edge Clips for Use with Dec 1983 Hybrid and Chip Carriers EIA/IS-47 Contact Termination Finish Standard for Surface Mount Devices Summary of Important Component, Material, Process and Design Standards 325

Switches IECQ-PQC-41 -US00003 Detail Specification, Dual-in-Line Switch, Surface Mountable, Slide Actuated EIA-448-23 Surface Mountable Switches, Qualification Test EIA-520EAAAA Detail Specification for Surface Mountable Dual In-Line Switches ofCertified Quality

Printed Boards IPC-FC-250 Performance Specification for Single and Double-sided Flexible Printed Boards IPC-RB-276 Performance Specification for Rigid Printed Boards IPC-SD-320 Performance Specification for Rigid Single and Double-sided Printed Boards IPC-ML-950 Performance Specification for Multilayer Printed Boards MIL-P-50884 Military Specification Printed Wiring, Flexible, and Rigid Flex MIL-P-55 110 Military Specification Printed Wiring Boards, General Specification For

Materials IPC-L-108 Specification for Thin Laminate Metal Clad primarily for High Temperature Multilayer Printed Boards IPC-L-109 Specification for Glass Cloth, Resin Preimpregnated (B Stage) for High Temperature Multilayer Printed Boards IPC-L-1l5 Specification for Plastic Sheet Laminated Metal Clad for High Temperature Performance Printed Boards IPC-CF-148 Resin Coated Metal for Multilayer Printed Boards IPC-CF-150 Copper Foil for Printed Wiring Applications IPC-CF-152 Metallic Foil Specification for Copper{Invar{Copper (CIC) for Printed Wiring and Other Related Applications IPC-SM-817 General Requirements for SMT Adhesives IPC-SF-818 General Requirements for Electronic Soldering Fluxes IPC-SP-819 General Requirements for Electronic Grade Solder Paste IPC-CC-830 Qualification and performance of Electrical Insulation Compounds for Printed Board Assemblies IPC-SM-840 Qualification and Performance of Permanent Polymer Coating (Solder Mask) for Printed Boards MIL-F-14256 Flux, Soldering, Liquid (Rosin Base)

Interconnecting Substrates IPC-RF-245 Performance Specification for Rigid-Flex Multilayer Printed Boards IPC-MC-324 Performance Specification for Metal Core Boards IPC-HM-860 Performance Specification for Hybrid Multilayer 326 Fine Pitch Surface Mount Technology

Design Activities IPC-T-50 Tenns and Definitions for Electronic Interconnections IPC-CM-78 Surface Mount and Interconnecting Chip Carrier Guidelines IPC-H-855 Hybrid Microcircuit Design Guide IPC-D-249 Design Standard for Flexible Single and Double-sided Printed Boards IPC-D-317 Design Standard for Electronic Packaging Utilizing High Speed Techniques IPC-D-319 Design Standards for Rigid Single and Double-sided Printed Boards IPC-SM-782 Surface Mount Land Patterns (Configuration and Design Rules) IPC-D-859 Design Standard for Multilayer Hybrid Circuits IPC-D-949 Design Standard for Rigid Multilayer Printed Boards IPD-D-275 Design Standard for Rigid Printed Boards and Rigid Printed Board Assemblies MIL-STD-275 Military Standard Printed Wiring for Electronic Equipment MIL-STD-2118 Design Standard for Flexible Printed Wiring

Component Mounting EIA-CB-ll Guidelines for the Surface Mounting of Multilayer Ceramic Chip Capacitors IPC-CM-770 Guidelines for Printed Board Component Mounting IPC-SM-784 Guidelines for Direct Chip Attachment SMC-TR-OOI An Introduction to Tape Automated Bonding and Fine pitch Technology

Attachment Techniques

IPC-SM-780 Electronic Component Packaging and Interconnection with Emphasis on Surface Mounting

Soldering and Solderability

EIA/IS-46 Test Procedure for Resistance to Soldering (Vapor Phase Technique) for Surface Mount Devices EIA/IS-49-A Solderability Test Method for Leads and Tenninations EIA-448-19 Method 19 Test Standard for Electromechanical Components Environmental Effects of Machine Soldering Using a Vapor Phase System IPC-TR-462 Solderability Evaluation of Printed Boards with Protective Coatings Over Long-tenn Storage IPC-TR-464 Accelerated Aging for Solderability Evaluations IPC-S-804 Solderability Test Method for Printed Wiring Boards (new revision ANSI/J-STD-003) IPC-S-805 Solderability Test for Component Leads and Ternlinations (new revision ANSI/J-STD-002) Summary of Important Component, Material, Process and Design Standards 327

IPC-S-815 General Requirements for Soldering Electronic Interconnections (new revision ANSI/J-STD-OOI) IPC-S-816 Troubleshooting for Surface Mount Soldering IPC-AJ-820 Assembly and Joining Handbook MIL-STD-2000A Standard Requirements for Soldered Electrical and Electronic Assemblies

Quality Assessment EIA-469-B Standard Test Method for Destructive Physical Analysis of High Reliability Ceramic Monolithic Capacitors EIA-510 Standard Test Method for Destructive Physical Analysis of Industrial Grade Ceramic Monolithic Capacitors IPC-A-600 Acceptability of Printed Boards IPC-A-610 Acceptability of Printed Board Assemblies MIL-STD-883 Methods and Procedures for Microelectronics

Reliability IPC-A-38 Fine Line Round Robin Test Pattern IPC-A-48 Surface Mount Artwork IPC-SC-60 Post Solder Solvent Cleaning Handbook IPC-AC-62 Post Solder Aqueous Cleaning Handbook IPC-AI-640 User Requirements for Automatic Inspection of Unpopulated Thick Film Hybrid Substrates IPC-AI-64I User Guidelines for Automated Solder Joint Inspection Systems IPC-AI-642 User Guidelines for Automated Inspection ofArtwork and Innerlayers IPC-AI-643 User Guidelines for Automatic Optical Inspection of Populated packaging and Interconnection Assemblies IPC-SM-785 Guidelines for Accelerated Surface Mount Attachment Reliability Testing

Test Methods EIA-JEDEC Method B lOS-A, Lead Integrity Plastic Leaded Chip Carrier (PLCC) Packages EIA-JEDEC Method B 102, Surface Mount Solderability Test (JESD22-B) EIA-JEDEC Method B 108, Coplanarity (intended for inclusion into JESD 22-C) IPC-TM-650 Test Methods Manual

Repair IPC-R-700 Guidelines for Repair and Modification of Printed Board Assemblies

Numerical Control Standards IPC-NC-349 Computer Numerical Formatting for Drilling and Routing Equipment IPC-D-350 Printed Board Description in Digital FormIPC-D-3S1 Printed Wiring Documentation in Digital Form 328 Fine Pitch Surface Mount Technology

IPC-D-352 Electronic Design Database Description for Printed Boards IPC-D-354 Library Fonnat Description for Printed Boards in Digital Fonn EIA-224-B Character Code for Numerical Machine Control Perforated Tape EIA-227-A One-Inch Perforated Tape EIA-267-B Axis and Motion Nomenclature for Numerically Controlled Machines EIA-274-D Interchangeable Variable Block Data Fonnat for Positioning, Contouring, and Contouring/Positioning Numerically Controlled Machines EIA-281-B Electrical and Construction Standards for Numerical Machine Control EIA-358-B Subset of American National Standard Code for Infonnation Interchange for Numerical Machine Control Perforated Tape EIA-408 Interface Between Numerical Control Equipment on Data Tenninal Equipment Employing Parallel Binary Data Interchange EIA-43I Electrical Interface Between Numerical Control and Machine Tools EIA-441 Operator Interface Function of Numerical Controls EIA-474 Flexible Disk Fonnat for Numerical Control Equipment Infonnation Interchange EIA-484 Electrical and. Mechanical Interface Characteristics and Line Control Protocol Using Communication Control Characters for Serial Data Link Between a Direct Numerical Control System and Numerical Control Equipment Employing Asynchronous Full Duplex Transmission EIA-494 32 BIT Binary CL Exchange (BCL) Input Fonnat for Numerically Controlled Machines Glossary

Adhesive Materials used to hold components in place during wave or reflow soldering which may become a permanent part of the assembly, or be subsequently removed.

Blow Hole A void in a solder connection caused by outgassing.

Castellation Metallized features that are recessed on the edges of a chip carrier which are used to interconnect conducting surfaces or planes within or on the chip carrier. Chip Carrier A low-profile rectangular component package, usually square, whose semiconductor chip cavity or mounting area is a large fraction of the package size and whose external connections are usually on all four sides of the package. Chip Component Besides ICs, the term includes diodes, inductors, resistors, and capacitors. A "1206" notation specifies the size of the device (0.120" X 0.060"), with other standard notations being 0805, 1210, 1812, etc. (CLCC) Ceramic Leaded Chip Carrier A ceramic chip carrier whose external connections consist of leads around and down the sides of the package. Cold Solder Joint A solder connection exhibiting poor wetting and a grayish, porous appearance due to insufficient heat, inadequate cleaning prior to soldering, or to ex cessive impurities in the solder. Component An individual part or combination of parts that, when together, perform a design function(s). Component Lead The solid or stranded wire or formed conductor that extends from a component and serves asa mechanical or electrical connection or both that is readily formable to a desired configuration. Component Mounting Site A location on a packaging and interconnection structure that consists of a land pattern and conductor fanout to additional lands/pads for test ing or vias that are associated with the mounting ofa single component. Constraining Core A supporting plane that is internal to a packaging and interconnecting structure. Contact Angle The angle enclosed within the solder fillet, between a plane tangent to the solder/base-metal surface and a plane tangent to the solder/air interface. Coplanarity Term used to describe the relationship of component leads to each other across the horizontal plane 329 330 Fine Pitch Surface Mount Technology

(CTE or TCE) Coefficient OfThermal Expansion The linear thermal expansion of a material per unit change as a result of temperature change.

Dewetting A condition which results when molten solder has coated a surface and then receded leaving irregularly shaped mounds of solder separated by areas cov ered with a thin solder film: Basis metal mayor may not be exposed. Double-Sided Assembly A packaging and interconnecting structure with components mounted on both the primary and secondary sides.

Fiducial An "etched" pattern on the printed circuit board used as an optical point of reference for measurement or calculation. Fillet The configuration ofsolder around a component lead and land. A blending or rounding of interconnecting conductors or leads which eliminates sharp comers. Flat Pack A component with two straight rows of leads, normally on 0.050" centers, which are parallel to the component body. Flux A chemically/physically active fonnation that is capable of enabling and promoting the wetting of metals with solder. Flux Solder Connection A solder joint characterized by entrapped flux that often causes high electrical resistance. Footprint(See preferred tenn LAND PATTERN). (FPT) Fine Pitch Technology The tenn used to describe the assembly technology for those IC packages having lead spacings of generally 0.65 mm (0.0256")or less. Fine Pitch IC Component Component packages with lead spacings of0.65 mm (0.0256") or less center to center.

(Ie) Integrated Circuit An assembly of miniature electronic components simulta- neously produced in batch processing, on or within a single substrate to perform an electronic circuit function. Infrared Radiation The band ofelectromagnetic wavelengths existing between the extreme of the visible and the shortest microwaves. The strong absorption of infra red by many substances renders it a useful means of applying heat energy. Infrared Reflow Soldering A reflow soldering furnace using infrared heating as the primary source of heat introduction in the furnace environment. Ionizableflonic Contaminants Process residues such as flux activators, fingerprints, etching and plating salts, etc., that exist as ions or when dissolved, increase electri cal conductivity.

Land A portion ofa conductive pattern usually, but not exclusively, used for the connection, or attachment, or both of components. Land Pattern A combination of lands intended for the mounting and interconnection of a particular component. (LCC) Leadless Chip Carrier A chip carrier whose external connections consist of metalized terminations.

(MELF) Metal Electrode Face A tubular shaped component with metalized tenninations for surface mounting. Glossary 331

Migration An undesirable phenomenon whereby metal ions, notably silver, are trans mitted through another metal in the molten state, or across an insulated surface, in the presence of moisture and an electrical potential. Mixed Mounting Technology A component mounting technology that uses both through-hole and surface mounting technologies on the same packaging and inter connecting structure.

Nonwetting A condition whereby a surface has contacted molten solder but the solder has not adhered to all of the surface: Base metal remains exposed.

(P/I Structure) Packaging And Interconnecting Structure The generic term for a completely processed combination of substrates, metal planes, or constraining cores and interconnection wiring used for the purpose of mounting components. Paste Flux A flux formulated in the form of a paste for special application, not to be confused with a solder paste or solder-paste flux. (PLCC or PCC) Plastic Leaded Chip Carrier A plastic chip carrier whose external connections consist of leads around and down the sides of the package. Primary Side The side ofthe packaging and interconnecting structure equivalent to layer # 1 (the same as the "component side" when using through-hole component mounting technology). (PCA or PWA) Printed Circuit or Wire Assemblyi.e. a PCB containing attached components and interconnecting traces. (PCB) Printed Circuit Board a board containing interconnecting traces.

Reworking The act of repeating one or more manufacturing operations for the purpose of improving the yield of acceptable parts

Secondary Side That side of the packaging and interconnecting structure furthest from layer# 1 (the same as the "solder side" when lIsing through-hole component mounting technology). Shadowing Occurs during wave soldering when the trailing termination of a component receives a smaller amount of solder than the leading termination due to the component body preventing the solder from flowing properly to the trailing termi nation. The body of the component may also cause "shadowing" of the termina tions of another component. Silk Screen A screen of a closely woven silk mesh stretched over a frame and used to hold an emulsion outlining a circuit pattern. Silk screens are lIsed in screen print ing solder paste. The term is used generically to describe any screen (stainless steel or nylon) used for screen printing. (SIP) Single In-Line Package A through-hole component which tenninates in one straight row of pins and lead wires. Single-Sided Assembly A packaging and interconnecting structure with components mounted only on the primary side. (SMA) Surface Mount Assembly Trademark by AWL A circuit assembly being primarily (60%) or wholly constructed using surface mount components. (SMC)Surface Mounted Component A component designed to be mounted and sol- 332 Fine Pitch Surface Mount Technology

dered to lands on the surface of a packaging and interconnecting structure rather than inserted into through-holes in the structure. (SMD)Surface Mount Device Trademark by Philips. The term is similar to SMC, surface mounted component. (SMT) Surface Mount Technology The mounting process of components on planar surface. (SO)Small Outline Similar to miniature dual in-line package, but with gull wing lead forms for surface mounting. Typical lead spacing:.050". (SOB) Small Outline Bridge A small outline full wave bridge similar in form to a SOT-143, but with greater body height. Solder A metallic alloy which has a melting temperature below 427°C (800°F). Solder Balls Small spheres of solder adhering to laminate, mask or conductor surfaces. Solder Bridging Unwanted formation of a conductive path by solder between conductors. Solder Connection An electrical/mechanical connection which employs solder for the joining of two or more metal parts. Solder Connection, Disturbed A cold solder joint resulting from motion between the joined members when the solder was solidifying. Solder Fillet A blended or meniscoid (rounded) configuration of solder around a component or wire lead and land. Solder Flux A chemically active formulation capable of promoting the wetting of metals with solder. Solder Paste (Cream) Mesh size controlled solder particles (spherical or nearly spherical) combined with a solder-paste-f1ux consisting of flux constituents to control vis cosity, thickness, slumping, drying rate, etc. Solder Projection An undesirable protmsion of solder from a solidified solder joint or- coating. Solder Webbing A continuous film or curtain ofsolder parallel to, but not necessarily adhering to, surface or between separate conductive patterns that should be free of solder. Solderability The ability ofametaI to be wetted by molten solder. Soldering A process ofjoining metallic surfaces with solder, without the melting of the base material. (SOT) Small Outline Transistor A surface mounted transistor package available in several forms. SOT-23, a three leaded device. SOT-89, a three leaded medium cur rent device. SOT-143, a four leaded device for gated transistors and dual diodes. Static Electricity An electric charge that has accumulated or built up on the surface of a material. The material may be conductive or nonconductive. In conductors, the charge can pass through the material. In nonconductors, the charge cannot pass and is in effect, locked in place, hence the tenn static electricity. Stencil A thin sheet material (metal) with a circuit pattern cut into it. Used for printing solder paste on a screen printer in lieu of a silk screen. Stress Relief The formed portion of a component lead or wire lead, providing suffi cient lead length to minimize stress between terminations. Supporting Plane A planar structure that is a part of a packaging and interconnecting structure to provide mechanical support, thennal-mechanical constraint, thermal Glossary 333

conduction, and/or electrical characteristics. It may be either internal or external to the packaging and interconnecting structure. Surface Mounting The electrical connection ofcomponents to the surface of a conductive pattern that does not utilize component lead holes. Surface Mount IC Component Component packages having lead spacings from 0.8 mm (0.03'') to 1.3 mm (0.05") center to center.

Terminal A metallic termination device used for making electrical connections. Thermal Expansion Mismatch The absolute difference in thermal expansion of two materials. Tinning A process for the application of solder coating on component leads, conductors and tenninals to enhance solderability. "Tombstones" The term describing component shift, by standing up vertically on one termination during the retlow process.

Vapor Phase Soldering Soldering accomplished by primarily conductive heat transfer during condensation of a high-temperature vapor of boiling fluorocarbon. The la tent heat of vaporization, given up during condensation of vapor on the relatively cool workpiece is the major source of heat for conductive transfer. Via A plated-through-hole used as a through connection between two or more layers of a packaging and interconnecting structure in which there is nointention to insert a component lead or other reinforcing material. Blind Via A via that is connected to either the primary or secondary side of a multilayer interconnecting structure but not both sides. Hidden Via A via located under a component. Tented Via A blind or thru-via that has the exposed surface on the primary, or secondary, or both sides of a packaging and interconnecting structure fully covered by a masking material, such as a dry film polymer covering (solder mask), pre-im pregnated glass cloth (prepreg), etc., in order to prevent hole access by process so lutions, solder, or contamination. Thru-Via A via that is connected between the primary and secondary side of a double sided or multilayer packaging and interconnecting structure. Visual Examination The qualitative observation of physical characteristics, utilizing the unaided eye or within stipulated levels of magnification. Void The absence of substances in a localized area.

Wetting The formation of a relatively uniform, smooth, unbroken and adherent film of solder to a basis metal. Whiskers Slender acicular (needle-shaped) metallic growth between conductors and lands. Index

Acceleration test, conditions and, 228 signature analysis, 249 Additive process, printed circuit boards, standards, 251-252 78-79 Buffer layer, 180 Adjustments, elimination of, 272 Bulk shipments, 51 Alloy Camera, and sequential automated placement, bismuth alloys, 110 159-162 eutectic solder, 11 0-111 Capabilities experiment, as predictive tool, indium alloys, 110 280-281 particle formation, 121-122 Capacitance particle shape, 119, 121 capacitance value, expression of, 102 solder creation of, 101-102 choices for solder, 108- I 12 Capacitors, 101 paste preparation, 119-121 Castellations, 104 tin-lead alloy, 109-110, 119 Ceramic quad flat packages, construction of, 38 tin-lead silver alloy, 109- 110 Chemical etching, 138 American Society for Testing and Materials, 29 Chip cracking, 62 Applications. See Product applications prevention of, 62 Aramid,83 Cleaning Automated optical inspection, other teclmology other technology compared to fine compared to fine pitch, 24 . pitch,24 Automotive sector, application for fine pitch post reflow. See Solder reflow, post reflow technology, 7 I cleaning Clock frequency, of digital circuit, 99 Bathtub curves, 219-221 Coefficient of thermal expansion, 56 Bed-of-nails testing, post reflow cleaning, 20 I, Compliant leads, 226, 230 202-203 Component testing, and placement of package, Bismaleimide triazine, 85 166-167 Bismuth alloys, 110 Component tolerances, 290 Board warpage, problem of, 96-99 Composite electrical properties, printed circuit Bond boards, 99- 104 bond and lead breakage, 59 Composite thermal properties, printed circuit low bond sweep angles, 59-62 boards, 104-106 Bonding resins, 84 Computer integrated manufacturing process printed circuit boards, 84-86 computer aided design, 310 Boundary scan testing, 248-252 computer aided engineering, 310 benefits of, 251 computer aided manufacturing, 310 new method for, 249 computer aided repair station, 311 334 Index 335

computer aided test system, 311 minimizing number ofdifference parts, Computers, application for fine pitch 273 technology, 68-69 use of standard parts, 268 Conduction, solder reflow, 181-186 written design guidelines, 273-274 Contract fabricators, printed circuit boards, Design of experiments, 280 79-80 Die flag, 30 Convection Digital voltage pulse, 84-85 free convection, 179-181 Direct contact printing, 134-135 solder reflow, 179-181 Downtime of system, 167 Copper coatings, 93-94 Dry film masks, 89-90 temporary coatings, 93-94 Dual-in-Iine packages, 6 Copper weights, specification for board, Ductility exponent, 230, 234 314-316 Costs Electrical guidelines, electrical testing, 260-263 advantages, of fine pitch technology, 10-14 Electrical properties, printed circuit boards, and design for manufacturability, 265-267 99-104 tooling and support costs, 26 Electrical testing Cracking of chip, 62 alternatives to in-circuit test Cracking of package, 53-59 boundary scan testing, 248-252 solution to, 58-59 no-test option, 246-248 Crosstalk, nature of, 102 contacting the assembly, 241-244 Cynate ester, 85 guidelines for electrical guidelines, 260-263 Defect collection, and placement of package, probing guidelines, 254-260 165 in-circuit test, disadvantages of, 244, 246 Defect rates, identification by cause, 274-276 nature of, 241 Delamination of board, 215 Electromotive force, 101 Delay time, computatio of, 10 I Electronic data transfer formats, types of, Design 310-311,313 abilities expected from designers, 284 Electronic design interchange format, 310 design review, 278 Electronic equipment fabrication of board, 309-316 application for fine pitch teclUlology, 69 land pattern size, 300-303 product use conditions and reliability, 234, package placement on board, 296-299 236 package selection, 285-296 Electronic Industries Association, 29, 49, 66 stencil fabrication, 317-318 Electrophoresis, 92 thermal management, 307-309 Epoxy resins, 84 trace routing, 304-307 types of, 56 Design for manufacturability Etching, stencil etching, 136-141 and cost, 265-267 Eutectic solder, 110- III implementation of Excise and fonn equipment, other technology acceptability of parts and materials, 282 compared to fine pitch, 24-25 management commitment, 281-282 Expanded polytetrafluoroethylene, 83 participation of company members, 276-278 Fabrication of board, 309-316 predictive tools, 278-281 correct copper weight, specification of, rules for 314-316 design for ease of orientation, 268-269 electronic data artwork, 310-314 design for variability, 274 fabrication notes, scope of, 310 determination of process capabilities, reduction of board warpage, 314 269-271 Fatigue at solder joint, cause of, 221-228 elimination of adjustments, 272 Fiberglass, 80, 82 elimination of multiple solder and cleaning Fiducial marks, and sequential automated steps, 271-272 placement, 162-163 identification of defect rates by cause, Fine pitch quad flat packages, construction of, 274-276 36 336 Index

Fine pitch technology Hot bar bonding, 164 advantages of solder reflow, 183-186 component cost savings, 12 cost advantages, 10 In-circuit testing. See Electrical testing package cost advantages, 10-12 Indium alloys, Il0 perfonnances advantages, 15-16 Infant mortality failures, 219-220 product cost savings, 12-14 Infrared heat source, solder reflow, 174-178 size advantages, 7-9 Initial graphics exchange definition, 310 assembly of packages, 7 Inspectability, 292 compared with through-hole and surface Inspection mount technologies, 19-25 subsurface inspection, 210-2 13 construction of packages, 29-30 surface inspection, 206-210 motivation for, 16-18 Interconnects-Packaging Connections nature of, 4-7 Association, 290 obstacles related to, 25-28 Internal energy, 194 core assembly techniques, 26-27 IPC-D-350 electronic data fonnat, 310, 313, elimination of rework and repair, 27 314 in-circuit testing, 27 IPC-D-358 electronic data fonnat, 313 package availability, 26 people resources, 28 Joint Electronic Device Engineering Council, process controls, 27-28 29,66 substrate compatibility, 27 Kevlar,83 package handling and shipping, 46-51 Kinetic energy, internal energy of molecule, 194 packages, types of, 6-7 plastic quad flat packages, 36-38 Lamination pressure, effects of, 98-99 printed circuit boards, 76-106 Laminography, 21 1-212 product applications, 68-74 Land quad flat packages, 30-36 land replacement, 216 reliability and quality of package, 51-64 meaning of, 300 selection issues Land pallern size number of options, 64, 66 design factors, 300-303 package standards, 66 length of land, 302-303 reliability and quality, 66-67 soldennask between land areas, 303 small outline packages, 38-42 width of land, 300-301 tape automated bonded packages, 42-45 Laser etching, 138 usage of, 74-75 Lasers, solder reflow, 186- 188 Flux,112-1l8 Leaching, definition of, 110 activity tests, 128 Lead breakage, 59 ideal, characteristics of, 112-113 Lead damage, problem of, 25 no-clean fluxes, 117 - 118, 201 Lead excise and fonn, and placement of post reflow cleaning, selection of no-clean package, 165- 166 flux, 201 Leadless chip carrier packages, 104-105 rosin fluxes, 113-114 and thermal expansion, 104-105 solder, paste preparation, 123 Lead planarity testing, and placement of synthetic resin fluxes, 115- 117 package, 165 Free convection, 179-181 Fudicial marks, 129 Management, commitment to design for manufacturing, 281 - 282 G+ fonnat, 311 Manual, design manual, 278 Gerberfonnat, 310-311, 313 Manual-aided placement, 155-156 Go-no-go test level, 291 of package, 155-156 Guard-ring flat package, 16 Manufacturability. See Design for manufaclurability Hardeners, types of, 56 Marking on package, 292 Heat absorption, basic concepts, 193-197 Mass reflow methods, 192-193 Heat insulators,.193, 196 Matrix trays, 34 Index 337

package handling and shipping, 47-48 construction of, 36, 38 Measles, 99 Polymide resin, 86 Memory cards, product applications, 71-74 Prebake, in solder reflow, 173-174 Prediction models, solder joint reliability, No-clean fluxes, 117-118, 201 228-234 No-test option, for fine pitch products, 246-248 Predictive tools capabilities experiment, 280-281 Offset printing, 134 Pareto analysis tool, 279 Original flat packages, construction of, 33-34 tally sheets, 278-279 Oxide reduction, solder reflow process, 170- 17 I Pre-reflowed solder, 94 Pressure, and placement of package, 165 Package handling and shipping, 46-51 Printed circuit board design, other teclmology bulk shipments, 51 compared to fine pitch, 24 matrix trays, 47-48 Printed circuit boards, 76-106 tape and reel, 49, 5 I composite electrical properties, 99-104 tubes, 48-49 composite thermal properties, 104-106 Package placement on board, 296-299 construction of, 76-80 design factors, 296-298 fabrication/assembly issues, 95-99 Package replacement, 215-216 functions of ideal board, 76 Package selection factors, 285-296 materials package designability, 285-288 bonding resins, 84-86 package manufacturability, 289-290 copper coatings, 93-94 package reliability, 293-296 reinforcing materials, 80-83 package repairability, 292-293 soldernlasks, 86-92 package testability, 291-292 Probing guidelines, electrical testing, 254-260 Pad with a hole, 300 Process capability Pareto analysis tool, as predictive tool, 279 definition of, 269 Parts orientation, 268-269 determination of, 270-271 Pattern plating, 99 index of, 269-270 Performance advantages, of fine pitch Product applications, 68-74 technology, 15-16 automotive sector, 71 Philips-Signetics tests, 56, 58 computers and peripherals, 68-69 Photoimageable masks, 90-92 electronic equipment, 69 Pin grid array, 6 memory cards, 71-74 Pin grid array package, 7 Pseudo-standards, 66 Placement machines other technology compared to fine pitch, 23 Quad flat packages, 6, 30-36 purpose of, 273 ceramic quad flat packages, 38 Placement of package construction of, 30-33 component testing, 166-167 fine pitch QFP, 36 defect collection, 165 original flat packages, 33-34 factors in, 149- 155 surface mount QFP, 34-35 lead excise and form, 165-166 thin quad flat package, 31, 33 lead planarity testing, 165 Quad flat style package, 25 manual-aided placement, 155-156 Quality of package, 51-64 place and reflow, 164 design factors, 293-296 placement pressure, 165 problems placement window values, 152-153 bond and lead breakage, 59 sequential automated placement, 156-163 chip cracking, 62 camera accuracy and resolution, 159-162 low bond sweep angles, 59-61 fiducial marks, use of, 162- 163 package cracking, 53-59 selection of system for, 158-159 thermal failures, 62-64 throughput requirements, 167 Quartz reinforcement, 82-83 Placement quill, 273 Quaternary solders, 110 Plastic chip carrier package, 16,25 Plastic quad flat packages, 36-38 Radiography, 211-212 338 Index

Reflow multiple solder, elimination of, 271-272 and placement of package, 164 paste application, 128-147 See also Solder reflow attaching the stencil, 144-146 Reinforcing materials, 80-83 design tips, 144 Aramid,83 squeegee, 130-135 expanded polytetrafluoroethylene, 83 stencil, 135-136 fiberglass, 80, 82 stencil alignment, 129 Kevlar,83 stencil etching, 136-141 printed circuit boards, 80-83 stencil frame, 146 quartz reinforcement, 82-83 stencil inspection, 147 Reliability. See Solder joint reliability stepped thickness stencils, 141 - 143 Rent's rule, I, 2 syringing solder paste, 146- 147 Replacement of package, 215-216 paste preparation, 119-123 Resin fluxes, synthetic, 115-117 particle formation, 121-122 Resins specifying the alloy, 119-121 bonding resins, 84 specifying flux, 123 epoxy resins, 84 paste testing, 125- 128 polymide resin, 86 flux activity tests, 128 Rework and repair slump test, 128 land replacement, 216 solder ball test, 125-126 other technology compared to fine pitch, 24 surface insulation resistance test, 127-128 package removal, 213-215 tack time test, 128 package replacement, 215-216 viscosity test, 126-127 Rosin solvents, and thixotropes, 118- 119 extraction from tree, 114 storage of, 123-125 grading of, 114 Solder ball test, 125-126 Rosin fluxes, 113-114 Solder joint reliability design for reliability guidelines, 236-239 Screenable masks, 88-89 lead size in, 238-239 Sequential automated placement, 156-163 electronic product use conditions, 234-236 camera accuracy and resolution, 159-162 factors in, 218 fiducial marks, use of, 162-163 failure probabilities, 219-221 selection of system for, 158- 159 infant mortality, 219 Signal attenuation, calculation of, 104 nature of, 218-219 Signal travel time, 100 prediction models, 228-234 Signature analysis, 249 solder joint fatigue, causes of, 221-228 Slump test, 128 Soldemlasks, 86-92 Small mount technology, semiconductor dry film masks, 89-90 outlines, 320--322 functions of, 86-87 Small outline packages, 38-42 ideal, characteristics of, 87 -88 construction of, 38-42 photoimageable masks, 90-92 thin small outline packages, 40, 42 screenable masks, 88-89 Snapoff height, 132 Solder reflow Soak, solder reflow, 196 changing component location during, Solder 197-198 alloy choices, 108-112 factors in success of, 169 application methods for fine pitch surface heat absorption, basic concepts, 193- 197 mount applications, 107 heat source, 174- 190 flux, 112-118 conduction, 181- 186 flux classification methods, 115-117 convection, 179- 181 ideal, characteristics of, 112-113 hot bar bonding, 183- 186 no-clean fluxes, 117 - 118 infrared heat source, 174- 178 rosin fluxes, 113-114 lasers, 186- 188 synthetic resin fluxes, 115- 117 themlode bonding, 183-186 ideal, characteristics of, 107 thermosonic energy, 188-191 issues related to, 108 vapor phase, 178-179 Index 339

other technology compared to fine pitch, Surface insulation resistance test, 127 - 128, 23-24 203-204 phases of Surface Mount Council, 290 complete solder melt, 171-172 Surface Mount Equipment Manufacturers' cool down, 172-173 Association, 178 oxide reduction, 170-171 Surface mount quad flat packages, construction prebake, 173-174 of,34-35 solder melt, 171 Surface mount technology, compared with fine solvent evaporation, 170 pitch technology, 19-25 temperature vs. time rate in, 173 Synthetic resin fluxes, 1I5-11? post reflow cleaning Syringing solder paste, 146-147 bed-of-nails testing, 201, 202-203 reason for cleaning, 200 Tack time test, 128 selection of no-clean flux, 20 I Tally sheets, as predictive tool, 278-279 shipping/storing no-clean assemblies, Tape automated bonded packages, 6, 42-45 205 assembly, II steps in no-clean process, 20I construction of, 42, 44 surface insulation resistance test patterns, TapePak,44-45 201-202 Tape on reel testing for cleanliness, 203-205 package handling and shipping, 49, 51 reflow method sequential automated placement, 157 criteria for method, 191-192 TapePak, construction of, 44-45 factors in selection of, 191 Tenting, 305-307 mass methods, 192- 193 advantages/disadvantages of, 307 Solvents Ternary solders, 110 evaporation, in solder reflow, 170 Testability, of package, 291-292 solder, 1I8-119 Test pattern, surface insulation resistance, Squeegee, solder paste application, 130-135 201-202 Standard parts, use of, 268 Thermal conductivity, 295-296 Standards Thermal conductors, 193 component/materialfprocess/design Thermal failures, 62-64 standards, 323-328 Thermal management, 307-309 organizations, addresses of, 319 drawing heat from bottom of package, Standards of package, 66 307-308 official bodies for, 66 thermal grease, 308 pseudo-standards, 66 thermal vias, 308-309 Stencil Thermal properties other technology compared to fine pitch, and leadless chip carrier packages, 104- 105 22-23 printed circuit boards, 104-106 solder paste application, 128-147 Thermal resistance, 295 attaching the stencil, 144-146 measure of, 62 design tips, 144 Thern10set plastics, 55-56 inspection, 147 Thermosonic energy, solder reflow, 188-191 squeegee, 130-135 Thin quad flat package, 31, 33 stencil, 135-136 Thin small outline packages, 6, 33, 36 stencil alignment, 129 construction of, 40, 42 stencil etching, 136-141 Thixotropes, solder, 118- 119 stencil frame, 146 Through-hole assembly technology, compared stepped thickness stencils, 141-143 with fine pitch technology, 19-25 syringing solder paste, 146- 147 Tin-lead alloy, 109-110, 119 Stencil fabrication, 317-318 Tin-lead silver alloy, 109-110 Stepped thickness stencils, 141-143 Trace routing, 304-307 Subsurface inspection, process of, 210-213 placement of vias, 304-305 Subtractive fabrication process, printed circuit tenting, 305-307 boards, 76-78 Transfer molding, 55 Surface inspection, process of, 206-210 Tubes, package handling and shipping, 48-49 340 Index

Thrbulent core, 180 Viscosity test, 126-127

Unencapsulated TAB, 6 Warpage of printed circuit board, 96-99 Vapor phase, solder reflow, 178-179 reduction of board warpage, 314 Variability, design for, 274 Wicking, 179 Very small outline, 6 Written guidelines, design guidelines; 273-274 VHSIC hardware description language, 310