An implant for a visual cortical stimulator

Jonathan Coulombe, Yamu Hu, Jean-François Gervais, Members, IEEE,

Mohammad Sawan, Fellow,T IEEET

Implant Device Abstract - We present the design of an implantable micro- External stimulator intended for a cortical visual . The device is Controller Modulated Power Carrier Power composed of several integrated modules to be assembled on a Recovery Amplifier thin and flexible substrate providing placement flexibility on the OUT/IN cortex. The stimulator provides the user with significant usage Stage Modulator/ Controller flexibility, supplying biphasic current pulses using either Demodulator monopolar or bipolar configurations, with single or distributed return electrode, and having a fixed or dynamic reference voltage. Monitoring of electrode-tissue interface condition is Fig. 1. Bloc diagram of a wireless implant. possible by measuring both simulation currents and voltages at hundred sites [4-5]. Transfer data rates usually grow any electrode for enhanced safety, and for enabling according to the number of stimulation sites. troubleshooting after implantation. In order to avoid erroneous In the specific case of implants designed for restoring stimulation to be executed, potentially caused by the implant's wireless transcutaneous power transfer, constant parameters functional vision to the blind via intra-cortical stimulation [6- stored in volatile memory are constantly monitored, and in case 8], subject of the current work, back telemetry (uplink) data of data corruption, stimulation is automatically disabled. rate for occasional monitoring, and the amplitude of A power efficient recovery and regulation circuit is proposed stimulation currents for single sites requirements are low, in for providing dual supply voltages. Also, a bidirectional wireless the range of tens of kHz and µA [9]. On the other hand, the link with data rates up to 1.5 Mbps and 500 kbps, downlink and number of stimulation sites/channels is very high. Indeed, for uplink respectively, has been designed for use with a 13.56 MHz a meaningful image to be perceived by the user, hundreds of carrier. Performances attained with a prototype, combined with the stimulator module's configurable communication protocol, stimulation sites are expected to be required [10]. This puts are suitable for a cortical implant having more than 1000 severe constraints on the external to internal (downlink) data stimulation sites, which is expected to be sufficient for providing rate and the total power efficiency of the device. blind subjects with a useful vision. This latter consideration is especially important for safety, most probably the prime concern for implants intended for I. INTRODUCTION chronic use. As a matter of fact, higher device power LECTRONIC implants are nowadays used in several consumption not only increases tissue temperature because it Ebiomedical applications, and share many features and dissipates heat, but also implies higher electromagnetic field basic components. As shown in Fig. 1, chronically implanted density through tissues when powering up the device by use wirelessly powered stimulating (recording) devices are of an electromagnetic link. composed of a power recovery module, external and internal In addition to keeping device’s power consumption to a communication modules for modulating and demodulating minimum, features to ensure safe stimulation are desired. data signal encoded over the electromagnetic wave, an output Finally, the current stage in research does not allow for (input) stage, and a central digital controller. deciding on definitive stimulation strategy and optimal The designer has to take into account the targeted parameters. Therefore flexibility is a key issue for today’s application for decisions concerning the required (tolerated) prototypes. maximum/minimum currents and voltages of the output We will present in the following sections the main modules (input) stage, the number of channels, the data rate, and so on. of an implantable intra-cortical visual stimulator design for Depending on the application, requirements can vary which specific optimization effort has been taken regarding substantially. For example, peripheral nerve stimulators issues mentioned above. Section II will give an overview of generate a few milliamperes on a very limited number of the design, described in more details in section III. Results channels [1-2]. Cochlear implants have similar current from experimental testing of the main modules are presented requirements, on up to 20 channels [3], and implants in section IV, and the main performances will be used to intend to deliver hundreds of µA to approximately one verify if the design is suitable for a prosthesis having more than one thousand stimulation sites.

Authors are with the PolySTIM Neurotechnology Laboratory, École Polytechnique de Montréal, Canada (corresponding author: Jonathan Coulombe; e-mail: [email protected]).

II. STIMULATOR OVERVIEW stimulation site is made available to the user. The voltage to For placement flexibility of the implant over the cortex and be monitored is buffered from the appropriate SM, and minimal pressure on tissues, a thin and modular approach is digitization is performed on the IM prior to uplink telemetry. adopted, as opposed to a monolithic design such as what is If a SM output current is to be monitored for electrode-tissue presented in [11]. The design comprises several small size interface impedance monitoring, the actual current is stimulation chips (Stimulator Module – SM) lying flat on the monitored through a second return electrode (MonRef). cortex, connected to penetrating microelectrode arrays, and a module, placed away from the stimulation sites, interfacing III. DESIGN DESCRIPTION with external components (Interface Module – IM). All A. Stimulator Module components are to be laid out on a common thin flexible substrate, eliminating the need for connectors. Fig. 2 shows a A simplified block diagram of the SM is shown in Fig. 3. In simplified schematic of the device to be implemented from the the case of the prototype presented in this paper, each SM has modules described in the next sections. four parallel channels, each driving four stimulation The SMs generate constant current biphasic pulses, using microelectrodes (sites). All parameters of stimulation pulses monopolar or bipolar configurations. In the case where (amplitude – A –, phase duration – D – and interphase monopolar stimulation is used, the return current indifferent duration) are programmable. Pulses frequency, as well as train electrode (Ref) can be distant from the stimulation sites, and inter-train durations, are determined by the rate at which connected to the interface module, or distributed among individual pulses are being triggered by the external inactive stimulation microelectrodes. controller. Electrode shorting can be performed between Communication is ensured by a half-duplex data link using pulses to ensure charge balance of biphasic pulses. amplitude modulation with On Off Keying (OOK) and Load In order to minimize power consumption, the controller Shift Keying (LSK) for downlink and uplink, respectively. uses a low voltage supply and a configurable communication Low voltages are used both for control and for stimulation. protocol, minimizing data transfers and its operating clock The latter, however, brings the risk of clipping the stimulation frequency. To achieve this, every stimulation parameter is sent pulses if large voltage swing for a particular is required. Since to the stimulator with a minimal resolution defined in an initial the electrode voltage is usually asymmetrical with respect to configuration sequence, or is omitted in case a constant the reference electrode, charge imbalance may occur, which in parameter can be used. Stimulation on parallel channels can turn may damage tissues permanently [12]. For this reason, be either sequential (activated upon reception of simulation considering that electrode-tissue impedance varies with time, data) or synchronized. In the latter case, parameters are stored and for troubleshooting after implantation, monitoring of any to the appropriate channel controller when received and all stimulations are activated by a subsequent trigger instruction. Interface Module. Stim Stim Mod. Mod. Bi-directional current sources are made of complementary Coil Regul. thermometer code digital to analog converters, as described in PWR Pwr Monit. [13], and have four operating ranges (from 17 to 140 µA). & Tx Stimulation sites are activated through a switch matrix (Fig. Data Ctrler. 4), which also performs the task of selecting sites for electrode voltage monitoring. The voltage is buffered by a unity gain Ref Stim Stim Mod. Mod. rail-to-rail amplifier, whose output is connected to a common Vmon bus for all SMs. Fig. 2. Proposed Multi-Module implant. Because the device is powered via an inductive link, power

Frame 0 Clk Error Start/ h c #

Detec./ t i . Correc. Stop l Data parall ) 0 Sw Ctr nel # . 3 V l . C

Configuration Manager han . 3 Ctr Err #3 d C

(Data Corrupt. Detec.) DA tor m .8 - a r 1 ( C . .

... Electrode s

m REF ene i Switch .. G fter St M i Matrix 3 h h c SSA S # RA t

. i l l r e l v 3 Sw Ct # Le nne . l a h C Ctr C #0 DA Stim Clk

Band-Gap Bias Vmon R2R

Fig. 3. Stimulator Module bloc diagram

VDD − transfers appropriate commands to one or many CAN vdd_on_i,j vdd_on_i,j+1 stimulation modules in a specific or broadcast manner; dac_on_i,j dac_on_i,j+1 − manages monitoring operations and results; ref_on_i,j ref_on_i,j+1 − sets the reference voltage (with respect to the tissue vss_on_i,j potential); REF − manages SM activity to minimize power consumption. mon_site_ j mon_site_ VSS mon_chan_i mon_chan_i

mon_site_ j+1 Vmon 1) Power regulation

For regulating the rectified signal VB ,B low drop-out (LDO) Fig. 4. Analog switches controlling the current flowing in stimulation sites j rec and j + 1 on channel i. Grey squares represent electrode. linear regulators are used in implantable applications due to From Config. Manager decoder their low-noise and small size, as shown in Fig. 7. Regulators

19 using N-type pass devices show fewer stability problems,

19 Parity Encoder better regulation and lower ohmic output impedance characteristics than their P-type equivalents. 20 Configuration Register Parity Checker However, regular N-type pass devices require their gate voltage to be significantly higher than their source output, 20 Error making the LDO impossible if the feedback amplifier is 20 powered by the input voltage. This would result in reduced power efficiency and stimulating current compliance, limited To Parameter bus/other modules by the voltage swing of the SMs output stage. The problem can be eliminated by using a transistor for Fig. 5. Configuration parameter corruption detection. which the threshold adjustment step is omitted in the shortage may occur caused by accidental coil movements. In fabrication process (native device). These transistors have such a case, parameters stored in volatile memory will be their VthB B much lower than regular transistors (typically corrupted, resulting in every subsequent stimulation to differ negative), at the expense of showing larger discrepancies from what is expected by the user, leading to hazardous between samples. In the case where the device is used in a results. To prevent such situation from happening, every negative feedback loop, however, this is not an issue. On the configuration parameter is parity encoded prior to be stored, other hand, a regular transistor can be used for the low voltage and valid parity of every parameter is continuously verified, as output since the high regulated voltage provides sufficient shown in Fig. 5. Upon data corruption detection, stimulation is voltage swing at the output of the feedback amplifier. inhibited, and registers have to be reloaded to continue For better power efficiency, a step-down switch capacitor stimulation normally. Odd parity on an even number of bits is circuit is intended to be used between NM1 and M1 drains. chosen to avoid undetected register set or reset errors. However, this has not been implemented to date and is part of current work. B. Interface Module The reference voltage required by both regulators, VrefB ,B is Fig. 6 shows a simplified schematic of the IM, which set by a bandgap circuit, for which the most important decodes and transfers stimulation instructions to the characteristic in the present application is its line rejection. As appropriate SMs and sends telemetry data to the external user. a matter of fact, temperature does not vary substantially, but The IM controller : the rectified voltage shows strong ripple because a small tank − manages half-duplex communication cycles; capacitor must be used at the input for size considerations. For

REF MONREF

VRef Return elec. set VRec & Monitoring

ASK in VH

Regulator VL PWR Vmon To/From Data, Clk SM 1 Error LSK out

VMod Communication Controller PWR M1 Vmon To/From Data, Clk SM N Error

Fig. 6. Interface Module simplified schematic.

Vrec Large VTh Coil NM 1 M Vref + + 2 A Error Error Env Amp1 Amp2 - V - V Majority H L Narrow VTh Delay B

a)

Fig. 7. Dual output LDO regulator. VTh1 VTh2

M 5 M6

Dig. In A M 7 Dig. In B Reg. A out M 8 Reg. B out M M M M 1 2 4 3 Bandgap Vref Env Vrec VH b) Fig. 9. a) Digital demodulator and b) associated waveforms. Fig. 8. Start-up and reference circuits for LDO regulator.

0 1 0 this reason, usage of the regulated VHB B voltage is preferred over Envelop VrecB B as the bandgap reference’s input. However, both the regulator and the reference are then interdependent. So a start- Counter 01… 0 1 N 01 0 up circuit is used to provide the bandgap reference with the Latched rectified voltage on power up, and then switch to the regulated Envelop voltage when the latter becomes sufficient. Clock

The start-up circuit compares VRecB B and VHB ,B and feeds the Data Out larger of the two to the bandgap reference, as shown in Fig. 78. Transistors M1-M6 form two positive feedback loops, Fig. 10. Extracted envelop and data waveforms. modulated by M1 and M3, and function as a regenerative digital clock and data extractor. The carrier is used for comparator. generating a data clock at a constant frequency determined by 2) Data link

a fixed fB /fB B B ratio. Data modulation uses a constant A completely digital demodulator is used for extracting Carrier Data clk high period for ones and a short low pulse at the end of the clock and data signals from an OOK modulated 13.56 MHz data period for zeros. Envelope low levels reset the carrier carrier. Envelope detection is performed by directly digitizing counter, which restarts running when the envelope goes back the input carrier using schmitt inverters with different to high. Waveforms associated to data extraction are shown in threshold levels (∆VB ),B as shown on Fig. 9. An envelope high th Fig. 10. level results in both inverters toggling at the carrier frequency, The modulation index of the received signal does not need while a low level results in constant high outputs. However,

to be equal to 100% for the large ∆VB B to stop toggling, and the because of the gradual decay/rise of the carrier envelope, th period for which the envelope is low is irrelevant for data caused by the channels limited bandwidth and the stored extraction. Therefore, low pulses can be kept short, allowing energy in the receiver resonant circuit continuing oscillations for a high duty cycle, highly desirable in ASK modulation when the rectifier cuts off, the inverters will cease their since the modulated signal is used for powering the device. toggling activity for different periods. The output of the The LSK modulation technique introduced by Tang et al. is narrow ∆VB B inverter is used for sampling the state of the wide th used for uploaded telemetry. Turning M1 (Fig. 6) on and off ∆VB B inverter. Also, to minimize the risk of glitches on th changes the rectifier from full-wave bridge to half-wave envelope level transitions, three consecutive samples are used configurations, hence its equivalent input impedance, resulting as inputs to a combinatorial logic majority detector. in detectable load variations [14]. Most of the power consumption is dissipated by the schmitt 3) Communication protocol inverters, being maximum when the input signal ceases and The implant uses a half-duplex communication protocol. stabilizes between logic input levels. The inverters are Each cycle is composed of an initializing header, any number optimized for presenting the largest possible output resistance of data instructions for the IM or SM (configuration, while allowing their output to toggle at the carrier frequency. stimulation, or monitoring), followed by a reply from the With the technology used (0.18µm 1.8/3.3V CMOS process), implant including monitoring results, and flags that are set in simulations shows that this results in a maximum short-circuit case communication errors were detected in the preceding current of 300 µA. downlink data stream, or if volatile configuration parameters The digitized carrier and envelope signals are fed to a are corrupted. A stream of ones for 400ms resets the system.

TABLE I INTEGRATED CIRCUITS MEASUREMENT RESULTS Ref En IM SM From Circuit Parameter Condition Measurement A Ctrl. Ref DAC Regul. VHB B ILB B = 5 mA 3.2 V B When VLB B ILB B = 5 mA 1.82 V AB Ref stimulating VDrop-outB HB ILB B = 5 mA < 140 mV 0 0 VSS 0 1 VDD/2 MonRef 1 0 VDD/2 VDrop-outB LB ILB B = 5 mA < 100 mV 1 1 VDD When IQuiescentB B 400 µA monitoring a To ADC Comm. Data rate ASK (Dn) max P P 1.507 Mbps a LSK (Up) max P P 1.13 Mbps Fig. 11. Return electrode (Ref) and current monitoring circuits. b IcommB PB P VinB B = VDD/2 130 µA SM Phase Mismatch < 3% On power-up, an initial handshake allows the user to ensure DNL 5-bit resolution 0.39 LSB INL 5-bit resolution 0.55 LSB that coil alignment and transmitted power are adequate for IAnalogB B 180 µA error free data transfer. This is followed by a configuration IDigitalB B fDataB clk =B 1 MHz 150 µA sequence, in which data rates are determined, as well as a P P fCarrierB =B 13.56 MHz. uplink/downlink packet lengths. 4) Return electrode and Monitoring measured allow us to make reasonable assumptions on the For monopolar stimulation, an indifferent return current performance of a complete prosthesis. electrode has to be set to a known fixed voltage. Typically, a 1) Data rate constant input voltage follower is used to keep the electrode A possible implementation of a complete visual stimulator sinking and sourcing the total stimulation current at a constant comprising 1024 stimulation sites is composed of 32 SM, each voltage [15]. counting 32 sites distributed on 6 channels. In this case, However, the SM output stage suffers then from reduced considering that 5 bits are required for addressing the voltage swing, limited to half the supply voltage. To increase stimulation sites, and using the configurable communication the allowable stimulation current, the return electrode voltage protocol of the SMs for defining instructions with 20 bits can be dynamically set to the positive or negative supplies by including data encoding for error detection and correction, the controller. stimulation patterns can be sent in 13.3 µs at a data rate of 1.5

Monitoring stimulation voltage and current should be Mbps (fCarrierB /fB DataB clk =B 9). Assuming that the uplink/downlink performed to ensure that stimulation stays within safe limits data ratio is negligible, images can be sent at a rate of 60 Hz and for troubleshooting. Fig. 11 shows the current monitoring for all sites. If one assumes that an average of two thirds of the circuit present on the IM. Monitoring voltage at some sites are activated for each transmitted image, stimulation can electrode is straightforward and needs no change in the be performed at a rate of 100 Hz. stimulation configuration. The voltage of one SM monitoring 2) Power Consumption buffer is enabled, and its output is sampled by an analog-to- A rough estimate of the total power consumption of such a digital converter on the IM. stimulator, including the dissipated power by the LDO pass For current monitoring, only a single stimulation site in the devices, can be calculated as system can be active, configured for monopolar stimulation, (1) PTotalB B = VrecB B (IIMB B + 32 ISMB B + IStimB )B and other electrodes have to remain in a high impedance state.

The return electrode Ref also goes to high impedance. The where, IIMB B and ISMB B denote the power consumption of the IM stimulation current is then forced to flow through MonRef, and SM. They are given by whose input voltage is kept to VrefB B by the monitoring IIMB =B IregB +B IcommB +B IctrlB +B IperiphB ,B (2) amplifier’s negative feedback, which output is proportional to the stimulation current. ISMB =B IAnalogB +B IDigitB .B (3)

And IStimB B is the stimulation pattern dependant current, IV. IMPLEMENTATION AND RESULTS calculated by The main circuits of the system, namely the

IB =B αN · A · 2 DP · f (4) communication, power regulation and SM circuits, have been Stim fabricated on a standard 0.18 µm CMOS process. Using these where αN represents the number of activated sites for an as well as commercial components, a non implantable average image, and A, DP and f are the average pulse prototype has been implemented. Assembly of the modules parameters respectively. and the micro-electrodes on a flexible miniature substrate are Considering that the number and size of the IM components to be completed before the device can be implanted for in- are approximately independent of the number of stimulation vivo testing. Performances of the tested integrated circuits are sites, that the power consumption of a SM is at maximum summarized in Table I. proportional to the number of channels, and assuming two Although the presented components are designed for a thirds of the total stimulation sites are activated at any time (α reduced size prototype, and complete integration as well as N = 2/3 · 1024) with parameters A = 100 µA, DP = 100 µs and final assembly remains to be realized, the parameters f = 100 Hz, a power budget of 40 mW is sufficient.

V. SUMMARY Topics Conference on Microtechnologies in Medicine and Biology, 277- 282, May (2002) The design and realization of prototypes of the main components of an intra-cortical visual stimulator have been presented. The device offers full latitude on parameters and configurations. Low power is achieved by low voltage of both control and stimulation stage modules, the later being possible especially with dynamic voltage low impedance return current electrode, as well as by the usage of programmable parameters, reducing data and clock rates. Safety features include volatile memory checking, and stimulation voltage monitoring. Measurement on prototype components show that the most stringent performance requirements for a stimulator with 1000 sites are met.

ACKNOWLEDGMENT Authors acknowledge helpful contributions from L.-X. Buffoni, the Canadian Microelectronics Corporation for fabrication and technical support, and the National Sciences and Engineering Research Council of Canada for financial support.

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