Remote Radio Heads and the Evolution Towards 4G Networks.Pdf

Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate.

Altera Corporation Altera European Headquarters Altera Japa Ltd. Altera International Ltd. 101 Innovation Drive Holmers Farm Way Shinjuku i-Land Tower 32F Unit 11- 18, 9/F San Jose, CA 95134 High Wycombe 6-5-1, Nishi-Shinjuku Millennium City 1, Tower 1 USA Buckinghamshire Shinjuku-ku, Tokyo 163-1332 388 Kwun Tong Road Telephone: (408) 544-7000 HP12 4XF Japan Kwun Tong www.altera.com United Kingdom Telephone: (81) 3 3340 9480 Kowloon, Hong Kong Telephone: (44) 1494 602000 www.altera.co.jp Telephone: (852) 2 945 7000 www.altera.com.cn

Christian F. Lanzani,∗ Georgios Kardaras,† Deepak Boppana‡

Abstract ::;<%:(("(> ::;<%,"??%@(=)' ::;<%5(8$*%.(=)' Distributed base stations with remote radio head (RRH) capability greatly help mobile operators to resolve cost, performance, and efficiency challenges when deploying new base stations on the road to fully developed 4G networks. Multi-mode radios capable of operating according to GSM, HSPA, LTE, and WiMAX standards and advanced software config- urability are key features in the deployment of more flexible and energy-efficient radio networks. This white ,-./0%(*% paper describes the key market and technology require- !"#$%&'"!()%&$*+$* 1233%456%7$'8(*9 ments for RRHs and how Radiocomps state-of-the-art WiMAX/LTE RRH and intellectual property (IP) core A!&/B%(*%C3:B%*"'$#%=>%'(%1# solutions, combined with latest FPGA technology from A>!H"?%!G$*#%=>%'(%FD%9@ Altera, helps design compact, green, and full-featured &("8"*$%H()!I=*"G?$%A!&/BLC3:B%G-'%*"'$ applications for mobile network solutions. &("8"*$%H()!I=*"G?$%HJ"))$?%G")K8-K'J

Keywords: LTE, WiMAX, Remote Radio Head, OB- SAI, CPRI, CFR, DPD, DSP, SRC, Radiocomp ApS, Altera, Figure 1: Distributed Wireless Base Station system. StratixIV GX, ArriaII GX, DTU, FPGA.

ure 1) have evolved in parallel with the evolution of INTRODUCTION the standards to provide a flexible, cheaper, and more scalable modular environment for managing the radio Wireless and mobile network operators face the con- access evolution. For example, the Open Base Station tinuing challenge of building networks that effectively Architecture Initiative (OBSAI) and the Common Pub- manage high data-traffic growth rates. Mobility and lic Radio Interface (CPRI) standards introduced stan- an increased level of multimedia content for end users dardized interfaces separating the Base Station server require end-to-end network adaptations that support and the remote radio head (RRH) part of a base station both new services and the increased demand for broad- by an optical fiber. band and flat-rate Internet access. In addition, network operators must consider the most cost-effective evolution of the networks towards 4G. Wireless and mo- II - RRH SYSTEM REQUIREMENTS bile technology standards are evolving towards higher bandwidth requirements for both peak rates and cell- The RRH concept constitutes a fundamental part of a throughput growth. The latest standards supporting state-of-the-art base station architecture. RRH-based this are HSPA+, WiMAX, and LTE. system implementation is driven by the need to reduce The network upgrades required to deploy networks both CAPEX and OPEX consistently, which allows a based on these standards must balance the limited more optimized, energy-efficient, and greener base de- availability of new spectrum, leverage existing spec- ployment. Figure 2 illustrates an architecture where trum, and ensure operation of all desired standards. a 2G/3G/4G base station is connected to RRHs over This all must take place at the same time during the optical fibers. Either CPRI or OBSAI may be used to transition phase, which usually spans many years. Dis- carry RF data to the RRH to cover a three-sector cell. tributed open base station architecture concepts (Fig- The RRH incorporates a large number of digital in- terfacing and processing functions as depicted in Fig- ∗email: [email protected], www.radiocomp.com †email: [email protected], www.radiocomp.com ure 3. It also includes high-performance, efficient, and ‡email: [email protected], www.altera.com frequency-agile analog functions, all packaged into a

1 Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate.

Figure 3: RRH System Architecture. Figure 2: Three-Sector Wireless Call using RRH.

more elegant and takes advantage of advanced digital low-weight (9.7 Kg) device with a small mechanical signal processing (DSP) techniques for converting each footprint. The key advantages of using RRHs such as rate into a common system rate. Together these tech- Radiocomps are listed in Table 1. niques are called sample rate conversion (SRC), and Smaller footprint. Easier installation, reduced when combined with multi-channel digital upconver- • wind load, lower site rental costs, optimized cover- sion (DUC) and digital downconversion (DDC),, they age. enable multiple sample rates to be processed concurrently in the same application and in the same clock Flexibility in Software. Remote upgrades domain of the digital-to-analog converter (DAC) or • and frequency-agile operations, easier capacity up- analog-to-digital converter (ADC). This method en- grades. ables flexibility by supporting both single-clock and multiple-clock techniques simultaneously. As an ex- Higher performance. High power efficiency, ample, the LTE and WiMAX standards define a selec- • spectral emissions requirements, sensitivity, capac- tion for a number of channels with instantaneous band- ity widths up to 20 MHz. In multi-mode radios support- Multi-mode operations.Combined and concur- ing OFDMA/WCDMA modulation schemes, a flexible • rent multi-standard operations reduce equipment SRC greatly helps to make software-defined operations needs. possible. Test results of Radiocomps SRC intellectual property (IP) shows that sampling noise added to a Flexible multi-carrier capability. Frequency • WiMAX signal with a sampling rate of 11.2 MHz to agility, easier capacity upgrades 122.88 MHz can be kept below 74 dB, thus providing The most recent OFDMA-based standardsWiMAX higher system performance together with software flex- and LTEinclude 20 MHz wideband radio channels for ibility. both Time Division Duplexing (TDD) and Frequency Division Duplexing (FDD) operational modes. The throughput is enhanced by multiple-in/multiple-out IV - CFR CREST FACTOR REDUCTION (MIMO) antenna techniques. Both 2x2 and 4x4 MIMO An OFDM signal has a large peak-to-average enve- systems are attractive solutions meeting the small lope power ratio, which results in significant distor- footprint requirements of the radio module. This is tion when passed through a non-linear device such as achieved by combining the energy-efficient radio mod- a power amplifier (PA). The objective of the crest fac- ule with advanced internal cable less geometry. tor reduction (CFR) technique is to reduce the peaks of the OFDM signal to a satisfactory level to ensure III - MULTI-RATE DSP APPLICATIONS FOR RRH better usage of the PA. Due to the signal’s reduced dynamic range, it is possible to operate at higher aver- It is highly desirable to support multiple radio channel age power and hence closer to the PAs saturation point bandwidths per channel, e.g., WiMAX 5, 7, 8.75, 10, when combined with digital pre-distortion (DPD). A and 20 MHz in one radio platform, using only pure soft- well-known effective CFR technique is the peak win- ware reconfiguration. Moreover, it is highly desirable dowing approach, where power peaks exceeding a cer- to support multiple channels concurrently in a multi- tain threshold are clipped and smoothed by filtering. carrier system fashion. To achieve this, the designer The filtering mitigates unwanted out-of-band spectral must choose between using a different clock domain for products caused by the sharp signal edges of conven- each rate and using one single-clock domain with soft- tional clipping. Peak windowing approaches may offer ware flexibility. The single-clock domain technique is several decibels of improvement, with 3 to 7 dBs of

2 Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate.

$PQZSJHIU¥"MUFSB$PSQPSBUJPO"MMSJHIUTSFTFSWFE"MUFSB ѮF1SPHSBNNBCMF4PMVUJPOT$PNQBOZ UIFTUZMJ[FE"MUFSBMPHP TQFDJêDEFWJDFEFTJHOBUJPOT BOEBMMPUIFSXPSET BOEMPHPTUIBUBSFJEFOUJêFEBTUSBEFNBSLTBOEPSTFSWJDFNBSLTBSF VOMFTTOPUFEPUIFSXJTF UIFUSBEFNBSLTBOETFSWJDFNBSLTPG"MUFSB$PSQPSBUJPOJOUIF64BOEPUIFSDPVO- USJFT"MMPUIFSQSPEVDUPSTFSWJDFOBNFTBSFUIFQSPQFSUZPGUIFJSSFTQFDUJWFIPMEFST"MUFSBQSPEVDUTBSFQSPUFDUFEVOEFSOVNFSPVT64BOEGPSFJHOQBUFOUTBOEQFOEJOHBQQMJDB- UJPOT NBTLXPSLSJHIUT BOEDPQZSJHIUT"MUFSBXBSSBOUTQFSGPSNBODFPGJUTTFNJDPOEVDUPSQSPEVDUTUPDVSSFOUTQFDJêDBUJPOTJOBDDPSEBODFXJUI"MUFSBTTUBOEBSEXBSSBOUZ CVU reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any JOGPSNBUJPO QSPEVDU PSTFSWJDFEFTDSJCFEIFSFJOFYDFQUBTFYQSFTTMZBHSFFEUPJOXSJUJOHCZ"MUFSB"MUFSBDVTUPNFSTBSFBEWJTFEUPPCUBJOUIFMBUFTUWFSTJPOPGEFWJDFTQFDJêDBUJPOT improvement to the complementary cumulative distri- Altera FPGA CFGPSFSFMZJOHPOBOZQVCMJTIFEJOGPSNBUJPOBOECFGPSFQMBDJOHPSEFSTGPSQSPEVDUTPSTFSWJDFT%FDFNCFS SS-01050-1.0 bution function (CCDF) demonstrated. Major factors Altera NiosII Processors Adaptive Coefficient to be considered are the window and filter selection, Calculations as well as the output power-clipping threshold. Note, D D however, that clipping inevitably will cause a distor- Analog OBSAI PA S CFR / DPD IP A TX Chain tion of the signal. Thus, it is necessary always to look / P C CPRI for the trade-off between acceptable error vector magni- IP I A Analog P D RX tude (EVM) levels and extra dBs of linear improvement C Chain obtained via CFR. The EVM requirement for WiMAX is as low as 2.8%, while the requirement for LTE is 8% for 64QAM modulation. Peak windowing works in the Figure 4: FPGA-Based Combined CFR/DPD Architec- time domain and uses less logical resource than spec- ture. tral analysis. A spectral analysis uses the more costly fast Fourier transform (FFT) and inverse FFT (IFFT) tage of these modules is their ability to adapt as well functions to benefit from working directly in the spec- as to be configured and upgraded remotely. For feed- trum. Peak windowing uses around one-tenth of the back DPD, the typical choices are to a table, a poly- hardware signal processing resources compared to spec- nomial approach, and a mixed approach. The DPD tral analysis. CFR techniques often are combined with corrects the nonlinearity in the PA, which causes inter- a DPD block to achieve high performance in the RF modulation distortion and leads to spectral re-growth. PA. The CFR block first cancels the peaks, thereby DPD also enables efficient use of the PA transistors preventing the high peak signal from driving the PA since it extends the linear region, taking advantage of into the non-linear operation region of the RF PA. In the normally prohibited higher power nonlinear region. contrast, the DPD block extends the linear operation A mixed approach using both polynomial and LUT region (detailed analysis in next section) and the RF methods is proposed. In implementation, the approxi- PA operates close to the saturation levels. mation that a polynomial can achieve is better suited to deal with wideband PAs due to memory effects. The ef- fectiveness of the polynomial approach is limited by its V - DPD DIGITAL PRE-DISTORTION order. Increasing the polynomial order also increases Trying to align a non-linear device such as a transmitter complexity and hardware usage. For fine resolution, PA is a well-known challenge. With DPD, the PA op- LUT sizes grow, and the adaptation time slows. Typi- erates in its highest efficiency region resulting in higher cally, the LUT approach has been used in narrowband transmission power levels. Pre-distortion techniques memory for less nonlinear solutions. However, the lim- have been developed for different domains of the trans- ited range of a LUT can be useful, especially for the mission chain between baseband and the RF/analog do- higher output power regions that must achieve the high- mains, each of which has a number of advantages and est levels of linearity. For certain parts of the nonlinear restrictions. One of the most effective and commonly transfer function, it is possible that a polynomial of a used approaches is DPD, mainly because of its flexi- rather high degree is needed. The benefits of both tech- bility, limited hardware design, and its software config- niques are exploited by combining a LUT where the urability. An effective DPD compensates for the non- polynomial linearity reaches its correction limit due to linearity of the transmitter PA, also taking into consid- lack of orders. The hardware resources of memory and eration any transistor memory effects and system tem- multipliers therefore are kept as low as possible for a perature variations. The commonly used DPD tech- high degree of linearity. These techniques are used to niques can be classified into feed-forward and feedback correct both amplitude and phase of baseband input techniques. In the feed-forward techniques, a static IQ samples. Radiocomps DPD solution makes efficient look-up table (LUT) is calculated and stored in the use of the feedback technique by taking advantage of FPGA memory. It is not updated at any point of the both the polynomial and the LUT-based approaches, system’s operation. This method is simple but lacks giving results as in Figure 5, and optimized for logical flexibility due to the absence of a feedback path. Once resources usage in conjunction with Radiocomps CFR a feedback path is available, the LUT can be updated IP. and adaptation algorithms can monitor and adjust the table entries. Feedback techniques, as shown in Figure 4, are ideal VI - HIGH-SPEED ADC/DACs for developing modules in a low footprint compared to RF pre-distortion techniques, which require hard- High sampling rates are required when increasing the ware changes and additional RF components. More- channel bandwidth to 20MHz. In addition, fifth-order over, they are suitable for previously built systems be- harmonics are needed to process the DPD. These high cause the feedback path RF-ADC-FPGA exists in most sampling rates make safely routing high-speed digital SDR implementations. Finally, another great advan- lines between ADC and DAC and logic devices a chal-

3 Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate.

Reduce cost, power, and size Designing remote radio head applications with transceiver FPGAs

To drive down cost, power consumption, and form factor of your remote radio head (RRH) and RF card applications, build your designs with custom logic devices with transceivers. Altera’s broad portfolio of 40-nm transceiver FPGAs and ASICs, combined with easy-to-use so!ware tools and intellectual property (IP), o"ers a variety of system-on-a-chipAltera Corporation Altera European Headquarters Altera Japa Ltd. Altera International Ltd. (SOC) options for RRH and RF card applications. 101 Innovation Drive Holmers Farm Way Shinjuku i-Land Tower 32F Unit 11- 18, 9/F Faster design cycle, lower costs San Jose, CA 95134 High Wycombe 6-5-1, Nishi-Shinjuku Millennium City 1, Tower 1 Our technologies support energy-e#cient multi-mode RF/RRH module development, while also providing toolsUSA to help Buckinghamshire Shinjuku-ku, Tokyo 163-1332 388 Kwun Tong Road streamline your design cycle and reduce related costs. Telephone: (408) 544-7000 HP12 4XF Japan Kwun Tong Highly integrated, scalable, reconﬁgurable FPGA and Productivity-enhancing tools, IP, and development ASIC SOC platforms boards www.altera.com United Kingdom Telephone: (81) 3 3340 9480 Kowloon, Hong Kong r$PNQBDU33)XJUIMPXFSQPXFSDPOTVNQUJPOBOECJMM r&BTZNVMUJDIBOOFMEJHJUBMVQDPOWFSUFS %6$ BOE of materials (BOM) EJHJUBMEPXODPOWFSUFS %%$ SFGFSFODFEFTJHOXJUI%41 Telephone: (44) 1494 602000 www.altera.co.jp Telephone: (852) 2 945 7000 Builder Advanced Blockset library r3FDPOêHVSBCMFNVMUJNPEF NVMUJCBOETVQQPSU www.altera.com.cn r0ĒUIFTIFMG*1DPSFTGPS$PNNPO1VCMJD3BEJP r4DBMBCMFNVMUJTFDUPS NVMUJBOUFOOBTVQQPSU Interface (CPRI) and Open Base Station Architecture Best-in-class crest-reduction factor (CFR) and digital Initiative (OBSAI) interfaces $PQZSJHIU¥"MUFSB$PSQPSBUJPO"MMSJHIUTSFTFSWFE"MUFSB ѮF1SPHSBNNBCMF4PMVUJPOT$PNQBOZ UIFTUZMJ[FE"MUFSBMPHP TQFDJêDEFWJDFEFTJHOBUJPOT BOEBMMPUIFSXPSET predistortion (DPD) solutions r4UBUFPGUIFBSU3'IBSEXBSFEFWFMPQNFOUBOEEFNPO- r*NQSPWFEQPXFSBNQMJêFS 1" FēDJFODZBOEMPXFSFE stration kits BOEMPHPTUIBUBSFJEFOUJêFEBTUSBEFNBSLTBOEPSTFSWJDFNBSLTBSF VOMFTTOPUFEPUIFSXJTF UIFUSBEFNBSLTBOETFSWJDFNBSLTPG"MUFSB$PSQPSBUJPOJOUIF64BOEPUIFSDPVO- operating expenses USJFT"MMPUIFSQSPEVDUPSTFSWJDFOBNFTBSFUIFQSPQFSUZPGUIFJSSFTQFDUJWFIPMEFST"MUFSBQSPEVDUTBSFQSPUFDUFEVOEFSOVNFSPVT64BOEGPSFJHOQBUFOUTBOEQFOEJOHBQQMJDB- UJPOT NBTLXPSLSJHIUT BOEDPQZSJHIUT"MUFSBXBSSBOUTQFSGPSNBODFPGJUTTFNJDPOEVDUPSQSPEVDUTUPDVSSFOUTQFDJêDBUJPOTJOBDDPSEBODFXJUI"MUFSBTTUBOEBSEXBSSBOUZ CVU 40-nm technology enables RF SOC integration reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

Ethernet RS-232 DDR2/3 Flash JOGPSNBUJPO QSPEVDU PSTFSWJDFEFTDSJCFEIFSFJOFYDFQUBTFYQSFTTMZBHSFFEUPJOXSJUJOHCZ"MUFSB"MUFSBDVTUPNFSTBSFBEWJTFEUPPCUBJOUIFMBUFTUWFSTJPOPGEFWJDFTQFDJêDBUJPOT '#$ )*+,-.+$/0/$ I/F I/F memory memory CFGPSFSFMZJOHPOBOZQVCMJTIFEJOGPSNBUJPOBOECFGPSFQMBDJOHPSEFSTGPSQSPEVDUTPSTFSWJDFT%FDFNCFS SS-01050-1.0 (#$ )*+,$/0/$ Altera® FPGA #$ 1234$15$&#'$"%%$ Memory controller !(#$ Nios II Nios® II O/M and !'#$ Ethernet DPD MAC con!guration software !"#$%&'()* !&#$

!%#$ Multi-channel Tx CFR DPD CPRI Tx SRC/DUC DAC !"#$ MIMO OBSAI DPD analog !"#$ !%#$ !&#$ !'#$ !(#$ #$ (#$ '#$ &#$ %#$ "#$ framer Multi-channel FB ADC RF +,-./-012*345-6*$*7()* Rx SRC/DDC Rx ADC Single sector, 2x2 MIMO (3G CPRI) - One Arria® II GX FPGA Single sector 4x4 MIMO or three sector 2x2 MIMO (6G CPRI) - One Stratix® IV GX/HardCopy® IV GX device Figure 5: Radiocomp’s DPD Measurement Results with a Figure 6: RF SoC Implementation With Alteras 40-nm WiMAX 10MHz OFDMA Signal. Arria II GX and Stratix IV GX FPGAs. lenge. Here a poor layout will result in digital switch- RRH designs have very stringent size and weight re- ing noise feeding back into the conversion stage with quirements, and the lack of forced airflow places a chal- a degradation of the overall system performance. The lenging requirement in terms of power consumption. latest generation of ADC and DAC solutions, such as With unique low-power consumption features such as the JEDEC204 standard, defines a high-speed, single- Programmable Power Technology and Selectable Core pair link between the ADC and the FPGA or proces- Voltage, Stratix IV GX FPGAs meet these allowable sor using bit encoding, synchronization, and alignment power-consumption levels. The high density of Stratix to achieve the high performance. Using such JEDEC- IV GX FPGAs also provides unprecedented levels of enabled devices to lower the amount of parallel digi- integration, enabling single-chip solutions for multiple tal lanes into a multi-channel radio card design, thus antenna-based systems, with further cost, size, and lowering and simplifying the PCB layout, and in turn power-consumption reduction via risk-free seamless mi- increasing reliability and time to market. gration to HardCopy IV GX ASICs. Altera also offers a variety of IP and reference designs for multi- VII - FPGA-BASED RF/RRH SOC IMPLEMENTATION ple standards including LTE, WiMAX, WCDMA, TD- SCDMA, etc. The combination of interface IP such Alteras broad portfolio of 40nm transceiver FPGAs and as CPRI and OBSAI, along with optimized designs for ASICs, combined with easy-to-use software tools and DUC/DDC and CFR, help improve productivity and IP, offers a variety of system-on-chip (SoC) implemen- accelerate time to market. Alteras CFR for OFDM tation options for RRH applications. With channel reference design is a high-performance solution capable bandwidth up to 20MHz, MIMO antenna configura- of achieving a Peak to Average Power Ratio (PAPR) re- tions, and multi-mode support, implementation of the duction up to 5dB, while meeting the EVM constraints signal processing functionality in the RRH requires a for WiMAX/LTE. Alteras advanced blockset library, highly integrated, flexible, and power-efficient silicon an enhancement to the DSP Builder software tool, has platform. Figure 6 illustrates how the entire digital a unique synthesis technology that optimizes the high- functionality in a RRH can be integrated into a single level, unregistered netlist into a pipelined register trans- Altera 40nm FPGA, resulting in a low-cost, low-power fer level (RTL), then optimizes it for a target device compact RRH solution. With more than 200K logic and desired clock rate. The benefits of the advanced elements (LEs), 700 18x18 multipliers and 10Mbits of blockset-based design methodology include: embedded memory, Arria II GX FPGAs offer a low- cost, low-power SoC option for RRHs requiring up to Automatic timing-driven FPGA implementation • 3.75Gbps transceiver support. For example, a single- from Simulink sector, a 2x2 MIMO configuration with functions such Push-button flow to create multi-channel, multi- as CPRI/OBSAI, DUC/DDC, CFR, and DPD can be • implemented in a single Arria II GX FPGA. antenna DUC/DDC designs For systems that support 4x4 MIMO schemes or re- System-level constraint-driven design methodol- quire greater than 3.75Gbps transceiver support, Al- • ogy to improve productivity teras Stratix IV FPGA serves as a high-performance SoC implementation platform. With up to 530K LEs, Fast multi-channel design implementation greater than 1200 18x18 multipliers and 20Mbits of em- • bedded RAM, Stratix IV FPGAs take performance to Automates control plane for time-division multi- a new level. With transceivers up to 8.5Gbps, Stratix • plexed (TDM) data paths IV FPGAs offer a future-proof platform capable of supporting 6.144Gbps CPRI/OBSAI rates and higher. Efficiently pipelines multi-channel data paths •

4 Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate.

Deepak Boppana is a Strategic Marketing Manager at Altera Corporation, where he focuses on the wireless infrastructure market. Deepak joined Altera in June 2003 and has a strong background in wireless commu- nications system design and implementation. He has been published in research publications, international conferences, and technical journals. Deepak holds a BSEE from the University College of Engineering, Osmania University, and a MSEE from Villanova University.

ABOUT RADIOCOMP

Denmark-based Radiocomp is an industry-leading provider of remote radio heads and optical interfac- ing and advanced signal processing subsystems for LTE and WiMAX mobile networks. Learn more at www.radiocomp.com.

ABOUT ALTERA

Altera programmable solutions enable system and semiconductor companies to rapidly and cost eﬀectively innovate, diﬀerentiate and win in their markets. Learn more at www.altera.com.