Farzan Fallah Fujitsu Laboratories of America, Inc. 1240 E. Arques M/S 345 Sunnyvale, CA 94085 Email: farzanf ATT acm DUT org

Education: Massachusetts Institute of Technology, Cambridge, MA. Ph.D. degree in Electrical Engineering and , GPA 5.0/5.0, March 99. : Coverage Directed Validation of Hardware Models. Thesis under Prof. Srinivas Devadas. Massachusetts Institute of Technology, Cambridge, MA. Master of Science in Electrical Engineering and Computer Science, GPA 5.0/5.0, May 96. Thesis: A New Algorithm for Factorization of Logic Expressions. Thesis under Prof. Srinivas Devadas. Sharif University of Technology, Tehran, . in Electrical Engineering, graduated first in class, GPA 17.34/20, January 92.

Achievements: Intellectual Property Award, Fujitsu Labs of America, Sunnyvale, 99, 00, 01, 01, 02, 02, 03, 03, 04. Design Automation Conference, Best paper award, San Francisco, 98. National Science Competition in Electrical Engineering, Second place, Iran, 90. Participated in the International Mathematics Olympiad, Cuba, 87. National Mathematics Competition, Third place, Iran, 87.

Invited Talks: Sharif University Reunion, Heidelberg, Germany, Aug. 2004. Stanford University, Palo Alto, CA, Sep. 2002. Sharif University Reunion, Toronto, Canada, Aug. 2002. UCLA, Los Angles, CA, Jan. 2001. U.C. Berkeley, Berkeley, CA, Sept 1999. Chrysalis Symbolic Design, Inc., North Billerica, MA, Jan 1999. 0-in Design Automation, San Jose, CA, Dec 1998.

Tutorial: F. Fallah, M. Pedram, Design and Runtime Techniques for Leakage Control and Minimization of CMOS VLSI Circuits in Active and Sleep Modes, Tutorial, ASP-DAC, Jan 2004.

Conference Program Committees: Initiated the Ph.D. Forum at the Asia South Pacific Design Automation Conference (ASP-DAC) 2005. Ph.D. Forum at the Design Automation Conference (DAC) 2003. Design Automation and Test in Europe (DATE) 2003, 2005. International High Level Design Validation and Test Workshop (HLDVT) 2001, 2002, 2003 and 2004. International Symposium on Quality Electronic Design (ISQED) 2003, 2004 and 2005.

Services: One of the founders of the Chapter of Northern California of Sharif University of Technology Association. Worked as a volunteer in the Society of Iranian Professionals. Served as a representative of Electrical Engineering and Computer Science Department at MIT Graduate Student Council. One of the founders of the Persian Students Association at MIT.

Co-Advising and Mentoring Graduate Students: Afshin Abdollahi Yazdan Aghaghiri Behnam Amelifard Eddie Benowitz Anup Hosangadi Seda Ogrenci Memik (currently Professor at Northwestern University)

University Collaborations: Present: • Professor Massahiro Fujita, University of Tokyo • Professor Ryan Kastner, UC Santa Barbara • Professor Massoud Pedram, USC Past: • Professor Milos Ercegovac, UCLA • Professor Kurt Keutzer, UC Berkeley • Professor Majid Sarrafzadeh, UCLA

Patents: Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (US. and International Patents filed through NEC CCRL). Method for Instruction-Set Based Test Program Generation (filed through Fujitsu Labs. of America, Inc.). Irredundant Address Bus Encoding (filed through Fujitsu Labs. of America, Inc.). Sector-based Bus Encoding (filed through Fujitsu Labs. of America, Inc.). Bus Encoding Based on Instruction-Set-Aware Memories (filed through Fujitsu Labs. of America, Inc.). Binary Time-Frame Expansion (filed through Fujitsu Labs. of America, Inc.). C Coverage Analysis Method (filed through Fujitsu Labs. of America, Inc.). 7 more in preparation.

Professional Membership: ACM (Association for Computing Machinery) IEEE (Institute of Electrical and Electronics Engineers) IEEE-EMS (IEEE’s Engineering Management Society)

Work Experience:

Project Leader, Fujitsu Labs. of America (April. 99 -- Present), Sunnyvale, CA. Managing projects on Computer Aided Design of VLSI, VLSI Design, and Computer Architecture. Currently leading the low power design project.

Massachusetts Institute of Technology (Spring 99), Cambridge, MA. Teaching Assistant for course CAD of VLSI.

NEC USA, Inc. (June. 98 -- Aug. 98), Princeton, NJ Worked on test vector generation for sequential HDL models.

Massachusetts Institute of Technology (Feb. 98 -- Mar. 99), Cambridge, MA Research Assistant at the Laboratory for Computer Science, MIT, in the Computer Aided Automation Group, working with Prof. Srinivas Devadas on Hardware and Software Testing.

Fujitsu Labs. of America (Summer 97), Santa Clara, CA. Worked on coverage metric for HDL Models.

Massachusetts Institute of Technology (Spring 97), Cambridge, MA. Teaching Assistant for course CAD of VLSI.

Siemens Corporate Research (Summer 96), Princeton, NJ. Developed methods for Software Testing.

Massachusetts Institute of Technology (June 95 -- Feb. 98), Cambridge, MA. Research Assistant at the Research Laboratory of Electronics, MIT, in the Circuits and Systems Group, working with Prof. Srinivas Devadas on , Hardware and Software Testing.

Patsa Microsystem Company, (91-92), Tehran, Iran. Tested computer-related sound board and wrote software for it. Modified Titler (a package for creating and moving around text on video screen) to work with the Persian alphabet.

Book Chapter: F. Fallah and M. Pedram, Power Aware Design Methodologies, Kluwer Academic Publishers. Papers: Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Reducing Hardware Complexity of Linear DSP Systems by Iteratively Eliminating Two Term Common Subexpressions” – Asia South Pacific Design Automation Conference (ASP-DAC), January 2005 (to appear). Anup Hosangadi, Farzan Fallah and Ryan Kastner, “Energy Efficient Hardware Synthesis of Polynomial Expressions”, International Conference on VLSI Design, January 2005 (to appear). Anup Hosangadi, Farzan Fallah and Ryan Kastner, Factoring and Eliminating Common Subexpressions in Polynomial Expressions, International Conference on Computer-Aided Design (ICCAD), November, 2004 (to appear). Anup Hosangadi, Farzan Fallah and Ryan Kastner, Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis, IEEE International Conference on Application-specific Systems, Architectures and Processors, September, 2004 (to appear). Y. Aghaghiri, F. Fallah, M. Pedram, Transition Reduction in Memory Buses Using Sector-based Encoding Techniques, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug. 2004. A. Hosangadi, R. Kastner, F. Fallah, Optimizing Polynomial Expressions by Factoring and Eliminating Common Subexpressions, International Workshop on Logic and Synthesis, Temecula, June 2004. A. Hosangadi, R. Kastner, F. Fallah, Algebraic Techniques for Optimizing Polynomial Expressions, ODES-2: 2nd Workshop on Optimizations for DSP and Embedded Systems, Palo Alto, Mar. 2004. A. Abdollahi, F. Fallah, M. Pedram, Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2004. A. Abdollahi, F. Fallah, I. Ghosh, M. Pedram, Precomputation-based Guarding for Dynamic and Leakage Power Reduction, International Conference on Computer Design, San Jose, CA, Oct. 2003. A. Abdollahi, F. Fallah, M. Pedram, Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains, International Symposium on Quality Electronic Design, San Jose, Mar. 2003. F. Fallah, I. Ghosh, M. Fujita, Event-Driven Observability Enhanced Coverage Analysis of C Programs for Functional Validation, Asia and South Pacific Design Automation Conference, Yokohama, Japan, Jan. 2003. Y. Aghaghiri, F. Fallah, M. Pedram, BEAM: Bus Encoding Based on Instruction-Set- Aware Memories, Asia and South Pacific Design Automation Conference, Yokohama , Japan , Jan. 2003. F. Fallah, P. Ashar, S. Devadas, Functional Vector Generation for Sequential HDL Models under an Observability-Based Code Coverage Metric, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec. 2002. F. Fallah, Binary Time-Frame Expansion, International Conference on Computer Aided Design, San Jose, Nov. 2002. E. G. Benowitz, M. D. Ercegovac, F. Fallah, Reducing the Latency of Division Operations with Partial Caching, Asilomar Conference on Signals, Systems and Computers, Pacific Grove, Nov. 2002. Y. Aghaghiri, F. Fallah, M. Pedram, A Class of Irredundant Encoding Techniques for Reducing Bus Power, Journal of World Scientific Publishing, Oct. 2002. S. O. Memik, F. Fallah, Accelerated Boolean Satisfiability for Scheduling Control/Data Flow Graphs, International Conference on Computer Design, Freiburg, Germany, Sept. 2002. A. Abdollahi, F. Fallah, M. Pedram, Runtime Mechanisms for Leakage Reduction in CMOS VLSI Circuits, International Symposium on Low Power Electronics and Design, California, Aug. 2002. Y. Aghaghiri, F. Fallah, M. Pedram, Reducing Transitions on Memory Buses using Sector-Based Encoding Technique, International Symposium on Low Power Electronics and Design, California, Aug. 2002. F. Fallah, I. Ghosh, M. Fujita, A Coverage Metric for Observability-Based Validation of C Programs, International Workshop on Microprocessor Test and Verification, Texas, June 2002. S. O. Memik, F. Fallah, Accelerated Boolean Satisfiability-Based Scheduling for High- Level Synthesis, International Workshop on Logic and Synthesis, New Orleans, June 2002. A. Abdollahi, F. Fallah, M. Pedram, Runtime Mechanisms for Leakage Reduction in CMOS VLSI Circuits, International Workshop on Logic and Synthesis, New Orleans, June 2002. F. Fallah, Binary Time-Frame Expansion, International Workshop on Logic and Synthesis, New Orleans, June 2002. Y. Aghaghiri, F. Fallah, M. Pedram, EZ: A Class of Irredundant Low Power Codes for Data-Address and Multiplexed Address Buses, Design Automation and Test in Europe, France, Mar. 2002. Y. Aghaghiri, F. Fallah, M. Pedram, ALBORZ: Address Level Bus Power Optimization, International Symposium on Quality Electronic Design, California, Mar. 2002. F. Fallah, I. Ghosh, Observability Enhanced Coverage Analysis of C Programs for Functional Validation, IEEE International High Level Design Validation and Test Workshop, California, Nov. 2001. F. Fallah, K. Takayama, A New Functional Test Program Generation Methodology, International Conference on Computer Design, Texas, Sept. 2001. S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, K. Keutzer, A Functional Validation Technique: Biased Random Simulation Guided by Observability-Based Coverage, International Conference on Computer Design, Texas, Sept. 2001. F. Fallah, S. Devadas, K. Keutzer, OCCOM: Efficient Computation of Observability- Based Code Coverage Metrics for Functional Verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug. 2001. F. Fallah, S. Devadas, K. Keutzer, Functional Vector Generation for HDL Models Using Linear Programming and Boolean Satisfiability, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Aug. 2001. Y. Aghaghiri, F. Fallah, M. Pedram, Irredundant Address Bus Encoding for low power, International Symposium on Low Power Electronics and Design, California, Aug. 2001. F. Fallah, K. Takayama, ART: A Functional Test Program Generation Tool, International Workshop on Logic and Synthesis, California, June 2001. Y. Aghaghiri, F. Fallah, M. Pedram, ALBORZ: Address Level Bus Power Optimization, International Workshop on Logic and Synthesis, California, June 2001. S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, K. Keutzer, Coverage-Directed Generation of Biased Random Inputs for Functional Validation of Sequential Circuits, International Workshop on Logic and Synthesis, California, June 2001. F. Fallah, S. Devadas, Functional Vector Generation from HDL Models for Observability-Based Code Coverage Metric, SCI2000/ISAS2000, Orlando, July 2000. F. Fallah, S. Devadas, S. Liao, Solving Covering Problems Using LPR-Based Lower Bounds, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2000. F. Fallah, P. Ashar, S. Devadas, Simulation Vector Generation from HDL Descriptions for Observability Enhanced Statement Coverage, 36th Design Automation Conference, New Orleans, June 1999. F. Fallah, S. Devadas, K. Keutzer, Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability, 35th Design Automation Conference, San Francisco, June 1998. F. Fallah, S. Devadas, K. Keutzer, OCCOM: Efficient Computation of Observability- Based Code Coverage Metrics for Functional Verification, 35th Design Automation Conference, San Francisco, June 1998 (best paper award).