WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•WiThe IDT WinChip™ n hip•IDT•WProcessorinChip•IDT•WinChi Architecture p DT•WinChip•IDT•WinChip•ID ® •WinChip•IDT•WinChip•IDTIntroduction • Even though the IDT WinChip™ processor is externally compatible with the Pentium processor with MMX™ WinChip•IDT•WinChip•IDT•Win Technology, the internal architecture and design of the IDT WinChip is very different from that of the Pentium hip•IDT•WinChip•IDT•WinChip processor and other contemporary processors such as the AMD-K6 and 6x86MX. DT•WinChip•IDT•WinChip•ID The IDT WinChip processor uses a unique design approach that provides significant benefits to the end-user. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win This design approach provides high performance at lower cost and lower power consumption using a relatively hip•IDT•WinChip•IDT•WinChip simple architecture that runs at high internal clock frequencies (MHz). The IDT WinChip includes large on-chip DT•WinChip•IDT•WinChip•ID caches and is extensively optimized for volume desktop and notebook PC product categories. The resulting IDT •WinChip•IDT•WinChip•IDT• WinChip processor is smaller (die size is only 88mm2 in 0.35-micron technology) and uses lower power than WinChip•IDT•WinChip•IDT•Win other 2.8V and 3.3V compatible processors with MMX Technology. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID Philosophically, this is a return to the same basic concepts of RISC (Reduced Instruction Set Computing) design •WinChip•IDT•WinChip•IDT• that allowed microprocessor performance breakthroughs in the 1980s. Recently, however, contemporary x86 WinChip•IDT•WinChip•IDT•Win processors have followed a different path, using very complex internal designs employing advanced architecture hip•IDT•WinChip•IDT•WinChip concepts such as superscalar execution, out-of-order instruction execution, reorder buffers, non-blocking caches, DT•WinChip•IDT•WinChip•ID and so forth (these terms are all found in the data sheets of competitive products). •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win Unfortunately, while these advanced technical concepts make for good technical reading, the real bottom-line hip•IDT•WinChip•IDT•WinChip benefit that they provide to the end-user has been limited, especially when considering the resultant large chip DT•WinChip•IDT•WinChip•ID sizes (resulting in higher manufacturing costs) and higher power consumption. No such advanced technical •WinChip•IDT•WinChip•IDT• hocus—pocus is to be found on an IDT WinChip processor——it merely offers compatibility with good WinChip•IDT•WinChip•IDT•Win performance, very low costs, and very low power consumption. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDTKey Concepts • The key concepts underlying the IDT WinChip processor design are: WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip • Simple instructions (load, store, branch, register-to-register) dominate instruction DT•WinChip•IDT•WinChip•ID execution time •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win This is the basic RISC design concept, which is also true in the x86 architecture: over 90% of instructions executed hip•IDT•WinChip•IDT•WinChip come from these basic categories. Of course, “simple” x86 instructions are much more complex than corresponding DT•WinChip•IDT•WinChip•ID RISC architecture instructions. The IDT WinChip processor optimizes performance of these types of basic x86 •WinChip•IDT•WinChip•IDT• instructions while minimizing the hardware provided for other little-used x86 functions. The little-used instruc- WinChip•IDT•WinChip•IDT•Win tions are primarily implemented in microcode with minimal hardware support. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID • Improving clock frequency has higher leverage than improving CPI •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win The result of advanced computer design approaches over the last few years has been that the improvements in hip•IDT•WinChip•IDT•WinChip cycles-per-instruction (CPI) come at the expense of cycle-time improvements such that total performance (a DT•WinChip•IDT•WinChip•ID linear function of frequency and CPI) of complex designs hasn’t improved as fast as performance of simpler, yet •WinChip•IDT•WinChip•IDT• high-clock-frequency designs. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip The IDT WinChip processor optimizes total system performance by generally optimizing for highest clock fre- DT•WinChip•IDT•WinChip•ID quency, even if this means reduced CPI for some functions versus more complex processor designs. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win • Memory performance is the limiting CPI performance factor hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID Due to the high ratio of internal clock speed versus the relatively limited PC processor-bus speed, off-chip •WinChip•IDT•WinChip•IDT• memory-access performance is the primary factor in processor CPI performance (as opposed to internal instruction WinChip•IDT•WinChip•IDT•Win execution performance). The IDT WinChip processor addresses this phenomenon by providing very large on- hip•IDT•WinChip•IDT•WinChip chip caches that run at the high internal processor clock frequency. In addition, sophisticated TLB and cache DT•WinChip•IDT•WinChip•ID management algorithms are included to further reduce bus activity. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•WiKey Concepts n • Optimize the design for the target user hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID The IDT WinChip processor implements very specific and detailed design trade-offs to provide high performance •WinChip•IDT•WinChip•IDT• with low cost. Minimal hardware is provided for functions that are not heavily used or that are not critical to WinChip•IDT•WinChip•IDT•Win performance in the target environments (low-end desktop and mobile systems). These design optimizations are hip•IDT•WinChip•IDT•WinChip based on extensive detailed analysis of actual behavior of modern PC operating systems and applications. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• • Small is beautiful WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip The IDT WinChip processor is highly optimized for small physical size and few logic transistors. In addition to DT•WinChip•IDT•WinChip•ID the obvious cost benefits, this small size provides secondary benefits of low power consumption and improved •WinChip•IDT•WinChip•IDT• reliability. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID Component Summary Components of the IDT WinChip processor •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win Fundamentally, the IDT WinChip processor’s internal hip•IDT•WGeneralinChip•IDT•WinChi Architecture p design is a relatively simple five-stage pipeline execution DT•WinChip•IDT•WinChip•ID core with an additional instruction translation stage. •WinChip•IDT•WinChip•IDT• This added instruction stage translates x86 instructions WinChip•IDT•WinChip•IDT•Win coming from the fetch stage into the internal micro- hip•IDT•WinChip•IDT•WinChip instruction format. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win Fetching and translating x86 instructions is asynchronous hip•IDT•WinChip•IDT•WinChip to the internal execution pipeline. Instructions are issued DT•WinChip•IDT•WinChip•ID one at a time in program order. Instructions are executed •WinChip•IDT•WinChip•IDT• and retired in order. Cache misses stall the pipeline until WinChip•IDT•WinChip•IDT•Win the data is available for the requesting instruction. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID Despite its very basic micro-architecture, the IDT •WinChip•IDT•WinChip•IDT• WinChip processor achieves very high performance WinChip•IDT•WinChip•IDT•Win through several mechanisms: hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID • High internal clock frequency. The design is heavily optimized to provide high frequency •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win • Good CPI on highly-used instructions. The IDT WinChip processor implements specific hip•IDT•WinChip•IDT•WinChip design features to reduce the number of clocks for heavily used instructions——including DT•WinChip•IDT•WinChip•ID complex functions such as protect-mode segment-register loads and string instructions. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win • Large and fast on-chip caches and TLBs hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID • Lots of fine-tuning and low-level optimizations. This includes such items as fast •WinChip•IDT•WinChip•IDT• unaligned data access and fewer pipeline interlocks than the Pentium processor. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•II-Cache D The I-cache contains 32KB organized as two-way set- Trap •WinChip•IDT•WinChip•IDT• Address STAGE associative with 32-byte lines. An LRU replacement WinChip•IDT•WinChip•IDT•Win RET Stk I-TLB I-Cache I algorithm is used. The associated I-TLB contains 64 x86 hip•IDT•WinChip•IDT•WinChip Fetch entries organized as a 4-way set-associative with a DT•WinChip•IDT•WinChip•ID pseudo-LRU replacement algorithm. This large cache has x86 Inst Buffer •WinChip•IDT•WinChip•IDT• x86-To-Microcode X a one-clock access time and operates at the high clock Translator WinChip•IDT•WinChip•IDT•Win Queue frequencies of the IDT WinChip processor. The I-TLB hip•IDT•WinChip•IDT•WinChip Trap utilizes an 8-entry unified page directory cache that Address DT•WinChip•IDT•WinChip•ID x86 x86 significantly reduces the TLB miss penalty. In addition, RF ROM Instruction Immed •WinChip•IDT•WinChip•IDT• Parameters Parameters the I-cache control logic includes several innovative

WinChip•IDT•WinChip•IDT•Win Bus Bus Internal features that minimize cache invalidates and unnecessary Unit hip•IDT•WinChip•IDT•WinChip Instructions bus fetches. As opposed to many other contemporary PDC Decode R DT•WinChip•IDT•WinChip•ID x86 processors, the data in the I-cache is exactly what Address Gen A •WinChip•IDT•WinChip•IDT• Address came from the bus; that is, there are no “hidden” pre- D-Cache FP MMX D WinChip•IDT•WinChip•IDT•Win Access & Execute decode bits. This facilitates the provision of large cache hip•IDT•WinChip•IDT•WinChip Writeback W capacity in a small physical size. In the mobile DT•WinChip•IDT•WinChip•ID IDT WinChip processor, the I-cache is dynamically •WinChip•IDT•WinChip•IDT• turned off when not used to reduce power requirements. WinChip•IDT•WinChip•IDT•Win D-TLB D-Cache hip•IDT•WinChip•IDT•WinChip BFRS DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•WiTranslator Unit n The I-cache or bus unit delivers 16 or 8 bytes per clock to an x86 instruction buffer in the translator unit. The hip•IDT•WinChip•IDT•WinChip translator converts x86 instructions to internal instruction and data forms. Assuming that the instruction is in DT•WinChip•IDT•WinChip•ID the x86 instruction buffer at the start of the cycle, the translator translates an entire x86 instruction in one clock. •WinChip•IDT•WinChip•IDT• Instruction prefixes require an additional translator cycle for each prefix. However, due to the asynchronous WinChip•IDT•WinChip•IDT•Win fetch and “look-ahead” capability of the translator, these extra cycles for prefixes rarely result in a bubble in the hip•IDT•WinChip•IDT•WinChip execution pipeline. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• The output of the translator unit is (1) the internal micro-instruction stream to perform the x86 instruction WinChip•IDT•WinChip•IDT•Win function, (2) the immediate data fields from the x86 instruction, and (3) various x86 state information used to hip•IDT•WinChip•IDT•WinChip control execution (for example, operand size). The internal instruction stream for an x86 instruction can consist DT•WinChip•IDT•WinChip•ID of micro-instructions directly generated by the translator, or micro-instructions from the on-chip ROM, or both. •WinChip•IDT•WinChip•IDT• For performance-sensitive instructions, there is no delay due to access of microcode from ROM. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip The microcode ROM capacity is larger than most x86 microcode ROMs, to allow more unimportant (relative to DT•WinChip•IDT•WinChip•ID performance) functions to be performed in microcode (versus in hardware), to allow extensive self-test microcode, •WinChip•IDT•WinChip•IDT• and to allow extensive built-in debugging aids for processor design debug. Instruction fetch and translator WinChip•IDT•WinChip•IDT•Win operation is made asynchronous from micro-instruction execution via a three-entry translated-instruction hip•IDT•WinChip•IDT•WinChip queue between the translator and the execution unit. This queue allows the translator to “look-ahead” and DT•WinChip•IDT•WinChip•ID continue translating x86 instructions even though the execution unit is stalled. The translator can also overlap •WinChip•IDT•WinChip•IDT• generation of multiple internal instructions with translating prefixes on the subsequent instruction. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID Execution Unit Internal micro-instructions are executed in a tightly coupled four-stage pipeline that is •WinChip•IDT•WinChip•IDT• very similar in structure to a basic RISC pipeline: WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID • Decode stage (R): Micro-instructions are decoded, register files are accessed, resource •WinChip•IDT•WinChip•IDT• dependencies evaluated, and so forth. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip • Addressing stage (A): Memory addresses are calculated and sent to the cache units. The DT•WinChip•IDT•WinChip•ID IDT WinChip processor is capable of calculating most x86 instruction address forms in •WinChip•IDT•WinChip•IDT• one clock; forms containing two registers require two clocks. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip • Execute stage (D): ALU operations or load accesses to the D-cache are performed. All basic DT•WinChip•IDT•WinChip•ID ALU functions take one clock except multiply and divide. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win • Write-back stage (W): The results of operations are committed to the registers and store hip•IDT•WinChip•IDT•WinChip data is written to the D-cache or external write buffers. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• Although the pipeline structure is similar to non-x86 processors, the micro-instructions and associated execution WinChip•IDT•WinChip•IDT•Win units are highly tuned to the x86 architecture. The micro-instructions closely resemble the corresponding x86 hip•IDT•WinChip•IDT•WinChip instructions. Examples of specialized hardware features supporting the x86 architecture are: hardware handling DT•WinChip•IDT•WinChip•ID of the x86 condition code, segment descriptor decode and manipulation instructions, hardware to automatically •WinChip•IDT•WinChip•IDT• save the x86 floating-point environment, and so forth. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID-Cache D The D-cache is very similar to the I-cache: 32KB organized as two-way set-associative with 32-byte lines. An •WinChip•IDT•WinChip•IDT• LRU replacement algorithm is used. The associated D-TLB contains 64 entries organized as 4-way set-associative WinChip•IDT•WinChip•IDT•Win with a pseudo-LRU replacement algorithm. This large cache has a one-clock access time and is designed to hip•IDT•WinChip•IDT•WinChip operate at the high clock frequencies of the IDT WinChip processor. The D-TLB utilizes a large unified page DT•WinChip•IDT•WinChip•ID directory cache (shared with the I-cache) which reduces the TLB miss penalty. In the mobile IDT WinChip •WinChip•IDT•WinChip•IDT• processor, the D-cache is dynamically turned off when not used to reduce power requirements. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip One of the most visible frequency and size-versus-CPI trade-offs made by the IDT WinChip processor is that DT•WinChip•IDT•WinChip•ID there is limited branch prediction: only a special 8-entry Call/Return stack. This computer-science heresy helps •WinChip•IDT•WinChip•IDT• support the high clock frequency and small die size but means that, on average, simple branches normally take WinChip•IDT•WinChip•IDT•Win more clocks on the IDT WinChip processor than on other contemporary x86 processors. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Wix86 Fetch Unit n However, the clock difference is not as high as might be expected due to: (1) Return instructions are accurately hip•IDT•WinChip•IDT•WinChip predicted with the special Call/Return stack mechanism, (2) the total performance of complex branches (such as DT•WinChip•IDT•WinChip•ID far calls) includes more than the actual branch time (which is overlapped with the additional operations on the •WinChip•IDT•WinChip•IDT• IDT WinChip processor), and (3) the short IDT WinChip processor pipeline. Also, a clock on the WinChip•IDT•WinChip•IDT•Win IDT WinChip processor is a shorter period than on many of the processors that require fewer clocks per hip•IDT•WinChip•IDT•WinChip branch. The most important consideration relative to the IDT WinChip processor’s lack of branch prediction is DT•WinChip•IDT•WinChip•ID that the gain from branch prediction is relatively small compared to the total time waiting on bus activity in •WinChip•IDT•WinChip•IDT• high-frequency x86 processors. The IDT WinChip processor design focuses on using its transistors to minimize WinChip•IDT•WinChip•IDT•Win this bus wait time: large caches, large TLBs, smart cache management algorithms, and so forth, as opposed to a hip•IDT•WinChip•IDT•WinChip large branch prediction array. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•WiFP Unit n In addition to the basic integer execution unit, the IDT WinChip processor has a separate 80-bit floating-point hip•IDT•WinChip•IDT•WinChip execution unit that can execute floating-point instructions in parallel with integer instructions. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• The floating-point unit is designed to maximize clock frequency and to minimize chip size while providing WinChip•IDT•WinChip•IDT•Win adequate levels of floating-point performance for typical desktop use. Some floating-point instructions are hip•IDT•WinChip•IDT•WinChip pipelined, but some are only partially pipelined. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• The IDT WinChip processor issues only one instruction per clock but most integer instructions and most float- WinChip•IDT•WinChip•IDT•Win ing-point instructions can execute in parallel. In the mobile IDT WinChip processor, the floating-point unit is hip•IDT•WinChip•IDT•WinChip dynamically turned off when not used to reduce power requirements. DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win The IDT WinChip processor contains a separate execution unit for the new MMX-compatible instructions. The hip•IDT•WinChip•IDT•WinChiMMX p MMX architecture registers are the same as the floating-point registers, otherwise the MMX execution unit has DT•WinChip•IDT•WinChip•IInstruction Unit D •WinChip•IDT•WinChip•IDT• its own adder, multiplier, and shifter separate from the floating-point unit. WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip In the mobile IDT WinChip processor, the MMX unit is dynamically turned off when not used to reduce power DT•WinChip•IDT•WinChip•ID requirements.. •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChiBus Unit p The IDT WinChip processor bus unit provides an external bus interface compatible with the Pentium processor. DT•WinChip•IDT•WinChip•ID In addition to the expected bus control functions, the bus unit implements a large page-directory cache to •WinChip•IDT•WinChip•IDT• reduce the impact of TLB misses as well as several special optimizations intended to reduce cache misses. Four 64- WinChip•IDT•WinChip•IDT•Win bit write buffers allow internal execution to proceed overlapped with waiting for external stores to complete. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT•Integrated Device WinChip•IDT•WinChip•IDT•WiTechnology, Inc. n hip•IDT•WinChip•IDT•WinChi2975 Stender Way p DT•WinChip•IDT•WinChip•ISanta Clara, CA D •WinChip•IDT•WinChip•IDT•95054-3090 WinChip•IDT•WinChip•IDT•Win hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID •WinChip•IDT•WinChip•IDT• WinChip•IDT•WinChip•IDT•Wi1(800) WINCHIP n hip•IDT•WinChip•IDT•WinChiTel: (800)946-2447 p DT•WinChip•IDT•WinChip•IFax: (408)492-8674 D •WinChip•IDT•WinChip•IDT• IDT WinChip is a trademark of Integrated Device Technology, Inc. Pentium is a registered trademark of Corp.; MMX is a trademark of Intel Corp. K6 is a trademark of AMD. 6x86 is a trademark of Cyrix. and Integrated Device Technology disclaim any WinChip•IDT•WinChip•IDT•Wiwww.winchip.com n proprietary interest in the trademarks of others. hip•IDT•WinChip•IDT•WinChip DT•WinChip•IDT•WinChip•ID © Copyright 1998 IDT WinChip SKU: TECHBR •WinChip•IDT•WinChip•IDT• Printed in U.S.A. WinChip•IDT•WinChip•IDT•Win