US007231474B1

(12) United States Patent (10) Patent N0.: US 7,231,474 B1 Helms et a]. (45) Date of Patent: Jun. 12, 2007

(54) SERIAL INTERFACE HAVING A READ 5,689,196 A 11/1997 Schutte TEMPERATURE COMMAND 6,038,623 A 3/2000 Schutte 6,092,138 A 7/2000 Schutte

(75) Inventors: glewlttt’Frank- P. Ausna; Helms,~ TtXLQJS)b;°€ItJtSl)EfR Tokyo (JP);_ Larry D. 6,172,611, , B1i *i 1/2001 E101?Hussaine er ettalie eta. al...... 340/584 “tans mm’ es Inn’ ’ 055 6,272,642 B2* 8/2001 PO16 et al...... 713/300 Volgt LaFetra’ Sunnyvale’ CA (Us) 6,282,126 B1 * 8/2001 Prall ...... 365/185.3 6,282,662 B1* 8/2001 Z 11 tal. 713/300 (73) Assigneei Advanced Micro Devices, Inc-s 6,347,379 B1 * 2/2002 13212121...... 713/320 Sunnyvale, CA (Us) 6,510,400 B1 * 1/2003 Moriyama . 702/132 6,523,126 B1* 2/2003 Brabenac ...... 713/323 ( * ) Notice: Subject to any disclaimer, the term of this 6,535,798 B1 * 3/2003 Bhatia et al...... 700/293 patent is extended or adjusted under 35 6,591,369 B1* 7/2003 Edwards et al...... 713/400 U_S_C_ 154(1)) by 143 days_ 6,714,891 B2* 3/2004 Dendinger ...... 702/132 7,050,885 B2 * 5/2006 Fiegle et al...... 700/276 (21) APPL No: 11/140,803 7,051,218 B1* 5/2006 Gulick et a1. 713/310 2005/0244972 A1* 11/2005 HllSOIl et al...... 436/47 (22) Filed. May 31 2005 2006/0146649 A1* 7/2006 Pappas et al...... 368/10 - a Related US. Application Data OTHER PUBLICATIONS

. . . . “A smart RTD temperature sensor With a prototype IEEE 1451.2 (60) PrOVlslOnal apphcanon NO’ 60/575’999’ ?led On Jun’ internet interface” by Wobschall et al. (abstract only) Publication 1’ 2004- Date: 2004*

51 I nt. Cl . C ontmue' d G06F 1/201/30 E20062006.01 01; Primary Examiner4Gopal C. Ray G06F 13/00 (200601) (74) Attorney, Agent, or FirmiZagorin O’Brien Graham (52) US. Cl...... 710/110; 713/300; 713/600; LLP 702/132; 340/584 (57) ABSTRACT (58) Field of Classi?cation Search ...... 710/100, 710/110’ 305’ 72; 712/32T33f 600’ 300f A serial communication system includes an integrated cir 712/310’ 320’ 322’ 700/291T293’_ 711/154’ cuit having a master serial interface; and a processor having _ _ 702/13m132; 340/584 a slave serial interface coupled to the master serial interface See apphcanon ?le for Complete Search hlstory' through a clock signal line and a data signal line. The slave (56) References Cited serial interface is responsive to a read temperature command issued by the master serial interface to return a ?rst tem U.S. PATENT DOCUMENTS perature value associated With the processor. 4,689,740 A 8/1987 Moelands et al. 5,559,502 A 9/1996 Schutte 20 Claims, 5 Drawing Sheets

SODIMMI [ I SODIMMO ' 7

CPU HyperTransport I SMB “S CHIPSET: SI

"99211395 ...... -_ I/O Hub

SIOLPC / Embedded Controller US 7,231,474 B1 Page 2

OTHER PUBLICATIONS Kalinsky, David and Kalinsky, Roee, “Introduction to 12C,” Embedded Systems Programing, Jul. 31, 2001, 4 pages, retrieved Kalinsky, David and Kalinsky, Roee, “Introduction to Serial Periph- Apr‘ 24, 2005 from URL: ‘ pages, retrieved Apr. 25, 2005 from URL: . * Cited by examiner U.S. Patent Jun. 12, 2007 Sheet 1 0f 5 US 7,231,474 B1

VDDIO O

P 108 Processor SID External Device (SI (SI Slave) : g - - Master) 102 _Jfj%; ‘SIC 106 i

m 104 Q

SID

TSU ‘ TH A ‘ A V U.S. Patent Jun. 12, 2007 Sheet 2 0f 5 US 7,231,474 B1

?)8 SIC IIIIIZZHAUUUZHWQZHII 3“) 2? J‘! ii ' V gliid Initialize or Idle Lt Data bit condition Stat-t (reads \__Y__J only) Command ¥__Y_—J or \ Phase Data Phase H16

301 303 305 307 309 U.S. Patent Jun. 12, 2007 Sheet 3 of 5 US 7,231,474 B1

DIMM3 DIMMZ DHVIMI DIMMO

CPU

HyperTransport SMBus CHIPSET: Graphics

Dim/13 r J DIMMZ l J DIMMI I j DIMMO I J S1 to SMBus CPU 0 SI Translator 501 SMBus segment 0 HyperTransport _

CHIPSET: SNLBuS "176111-15 ------" SMBus A SNIBuS SMBus segment I segméms segment --—-———- assoclated selector .W with other Baseboard Processors Management SMBus B SMBus Segment N m an MP Controller Q ‘-—__— system

FIG. 5 U.S. Patent Jun. 12, 2007 Sheet 4 0f 5 US 7,231,474 B1

DIMM3 l DIMMZ l DIMMl % DIMMO ' SI to SMBus CP U SI Translator with ‘ Integrated CPU HyperTransport I fan control

CHIPSET:

..<.3.r?PP.i9§ ______I/O Hub ' " 601 m1 810/ HW SMBus Monitor

SODIMMl [ SODIMMO @

CPU HyperTransport I SMBus CHLPSET:

"9352192159 ...... -. I/O Hub

SIOLPC / Embedded Controller U.S. Patent Jun. 12, 2007 Sheet 5 0f 5 US 7,231,474 B1

DIMM3 I I D1MM2 F I

DIMMI ' ' DIMMO I 1

CPU SI HvperTransport T SI to SMBUS CHIPSET: Diode 1c

“Gtapbics...... _. I/O Hub \ LPC I ThermDA SIO / HW Monitor ThennDC 80‘

FIG.8

VDD 8 NC

D+ 7 SID SI TO DIODE D- 6 SIC

NC 5 GND

FIG. 9 US 7,231,474 B1 1 2 SERIAL INTERFACE HAVING A READ to a version command to return an identi?cation of a version TEMPERATURE COMMAND of the serial interface supported by the microprocessor.

CROSS-REFERENCE TO RELATED BRIEF DESCRIPTION OF THE DRAWINGS APPLICATION(S) The present invention may be better understood, and its This application claims bene?t under 35 USC § 119(e) numerous objects, features, and advantages made apparent of application No. 60/575,999 ?led Jun. 1, 2004, entitled to those skilled in the art by referencing the accompanying Method and Apparatus for Serial Interface, Which applica draWings. tion is incorporated herein by reference. FIG. 1 shoWs a block diagram With the Serial Interface used to monitor processor temperature. BACKGROUND FIG. 2 shoWs a Serial Interface timing diagram. FIG. 3 shoWs Serial Interface protocol phases. 1. Field of the Invention FIG. 4 shoWs a topology in Which an SIO/HardWare This invention relates to a serial interface for use on monitor provides native support for the Serial Interface. integrated circuits, particularly a serial interface for a micro FIG. 5 shoWs an exemplary multiprocessor (MP) system processor. With one Serial Interface to SMBus translator integrated 2. Description of the Related Art circuit per processor. Microprocessors have traditionally utiliZed an on-die ther FIG. 6 shoWs an exemplary Serial Interface to SMBus mal diode to provide temperature information to an off-chip 20 translator With integrated CPU fan control. monitoring device. In traditional implementations, tWo pins FIG. 7 shoWs an exemplary notebook implementation on the microprocessor are utiliZed to interface the diode to With Serial Interface accessed by an embedded controller. the monitoring device, Which determines the temperature of FIG. 8 shoWs a topology that utiliZes a Serial Interface to the microprocessor based on the diode. The temperature diode translation implementation. information is utiliZed for thermal control, e.g., fan control 25 FIG. 9 shoWs an exemplary Serial Interface to diode or other thermal management activities. integrated circuit pinout. The use of the same reference symbols in different draW SUMMARY ings indicates similar or identical items.

Some microprocessors have developed the capability of 30 DESCRIPTION OF THE PREFERRED generating a digital temperature value rather than supplying EMBODIMENT(S) temperature information via a thermal diode interface. In order to provide access to that temperature and other pro Referring noW to FIG. 1, illustrated is an exemplary cessor information, it Would be desirable to provide a simple embodiment of a Serial Interface (SI). In one embodiment, interface that alloWs that digital temperature value to be 35 the Serial Interface is a simple digital interface that provides read. access to the processor’s temperature and Node ID. The Accordingly, in an embodiment a serial communication Serial Interface can be used in place of externally accessible system is provided that includes an integrated circuit having on-die thermal diode supported by previous processors, a master serial interface; and a processor having a slave Where the processor provides a temperature in a digital serial interface coupled to the master serial interface through 40 format. The serial interface includes a slave device 101, a clock signal line and a data signal line. The slave serial Which in the illustrated embodiment is a processor and an interface is responsive to a read temperature command external master device 103. The slave device 101 and master issued by the master serial interface to return a ?rst tem device 103 are coupled by a tWo Wire point-to-point com perature value associated With the processor. munication link that alloWs one master device and one slave In the serial communication system, the ?rst temperature 45 device to communicate. value is returned as a sixteen bit value having a most The tWo Wire communication link includes a Serial Inter signi?cant and a least signi?cant byte, and Wherein the most face Clock (SIC) signal 104. The SIC signal is an input to the signi?cant byte returned represents an integer portion of the processor 101 and is used to clock information into and out ?rst temperature value from 00 to 255° C. and Wherein the of the processor on the Serial Interface Data (SID) signal upper three bits of the least signi?cant byte returned repre 50 102. Information is transmitted of the Serial Interface most sents a fractional portion of the ?rst temperature value from signi?cant bit (MSB) ?rst. Referring to FIG. 2, information 00 C. to 0.875° C. in increments equal to 0.l25° C. is shifted out on SID 102 based on the rising edge of SIC In an embodiment, the protocol on the serial communi 201. SID is sampled as an input With the falling edge of SIC cation system includes an initialiZation condition Where the 203. In one embodiment, SIC and SID are pulled up on the serial interface master drives at least 32 consecutive clock 55 motherboard to VDDIO through 300 ohm resistors 106 and cycles of l’s on the data line to the serial interface slave, a 108. The SIC signal 104 may be an open drain output on the start condition Wherein the master serial interface signals a SI master 105. SID is bidirectional and implemented as an start condition by driving the data line loW for one clock open drain output (or drive loW for loW, and high impedance cycle of the clock signal line folloWing the initialiZation for high). In the illustrated embodiment, VDDIO is the condition, a command phase, a data phase. The last bit of the 60 voltage plane that poWers the processor memory interface data phase for a read temperature command includes a valid and the processor Serial Interface slave circuitry. In an bit, Which is at a ?rst value to indicate that the data is valid embodiment VDDIO is 1.8V nominal for DDR2. In other and at a second value to indicate that the slave serial embodiments VDDIO may be 1.5V nominal or other volt interface is not ready. ages. The masters may be implemented to operate at mul In an embodiment the slave is further responsive to a read 65 tiple voltage levels. node ID command to return an identi?cation associated With Referring to FIG. 2 exemplary timing relationships are the processor. The serial interface slave is further responsive shoWn for SIC and SID. In one embodiment the SIC period US 7,231,474 B1 3 4 TP is minimum 1000 nanoseconds (ns) and has no maxi after signaling an idle condition for one clock. It is expected mum. Thus, the frequency can range from 0 to 1000 KHZ in that SIC Will be stopped in the high state if an idle condition such an embodiment. Various setup (TSU) and hold (TH) is going to persist for some number of SIC cycles. requirements and other electrical parameters may be speci The Serial Interface provides speci?c commands that ?ed according to the particular implementation. Note that return a prede?ned type of data over the Serial Interface. internal logical hysteresis may be implemented to cover Table 1 lists exemplary Serial Interface commands that are motherboard related signal integrity issues With SIC (rising supported in an embodiment of the Serial Interface. or falling edges that are not clean). Referring to FIG. 3, the Serial Interface protocol includes TABLE 1 an initialiZation condition 301, a start condition 303, a command phase 305, a data phase 307, and an idle condition Command [7:0] Attribute Data Size Description 309. The master initialiZes the slave before signaling a start 00h Read 8 bits Read Serial Interface Version and issuing a command. In one embodiment, initialiZation is 01h Read 16 bits Read Processor Control de?ned as the master driving at least 16 consecutive SIC Temperature (Tcontrol). cycles of 1’s on SID to the slave. In other embodiments, the 02h Read 8 bits Read Processor Node ID. initialiZation period may be 32 consecutive SIC cycles of 1’s 03h to FFh Reserved or other appropriate number suitable to ensure the slave is initialiZed. During the initialiZation period, the Serial Inter The command Read Serial Interface Version causes the face is being initialiZed and is idle. The slave does not slave to report the 8-bit Version of the Serial Interface that respond to the master until it has detected the initialiZation. 20 it supports. For example, a version number of “00” can be Note that the slave may only look for a 16 clock initialiZa used to indicate that the supported serial interface com tion sequence once after its PWROK signal has asserted. But mands are 00h through 02h. Another version number can be the master should consecutively shift out an additional 16 used to indicate that other commands are supported. clocks for a total of 32 consecutive clocks While SID is high The Read Processor Control Temperature command or to ensure that the slave’s state machine is ?ushed and is at 25 Tcontrol command causes the Serial Interface slave to return an idles state. It is the master’s responsibility to ensure that a representation of the processor temperature, Which in one SID is sampled high for at least 32 SIC cycles before embodiment is a left justi?ed ?xed point number represen signaling a start and issuing a command. If the slave has not tation of the processor temperature. In one embodiment, the detected initialiZation or is not able to respond to a com temperature is returned in a 16 bit binary representation mand, the slave signals that it is not ready by not asserting 30 (MSBzLSB) of the processor temperature in o C. in Which the valid bit (slave leaves SID high) after the data transfer the most signi?cant byte represents the integer portion of the during a read command. If the master detects a valid bit:1, temperature from 00 to 255° and the upper three bits (left then it re-initialiZes the Serial Interface by signaling the idle justi?ed) of the least signi?cant byte represents the frac condition, e.g., for at least 32 SIC cycles before trying to tional portion of the temperature. One increment of the access the slave again. 35 upper three bits of the LSB equals 0.1250 C. For example, After initialiZation the master signals a start condition 303 a control temperature of 25.125 is represented in the most by driving SID loW for one SIC cycle folloWing an initial signi?cant byte as 0001 1001 and in the loWer byte as iZation condition, an idle condition, or a data phase. The 001>x86 pro Monitor 401 reads the temperature of the processor using the cessors. The equation for temperature measurement from Tcontrol temperature command to determine What actions if 30 such a diode is beloW. any need to be taken relative to processor fan speed, or causing an SCI (system control interrupt) to invoke an Advanced Con?guration PoWer Interface (ACPI) thermal Zone action in response to a change in processor tempera ture. 35 In another topology illustrated in FIG. 5, a Serial Interface to SMBus translator integrated circuit 501 that replaces the Where: SMBus temperature sensor reads the processor on-die diode. KIBoItZmann’s constant The SMBus is Well knoWn in the industry. An embodiment, such as shoWn in FIG. 5, may utiliZe the translator integrated 40 circuit (IC) 501 as a slave on the SMBus link and the master T:control temperature provided by the Serial Interface on the Serial Interface link. Such a translator IC may be useful in a system Where devices can interface to the SMBus NIratio of tWo currents supplied to diode but not the Serial Interface. Thus, the translator provides a n:ideality factor of the diode:l.008 translation betWeen the protocols and functionality of the 45 Thus, various embodiments have been described relating Serial Interface and the SMBus. to utiliZation of a serial interface. The description of the In multiprocessor systems a Serial Interface to SMBus invention set forth herein is illustrative, and is not intended translator integrated circuit is associated With each proces to limit the scope of the invention as set forth in the sor. Each processor in an MP system has an SMBus segment folloWing claims. Other variations and modi?cations of the associated With it. Each SMBus segment has the Serial 50 embodiments disclosed herein may be made based on the Presence Detect (SPD) EEPROMs for the dual in line description set forth herein, Without departing from the memory modules (DIMMs) and the Serial Interface to scope of the invention as set forth in the folloWing claims. SMBus translator associated With the processor. An SMBus segment selector (Which could be an additional device or What is claimed is: incorporated into existing devices) alloWs the chipset asso 55 1. A serial communication system comprising: ciated With the BSP (Bootstrap processor) to control the an integrated circuit having a master serial interface; and SMBus selector during poWer on self test (POST). This a processor having a slave serial interface coupled to the enables the BIOS to directly associate each processor With master serial interface through a clock signal line and the memory physically connected to it, by reading the Node a data signal line Wherein the slave serial interface is ID of the processor associated With each SMBus segment. 60 responsive to a read temperature command issued by After POST, the BIOS passes control of the SMBus segment the master serial interface to return a temperature value selector to the BMC (baseboard management controller) so associated With the processor. that the BMC can monitor the temperature of the processors 2. The serial communication system as recited in claim 1 in the system. FIG. 5 depicts an MP system in Which each Wherein the temperature value is returned as a sixteen bit processor has a Serial Interface to SMBus translator IC 501 65 value having a most signi?cant and a least signi?cant byte, associated With it. Only CPU 0 of the MP system is shoWn. and Wherein the most signi?cant byte returned represents an The SMBus segment selector 503 is also shoWn. integer portion of the temperature value from 0° to 255° C. US 7,231,474 B1 7 8 and wherein the upper three bits of the least signi?cant byte phase for a read temperature command a valid bit, the valid returned represents a fractional portion of the temperature bit being at a ?rst value to indicate that the data is valid and value from 0° C. to 0.875° C. in increments equal to 0.1250 at a second value to indicate that the serial interface slave is C. not ready. 3. The serial communication system as recited in claim 1 13. The method as recited in claim 11 further comprising Wherein the slave serial interface is responsive to at least one the serial interface slave responding to a read node ID additional read temperature command to return at least one command to return an identi?cation associated With the additional temperature value associated With the processor. 4. The serial communication system as recited in 3 processor over the data line. Wherein the temperature value includes one or more offsets 14. A serial communication system comprising: to a measured temperature. a microprocessor having a slave serial interface for cou 5. The serial communication system as recited in claim 1 pling to a master serial interface through a clock signal Wherein protocol on the serial communication system line output terminal and a data signal line output includes, an initialiZation condition Where the master serial terminal Wherein the slave serial interface is responsive interface drives at least 32 consecutive clock cycles of 1 ’s on to a read temperature command issued by the master the data line to the slave serial interface, a start condition serial interface to return to the master serial interface a Wherein the master serial interface signals a start condition temperature value associated With the microprocessor. by driving the data line loW for one clock cycle of the clock signal line folloWing the initialiZation condition, a command 15. The serial communication system as recited in claim 14 further comprising an integrated circuit incorporating the phase, and a data phase. 20 6. The serial communication system as recited in claim 5 master serial interface coupled to the clock signal line output Wherein a last bit of the data phase for a read temperature terminal and a data signal line output terminal via a clock command includes a valid bit, the valid bit being at a ?rst signal line and a data signal line coupled to the master serial value to indicate that the data is valid and at a second value interface. to indicate that the slave serial interface is not ready. 25 16. The serial communication system as recited in claim 7. The serial communication system as recited in claim 1 15 Wherein the slave serial interface is responsive to another Wherein the slave serial interface is further responsive to a read temperature command, the other read temperature read node ID command to return an identi?cation associated command having a different decode value than the read With the processor. temperature command, to return another temperature value 8. A method for communicating over a point to point 30 associated With the microprocessor. serial communication system having a clock signal line and 17. The serial communication system as recited in claim a data signal line coupling a serial interface master and a 15 Wherein protocol on the serial communication system serial interface slave, the method comprising: includes an initialiZation condition Where the master serial sending a read temperature command to the serial inter interface drives at least 32 consecutive clock cycles of 1 ’s on face slave from the serial interface master using the 35 the data line to the slave serial interface, a start condition clock signal line and the data signal line; and Wherein the master serial interface signals a start condition in response to the read temperature command, the serial by driving the data line loW for one clock cycle of the clock interface slave supplying over the data signal line a signal line folloWing the initialiZation condition, a command temperature value associated With a processor on an phase, and a data phase. integrated circuit containing the serial interface slave. 40 18. The serial communication system as recited in claim 9. The method as recited in claim 8 Wherein the tempera 17 Wherein a last bit of the data phase for the read tempera ture value is returned as a ?xed point number. ture command includes a valid bit, the valid bit being at a 10. The method as recited in claim 8 further comprising ?rst value to indicate that the data is valid and at a second the serial interface slave responding to another read tem value to indicate that the slave serial interface is not ready. perature command from the serial interface master to return another temperature value associated With the processor. 19. The serial communication system as recited in claim 11. The method as recited in claim 8 Wherein protocol on 15 Wherein the slave serial interface is further responsive to the serial communication system includes an initialiZation a read node ID command to return an identi?cation associ condition Where the serial interface master drives at least 32 ated With the microprocessor. consecutive clock cycles of l’s on the data line to the serial 50 20. The serial communication system as recited in claim interface slave, a start condition Wherein the serial interface 19 Wherein the slave serial interface is further responsive to master signals a start condition by driving the data line loW a version command to return an identi?cation of a version of for one clock cycle of the clock signal line folloWing the the serial communication system supported by the micro initialiZation condition, a command phase, and a data phase. processor. 12. The method as recited in claim 11 further comprising 55 the serial interface slave sending as a last bit of the data