Carbon Nanotube Interconnects for End-Of-Roadmap Semiconductor Technology Nodes" (2016)

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12-1-2016 Carbon Nanotube Interconnects for End-of- Roadmap Semiconductor Technology Nodes Anshul A. Vyas Santa Clara University

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Carbon Nanotube Interconnects for End-of- Roadmap Semiconductor Technology Nodes

Anshul A. Vyas

Dissertation

Submitted in partial fulfillment of the requirements

for the degree of Doctor of Philosophy in Electrical Engineering

School of Engineering

Santa Clara University

Santa Clara, California

November, 2016

Acknowledgements

I would like to take this opportunity to express my sincere gratitude and acknowledge all the people who have supported me in various capacities through my Ph.D. program. First and foremost, I would like to show my deepest appreciation to Prof. Cary Yang who has guided, supported, and mentored me throughout this period. His patience, guidance, and encouragement throughout the program has been well beyond any measure. I like to thank him for giving me an opportunity to be a part of his research group.

I would like to express special thanks and acknowledgement to Dr. Changjian Zhou who helped in fabrication of test devices during his tenure as postdoctoral research associate at HKUST and in assisting me on data analysis. Without Dr. Zhou’s expertise, it would not have been possible to fabricate devices at such fine linewidths. I also thank Prof. Mansun Chan for granting us access to the Nanosystem Fabrication Facility at HKUST for the test-structure fabrication.

I want to acknowledge Phillip Wang, Jerry Gelatos, Bo Zheng, and Vik Banthia at Applied Materials for helping me with experiments, scientific inputs, and multiple grants to support me throughout this program. I also want to thank Murali Narasimhan for the initial offer to work at Applied Materials as a Co-op. Without their help and support it would not have been possible to continue and finish this program.

I would also like to thank my doctoral committee members, Dr. Stephen Hudgens, Dr. Drazen Fabris, Dr. Ramesh Abhari, and Dr. Jeongwon Park for agreeing to serve on the committee and for their advice and guidance. I also thank Dr. Toshishige Yamada for mentoring me throughout my doctoral program. Finally, I want to extend my warm appreciation to my bright and cheerful colleagues and collaborators at TENT Laboratory, Patrick Wilhite, Francisco Madriz, Nobuhiko Kanzaki, Yusuke Abe, Gregory Laskowski, and Ayo Adesida, as well as Dr. Jessica Koehne at NASA Ames, for their constant support and advice. I have worked with them over the years and have benefited from their wisdom on various aspects of my work and their enduring friendship.

iii

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes Anshul A. Vyas Department of Electrical Engineering, Santa Clara University

ABSTRACT

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior current- carrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm  40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current- carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge.

Contents

List of Figures……………….………………….……………………………………………1

List of Tables………………..……………….……………………………………………..11

1. Introduction…………………………....……………………………………………....12 1.1.Moore’s Law its Impact on Interconnects………………………...... ………….…14 1.2.Potential Replacement Interconnect Conductors...…………….….….……….20 1.3.State of CNT Interconnects………...…………………..……….….…...……….24 1.4.Organization of Dissertation…………………………………….………………...26

2. Properties and Growth of Carbon Nanotubes………………….………………….35 2.1.Carbon Electronic Structure……...………………………….…………………..36 2.2.Graphene….…………………………………………….……….…….……………38 2.3.Carbon Nanotube……………………………………………..…....…………….42 2.3.1. Chiral Vector…………………………………………….…...…………...43 2.3.2. Translational Vector…………………………………………………..45 2.4.Electronic Structure of CNT……………………………………………………..46 2.5.CNT Growth Methods………………………………………………….………..57 2.5.1. Catalyst-Assisted CNT Growth………………………………………….58 2.5.2. CNT Growth Process Development…………………………………….59

3. Carbon Nanotubes Horizontal Interconnects………...……………………………72 3.1.Overview of Horizontal CNT Interconnects……………………….…………..73 3.2.CNT Resistance and Metal-CNT Contacts………………………….…………...75 3.3.DC Characteristics…………………………………………………….………….85 3.4.RF Characteristics……………………………………………………….………..92

4. Carbon Nanotube Vias: Test Structure Fabrication and Nanostructure Characterization...…………………………………...……………………………..100 4.1.Test Structure Design Considerations……………………………………….….101 4.2.Via Test Structure Fabrication……………………………………………….….104 4.3.CNT Growth in Vias…………………………………………………………...109 4.4.Dielectric Fill and Polish…………………………………………………….….110 4.5.CNT Via Top Contact Metallization…………………………………………….112 4.6.Nanostructure Characterization………………………………………………114 4.6.1. Electron Microscopic Analyses………………………………………...114

4.6.2. Raman Spectral Analysis……………………………………………….117

5. Carbon Nanotube Vias: Electrical Characterization…………………………….124 5.1.Overview of Nanoprobing System………………….………………………....125 5.2.CNT Via Resistance Measurements………………….………………………...127 5.3.Current-Carrying Capacity Measurements………….………………………..137 5.3.1. Current Stress Test……………………………………………………...... 137 5.3.2. Voltage-Sweep Test…………………………………………………….139

6. Conclusions and Future Work…………………………………………...………..146 6.1.Conclusions…………………………………………….……………………...…..147 6.2.Future Work on Nanocarbon Interconnects………….……………………….148

List of Publications………………………..……………………..……………………155

List of Figures

Figure 1.1 Cross-sectional SEM images of chips from Intel’s 20 nm and 14 nm processes, showing downscaling of components by 0.65x……………………………………………...14

Figure 1.2 Schematic of electron scattering at grain boundaries and surfaces inside a copper trench structure………………………………………………………………...……....15

Figure 1.3 Resistance and capacitance components in an interconnect structure……..….16

Figure 1.4 Projected effective dielectric constant for interconnect system to manage propagation delay……………………………………………………………………………...17

Figure 1.5 Projected gate, interconnect, and (gate + interconnect) delay for Al and Cu interconnect materials. At 180 nm node and beyond, delay of Cu/low-k interconnect system exceeds gate delay and becomes the primary limiting factor for circuit performance………………………………………………………………………………….....18

Figure 1.6 Projected maximum current IMAX through interconnects for future technology generations and the corresponding current density JMAX. The yellow and red shaded regions indicate EM and post-EM regimes, respectively. While IMAX through the interconnect is scaled downwards for each generation, JMAX increases due to continuous reduction of interconnect cross-sectional area…………….………………………………....19

Figure 1.7 EM lifetime of various capping materials on Cu versus resulting interconnect resistance increase. Materials with the least resistance change for extended EM lifetime are preferred…………………………………………………………………………………….20

Figure 1.8 Percentage of Cu volume in trench structure versus its half pitch (HP)……….21

Figure 1.9 (a) Barrierless and seedless structure for Co interconnect with low-k dielectric. (b) Comparison of Cu, W, and Co resistances for different linewidths. (c) Comparison of delays from various interconnect configurations with gate delay…………………………23

Figure 2.1(a) Electronic energy levels (not to scale) of carbon atom. Inset shows electronic states where arrows represent the direction of electron spin. (b) sp-hybridized bonding in carbyne. (c) sp2-hybridized bonding in graphene. (d) sp3-hybridized bonding in diamond …………………………………………………………………….…………………..36

Figure 2.2. The two-dimensional lattice of graphene has a trigonal diatomic unit cell (light green), defined by the unit lattice vectors a1 and a2 with |a1| = |a2| = a = √3dCC and ∠ (a1,

1 a2) = 60°. Nearest neighbor distance dCC = 1.42 Å as in graphite. Spacings dC1, dC2, and dC3 are introduced for convenience. Ahex is the area of a hexagon (light blue), which equals to that of unit cell, and dC1 + 2dC2 = 2dCC is the distance between opposite vertices. (b) Top- view HRTEM image of a monolayer of graphene…………………………………………...38

Figure 2.3 (a) Complete energy band structure of monolayer graphene obtained using tight-binding approach [9, 10]. The hexagonal first BZ is also shown. (b) E(k) behavior along MΓKM direction with inset zoomed in around K………………………………...…..40

Figure 2.4 (a) Bernal stacking or symmetric bi-layer graphene. AB stacked, bi-layer graphene refers to the stacking of the B site (denoted by blue ring) in the top layer n2 directly above the A site (denoted by orange ring) in the bottom layer n1. Interplanar distance d1=3.37 Å [12]. (b) Turbostratic stacking or asymmetric bi-layer graphene. Interplanar distance d1=3.44 Å. (c) Band structure of metallic symmetric bi-layer graphene along a K to Γ direction. (d) Band structure of semiconducting asymmetric bi-layer graphene along a K to Γ direction………………..……………………………………………41

Figure 2.5 (a) First reported electron microscope image of 50 nm diameter CNT. (b) TEM image of SWCNT. (c) TEM image of MWCNT. (d) TEM image of a bundle of SWCNTs. (e) TEM image of an isolated SWCNT grown using laser ablation. (f) TEM image of commercially available MWCNT. (g) TEM image of MWCNT produced with arc- discharge………………………………………………………………………………………..43

Figure 2.6 (a) Schematic of honeycomb graphene sheet showing chiral, translational, and symmetry vectors. (b) Schematic of honeycomb graphene sheet with various chiral vectors (n, m). (c) Illustration of a single graphene sheet rolled into SWCNT in armchair configuration. (d) Schematic of SWCNT with different chiralities………………………...44

Figure 2.7 Reciprocal space of the graphene layer. (a) Parallel equidistant lines give the fully K1-extended representation of the 28 cutting lines for (4, 2) CNT. K1, K2 indicate the reciprocal lattice unit vectors of CNT. A K2 line is 1D BZ of CNT. The rectangle bordered by dashed line has an area equal to that of graphene BZ. (b) The fully reduced representation of the cutting lines for the same CNT, which fills the area of graphene BZ………………………………………………………………………………………………..48

Figure 2.8 (a) Band structure of (5, 5) CNT constructed using ZF. The purple bands crossing the Fermi energy stem from the purple cutting line in (c), which crosses K and K’ points. (b) Band structure of (9, 0) CNT, showing double degeneracy at the valence and conduction band crossing due to the two blue thick cutting lines in (d). (c) The 10 cutting lines of (5, 5) CNT projected onto graphene BZ, with same color coding as

2 corresponding bands in (a). The green rectangle indicates the bordering rectangle as in Fig. 2.7(a). (d) Similar to (c) for (9,0) zigzag CNT. (e) With curvature effect, K and K’ points move away from corners of hexagon to red dots. Armchair nanotubes thus stay metallic (left), while metallic zigzag nanotubes become small bandgap semiconductors (right), such as that for (8, 0) CNT in (f). k‖ ≡ K2 and k⊥ ≡ K1………………………………...49

Figure 2.9. (a) Rolled sheet of graphene showing k components along T and Ch. (b) Cutting lines of SWCNT on graphene BZ, with Dirac cones at BZ corners. (c) Enlarged view of a Dirac cone with cutting lines. (d) Energy bands of SWCNT obtained by projecting slices of Dirac cone in a plane containing a cutting line. (e) Densities of states (DOS) of SWCNT obtained from energy bands……………………………………………...50

Figure 2.10 Ab initio calculation of band structure of (10, 0) CNT. Solid dots corresponds to energy values obtained from projection of cutting lines onto 2D BZ of graphene using zone-folding method…………………………………………………………………………..51

Figure 2.11 Illustration of condition for cutting line to pass through corner of graphene BZ. K2 represents a cutting line for (10,5) CNT. Line ΓY is projection of vector ΓK = K onto K1 direction……………………………………………………………………………………...52

Figure 2.12 (a) Display of T and Ch vectors on graphene lattice for (3, 3) and (4, 2) CNTs. Projection of cutting lines onto graphene BZ for (b) (3, 3) CNT and (d) (4, 2) CNT. The 1D BZs of CNT are indicated by thicker red portions of lines, 6 for (3, 3) in (b) and 28 for (4,2) in (d). These lines are continuous for a long nanotube. (c) 1D energy band structures of metallic (3, 3) CNT in (c) and semiconducting (4, 2) CNT in (e) obtained with ZF method…………………………………………………………………………………………..53

Figure 2.13 Projection of cutting lines of a semiconducting CNT on graphene BZ, showing the graphene Fermi vector kF and vector δk representing the perpendicular from K point to the nearest cutting line inside BZ. The CNT bandgap occurs at the base of the perpendicular with wave vector k……………………………………………………………54

Figure 2.14. (a) Base growth and (b) tip growth of CNT on substrate resulting from catalyst-assisted dissociation of gaseous hydrocarbon source……………………………..58

Figure 2.15. Effect of catalyst thickness and underlayer combination on CNT growth…60

Figure 2.16. (a) CNT growth after 5 min annealing in ammonia ambient. (b) CNT growth without annealing. Both samples grown using 12 nm Ni film……………………………...61

Figure 2.17. Effect of catalyst thickness on CNT diameter distribution. (Inset) Top-view SEM images of CNTs grown on unpatterned Cr substrate with 4 nm Ni catalyst………..61

Figure 2.18 TEM image of CNTs grown using PECVD with Ni catalyst, revealing bamboo-like structure and variation in diameter along CNT length………………………62

Figure 2.19 Typical variations of process parameters versus time before, during, and after CNT growth. SP denotes setpoint and PV for parameter value……………………………64

Figure 2.20 Gas flow rates versus time during and after CNT growth. MFC1 is for ammonia, MFC2 for argon, and MFC3 for acetylene………………………………………..64

Figure 3.1 SEM images of CNTs grown on quartz substrate using different catalysts….73

Figure 3.2 SEM images of horizontally aligned SWCNTs grown on quartz substrate…...74

Figure 3.3 (a) Top-view SEM image of a single MWCNT grown between two metal electrodes. (b) Cross-sectional SEM images of a bundle of MWCNTs grown between sidewalls of a trench……………………………………………………………………………75

Figure 3.4(a) (a) Resistance of MWCNT as a function of length. (b) Mean free path and contact resistance (excluding quantum resistance) of MWCNT as a function of diameter…………………………………………………………………………………………76

Figure 3.5 (a) End-contacted CNT-metal interface. (b) Side-contacted CNT-metal interface…………………………………………………………………………………………77

Figure 3.6 Optimized geometries for the end-contacted graphene-metal interface. The top frame shows the top view (x-y plane). The middle frame shows the side view (z-x plane). The bottom frame shows the side view (z-y plane). The unit cell is 0.846 nm × 0.489 nm (periodic in x-y directions) with 24 metal atoms (6 atoms × 4 layers) and 16 carbon atoms (4 atoms × 4 layers). The metal layers are built up atom by atom, leading to an hcp packing for Ti, while the others have fcc packing. C denotes graphene layer at the interface, M1 metal layer at the interface (first layer), M2 second metal layer, M3 third metal layer, and M4 fourth metal layer…………………………………………………………………………..77

Figure 3.7 (a) I-V behavior for end-contacted metal-graphene interfaces. (b) Resistance versus voltage plot for the same interfaces…………………………………………………...78

Figure 3.8 Optimized geometry for each system yields metal interatomic distance for each layer within 10% of that in the bulk crystal. The top and side views of (a) Ti and (b) Pd on a 4 × 4 graphene sheet. Unit cell for optimization is a 2 × 2 graphene sheet. Three metal layers are used: green -first layer, orange - second layer, light blue - third layer. (c) Binding energy between metal atom and graphene, with the energy for Ti scaled by 1/5. (d) Resistance normalized per unit area at metal-graphene interface……………………..78

Figure 3.9 (a)-(d) Cross-sectional schematic of models for Ti-(7, 7)CNT, Pd-(7, 7)CNT, Ti- (13, 0)CNT, and Pd-(13, 0)CNT interfaces. (e) Calculated I-V behaviors. (f) Contact resistance per nm of CNT……………………………………………………………………...79

Figure 3.10. Hybrid contact configuration proposed by Matsuda where d is the length of side-contact between metal and CNT………………………………………………………...80

Figure 3.11 (a) Measured metal-CNT contact resistance versus metal work-function [37]. (b) Metal-CNT contact resistance versus work function of selected metals with work functions between 4.2 – 5.7 eV. (c) Schematics of good wettability metal-CNT contact [37]. (d) Schematics of poor-wettability metal-CNT contact.…………………………………….82

Figure 3.12 TEM images of 5 nm metal films deposited on surface of SWCNT…………...82

Figure 3.13 Current-stressing experiments. (a) Configuration 1: CNF suspended on Au electrodes. (b) Configuration 2: CNF supported by SiO2 substrate. (c) Configuration 3: CNF suspended with W deposited on contacts. (d) Configuration 4: CNF supported by SiO2 substrate with W deposited on contacts. Upper frame in each Figure shows SEM image of device from 75° tilted-angle view, and lower frame is electrical measurement schematic………………………………………………………………………………………..86

Figure 3.14 (a) Typical I-V characteristics for Configuration 1 measured before current stressing. (b) Typical I-V characteristics for Configuration 3 measured before current stressing…………………………………………………………………………………………87

Figure 3.15 (a) Resistance of CNF devices without W deposition as a function of stressing current after each stress cycle. Each symbol represents an individual device. (b) Resistance of CNF devices with W-deposited contacts as a function of stressing current after each stress cycle…………………………………………………………………………..88

Figure 3.16 Maximum current density as a function of reciprocal CNF length for 36 devices. Solid circles indicate the results for Configuration 1, open circles for Configuration 2, solid triangles for Configuration 3, and open triangles for Configuration

4 [45]. The solid line shows a linear fit for suspended CNFs, based on a thermal transport model……………………………………………………………………………………………89

Figure 3.17. Comparison of resistances of three CNF test devices under current stressing in vacuum……………………………………………………………………………………….90

Figure 3.18 (a) Bright-field TEM cross-sectional view of the CNF–Au–W electrode contact (IBID), with an inset containing a schematic of the contact region and the ultra-thin slice from which the image was obtained. Voids at the intersection of all three materials are present as a result of the CNFs’ shadow during W deposition. (b) High-resolution image of the IBID-W contact shows a clean interface with CNF, with the inset displaying EDS results for W deposit near the interface. (c), (d) Circled region exemplifies difference in W grain sizes before (c) and after anneal (d). (c) Before current stressing, EBID-W contact reveals small W grains (darker spots) embedded in a carbon matrix. The interface is less abrupt than that in (b) due to the similar contrasts of C within the CNF and W deposit. (d) W grain size in EBID-W contact increases after current stressing. Contrast at the interface is increased due to larger W grains and C reduction. Insets in (c) and (d) display EDS results for W deposits near their respective interfaces, showing W/O atomic ratio increases from 0.37 to 1.4 (weight ratio from 4.3 to 16) due to current stressing. Carbon content is considerably reduced by current stressing to a negligible amount, from an initial W/C atomic ratio of 0.33………………………………………………………………...91

Figure 3.19 (a) Schematics of layout and cross-section of GSG test structure. All labeled spacings in µm. D indicates pad-to-pad spacing ranging from 1 µm to 10 µm. (b) Drop- casted CNF bridging Au inner pads. (c) Test device after contact metallization with IBID- W………………………………………………………………………………..………………..93

Figure 3.20 (a) Circuit model of open test structure without CNF. (b) Capacitive components in open test structure (c) Resistive components in open test structure…...... 93

Figure 3.21 3D schematic of entire test structure showing various components and their corresponding model circuit elements……………………………………………………….94

Figure 3.22. (a) I–V characteristics of a typical CNF test device before (grey) and after (black) W deposition using IBID. (b) Frequency dependence of circuit model parameters RF and CF for the same test device extracted from S-parameter measurements, before (grey) and after (black) formation of IBID-W contacts………………………………………95

Figure 4.1 (a) Schematic of 4PP CBKR test structure. (b) SEM image of 4PP measurement on a pair of metallized CNT vias. (c) Schematic of 2PP measurement setup for direct probing of a single CNT via and SEM image of the 2PP setup…………………………....102

Figure 4.2 Image of mask for arrays of vias with widths 150 nm, 120 nm, 90 nm, 60 nm, and 40 nm. The pitch between vias is ~3 × via width, which allows sufficient room to probe individual vias with appropriate nanoprobes having diameters ranging from 60 nm to 300 nm. Further, such pitch would prevent overlap of metal deposited on adjacent via top contacts. ……………………………………………………………………………….104

Figure 4.3 Process flow for via test structure fabrication…………………………………106

Figure 4.4 Top-view SEM images of Cr underlayer (a) after deposition and (b) after annealing at 400°C………………………………………………………………………….....106

Figure 4.5 (a) Cross-sectional SEM image of resist film after developing. (b) Cross- sectional SEM image of a 60 nm CNT via with tapered profile………………………….107

Figure 4.6 (a) Cross-sectional SEM image of 60 nm vias showing vertical sidewalls. (b) Cross-sectional SEM image of an under-etched 40 nm via………………………………...108

Figure 4.7 (a) Side-view SEM image of a blanket-grown sample to determine CNT growth rate. (b) Top-view SEM image of 60 nm wide vias in sample A. (c) Top-view SEM images of 40 nm wide vias in sample B……………………………………………………………....109

Figure 4.8 (a) SEM image of CNT vias in sample A after Al2O3 filling. (b) Cross-sectional TEM image of a 60 nm CNT via after deposition of a 10 nm Al2O3 layer……………...... 111

Figure 4.9 (a) Low-magnification view of sample A. (b) Top-view SEM image of an array of 60 nm via after ion milling…………………………………………………………………111

Figure 4.10 (a) Cross-sectional schematic of CNT via wedge structure with varying height h. (b) Top-view SEM image of 40 nm CNT vias on wedge structure with arrow indicating direction of wedge………………………………………………………………………….....112

Figure 4.11 (a) Array of 60 nm vias with metallized contacts. (b) SEM image of 60 nm vias with EBID-Pt contacts. (c) Top view of 40 nm via wedge with EBID-Pt contacts. Arrow direction indicates direction of wedge as shown schematically in 4.10(a). (d) SEM image of 40 nm CNT vias with EBID-Pt contacts. Alternate vias are metallized to avoid electrical short due to potential overlap of adjacent Pt deposits……………………………………..113

Figure 4.12 (a) Cross-sectional TEM image of 60 nm vias before polishing. (b) Cross- sectional TEM image of 40 nm via with EBID-Pt “end-bonded” top contact…………….114

Figure 4.13 TEM image of 60 nm via with EDS elemental maps shown in different colors. Carbon signal can be traced to the bottom of the via which confirms CNT growth from via bottom and that CNT base is embedded inside Cr……………………………………..115

Figure. 4.14 Model for CNT growth inside via. The substrate temperature is ramped up to 650°C, at which carbon precursor C2H2 is introduced. Prior to flow of C2H2 at 650°C (Stage I), the deposited Ni film is dewetted forming catalytic particles for the reaction. In Stage IIa, when the temperature is being ramped up to 700°C, the Cr underlayer softens and rises inside the via due to capillary force while tip-growth of CNTs continues (Stages IIb). Such CNT growth through the protruded Cr is somewhat similar to the Ni/Cr liftoff during growth observed by Herman……………..…………………………………………116

Figure. 4.15 Raman spectra of CNTs grown at three different temperatures. The signal intensity in each plot is normalized to the G-band peak……………………………...……117

Figure 5.1. Photo of nanoprobing system consisting of four probes. The setup is made to rest on SEM sample stage which allows in situ imaging and probing of nanoscale devices…………………………………………………………………………………………125

Figure 5.2 (a) SEM image of shorting two nanoprobes. (b) Resulting I-V and resistance behaviors……………………………………………………………………………………....126

Figure 5.3(a) Voltage between nanoprobes before and after making contact with Cr, with inset showing SEM image of nanoprobes on Cr underlayer. (b) I-V and resistance behaviors when nanoprobes are in contact with Cr underlay…………………………….126

Figure 5.4 (a) Schematic of I-V measurement setup. (b) SEM image showing nanoprobe in contact with 60 nm CNT via without metallized top contact. (c) Typical I-V plot of a 60 nm via without metallized top contact……………………………………………....….…..128

Figure 5.5. Measured CNT via resistance versus via width (data points) and statistical linear regression fit of the measured data (solid line). Slope of the fitted solid line is -1.9, compared to the ideal case of -2. The dash lines show the fits based on the lowest and highest resistances, respectively, for each width. The lowest resistance obtained for a 60 nm via is 150 Ω and the lowest extrapolated resistance for a 30 nm via is 295 Ω. Based on the log-log plot, the statistical average Rvia for 60 nm vias is 1.7 kΩ with standard deviation

8 between 420 Ω and 7.1 kΩ. As a comparison, the inset shows the arithmetical mean (data point) and standard deviation (vertical bar) for each via width…………………………130

Figure 5.6. Cumulative distribution frequency plot for 60 nm CNT via resistance with and without EBID-Pt top contacts…………………………………………………………...131

Figure 5.7 (a) Top-view SEM images of 40 nm vias after CNT growth. (b) CNT vias of 40 nm after Al2O3 filling and polishing. (c) Top-view of wedge formed after polishing and before EBID-Pt deposition. The arrow indicates the direction of the wedge from low to high. (d) Typical measured I–V behavior that yields via resistance Rvia before EBID-Pt top- contact metallization. (e) Glancing view of CNT vias after EBID-Pt. Alternate vias are selectively metallized in order to avoid overlaps. (f) Cross-sectional schematic of wedge with nanoprobing setup showing varying via height h used for contact resistance extraction. The arrow indicates the direction of the wedge as in (c)……………………....133

Figure 5.8 (a) Measured resistance versus height for 40 nm CNT vias with and without metallized top contacts. Statistical linear fit yields an average contact resistance RC from Rvia intercept. (b) Mean and standard deviation of measured resistances for each via height with R2 > 0.9 for both data sets………………………………………………………..134

Figure 5.9 SEM images of vias used to estimate average total area of CNTs inside 40 nm via...... 135

Figure 5.10 (a) Resistance versus stress current behaviors for two 40 nm vias with and without EBID-Pt top contacts. Metallization and current stressing improve and stabilize top via contact by making conformal interfaces between metal and exposed CNT tips, resulting in lower via resistance and improved current-carrying capacity compared to unmetallized vias. (b) Resistance versus stress current behavior for three 60 nm vias with and without EBID-Pt top contacts, showing the same trend as 40 nm vias………………138

Figure 5.11 (a) SEM image of 40 nm CNT vias after voltage-sweep test. Different current ranges are used to reveal via current-carrying capacity. Only the device with current compliance of 1 mA remains intact and those with higher compliances break down, confirming the measured current-carrying capacity of 330 MA/cm2. (b) I-V behavior with current capped at 1 mA……………………………………………………………………...140

Figure 6.1(a) Cross-sectional SEM image of a six level interconnect structure in an IC (b) Schematic of a six level all carbon interconnect structure with CNT as vias and graphene as interconnects……………………………………………………………………….………149

Figure 6.2 Process flow for CNT-graphene heterostructure fabrication………………....150

Figure 6.3 Cross-sectional TEM images of CNTs grown on graphene with (a) Fe catalyst and (b) Ni catalyst. Distorted graphene is indicated near the base of the grown CNT in (a), while some graphene is missing at the interface after CNT growth in (b)…………...150

Figure 6.4 (a) Electrical measurement schematic and resistance versus graphene length behavior after CNT growth, where W denotes the width of graphene stripe, RS the sheet resistance, and RC the contact resistivity. (b) Electrical measurement schematic and I-V characteristics of CNT-graphene heterostructure after oxide filling and polishing to expose CNT tips, where Rtotal denotes the total extracted resistance and LCNT the CNT height………………………………………………………………..…………………………151

List of Tables

Table 1.1 Properties of candidate materials for interconnect vias and comparison with Cu and W……………………………………………………………………………………………24

Table 1.2 Summary of current state of horizontal CNT interconnects…………………….25

Table 1.3 Summary of current state of horizontal CNT interconnects…………………….26

Table 2.1 Summary of spn hybridization and corresponding allotropes of carbon……....37

Table 2.2. Steps for CNT growth process…………………………………………………….63

Table 3.1 Normalized contact resistance per surface C atom……………………………....80

Table 3.2 d-orbital vacancies and work functions of various transition and noble metals……………………………………………………………………………………………84

Table 4.1. Summary of via samples prepared for CNT growth…………………………...108

Table 4.2 Electron mean free paths for as-grown CNTs from their Raman data………...118

Table 5.1. Summary of CNT via sample parameters and resistance measurements……127

Table 5.2. Statistics of 40 nm CNT via parameters which contribute to variations in measured via resistance and extracted contact resistance. For diameter and number of CNTs, the data are obtained from SEM images of unfilled and unpolished vias such as those in Fig. 5.7(a), whereas the total CNT area in via is obtained from SEM images of polished samples shown in Fig. 5.7(b). For each parameter, the mean µ, standard deviation σ, and coefficient of variation CV are obtained, showing similarities in variations for ACNT and RC in metallized vias………………………………………………..136

Table 5.3 Comparison of properties of CNT vias studied here and reported by others, and with Cu and W vias of similar dimensions……………….…………………………………141

1 Introduction

This chapter serves as an introduction to this dissertation. First, an overview of advancements in computing technology is given, which resulted from the downward scaling of integrated circuits (ICs). This is followed by a narrative on Moore’s law, which facilitated developments and manufacturing of transistors with smaller geometry, faster switching speeds, lower power consumption, and lower costs for subsequent generations of semiconductor technology nodes. However, shrinking interconnects among transistors on-chip have suffered degradations in both performance and reliability, which in turn limit the IC speed and lifetime. Therefore, to sustain the continuous downward scaling, alternative materials to replace copper (Cu) and tungsten (W) as the interconnect conductor must be explored to meet and overcome these challenges. A brief overview of the state of interconnect technology and potential replacement materials are presented. The chapter concludes with a statement of research and an organizational structure of this dissertation.

Chapter 1

For the past five decades, there have been significant advancements in computers due to an enormous surge in computing power and reduction in computer form factors. This has enabled rapid developments of various computer-based consumer products such as desktops, laptops, tablets, smartphones, navigation systems, smart home appliances, and self-driven cars. Integrated circuit (IC) or chip technology, which allows the manufacture of the entire circuit or system on a monolithic silicon or other semiconductor substrates, is the primary engine driving the form factor reduction. For every generation of products, dimensions of components (transistors and interconnects) on an IC are scaled downwards, enabling increased functionality and data storage per unit area [1]. The signals processed by transistors and their accompanying power are transported between transistors via on-chip interconnect conductors. In current digital circuits, transistors are usually made from silicon and interconnects from copper (Cu) and tungsten (W) [2, 3]. In the early years of chip technology, component dimensions were scaled continuously, resulting in approximately doubling the number of transistors on-chip every year, as observed by Gordon Moore in 1965 [4]. He later revised this empirical trend to doubling the number of transistors on-chip every two years, famously known as Moore’s law [5- 12]. This non-science-based projection has been adopted throughout the IC industry since and its realization was made technologically possible by advancements in photolithography, which allows downscaling of chip components fabricated [8]. As voltage-controlled devices, reducing transistor dimensions results in lower operating voltages, increased switching speeds, and less power consumption, which in turn yield orders of magnitude increase in switching speed or clock frequency of microprocessors from the initial generation of Intel 4004 (750 kHz) [13] to Pentium-IV (3.8 GHz) [14, 15] and now sixth generation Core i7 which has four data processing cores each with clock speed 4.2 GHz, built using Intel’s 14 nm process technology [16]. AMD’s FX processor built using 32 nm silicon-on-insulator (SOI) technology reported clock speed of 5 GHz and overdriven up to 8.6 GHz, which is highest ever for consumer applications [17]. However, downscaling of interconnect dimensions raises the conductor resistance as well as intermetal capacitance, thus hampering chip performance [18]. Further, as interconnect linewidths are reduced, the current density increases, leading to material breakdown along the conducting path and circuit failure. Therefore, alternative interconnect conductors are needed that can withstand aggressive performance and reliability constraints posed by advanced silicon technology. Section 1.1 below presents the impact of downscaling on performance and reliability of existing interconnects and the engineering solutions to meet the challenges. Section 1.2 describes the advantages and 13

Chapter 1 challenges associated with potential materials to replace Cu and W. One promising replacement candidate for next-generation interconnects, carbon nanotube, is introduced in Section 1.3. The organization of this dissertation and specific contributions by collaborators are presented in Section 1.4.

1.1. Moore’s law and its impact on interconnects

As mentioned above, Moore’s law served as the guide to photolithography-driven downward scaling of semiconductor components. Every 24 months, a new IC technology node has been brought to high-volume production. Every new node has components printed on a monolithic silicon substrate with dimensions scaled by ~0.7× the previous node. Components on a chip can be classified into three categories depending on the stage in the manufacturing process. The first is Front-End-Of-Line (FEOL) for transistor fabrication. Then comes the Middle-Of-Line (MOL) which includes contacts to source/drain regions of transistors and first metal level consisting of W interconnects. The final category is the Back-End-Of-Line (BEOL) for the upper levels of Cu metallization [1]. Fig 1.1(a) shows cross-sectional scanning electron microscope (SEM) images of a chip fabricated by Intel using technologies from two recent nodes.

Figure 1.1 Cross-sectional SEM images of chips from Intel’s 20 nm and 14 nm processes, showing downscaling of components by 0.65x [19].

Chapter 1

The IC building block is the metal-oxide-semiconductor field effect transistor (MOSFET), which can be used for both analog and digital applications. For the latter, it functions as a voltage-controlled switch (On/Off) through suitable combinations of gate and source/drain biases. With downscaling of transistor dimensions, features such as gate capacitance are reduced [2, 3, 20]. This allows the transistor to function at a voltage lower than that for the previous node while storing less charge. Lower operating voltage and shorter charge-discharge cycle result in transistors with less power consumption and faster switching speed. Thus, transistor performance is enhanced by downscaling its dimensions [1]. However, leakage current due to reduced gate dielectric thickness and control of gate over channel present challenges. To mitigate such challenges, new device structures such as FinFET and Gate-all-around were introduced [21-24] and are prevalent in advanced technology nodes [25, 26].

A Cu interconnects structure consists of the following components: barrier layer to prevent Cu diffusion into the surrounding dielectric, nucleation layer on the barrier layer to enable metal film growth, and a bulk metal layer [27-30]. As interconnect dimensions are scaled, the thickness and volume of each of the aforementioned layer are reduced. Therefore, as reported by Steinhogl on Cu and W interconnects [31-35], downscaling interconnect dimensions causes electrical resistivity of Cu and W to rise exponentially in the sub-50 nm regime. This is a result of increased electron scattering at metal grain boundaries and at surface/interfaces. A schematic of such scattering phenomena in an interconnect structure is shown in Fig 1.2.

Figure 1.2 Schematic of electron scattering at grain boundaries and surfaces inside a copper trench structure [32].

Chapter 1

Parameters contributing to the total resistance of an interconnect consist of electrical resistivity of conductor filling it, contact resistance, and geometry [36, 37]. With continued downscaling of dimensions, resistivity increases rapidly with decreasing linewidth due to additional electron scattering contributions from conductor’s grain boundaries and surfaces, and contact resistance also increases as the contact area is reduced. The combined result from these effects degrades the interconnect performance through significant increase in resistance. Another factor governing interconnect performance is intermetal capacitance, which depends on geometry and dielectric constant k of the surrounding insulating material. The resistance and capacitance components in an interconnect structure are indicated in the cross-sectional SEM image shown in Fig 1.3.

Conductor

Dielectric

Figure 1.3 Resistance and capacitance components in an interconnect structure [1].

In general, performance of interconnects is measured by the time taken by an electric signal to propagate through the network of lines and vias. This delay in signal propagation is mathematically expressed as τ = RC, where R is resistance and C the capacitance of the entire interconnect system. As downscaling results in increase in R, the resulting increase in delay is compensated by employing a dielectric material with a lower k which then reduces C. Intel’s recent release of 14 nm process technology shows that air gaps have been employed in the dielectric network to further reduce the effective dielectric constant and lower the capacitance [19]. The requirements for effective dielectric constant for subsequent nodes is shown in Fig. 1.4.

Chapter 1

Figure 1.4 Projected effective dielectric constant for interconnect system to manage propagation delay [1].

In 1997, Sun [18] reported a detailed analysis on the effect of scaling on transistor (gate), interconnect, and unit circuit (gate + interconnect) performance, in which two interconnect systems were compared. The projected behaviors of delay versus technology node from (0.65 to 0.09 µm) are shown in Fig. 1.5. With continued downscaling, the performance of the Al/SiO2 system degrades drastically in this node range. On the other hand, the corresponding increase in delay for the Cu/low-k material system is much less, making it a viable substitute for the Al/SiO2 system in sub-100 nm nodes. However, at 180 nm node, even the Cu/low-k system’s delay surpasses that from the gate. In the composite plot for (gate + Cu/low-k) shown in Fig. 1.5, the total delay decreases up to the point where interconnect and gate delays are comparable, beyond which the total delay of the unit begins to increase. Thus, according to Sun’s projection [18], the performance of a circuit is dominated by interconnects in the sub-180 nm regime and the impact is more acute in the sub-30 nm nodes as the surge in interconnect delay continues, due largely to increase in conductor resistance [1]. Therefore, alternative conductor materials are needed to replace Cu and W at sub-30 nm technology nodes to mitigate this resistance increase.

Chapter 1

Figure 1.5 Projected gate, interconnect, and (gate + interconnect) delay for Al and Cu interconnect materials [18, 38]. At 180 nm node and beyond, delay of Cu/low-k interconnect system exceeds gate delay and becomes the primary limiting factor for circuit performance.

Aside from performance, the other critical metric for an interconnect system is its reliability, which is the extent to which the interconnect can maintain charge flow through it without degradation in performance or worse, such as material breakdown. Downscaling of interconnect dimensions at each node results in a reduction of cross- sectional area and the maximum current through it before the conductor breaks down. At the same time, the operating current density J, in A/cm2, in a circuit increases with downscaling [39]. Once the current density approaches the current-carrying capacity for a conductor material, the electric field associated with the moving electrons is sufficiently large to displace the atoms from their lattice sites along the current path. This phenomenon is known as electromigration (EM). If the conductor operates at or near its EM limit continuously, void formations along the current path can result, leading to an open circuit and chip failure. The maximum current IMAX projected for interconnects and the corresponding current density JMAX for future nodes are given in Fig. 1.6 [39], which shows JMAX ≥ 2 MA/cm2. Cu and W exhibit bulk maximum current-carrying capacities of

Chapter 1

2 MA/cm2 and 1 MA/cm2, respectively, and clearly cannot meet such current density requirements [40]. Therefore, materials engineering approaches for extending the electromigration limit are used to enhance the reliability of conventional materials [1].

One such approach is to consider the Blech length (LB) in designing interconnects, defined as the maximum length of conductor at which the internal mechanical stress can offset electromigration [41, 42]. If the (J  conductor length) product is less than the critical product (JC  LB), where JC is the critical current density for EM failure [43], electromigration does not occur. Therefore, lengths of Cu interconnects are designed in such a way that the (JMAX  conductor length) product does not exceed the critical value. The critical product is dependent on thermomechanical properties of the interconnect system. For example, Cu/SiO2 has a higher critical product than Cu/low-k porous film used at advanced nodes to reduce the interconnect capacitance [44]. The critical product for the latter is 2500 A/cm, giving values of LB = 25  8.3 µm for JC = 1  3 MA/cm2 [44]. Further increase in the porosity of dielectric film will reduce the critical product, limit the Blech length, and result in electromigration for current densities operating in the range above 2 MA/cm2 for future nodes, as illustrated in Fig. 1.6. Thus the tradeoff between lowering interconnect capacitance and avoiding EM must be carefully managed. Another approach is adding a capping layer on Cu to prevent mass transport out of the Cu bulk using the adhesive force between Cu and capping layer [45-47].

Chapter 1

Fig. 1.7 shows the properties of materials evaluated as capping layers for Cu. The selection criterion is minimum added resistance to interconnect with an extended lifetime. An analysis of the EM lifetime versus resistance increase behavior is used to identify capping materials that yield higher slope, having enhanced EM lifetime with minimum impact on resistance. The results given in Fig. 1.7 point to CuSiN with Ti as barrier metal (BM) and CoWP as the most suitable materials for capping Cu interconnects [1]. Combining Blech length consideration and capping layer in designing interconnects, the current-carrying capacity of Cu can be extended up to 3 MA/cm2 [1]. Figure 1.6 shows that the interconnect current density requirements are approaching 5 MA/cm2 for the most advanced nodes. Therefore, in order to continue downward scaling trend and meet such JMAX requirements, alternative conductor materials which can match the performance of Cu and W while exceeding the reliability requirements are needed.

Figure 1.7 EM lifetime of various capping materials on Cu versus resulting interconnect resistance increase. Materials with the least resistance change for extended EM lifetime are preferred [1].

1.2. Potential replacement interconnect conductors

With reduced interconnect dimensions at sub-30 nm nodes, the resistivities of Cu and W increase significantly from their respective bulk values of 1.7 µΩ·cm and 11 µΩ·cm due to enhanced electron scattering at conductor surfaces and grain boundaries [31, 32, 35]. Hence, to mitigate the resulting performance degradation, alternative conductors with

Chapter 1 smaller resistivities at such dimensions are needed. One criterion for evaluating potential replacement materials is lesser resistance degradation than Cu and W with downscaling [1]. Another is that high-resistance barrier and seed layers are not required [48], as these layers can reduce the relative Cu volume by as much as 70% as shown in Fig. 1.8, resulting in further performance degradation.

Figure 1.8 Percentage of Cu volume in trench structure versus its half pitch (HP) [49].

The evaluation of potential replacement conductors is being pursued using one of three approaches. Two were described in ITRS 2013 [1] and the third one was patented by Intel in 2012 [50]. In the first approach, materials with smaller electron mean free path than those of Cu and W such as silicides (in particular Ni silicides) have been evaluated extensively. The monosilicide phase, NiSi, has been demonstrated to preserve its bulk resistivity (~10 µΩ·cm) for single crystal nanowires (SCNW) with diameters down to 58 nm, attributable to NiSi having significantly smaller electron mean free path (~5 nm) compared to Cu and W [51]. SCNW using other phases of Ni silicides such as NiSi2 and

Ni2Si exhibited resistivities of 30 µΩ·cm and 21 µΩ·cm, respectively, for diameters down to 40 nm [52] and 34 nm [53], respectively, both preserving their bulk resistivities. Thus, the monosilicide phase seems to have the lowest resistivity for the dimensions of interest. By virtue of their single-crystalline nature, current-carrying capacity of NiSi SCNW is in the range of 100 MA/cm2 [52]. Thus single-crystalline NiSi is a potential candidate as an interconnect material. The experiments reported so far consists of either NiSi thin films or test structures consisting of NiSi nanowires fabricated by annealing of Ni on self- assembled Si nanowires [52]. A process to selectively deposit Ni silicide in an integrated

Chapter 1 interconnect or via structure with the desired phase has yet to be demonstrated but continues to be investigated [1].

The second approach is to evaluate materials having significantly longer electron mean free path than Cu and W. Single-walled and multi-walled CNTs (MWCNTs) are known to exhibit electron mean free paths in the micrometer range. MWCNTs have been studied extensively during the last decade as a potential on-chip interconnect material, pioneered by Graham [54-56] who reported findings on the first 30 nm CNT via. Subsequently, various academic and industrial research groups have focused on different aspects of realizing CNT vias. Nihei [57, 58] focused on developing a process of integrating CNT vias that is compatible with BEOL thermal budget of 400~450°C. Their most recent report demonstrated a CNT via with 70 nm width and aspect ratio of ~1, yielding a resistance of 11 kΩ [59, 60]. Vollebregt [61-68] also focused on lowering the CNT growth temperature to as low as 350°C. However, the feature sizes of interconnects reported were in the 1~3 µm range, much larger than those in advanced technology nodes. Van der Veen [69] characterized CNT vias with 150 nm width and Cu contact integration. Chiodarelli [70- 72] focused on increasing the packing density of CNT in a via by employing an AlCu alloy underlayer, which enhanced Fe catalyst dewetting to increase CNT packing density in a via. This approach resulted in more CNT shells as conducting paths and could potentially yield lower via resistance. However, their low-temperature CNT growth resulted in via resistance in the 10 kΩ range. Growing CNTs at low temperature introduces defects which in turn reduces electron mean free path and increases resistance. Therefore, for BEOL-compatible process CNT via resistance remains significantly higher than its Cu and W counterparts. Nevertheless, CNTs exhibit high mechanical strength in their structure due to sp2 C-C bonding which makes them resistant to electromigration. Current-carrying capacities reported for CNT vias generally range from 100 to 1000 MA/cm2 [73, 74]. Such attractive reliability makes CNT a contender to replace Cu and W, especially in vias, if the CNT via resistance can be reduced to approach its Cu and W counterparts. To achieve better CNT via performance is indeed a daunting challenge, which at the very least requires lowering contact resistance and via resistance by optimizing CNT growth and contact metallization processes.

The third approach to identify suitable materials to replace Cu was first described by Jezewski in a 2012 patent [50] and subsequently reported by van der Veen in 2015 [48]. Cu and W interconnects require barrier and liner layers in the interconnect structure to 22

Chapter 1 provide diffusion barrier and adhesion, respectively. Addition of these resistive layers reduces the total volume available for low-resistivity Cu and W. Therefore, if an alternative conductor can be integrated with the surrounding low-k dielectric without the need for any barrier and liner, it can yield lower via resistance than Cu at sub-20 nm linewidths [48]. Electroless deposited Co in a via structure was demonstrated to possess such characteristics [48]. Fig. 1.9(a) shows the proposed via structure and comparison with Cu and W based on resistance measurements. As shown in Fig. 1.9(b), Co outperforms Cu with barrier for widths below 15 nm. The delay due to barrier-less Co interconnects with airgap is ~67% lower than that from Cu interconnects, and even lower than gate delay at 5 nm node, as shown in Fig 1.9(c), thus underscoring the significant improvements in interconnect technology since the 1997 projection shown in Fig. 1.5.

(a) (b)

Co w/o barrier and liner

(c)

delay (pSec) delay

Figure 1.9 (a) Barrierless and seedless structure for Co interconnect with low-k dielectric [50, 75]. (b) Comparison of Cu, W, and Co resistances for different linewidths [48]. (c) Comparison of delays from various interconnect configurations with gate delay [49].

Chapter 1

Compared to nanocarbons, Co is more compatible with conventional silicon IC processes, as it can be deposited using chemical vapor deposition (CVD) with organometallic or metal-halide precursors [48]. Kim [76] reported a resistivity of 22 µΩ-cm for 10 nm thick CVD Co film using organometallic precursor. The current-carrying capacity of Co is similar to that of Cu (1~2 MA/cm2) [48]. Thus, reliability challenges will remain for Co interconnects in future nodes. Very recently, similar results for Ru interconnects were reported [77]. The properties of candidates to replace Cu and W in interconnect vias are summarized in Table 1.1.

Table 1.1 Properties of candidate materials for interconnect vias and comparison with Cu and W. Dimensions Contact Via Current Interconnect Resistance Resistivity (Width × Resistance Capacity Material (kΩ) (µΩ-cm) Length) (kΩ) (MA/cm2) NiSi nanowire [51, 78] 58 nm × 2.9 µm 0.066 10.8 NA 100 Co [48, 76] 9 nm × 18 nm 0.11 22 NA 1~2 Ru [77] 20 nm × 1 µm 0.200 18 NA 6.5 Ag Nanowire [79] 28 nm × 1.4 µm 1.3 42.7 0.365 10 CNT [54-56] 30 nm × 150 nm 7.8 NA NA 400 Multi-layer graphene [80] 250 nm × 5 µm 3.8 10 1 500 Cu [40] 30 nm × 130 nm 0.024 7 15 2 W [36] 30 nm × 130 nm 0.060 38 5 1

The reported via dimensions, material resistivity, via resistance, contact resistance, and via current-carrying capacity for each material are given in Table 1.1. While the performance and IC process compatibility of Co and Ru as interconnect via materials are superior to what are currently known about CNTs, the incomparably high current capacity of CNT keeps it viable as a leading candidate to replace Cu and W in sub-10 nm technology nodes. Such appealing reliability will continue to drive further research to improve the CNT via performance and to narrow the gap in IC process compatibility.

1.3. State of CNT interconnects

CNT has been extensively studied as a potential replacement interconnect material since the turn of the millennium. Its performance and reliability in both horizontal and vertical configurations have been investigated. In the vertical configuration, integrating an aligned array of CNTs in an on-chip patterned array of vias and growing a CNT bundle at metal contacts have been achieved [81-83]. On the other hand, fashioning horizontal

Chapter 1

CNTs at a pre-defined location on a substrate while controlling the packing density is more challenging [84]. Nonetheless, on-chip CNT FETs and high-density horizontal CNT interconnects were successfully integrated by multiple transfers of pre-grown CNTs onto the final substrate [85]. Recently, an 8-bit CNT FET-based computer was demonstrated using such technique [86], while in most CNT reports on horizontal interconnects, drop- casting CNTs on pre-patterned test-structures was carried out [87-89]. Table 1.2 summarizes the current state of horizontal CNT interconnects.

Table 1.2 Summary of current state of horizontal CNT interconnects

RTotal Electrical Length/ Contact CNT type (DC & LCNT CCNT Measurement Diameter metal RF) kΩ SWCNT [90] 0 - 10 GHz 25 µm/2 nm 150/150 NA NA Cr/Au SWCNT bundle 0 - 50 GHz 5 µm/1.1 nm 0.8/ 0.75 37 pH 27 fF NA [91] MWCNT [92] 0 - 50 GHz 5 µm/25 nm 7.8 /0.28 215 - 0.02 µH 3.5 -0.9 fF Nb MWCNT [93] 0 - 110 GHz 8 µm/18 nm 15 /0.2 18 - 0.1 nH 10 – 0.1 fF Au MWCNT [85] 0 - 15 GHz 5 µm/70 nm 20/3 NA 1.5 fF Au SWCNT [94] 0 - 7 GHz 1 µm/NA 20/13 70 nH 17 fF Au/Pd MWCNT [88, 89] 0 - 50 GHz 2 µm/70 nm 11/8 NA 0.1 fF Pt MWCNT [95] 0 - 24 GHz 5 µm/30 nm 400/1 NA 1.4 fF EBID-C

Table 1.2 presents results for both DC and radio-frequency (RF) measurements, the latter at maximum frequency. The decrease is resistance from DC to RF is attributed to improvement in contact impedance due to its low capacitive component at the CNT- metal interface at high-frequency, which serves as an electrical shunt at the contact. This frequency dependence results in significant variations of interconnect performance at different frequencies. Therefore, it is desirable to improve the contact impedance by depositing a high-purity material at the CNT contacts. Contacts with deposited Pt and W have been shown to reduce the overall impedance of the interconnect structure, with negligible frequency dependence [87-89]. An extensive review of horizontal CNT interconnects and further experiments to improve contacts are given in Chapter 3.

As discussed in Section 1.2, vertically aligned CNTs have been integrated in patterned vias with widths ranging from microns to sub-100 nm. In order to evaluate CNT vias with relevant linewidths and at BEOL-compatible temperatures [61], the experimental focus has been on growing CNTs at temperatures less than 450°C, as indicated in Table 1.3, 25

Chapter 1 which summarizes the results for CNT vias reported. Growth at temperatures below 700°C results in CNTs with high defect densities [62], while good-quality CNTs grown in 30 nm vias at 700°C were demonstrated [54]. Despite such extensive efforts on CNT vias as summarized in Table 1.3, a comprehensive study on performance and reliability of sub-100 nm CNT vias, as well as the role of contacts on both, has not been reported.

Table 1.3 Summary of current state of CNT via interconnects Via W/L (in nm) CNT CNT Areal Via CNT Contact Current growth Density Resistance resistivity resistance Capacity temperature (#/cm2) (kΩ) (mΩ-cm) (kΩ) (MA/cm2) (°C) 30/150 [54-56] 700 1.5 x 1011 7.8 0.15 NA 400 70/80 [59, 60, 96] 450 3 x 1011 11 NA NA 100 300/450 [70-72] 470 2 x 1011 8 3.7 1.16 NA 150/360 [97] 540 ~1011 7 5.1 1.8 NA 1000/1000 [61, 64, 65] 350 1010 0.159 110 NA NA

The objective of this work is to carry out such a study, based on the results and understanding reported by others. The descriptions of experiments and analyses are presented in Chapters 4 through 6. The resulting comparison with Cu and W vias of similar dimensions is intended to lay the groundwork for further improving the performance of CNT vias so that they will remain viable as potential replacements in sub- 10 nm technology nodes.

1.4. Organization of dissertation

This dissertation covers the background, motivation, experiments, results, and analyses of CNT via interconnects, with primary focus on 40 nm × 40 nm vias. It is divided into seven chapters. The first chapter serves as an introduction and provides the background and motivation for this study. Chapter 2 reviews the CNT properties and surveys the growth methods. Chapter 3 presents experiments and analyses of horizontal CNT interconnects. Chapter 4 describes the via fabrication process and subsequent CNT growth in vias, the structural characterizations using electron microscopies and Raman spectroscopy are presented in this chapter. Chapter 5 contains a comprehensive narrative on the electrical performance and reliability of CNT vias. The dissertation is concluded in the final chapter, with recommendations for future work including an all-carbon 3-D interconnect structure.

Chapter 1

This work has been made possible with contributions from many individuals serving in various capacities. Their specific contributions are recognized here. Dr. Changjian Zhou carried out via test structure fabrication at Hong Kong University of Science and Technology (HKUST). Dr. Phillip Wang of Applied Materials performed TEM and EDS analyses, and provided training on EBID-Pt deposition system. Patrick Wilhite at the Center for Nanostructures trained and guided me on the PECVD system, sputterer, nanoprober, and SEM, as well as provided valuable inputs on experiments at various stages. Richie Senegor and Ayodeji Adesida performed analysis on SEM images to measure CNT density and area of CNTs inside the vias. Prof. Mansun Chan provided the resource for via fabrication at the Nano Fabrication Facility at HKUST. Dr. Jessica Koehne assisted with recipe development for electroplating Ni catalyst. With the valuable support and assistance of these individuals, I was able to coordinate the test structure design and fabrication, and carried out CNT growth in vias along with top-contact metallization. In addition, I conducted all electrical measurements, and performed data reduction and analyses to extract the key electrical parameters and correlate them with results from nanostructure characterization. Last but not least, the most important and critical contribution is from Prof. Cary Yang, who defined at the outset the overall scope of this work, as well as initiated and shepherded collaborations with HKUST, Hong Kong Polytechnic University, Tsinghua University, NASA Ames, and Applied Materials, which led to seamless execution of the entire project.

References

[1] International Technology Roadmap for Semiconductors, 2013 edition, available at www.itrs2.net. [2] J. M. Rabaey, A. P. Chandrakasan, and B. Nikoliâc, Digital integrated circuits : a design perspective, 2nd ed. Upper Saddle River, N.J.: Pearson Education, 2003. [3] J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital integrated circuits vol. 2: Prentice hall Englewood Cliffs, 2002. [4] G. Moore, "Cramming More Components Onto Integrated Circuits, Electronics,(38) 8," ed, 1965. [5] G. E. Moore, "Progress in digital integrated electronics," in Electron Devices Meeting, 1975, pp. 11-13, Dec 1975. [6] C. R. Moore and J. E. Penn, "Custom Design of Monolithic Microwave Integrated- Circuits," Johns Hopkins Apl Technical Digest, vol. 14, pp. 300-306, Oct-Dec 1993. [7] G. E. Moore, "A Quarter of a Century of Microelectronics," Microelectronics Journal, vol. 25, pp. R11-R15, Feb 1994.

Chapter 1

[8] G. E. Moore, "Lithography and the future of Moore's law," in SPIE's 1995 Symposium on Microlithography, pp. 2-17, May 1995. [9] G. E. Moore, "Intel - Memories and the microprocessor," Daedalus, vol. 125, pp. 55-80, Apr 1996. [10] G. E. Moore, "The microprocessor: Engine of the technology revolution," Communications of the Acm, vol. 40, pp. 112-114, Feb 1997. [11] T. M. Elliott, E. A. Parrish, T. Hoare, F. J. Corbato, E. Bloch, M. R. Barbacci, J. A. Haddad, D. A. Wheeler, L. V. Kaleda, J. F. Clark, M. Smith, M. V. Wilkes, D. B. Fogel, G. E. Moore, B. O. Evans, R. I. Tanaka, W. H. Ware, O. N. Garcia, and B. Shriver, "The next 50 years of computing," Computer, vol. 30, pp. 16-21, Jan 1997. [12] G. E. Moore, "Cramming more components onto integrated circuits," Proceedings of the IEEE, vol. 86, pp. 82-85, Nov 1998. [13] W. Aspray, "The Intel 4004 microprocessor: What constituted invention?," IEEE Annals of the History of Computing, vol. 19, pp. 4-15, Jul 1997. [14] N. A. Kurd, J. S. Barkatullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, "A multigigahertz clocking scheme for the Pentium (R) 4 microprocessor," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1647-1653, Nov 2001. [15] D. J. Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, M. Morrise, D. Milliron, A. P. Singh, and S. Wijeratne, "Low-voltage swing logic circuits for a pentium (R) 4 processor integer core," Ieee Journal of Solid-State Circuits, vol. 40, pp. 36-43, Jan 2005. [16] E. Fayneh, M. Yuffe, E. Knoll, M. Zelikson, M. Abozaed, Y. Talker, Z. Shmuely, and S. A. Rahme, "4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance," in 2016 IEEE International Solid-State Circuits Conference (ISSCC), pp. 72-73, Jan 2016. [17] B. Hollingsworth, "New “Bulldozer” and “Piledriver” Instructions," Advanced Micro Devices Inc, 2012. [18] S. Sun, "Process technologies for advanced metallization and interconnect systems," in Electron Devices Meeting, 1997. IEDM'97. Technical Digest., International, pp. 765-768, Dec 1997. [19] S. Natarajan, M. Agostinelli, S. Akbar, M. Bost, A. Bowonder, V. Chikarmane, S. Chouksey, A. Dasgupta, K. Fischer, and Q. Fu, "A 14nm logic technology featuring 2 nd- generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm 2 SRAM cell size," in Electron Devices Meeting (IEDM), 2014 IEEE International, pp. 3.7. 1-3.7. 3, Dec 2014. [20] J. M. Rabaey, Low power design essentials. New York ; London: Springer, 2009. [21] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. M. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," Ieee Transactions on Electron Devices, vol. 47, pp. 2320-2325, Dec 2000. [22] N. Lindert, L. L. Chang, Y. K. Choi, E. H. Anderson, W. C. Lee, T. J. King, J. Bokor, and C. M. Hu, "Sub-60-nm quasi-planar FinFETs fabricated using a simplified process," Ieee Electron Device Letters, vol. 22, pp. 487-489, Oct 2001. [23] X. J. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. M. Hu, "Sub-

Chapter 1

50 nm p-channel FinFET," Ieee Transactions on Electron Devices, vol. 48, pp. 880-886, May 2001. [24] D. S. Woo, J. H. Lee, W. Y. Choi, B. Y. Choi, Y. J. Choi, J. D. Lee, and B. G. Park, "Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile," Ieee Transactions on Nanotechnology, vol. 1, pp. 233-237, Dec 2002. [25] Y.-J. Lee, F.-J. Hou, S.-S. Chuang, F.-K. Hsueh, K.-H. Kao, P.-J. Sung, W.-Y. Yuan, J.-Y. Yao, Y.-C. Lu, and K.-L. Lin, "Diamond-shaped Ge and Ge0. 9Si0. 1 gate-all-around nanowire FETs with four {111} facets by dry etch technology," IEEE International Electron Devices Meeting (IEDM), 2015, pp. 15.11. 11-15.11. 14, Dec 2015 [26] N. Waldron, S. Sioncke, J. Franco, L. Nyns, A. Vais, X. Zhou, H. Lin, G. Boccardi, J. Maes, and Q. Xie, "Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200?? S/?? m at 50nm Lg using a replacement Fin RMG flow," IEEE International Electron Devices Meeting (IEDM), 2015, pp. 31.31. 31-31.31. 34, Dec 2015. [27] V. M. Dubin, Y. ShachamDiamand, B. Zhao, P. K. Vasudev, and C. H. Ting, "Selective and blanket electroless copper deposition for ultralarge scale integration," Journal of the Electrochemical Society, vol. 144, pp. 898-908, Mar 1997. [28] S. Kim, D. J. Choi, K. R. Yoon, K. H. Kim, and S. K. Koh, "Characteristics of chemical- vapor-deposited copper on the Cu-seeded TiN substrates," Thin Solid Films, vol. 311, pp. 218-224, Dec 31 1997. [29] K. Ueno, T. Ritzdorf, and S. Grace, "Seed layer dependence of room-temperature recrystallization in electroplated copper films," Journal of Applied Physics, vol. 86, pp. 4930- 4935, Nov 1999. [30] K. Weiss, S. Riedel, S. E. Schulz, M. Schwerd, H. Helneder, H. Wendt, and T. Gessner, "Development of different copper seed layers with respect to the copper electroplating process," Microelectronic Engineering, vol. 50, pp. 433-440, Jan 2000. [31] G. Steinlesberger, M. Engelhardt, G. Schindler, W. Steinhogl, A. von Glasow, K. Mosig, and E. Bertagnolli, "Electrical assessment of copper damascene interconnects down to sub- 50 nm feature sizes," Microelectronic Engineering, vol. 64, pp. 409-416, Oct 2002. [32] W. Steinhogl, G. Schindler, G. Steinlesberger, and M. Engelhardt, "Size-dependent resistivity of metallic wires in the mesoscopic range," Physical Review B, vol. 66, Aug 15 2002. [33] G. Schindler, G. Steinlesberger, M. Engelhardt, and W. Steinhogl, "Electrical characterization of copper interconnects with end-of-roadmap feature sizes," Solid-State Electronics, vol. 47, pp. 1233-1236, Jul 2003. [34] W. Steinhogl, G. Steinlesberger, M. Perrin, G. Scheinbacher, G. Schindler, M. Traving, and M. Engelhardt, "Tungsten interconnects in the nano-scale regime," Microelectronic Engineering, vol. 82, pp. 266-272, Dec 2005. [35] W. Steinhogl, G. Schindler, G. Steinlesberger, M. Traving, and M. Engelhardt, "Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller," Journal of Applied Physics, vol. 97, Jan 2005. [36] C. J. Zhou, A. A. Vyas, P. Wilhite, P. Wang, M. S. Chan, and C. Y. Yang, "Resistance Determination for Sub-100-nm Carbon Nanotube Vias," IEEE Electron Device Letters, vol. 36, pp. 71-73, Jan 2015.

Chapter 1

[37] P. Wilhite, A. A. Vyas, J. Tan, J. Tan, T. Yamada, P. Wang, J. Park, and C. Y. Yang, "Metal- nanocarbon contacts," Semiconductor Science and Technology, vol. 29, May 2014. [38] S. Vollebregt, "Carbon Nanotubes as Vertical Interconnects in 3D Integrated Circuits," Delft University of Technology, PhD thesis, Dec 2014. [39] J. Lienig, "Electromigration and its impact on physical design in future technologies," in Proceedings of the 2013 ACM international symposium on International symposium on physical design, pp. 33-40, Mar 2013/ [40] C. Adelmann, L. G. Wen, A. P. Peter, Y. K. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, and S. Van Elshocht, "Alternative metals for advanced interconnects," in IEEE International Interconnect Technology Conference, May 2014. [41] P. C. Wang and R. G. Filippi, "Electromigration threshold in copper interconnects," Applied Physics Letters, vol. 78, pp. 3598-3600, Jun 2001. [42] E. T. Ogawa, A. J. Bierwag, K. D. Lee, H. Matsuhashi, P. R. Justison, A. N. Ramamurthi, P. S. Ho, V. A. Blaschke, D. Griffiths, A. Nelsen, M. Breen, and R. H. Havemann, "Direct observation of a critical length effect in dual-damascene Cu/oxide interconnects," Applied Physics Letters, vol. 78, pp. 2652-2654, Apr 2001. [43] A. Oates and M. Lin, "The scaling of electromigration lifetimes," in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6B. 2.1-6B. 2.7, Apr 2012. [44] K. D. Lee, E. T. Ogawa, S. Yoon, X. Lu, and P. S. Ho, "Electromigration reliability of dual- damascene Cu/porous methylsilsesquioxane low k interconnects," Applied Physics Letters, vol. 82, pp. 2032-2034, Mar 2003. [45] C. C. Yang, B. Li, D. Edelstein, and R. Rosenberg, "Effects of Metal Capping on Thermal Annealing of Copper Interconnects," Ieee Electron Device Letters, vol. 33, pp. 1051-1053, Jul 2012. [46] J. Hohage, U. Mayer, M. U. Lehr, F. Feustel, O. Aubel, and C. Hennesthal, "Copper- dielectric cap interface with enhanced reliability for 45 nm technology and beyond," Microelectronic Engineering, vol. 87, pp. 2119-2123, Nov 2010. [47] B. Liu, K. W. Xu, Z. X. Song, and T. Bell, "Multilayered metal capping barrier including CuSiN, for sub-65-nm technology nodes," Journal of Applied Physics, vol. 102, Oct 2007. [48] M. H. van der Veen, K. Vandersmissen, D. Dictus, S. Demuynck, R. Liu, X. Bin, P. Nalla, A. Lesniewska, L. Hall, and K. Croes, "Cobalt bottom-up contact and via prefill enabling advanced logic and DRAM technologies," in 2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM), pp. 25-28, May 2015. [49] Z. Tőkei, "End of Cu roadmap and beyond Cu," in 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), pp. 1-58, May 2016. [50] C. J. Jezewski, J. S. Clarke, T. K. Indukuri, F. Gstrein, and D. J. Zierath, "Cobalt based interconnects and methods of fabrication thereof," ed: Google Patents, Dec 2012. [51] J. Kim and W. A. Anderson, "Direct electrical measurement of the self-assembled nickel silicide nanowire," Nano Letters, vol. 6, pp. 1356-1359, Jul 2006. [52] C. Y. Lee, M. P. Lu, K. F. Liao, W. F. Lee, C. T. Huang, S. Y. Chen, and L. J. Chen, "Free- Standing Single-Crystal NiSi2 Nanowires with Excellent Electrical Transport and Field Emission Properties," Journal of Physical Chemistry C, vol. 113, pp. 2286-2289, Feb 2009.

Chapter 1

[53] C. Y. Lee, M. P. Lu, K. F. Liao, W. W. Wu, and L. J. Chen, "Vertically well-aligned epitaxial Ni(31)Si(12) nanowire arrays with excellent field emission properties," Applied Physics Letters, vol. 93, Sep 2008. [54] A. P. Graham, G. S. Duesberg, W. Hoenlein, F. Kreupl, M. Liebau, R. Martin, B. Rajasekharan, W. Pamler, R. Seidel, W. Steinhoegl, and E. Unger, "How do carbon nanotubes fit into the semiconductor roadmap?," Applied Physics a-Materials Science & Processing, vol. 80, pp. 1141-1151, Mar 2005. [55] A. P. Graham, G. S. Duesberg, R. Seidel, M. Liebau, E. Unger, F. Kreupl, and W. Honlein, "Towards the integration of carbon nanotubes in microelectronics," Diamond and Related Materials, vol. 13, pp. 1296-1300, Apr-Aug 2004. [56] A. P. Graham, G. S. Duesberg, R. V. Seidel, M. Liebau, E. Unger, W. Pamler, F. Kreupl, and W. Hoenlein, "Carbon nanotubes for microelectronics?," Small, vol. 1, pp. 382-390, Apr 2005. [57] M. Nihei, A. Kawabata, D. Kondo, M. Horibe, S. Sato, and Y. Awano, "Electrical properties of carbon nanotube bundles for future via interconnects," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, vol. 44, pp. 1626-1628, Apr 2005. [58] M. Nihei, A. Kawabata, and Y. Awano, "Direct diameter-controlled growth of multiwall carbon nanotubes on nickel-silicide layer," Japanese Journal of Applied Physics Part 2-Letters & Express Letters, vol. 42, pp. L721-L723, Jun 2003. [59] M. Katagiri, Y. Yamazaki, N. Sakuma, M. Suzuki, T. Sakai, M. Wada, N. Nakamura, N. Matsunaga, S. Sato, and M. Nihei, "Fabrication of 70-nm-diameter carbon nanotube via interconnects by remote plasma-enhanced chemical vapor deposition and their electrical properties," Interconnect Technology Conference, IEEE International, pp. 44-46, May 2009 [60] M. Katagiri, M. Wada, B. Ito, Y. Yamazaki, M. Suzuki, M. Kitamura, T. Saito, A. Isobayashi, A. Sakata, N. Sakuma, A. Kajita, and T. Sakai, "Fabrication and Characterization of Planarized Carbon Nanotube Via Interconnects," Japanese Journal of Applied Physics, vol. 51, May 2012. [61] S. Vollebregt, F. D. Tichelaar, H. Schellevis, C. I. M. Beenakker, and R. Ishihara, "Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 degrees C," Carbon, vol. 71, pp. 249-256, May 2014. [62] S. Vollebregt, R. Ishihara, F. D. Tichelaar, Y. Hou, and C. I. M. Beenakker, "Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers," Carbon, vol. 50, pp. 3542-3554, Aug 2012. [63] S. Vollebregt, J. Derakhshandeh, R. Ishihara, M. Y. Wu, and C. I. M. Beenakker, "Growth of High-Density Self-Aligned Carbon Nanotubes and Nanofibers Using Palladium Catalyst," Journal of Electronic Materials, vol. 39, pp. 371-375, Apr 2010. [64] S. Vollebregt, A. N. Chiaramonti, J. van der Cingel, K. Beenakker, and R. Ishihara, "Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits," Japanese Journal of Applied Physics, vol. 52, Apr 2013. [65] S. Vollebregt, A. N. Chiaramonti, R. Ishihara, H. Schellevis, and K. Beenakker, "Contact resistance of low-temperature carbon nanotube vertical interconnects," in Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on, pp. 1-5, Aug 2012

Chapter 1

[66] S. Vollebregt, S. Banerjee, A. N. Chiaramonti, F. D. Tichelaar, K. Beenakker, and R. Ishihara, "Dominant thermal boundary resistance in multi-walled carbon nanotube bundles fabricated at low temperature," Journal of Applied Physics, vol. 116, Jul 2014. [67] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Size-Dependent Effects on the Temperature Coefficient of Resistance of Carbon Nanotube Vias," IEEE Transactions on Electron Devices, vol. 60, pp. 4085-4089, Dec 2013. [68] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Thermal conductivity of low temperature grown vertical carbon nanotube bundles measured using the three-omega method," Applied Physics Letters, vol. 102, May 2013. [69] M. H. van der Veen, Y. Barbarin, Y. Kashiwagi, and Z. Tokei, "Electron mean-free path for CNT in vertical interconnects approaches Cu," in Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2014 IEEE International, pp. 181- 184, May 2014. [70] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, p. 085302, Feb 2011. [71] N. Chiodarelli, Y. L. Li, D. J. Cott, S. Mertens, N. Peys, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration and electrical characterization of carbon nanotube via interconnects," Microelectronic Engineering, vol. 88, pp. 837-843, May 2011. [72] N. Chiodarelli, K. Kellens, D. J. Cott, N. Peys, K. Arstila, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration of Vertical Carbon Nanotube Bundles for Interconnects," Journal of the Electrochemical Society, vol. 157, pp. K211-K217, Oct 2010. [73] Y. Nakayama, A. Nagataki, O. Suekane, X. Y. Cai, and S. Akita, "Current-induced plastic deformation of double-walled carbon nanotubes," Japanese Journal of Applied Physics Part 2-Letters & Express Letters, vol. 44, pp. L720-L722, May 2005. [74] M. Sato, T. Hyakushima, A. Kawabata, T. Nozue, S. Sato, M. Nihei, and Y. Awano, "High- Current Reliability of Carbon Nanotube Via Interconnects," Japanese Journal of Applied Physics, vol. 49, 2010. [75] D. X. Ye, S. Pimanpang, C. Jezewski, F. Tang, J. J. Senkevich, G. C. Wang, and T. M. Lu, "Low temperature chemical vapor deposition of Co thin films from Co-2(CO)(8)," Thin Solid Films, vol. 485, pp. 95-100, Aug 2005. [76] M. Kim, S. Whang, Y. Lee, J. Han, J. Choi, B. Lee, D. Sheen, S. Pyi, and J. Kim, "CVD-cobalt for low resistance word line electrode of 3D NAND flash memory," in 2011 IEEE International Interconnect Technology Conference, pp. 1-3, May 2011. [77] X. Zhang, H. Huang, R. Patlolla, W. Wang, F. W. Mont, J. Li, C.-K. Hu, E. G. Liniger, P. S. McLaughlin, and C. Labelle, "Ruthenium interconnect resistivity and reliability at 48 nm pitch," in 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), pp. 31-33, May 2016. [78] Y. Wu, J. Xiang, C. Yang, W. Lu, and C. M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures," Nature, vol. 430, pp. 61-65, Jul 2004. [79] X. H. Liu, J. Zhu, C. H. Jin, L. M. Peng, D. M. Tang, and H. M. Cheng, "In situ electrical measurements of polytypic silver nanowires," Nanotechnology, vol. 19, Feb 2008.

Chapter 1

[80] T. Yu, C.-W. Liang, C. Kim, E.-S. Song, and B. Yu, "Three-dimensional stacked multilayer graphene interconnects," IEEE Electron Device Letters, vol. 32, pp. 1110-1112, Aug 2011. [81] X. Z. Wang, Y. Zhang, M. S. Haque, K. B. K. Teo, M. Mann, H. E. Unalan, P. A. Warburton, F. Udrea, and W. I. Milne, "Deposition of Carbon Nanotubes on CMOS," IEEE Transactions on Nanotechnology, vol. 11, pp. 215-219, Mar 2012. [82] Y. Zhou, J. L. Johnson, A. Ural, and H. K. Xie, "Localized Growth of Carbon Nanotubes on CMOS Substrate at Room Temperature Using Maskless Post-CMOS Processing," Ieee Transactions on Nanotechnology, vol. 11, pp. 16-20, Jan 2012. [83] L. Ding, S. B. Liang, T. Pei, Z. Y. Zhang, S. Wang, W. W. Zhou, J. Liu, and L. M. Peng, "Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4V," Applied Physics Letters, vol. 100, Jun 2012. [84] N. Patil, A. Lin, E. R. Myers, K. Ryu, A. Badmaev, C. W. Zhou, H. S. P. Wong, and S. Mitra, "Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes," Ieee Transactions on Nanotechnology, vol. 8, pp. 498-504, Jul 2009. [85] G. F. Close, S. Yasuda, B. Paul, S. Fujita, and H. S. P. Wong, "A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors," Nano Letters, vol. 8, pp. 706- 709, Feb 2008. [86] M. M. Shulaker, G. Hills, N. Patil, H. Wei, H.-Y. Chen, H.-S. P. Wong, and S. Mitra, "Carbon nanotube computer," Nature, vol. 501, pp. 526-530, May 2013. [87] A. A. Vyas, F. Madriz, N. Kanzaki, P. Wilhite, X. H. Sun, T. Yamada, and C. Y. Yang, "Carbon Nanofiber Interconnect RF Characteristics Improvement with Deposited Tungsten Contacts," Journal of Nanoscience and Nanotechnology, vol. 14, pp. 2683-2686, Mar 2014. [88] F. R. Madriz, T. Yamada, X. H. Sun, J. G. Nickel, and C. Y. Yang, "Frequency-Independent RC Circuit Model for One-Dimensional Carbon Nanostructures," Ieee Electron Device Letters, vol. 31, pp. 263-265, Apr 2010. [89] F. R. Madriz, J. R. Jameson, S. Krishnan, X. H. Sun, and C. Y. Yang, "Circuit Modeling of High-Frequency Electrical Conduction in Carbon Nanofibers," IEEE Transactions on Electron Devices, vol. 56, pp. 1557-1561, Aug 2009. [90] Z. Yu and P. J. Burke, "Microwave transport in metallic single-walled carbon nanotubes," Nano Letters, vol. 5, pp. 1403-1406, Jul 2005. [91] J. J. Plombon, K. P. O'Brien, F. Gstrein, V. M. Dubin, and Y. Jiao, "High-frequency electrical properties of individual and bundled carbon nanotubes," Applied Physics Letters, vol. 90, Feb 2007. [92] S. C. Jun, J. H. Choi, S. N. Cha, C. W. Baik, S. Lee, H. J. Kim, J. Hone, and J. M. Kim, "Radio- frequency transmission characteristics of a multi-walled carbon nanotube," Nanotechnology, vol. 18, Jun 2007. [93] S. C. Jun, X. M. H. Huang, S. Moon, H. J. Kim, J. Hone, Y. W. Jin, and J. M. Kim, "Passive electrical properties of multi-walled carbon nanotubes up to 0.1 THz," New Journal of Physics, vol. 9, Aug 2007. [94] L. Nougaret, G. Dambrine, S. Lepilliet, H. Happy, N. Chimot, V. Derycke, and J. P. Bourgoin, "Gigahertz characterization of a single carbon nanotube," Applied Physics Letters, vol. 96, Jan 2010.

Chapter 1

[95] P. Rice, T. M. Wallis, S. E. Russek, and P. Kabos, "Broadband electrical characterization of multiwalled carbon nanotubes and contacts," Nano Letters, vol. 7, pp. 1086-1090, Apr 2007. [96] M. Katagiri, Y. Yamazaki, M. Wada, M. Kitamura, N. Sakuma, M. Suzuki, S. Sato, M. Nihei, A. Kajita, T. Sakai, and Y. Awano, "Improvement in Electrical Properties of Carbon Nanotube Via Interconnects," Japanese Journal of Applied Physics, vol. 50, May 2011. [97] M. H. van der Veen, B. Vereecke, C. Huyghebaert, D. J. Cott, M. Sugiura, Y. Kashiwagi, L. Teugels, R. Caluwaerts, N. Chiodarelli, P. M. Vereecken, G. P. Beyer, M. M. Heyns, S. De Gendt, and Z. Tokei, "Electrical characterization of CNT contacts with Cu Damascene top contact," Microelectronic Engineering, vol. 106, pp. 106-111, Jun 2013.

Properties and Growth of Carbon Nanotubes

An overview of the structure and properties of CNT and its growth methods are presented. We start with a description of types of carbon bonds and the resulting allotropes, followed by a narrative on graphene and CNT crystal structures, and their respective relationships with electrical properties. The one-dimensional nature of a metallic CNT allows it to act as a quantum resistor and exhibits near-ballistic electron transport over a longer mean free path than conventional metals. However, interfacing CNT with a conventional metal generally results in high contact resistance compared to that across metal-metal interface. The chapter concludes with a discussion on methods to grow CNTs on various substrates, with focus on the method used in this work.

Chapter 2

2.1. Carbon electronic structure

Carbon is the sixth element in the periodic table, in group IV-A. It has four electrons in its outermost shell and its electronic configuration in ground state is 1s22s22p2. Its electronic energy diagram and valence orbitals are shown in Fig. 2.1. The energy difference between 2s and 2p orbitals is negligible compared to the ionization energy of carbon atom, allowing wave functions of s and p orbitals to mix with each other, generally known as spn orbital hybridization. In spn hybridization, (n + 1) covalent bonds are responsible for the local structure which results in various allotropes of carbon, as illustrated in Fig. 2.1 for sp, sp2, and sp3.

(a) (b)

(c)

Energy (d)

Atomic nucleus

Figure 2.1(a) Electronic energy levels (not to scale) of carbon atom. Inset shows electronic states where arrows represent the direction of electron spin [1-3]. (b) sp-hybridized bonding in carbyne [4]. (c) sp2-hybridized bonding in graphene [5]. (d) sp3-hybridized bonding in diamond [6].

In bonding with other carbon atoms, the four valence electrons in each atom form

hybridized orbitals among 2s, 2px, 2py, and 2pz, resulting in four equal-energy covalent

Chapter 2 bonds. In spn hybridization, n+1 electrons participate in forming covalent bonds and remaining electrons (if any) exist as lone pairs. In sp hybridization, each carbon atom forms covalent bonds (σ) with two carbon atoms resulting in a linear structure and two electrons exist as a lone pair, e.g., carbyne in Fig 2.1(b). In sp2 hybridization, each carbon atom forms covalent bonds with three neighboring atoms resulting in a planar structure, e.g., graphene and graphite. A weak bond (π) among neighboring atoms exists for electrons in 2pz orbitals as shown in Fig 2.1(c).

In sp3 hybridization, each carbon atoms covalently bonds with three carbon atoms resulting in a tetrahedral structure, e.g., diamond, as shown in Fig 2.1(d). In this case, all four valence electrons participate in bonding and no lone pair exists. Table 2.1 summarizes the three types of carbon hybridization.

Table 2.1 Summary of spn hybridization and corresponding allotropes of carbon.

Hybridization Geometry Schematic of C-C Corresponding allotrope bond structure of carbon

sp Linear Carbyne

Graphene, Graphite, sp2 Planar trigonal Carbon nanotube

sp3 Tetrahedral Diamond

Chapter 2

2.2. Graphene

Structure of graphene consists of sp2 hybridized C-C atoms in a planar honeycomb lattice. The graphene lattice and its unit lattice vectors, together with atomic spacing and a TEM image are shown in Fig. 2.2. The honeycomb lattice is not a Bravais lattice, but can be defined by a triangular Bravais lattice with a two-atom basis, with its unit cell indicated in green in Fig. 2.2(a).

(a)

(b)

Figure 2.2. The two-dimensional lattice of graphene has a trigonal diatomic unit cell (light green), defined by the unit lattice vectors a1 and a2 with |a1| = |a2| = a = √3dCC and ∠ (a1, a2) = 60°. Nearest neighbor distance dCC = 1.42 Å as in graphite. Spacings dC1, dC2, and dC3 are introduced for convenience. Ahex is the area of a hexagon (light blue), which equals to that of unit cell, and dC1 + 2dC2 = 2dCC is the distance between opposite vertices [7]. (b) Top-view HRTEM image of a monolayer of graphene [8].

Chapter 2

Graphene can exist as a monolayer or multi-layer graphene (MLG). Energy band structure for either configuration can be computed based on the graphene lattice shown in Fig. 2.2(a). The graphene lattice can be constructed from a trigonal unit cell defined by vectors a1 and a2 expressed in unit vectors in x- and y-directions.

a1 = a/2 (√3, 1) (2.1) a2 = a/2 (√3, -1) (2.2)

The unit lattice vector length a is given in terms of the nearest neighbor distance dCC = 1.42 Å by

a = |a1| = |a2| = √3dcc = 2.46 Å. (2.3)

2 The unit cell area is given by|a1 x a2|= a √3/2 = Ahex. The symmetry of the graphene lattice results in a triangular reciprocal lattice, with unit reciprocal lattice vectors defined by b1·a1 = b2·a2 = 2π and b1·a2 = b2·a1 = 0.

b1 = 2π/a (1/√3, 1) (2.4) b2 = 2π/a (1/√3, -1) (2.5)

The reciprocal space unit cell area is given by |b1 x b2|= 8π2/(a2√3) = area of hexagonal first Brillouin zone (BZ). The corners of the BZ shown in Fig. 2.3(a) are given by

4휋 휋 휋 K = (sin (푖 ) , cos(푖 )), where i = 1, 3, 5, and 3푎 3 3 4휋 휋 휋 K’ = (sin (푖 ) , cos(푖 )), where i = 2, 4, 6. (2.6) 3푎 3 3

K and K’ are inequivalent. A simple tight-binding band structure calculation for monolayer graphene results in the following energy dispersion relations for valance and conduction bands [3].

√3 푘푥푎 푘푦푎 푘푦푎 E(kx, ky) = ±γ0 [1 + 4cos ( ) cos ( ) + 4cos2 ( )] 1/2 (2.7) 2 2 2

kx and ky are the wave vector components in reciprocal space and γo (in eV) denotes the nearest-neighbor overlap integral.

Chapter 2

Using tight-binding approach and taking into account both nearest and next-nearest neighbors, the energy dispersion relations become [9]

E±(k) = ± t√3 + 푓(퐤)– t’푓(k) , (2.8)

√3푘 푎 3푘 푎 where 푓(퐤) = 2cos (√3푘 푎) + 4cos ( 푦 ) cos ( 푥 ) . (2.9) 푦 2 2 t (~2.8 eV) is the nearest-neighbor hopping energy and t’ (~0.1 eV) the next-nearest- neighbor hopping energy [9]. The energy bands are symmetric around zero energy if t’=0. For finite values of t’, electron-hole symmetry is broken causing valence and conduction bands to become asymmetric. The full energy band structure of a graphene monolayer is given in Fig. 2.3(a), showing the valence and conduction bands. For a material to be classified as conductor, electrons must populate the conduction band. In graphene, the valence and conduction bands meet at K and K’ points, which allow electrons to easily populate the conduction band at finite temperatures and participate in conduction. The point in reciprocal lattice where valence and conduction bands meet is called Dirac point. In graphene, it happens to coincide with a K or K’ point. As there is no bandgap between conduction and valence bands, monolayer graphene is considered a zero-bandgap material [9].

Conduction band

Valence band

Figure 2.3 (a) Complete energy band structure of monolayer graphene obtained using tight- binding approach [9, 10]. The hexagonal first BZ is also shown. (b) E(k) behavior along MΓKM direction with inset zoomed in around K [11].

Chapter 2

The tight-binding approach can be extended to bi-layer and multi-layer graphene as well

[9]. Using the nearest-neighbor overlap integral values for γo from graphite, the band structure for bi-layer graphene can be obtained. For bi-layer graphene, the stacking of the two layers can be either symmetric (Bernal stacking) or asymmetric (Turbostratic) as show in Fig 2.4 (a) and (b), respectively. In Bernal stacking, the top and bottom layers are displaced along a nearest-neighbor direction by dCC, with half of the atoms aligned in the z-direction.

(d)

Conduction band Conduction band

Valence band Valence band

Figure 2.4 (a) Bernal stacking or symmetric bi-layer graphene. AB stacked, bi-layer graphene refers to the stacking of the B site (denoted by blue ring) in the top layer n2 directly above the A site (denoted by orange ring) in the bottom layer n1. Interplanar distance d1=3.37 Å [12]. (b) Turbostratic stacking or asymmetric bi-layer graphene. Interplanar distance d1=3.44 Å [12]. (c) Band structure of metallic symmetric bi-layer graphene along a K to Γ direction. (d) Band structure of semiconducting asymmetric bi-layer graphene along a K to Γ direction [9, 13, 14].

Chapter 2

The next-neighbor hopping model can be used in the case of Bernal stacking, resulting in overlapping conduction and valence bands as shown in Fig. 2.4(c). On the other hand, Turbostratic stacking results in a bandgap between conduction and valence bands as shown in Fig. 2.4(d). Therefore, depending on the orientation between graphene layers, bandgap of graphene can be tuned. This approach can be extended to MLG [9]. The band structure of MLG has been determined using angle-resolved photoemission spectroscopy [15]. Based on the energy band structure of graphene, the electronic structure and properties of CNT in various configurations can be derived.

2.3. Carbon nanotube

CNT structure can be broadly classified into two types, SWCNT and MWCNT. SWCNT can be further classified into metallic and semiconducting depending on its atomic configuration. MWCNT can appear as concentric multi-walled CNT with hollow interior and stacked-cup CNT or carbon nanofiber (CNF). Fig. 2.5(a) shows the first experimental evidence of MWCNT with 50 nm diameter reported by Radushkevich and Lukyanovich in 1952 [16]. In 1991, Iijima reported TEM images of SWCNT and MWCNT as shown in Fig. 2.5(b) and (c), respectively [17-21]. It was followed by development of batch processing methods to grow CNTs and investigating CNTs for potential applications [22- 32]. In 1998, IBM reported the first FET by employing semiconducting CNT as channel material [33]. Additional TEM images of SWCNTs and MWCNTs are shown in Fig. 2.5(d)-(g) [36-40].

The images shown in Fig 2.5 strongly suggest that a SWCNT consists of a single shell of carbon atoms formed by rolling up a graphene sheet into a cylinder, and that MWCNT is made up of concentric shells of graphene. The direction of such rolling, known as chirality, determines the CNT properties. Identification of SWCNT’s chirality has been carried out using optical absorption spectroscopy [34]. The orientation and atomic arrangements of a single CNT shell can be specified using three vectors: chiral vector Ch, translational vector T, and symmetry vector R, as shown schematically in Fig. 2.6(a). The first two of these vectors, used in specifying CNT unit cells in real and reciprocal spaces, are briefly described in the ensuing sub-sections and in Section 2.4, while a detailed treatment of the third can be found in [3].

Chapter 2

(a) (b) (c) (d) (e)

50 nm

≈

10 nm 10 nm

(f) (g)

6 nm 4 nm

Figure 2.5 (a) First reported electron microscope image of 50 nm diameter CNT [16]. (b) TEM image of SWCNT [35]. (c) TEM image of MWCNT [19]. (d) TEM image of a bundle of SWCNTs [36]. (e) TEM image of an isolated SWCNT grown using laser ablation [37, 38]. (f) TEM image of commercially available MWCNT [39]. (g) TEM image of MWCNT produced with arc-discharge [40].

2.3.1. Chiral vector (Ch)

The chiral vector Ch is the vector along which the graphene sheet is rolled into a cylinder to form a CNT shell, superimposing both ends of Ch in the process. In the planar honeycomb lattice of graphene shown in Fig. 2.6(a), OA is a chiral vector, with Ch=(4, 2), while OB is parallel to the CNT axis. The chiral vector can be expressed in terms of the 2D unit lattice vectors defined in Eqs. (2.1) and (2.2).

Ch = na1 + ma2, where n, m are integers with 0 ≤ |m|≤ n. (2.10)

Chapter 2

Various chiral vectors (n, m) are shown in Fig. 2.6(b) and some CNT structures resulting from them are given in Fig. 2.6(d). The rolling of graphene sheet for one specific case, the so-called armchair configuration, with Ch=(n, n) and n>0, is given in Fig. 2(c). Another case, the zig-zag configuration, corresponds to m=0 and n>0.

Chiral vector can be used to calculate SWCNT diameter, DCNT.

DCNT = L/π, (2.11) where L is the CNT circumference given by

2 2 L = |Ch|= a√(n + m + nm) . (2.12)

(a) (b) (c)

(d)

(n, n) (n, 0) (n, m)

The graphene lattice constant a is given by Eq. (2.3) and the following dot products are used in obtaining Eq. (2.12).

Chapter 2

a1•a1 = a2•a2 = a2 a1•a2 = a2/2 (2.13)

Note that in CNT, the C-C bond length or nearest-neighbor distance is 1.44 Å [3], slightly larger than that in graphite, resulting in a=2.49 Å. Thus the (4,2) CNT circumference is

13.18 Å. The chiral angle θ, defined and labeled as the angle between vectors Ch and a1 in Fig. 2.6(a), has values in the range 0 ≤ |θ|≤ 30. The chiral angle also denotes the tilt of hexagons in the graphene lattice with respect to the axis of nanotube.

푪풉 .풂ퟏ 2푛+푚 푐표푠 휃 = = 2 2 (2.14) |푪풉||풂ퟏ| 2√(n +m +nm)

In particular, zigzag and armchair nanotubes correspond to θ = 0’ and θ = 30°, respectively.

2.3.2. Translational vector (T)

The translational vector T is defined as the unit lattice vector of carbon nanotube, along the nanotube axis and normal to the chiral vector, as illustrated in Fig. 2.6(a). It can be expressed as

T = t1a1 + t2a2, (2.15)

where t1 and t2 are integers and do not have common divisors except unity. Since Ch and

T are perpendicular to each other, or Ch•T = 0, t1 and t2 are obtained as

2푚+푛 2푛+푚 t1 = , t2 = − , (2.16) 𝑔 𝑔

where g is the highest common divisor of (2m + n) and (2n + m). For Ch=(4, 2) in Fig. 2.6(a), g=2 and T=(4, -5). From Eqs. (2.13), (2.15), and (2.16), the magnitude of T is obtained.

T = |T| = √3 L/g (2.17)

= 11.41Å for Ch = (4,2)

Chapter 2

The unit cell of carbon nanotube is the rectangle OAB'B in Fig. 2.6(a), defined by the vectors Ch and T, while the unit lattice vectors a1 and a2 define the unit cell of 2D graphene. Thus, the CNT 2D lattice is rectangular. Dividing the area of the nanotube unit cell, given by |Ch x T|, by the area of the graphene unit cell, |a1 x a2|, yields the number of hexagons per unit nanotube cell, N.

2 2 2 |푪풉 × 푻| 2(푚 +푛 +푚푛) 2퐿 푁 = = = 2 (2.18) |풂ퟏ × 풂ퟐ| 𝑔 𝑔푎

= 28 for Ch = (4, 2)

Since each hexagon contains 2 carbon atoms, there are 2N carbon atoms in each unit cell of a SWCNT. It is interesting to note that despite its inherent 3D geometry, each cylindrical CNT shell is considered to be a 1D system in the axial direction.

The preceding discussion assume a perfect crystallinity for CNT. As in any crystal, CNT contains defects [42-44], and it is critical to understand the types of defects in CNT as they affect its electrical and mechanical properties. Point defects in CNT can manifest themselves as pentagonal and heptagonal distortions of the hexagonal network. Structural defects comprise of caps, bends, branches, and helical structures. In general, MWCNTs are relatively more prone to defects as multiple shells are present in each nanotube. In particular, instead of concentric cylindrical shells, cup-shaped structures (known as carbon nanofiber) are frequently observed and can be considered a defective form of MWCNT [10]. In all cases, defects invariably lead to reduction of carrier mean free path and degradation of electrical and thermal conduction.

2.4. Electronic structure of CNT

This section covers the electronic structure and electrical properties of SWCNT. The electrical properties of MWCNT depend largely on those of metallic walls within it, as it is essentially a set of parallel conductors. The SWCNT electronic structure, similar to its atomic structure, can be derived from that of graphene by neglecting the cylindrical curvature of CNT wall. The 2D reciprocal space unit vectors K1 and K2 for SWCNT can be obtained from the real space unit vectors as follows.

Ch.K1 = T.K2 = 2π (2.19)

Chapter 2

Ch.K2 = T.K1 = 0 (2.20)

Thus, K1 is parallel to Ch and K2 is parallel to T, and the CNT reciprocal lattice is also rectangular. K1 and K2 can be expressed in terms of reciprocal space unit vectors for graphene as follows [45].

K1 = - (t2b1-t1b2)/N (2.21)

K2 = (mb1 – nb2)/N (2.22)

5 1 1 −1 For Ch = (4, 2) in Fig. 2.6(a), K1 = ( , ) and K2 = ( , ), expressed in terms of b1, b2. 28 7 14 7

The magnitudes of K1 and K2 are given by

K1 = |K1| = 2/DCNT (2.23)

K2 = |K2| = 2π/T. (2.24)

While the 2D unit cell of CNT is rectangular, rolling it into a cylinder in the chiral direction (same as K1) results in quantization of projections of wave vectors along this direction imposed by periodic boundary condition. Thus,

Ch•k = 2πµ (2.25) where µ = 1, 2,…, N, and N is the number of hexagons in the 2D CNT unit cell, given by

Eq. (2.18). The translation vector T is parallel to K2, and the wave vectors along this direction is continuous for an infinitely long CNT. The first BZ of a CNT is a line segment with length K2=2π/T within the reciprocal lattice unit cell defined by K1 and K2. The N parallel segments make up a set of equidistant “cutting lines” with pitch K1 along the K1 direction, as shown in Fig. 2.7(a). Thus CNT can indeed be considered a 1D material in only the axial direction. One can then project the cutting lines onto the reciprocal lattice of graphene to derive the 1D CNT band structure (E versus k, with k=(-π/T, π/T)) from that of graphene, using a scheme known as zone-folding (ZF) [3]. The number of cutting lines for (4, 2) CNT is N=28. This set of parallel equidistant lines is called a fully K1-extended representation [45], as indicated by the bordering rectangle in Fig. 2.7(a), which has an area equal to that of the first BZ of graphene [45]. Therefore, the cutting lines can be shifted along K1 and K2 directions in the graphene reciprocal space to cover completely

Chapter 2 the first BZ (hexagon) of graphene [45], as shown in Fig. 2.7(b), which is the fully reduced representation of the cutting lines for (4, 2) CNT.

(a) (b)

Figure 2.7 Reciprocal space of the graphene layer. (a) Parallel equidistant lines give the fully K1- extended representation of the 28 cutting lines for (4, 2) CNT. K1, K2 indicate the reciprocal lattice unit vectors of CNT. A K2 line is 1D BZ of CNT. The rectangle bordered by dashed line has an area equal to that of graphene BZ. (b) The fully reduced representation of the cutting lines for the same CNT, which fills the area of graphene BZ [45].

The electronic structure of SWCNT can be derived from graphene using the ZF approximation [45], in which the 1D energy sub-bands of CNT are constructed by “cutting” into the 2D graphene bands in its BZ with the set of cutting lines. An example of ZF for an armchair and zigzag CNT is shown in Fig. 2.8. The number of cutting lines for an armchair (5,5) CNT is N=10. This set of parallel equidistant lines is projected onto the 2D BZ of graphene as shown in Fig. 2.8(c) and the corresponding energy band obtained from each cutting line is shown in Fig. 2.8(a). The quantized purple line crosses the Fermi level at K and K’ points of the graphene BZ, thus resulting in metallic behavior for CNT, since the valence and conduction bands of graphene intersect at these points (see Fig. 2.3).

For a zigzag (9,0) CNT, the number of cutting lines is N=18. The projections of these parallel lines onto graphene BZ are shown in Fig. 2.8(d) and the resulting CNT band structure has a zero bandgap, as shown in Fig. 2.8(b). The ZF method thus provides a good approximation of obtaining electronic band structure of CNT from graphene for CNTs having large diameter as curvature effects can be neglected. For CNTs with diameter < 1.5 nm [10], the curvature effects cannot be neglected as it causes K points to move away from corners of hexagon to red dots shown in Fig. 2.8(e). For armchair (5, 5) CNT, a cutting line intersect K and K’ points as shown in Fig. 2.8(e, left) and it still exhibits metallic behavior even if curvature effect is taken into account. However, for zigzag (9,

Chapter 2

0) CNT, the cutting lines miss the K and K’ points, making it a narrow bandgap semiconductor, as shown in Fig. 2.8(e, right). Fig. 2.8(f) shows an example of a semiconducting zigzag (8, 0) CNT with a bandgap due to curvature effect.

b1 b2 b1 b2

Figure 2.8 (a) Band structure of (5, 5) CNT constructed using ZF. The purple bands crossing the Fermi energy stem from the purple cutting line in (c), which crosses K and K’ points [46]. (b) Band structure of (9, 0) CNT, showing double degeneracy at the valence and conduction band crossing due to the two blue thick cutting lines in (d) [46]. (c) The 10 cutting lines of (5, 5) CNT projected onto graphene BZ, with same color coding as corresponding bands in (a). The green rectangle indicates the bordering rectangle as in Fig. 2.7(a) [46]. (d) Similar to (c) for (9,0) zigzag CNT [46]. (e) With curvature effect, K and K’ points move away from corners of hexagon to red dots. Armchair nanotubes thus stay metallic (left), while metallic zigzag nanotubes become small bandgap semiconductors (right) [46], such as that for (8, 0) CNT in (f) [46]. k‖ ≡ K2 and k⊥ ≡ K1.

Chapter 2

Another view of ZF is illustrated schematically in Fig. 2.9, in which the energy band structure of CNT can be constructed by projecting the parallel lines onto the graphene BZ, and cutting the so-called Dirac cone surface at K or K’ points. A Dirac cone is a 3D representation of E(k) around a Dirac point; for graphene, the Dirac points coincide with K or K’ points [47]. Again the diameter of SWCNT is assumed to be sufficiently large that the effect of the cylindrical curvature can be ignored.

(a) (b) (c) (d) (e)

From Fig. 2.9, one can deduce that if the projection of cutting lines intersect the Dirac cones at the corners of the graphene BZ, the corresponding CNT will not exhibit a bandgap. Also, Fig. 2.9(e) shows that the DOS of SWCNT consists of quantized spikes consistent with a 1D structure in which the electrons are confined to move only along the length of the conductor [45, 50]. Charlier [50] showed that the Fermi wave vector is along the length of the cutting line. If the cutting line intersects the BZ of graphene at a corner, then the Fermi vector lies at intersection of valence and conduction band of that CNT, resulting in a metallic conductor. Thus, the ZF method can be verified by projecting the cutting lines on Dirac cones.

The full electronic structure of SWCNT can be calculated using ab initio or first-principles method [51]. Reich [51] demonstrated an example of ab initio calculations of electronic band structure of graphene and subsequently applying ZF to construct the (10, 0) CNT band structure. The electronic structure of the same CNT was also calculated using the exact CNT geometry with an ab initio method. The calculated electronic band structures from both approaches show similar behaviors, as shown in Fig. 2.10, confirming that the ZF method provides a good approximation of the CNT band structure.

Chapter 2

The previous discussion is focused on constructing the band structure of CNT from that of graphene. An expression for energy dispersion relation of CNT can also be obtained from that of graphene, as illustrated below for an armchair (n, n) CNT. Using the periodic boundary condition in Eq. 2.25, one can obtain the quantized values of the wave vector component projected onto the chiral direction as follows.

Ch·k = n√3kxa = 2πq, where q = 1, 2, 3,…..,N=2n . (2.26)

Substituting Eq. 2.26 in energy dispersion relation of graphene, Eq. 2.7, a closed form expression for (n, n) CNT 2D energy bands is obtained.

휋푞 푘푦푎 푘푦푎 E(k) = ±γ0 [1 + 4cos( ) cos( ) + 4cos2( )]1/2 (2.27) 푛 2 2

Note that q is a quantum number that denotes a specific energy band for (n, n) CNT, which has a total of 2N=4n bands, counting degenerate bands. Further, one can also obtain an expression to characterize the electronic conduction of CNT using ZF. We have demonstrated in Fig. 2.8 that a CNT exhibits metallic behavior if a cutting line (a K2 vector) passes through K or K’ points of the graphene BZ. An example of such line for

Chapter 2

(10,5) CNT projected on the graphene BZ is shown in Fig. 2.11. Segment KY is drawn parallel to K2 passing through K point. Since the pitch between parallel K2 vectors is K1, for a K2 cutting line to pass through K point, line ΓY must be an integer multiple of K1. Using Γ as the origin and from Eqs. 2.6 and 2.23, this condition can be expressed as

퐊•퐊ퟏ 2푛+푚 ΓY = = K1 . (2.28) K1 3

From Eq. 2.28, ΓY is an integer multiple of K1 if (2n+m)/3 is an integer, or equivalently, (n-m) = 3i, where i is an integer [7]. CNTs that satisfy this condition have cutting lines pass through K or K’ points of graphene, resulting in zero bandgap at these points and exhibiting metallic behavior. All of this is based on the neglect of curvature effects, which can give rise to small bandgaps at these points in some cases, as shown in Fig. 2.8.

Alternatively, the electronic type of CNT can also be obtained by plotting Ch and T vectors on the graphene lattice and identifying the location at which T intersects the unit cell of graphene. An example each of metallic and semiconducting CNT is demonstrated in Fig. 2.12, for Ch = (3, 3), T = (1, -1) and for Ch = (4, 2), T= (4, -5). Plotting the two chiral

Chapter 2 vectors and their corresponding translational vectors on the graphene lattice in Fig.

2.12(a), for Ch = (3, 3), T intersects the hexagons only at its corners, corresponding to metallic behavior, as confirmed by ZF and energy bands in Fig. 2.12(b) and (c), respectively. Similarly, for Ch = (4, 2), T intersects the hexagons at non-corner points, resulting in a finite bandgap as confirmed in Fig. 2.12(d) and (e). Therefore, the electronic properties of SWCNT can be derived from graphene band structure using ZF method, and can be deduced from its chiral or translational vector. Chandra [52] reported measurements of the CNT conductance and confirmed that a SWCNT with chirality (21, 12) with n-m = 9 resulted in metallic conduction and a SWCNT (20, 9) with n-m = 11 ≠ 3i resulted in a p-type semiconducting behavior, consistent with Eq. 2.28.

(a) (b) (c)

Ch (d) (e)

The condition (n-m) = 3i (integer i) infers that for all the possible values of Ch, 1/3 of SWCNTs are metallic and the remaining 2/3 are semiconducting. An expression for energy bandgap of CNT can be obtained using cutting lines on the graphene BZ. The bandgap of a CNT is dependent on how and where the plane (normal to BZ) containing a cutting line (K2) intersects the Dirac cones of graphene in the vicinity of a BZ corner (K

Chapter 2 or K’). Mintmire [53, 54] derived a general expression for the CNT bandgap using an approximate energy dispersion relation for graphene by considering the cutting line in closest proximity to K, with δk being the perpendicular vector from K to the nearest cutting line K2, as shown in Fig. 2.13

Since δk lies in a K1 direction and the projection of wave vector k in this direction is quantized, the bandgap at the point on the cutting line closest to K, k = kF + δk, where kF denotes the Fermi vector from Γ to K, can be deduced [53].

√3푎훾0 훿푘 Eg = (2.29) 2

Eq. 2.30 is a general expression for approximating CNT bandgap. In case of metallic CNT,

δk=0, and Eq. 2.30 yields zero bandgap. Further, δk can be expressed in terms of Ch since both vectors are collinear. Thus, Eq. 2.29 can be rewritten as [53]

Chapter 2

√3푎훾0 2휋 푑푐푐훾0 Eg = ( |3푖 − 푛 + 푚|) = (|3푖 − 푛 + 푚|) , (2.30) 2 3퐶ℎ 퐷퐶푁푇 where i is an integer. Thus, the bandgap of a semiconducting CNT is inversely proportional to its diameter. The nearest-neighbor overlap integral of graphene γ0 = 2.5 eV was assumed [50]. A semiconducting (n, m) CNT has (n-m) = 3i+1 or 3i+2, and hence |3i-n+m| can be either 1 or 2, respectively. From Eq. 2.30, assuming (n-m)=3i+2, a semiconducting CNT with 1 nm diameter has a bandgap 0.7 eV [45]. For CNTs with diameter >10 nm, as in case of the outer shells of MWCNT, the bandgap becomes vanishingly small. Therefore, for all practical purposes, all SWCNTs with diameters >10 nm can be considered metallic, even if chirality predicts semiconducting behavior. Further, a MWCNT consisting of shells with one or more chiralities can be considered metallic as well, since the conduction is dominated by the shells with the lesser resistance, which are usually the outer shells with the larger diameters.

Resistance of an ideal metallic CNT can be derived from the concept of cutting lines on the graphene BZ. The result for SWCNT can then be extended to MWCNT. Each cutting line of SW that passes through K or K’ points of the graphene BZ represents a channel for electron to travel along the CNT axis. The number of channels ME is dependent on Ch. Further, the probability that a continuous channel exists for electron to travel unimpeded between two electrodes is denoted by ψ. Therefore, the CNT resistance can be expressed in terms of a combined quantum resistance of all parallel channels between the electrodes [3].

푅0 ℎ 1 RCNT = = 2 (2.31) 푀퐸 휓 2푒 푀퐸 휓

R0 is the quantum resistance of a 1D conductor with ballistic transport and ideal electrode contacts are assumed. If a channel is non-continuous between electrodes, then an electron travelling along the CNT axis experiences scattering, giving rise to a mean free path, λe, and the probability of such an event in terms of λe and CNT length, LCNT, can be expressed as [3]

1 ψ = 퐿 . (2.32) (1+ 퐶푁푇) 휆푒

Chapter 2

For the case of near-ballistic transport, λe >> LCNT, ψ ≈ 1. Thus a metallic CNT with ME = 2, near-ballistic transport, and ideal contacts would yield a resistance of 6.45 kΩ [3].

Extending Eq. 2.31 to MWCNT with Nshells shells, it can be treated as a parallel combination of resistors. Using Fermi statistics and the energy dispersion relation of graphene given by Eq. 2.7, Naeemi [55] obtained an approximate expression for the average number of channels per MWCNT shell in terms of shell diameter (in nm).

ME(DCNT) = 0.062 DCNT + 0.425, 3 nm < DCNT < 85 nm (2.33)

Such expression predicts that for MWCNT, the outer shells yield lower resistance than inner shells as more conduction channels exist. Further, each conducting shell has a finite contact resistance RC at each electrode [56-59]. Therefore, resistance of a MWCNT with finite contact resistance at both contacts can be obtained from Eq. 2.31, 2.32, and 2.33 as

ℎ 퐿퐶푁푇 2푅푐 RCNT = ∑푎푙푙 푠ℎ푒푙푙푠[ 2 (1 + )] + . (2.34) 2푒 푀퐸(퐷퐶푁푇) 휆푒 푁푠ℎ푒푙푙푠

λe can be considered the average distance an electron travels within the material between scattering events. which can be due to electron-phonon interactions, contacts, impurities, and imperfections in the crystal structure [10]. For CNT interconnects with submicron lengths, defects are the primary factor in determining electron mean free path [45]. CNT is prone to defects such as missing C atom in graphene lattice, extra C atom in lattice, local bonding between shells, and abrupt shell terminations along the length of CNT [60- 65]. These defects result in modification of chiral property of CNT and deviation of its electrical properties from that of an ideal CNT structure. For example, for a CNT with negligible defects, λe ~ 24 µm was obtained [10], whereas a highly-defective MWCNT yielded λe ~ 5 nm [66]. A small electron mean free path generally results in high resistance, consistent with Eq. 2.35. The minimum contact resistance of CNT is its quantum resistance but as CNT structure deviates from ideal, contact resistance increases. The imperfect metal-CNT interface and impurities can create contact resistance that dominates the total resistance. For MWCNT, contact resistance was reported to be in kΩ range [67-73]. The current-carrying capacity of CNT depends largely on density and location of defects as they enhance the resistance, and oxygen can react with impurities at elevated temperatures due to Joule heating [74]. Nevertheless, current-carrying

Chapter 2 capacities of CNTs were reported to be in the 10 – 1000 MA/cm2 range [75-79], which is 1~3 orders of magnitude higher than Cu and W [80]. To ensure a large current-carrying capacity and hence device reliability superior to conventional metals, it is critical to minimize defect formation in CNT by controlling its growth process [81]. Various methods for CNT growth are discussed in the next section, and the growth process characterization techniques are presented in Chapter 5.

2.5. CNT Growth Methods

SWCNT and MWCNT can be grown using various vapor deposition methods [82, 83]. A sample of grown SWCNT can result in a distribution of different chiralities and hence conduction properties within the sample [84]. Recently, process has been reported on chirality-controlled synthesis of semiconducting SWCNTs on a wafer scale but these cannot be used for interconnect applications [82]. As discussed in the previous section, MWCNT generally exhibits semi-metallic or metallic behavior and hence more suitable for interconnects. Therefore, subsequent discussions are focused on growth methods for MWCNTs only.

The most critical requirement for CNT growth is a very high thermal gradient for gaseous carbon species to crystalize in the form of a tubular structure. This process can be realized by arc-discharge between two graphite electrodes [85], laser ablation of a graphite target in a reactor [86], or catalyst-assisted vapor deposition of carbon species on transition metal nucleation sites [87]. In the arc-discharge method, a cathode made of graphite is brought in proximity to an anode (separated by 1~2 mm) containing carbon powder and catalyst, in a gas ambient to generate discharge. The temperature during discharge is in the range of 4000°C - 6000°C, which causes the carbon powder in anode to sublimate and the vapor is aggregated on the cathode due to the high-temperature gradient, resulting in CNT along with soot. For laser ablation, a graphite target is ablated with KrF laser and the carbon vapor is directed to a water-cooled Cu collector where the vapor condensates, resulting in CNTs. The process temperature during laser ablation is in the range of 1000°C - 1500°C. Catalyst- assisted vapor deposition is carried out by precipitation of dissociated hydrocarbon species on transition metal nucleation particle sites. Dissociation of hydrocarbons occurs with the help of elevated temperature and/or plasma. Using catalyst reduces the process temperature to 350°C - 700°C [57, 88, 89], closer to IC fabrication

Chapter 2 process temperature range. Therefore, catalyst-based CNT growth methods can be compatible to and integrated into conventional IC processing.

2.5.1. Catalyst-assisted CNT growth

Inclusion of CNTs in an IC not only requires CNT growth at compatible temperature of less than 450°C [66, 81, 88, 90, 91], it must also be at specified interconnect locations with minimal impurity contribution from the growth process. Arc-discharge and laser ablation are conducted at an order of magnitude higher temperature than BEOL limits, and also result in soot as an undesirable impurity byproduct. Therefore, catalyst-assisted vapor deposition methods are more suitable for application of CNTs in ICs. Two such methods are chemical vapor deposition (CVD) and plasma-enhanced chemical vapor deposition (PECVD). In CVD, a substrate with catalyst film such as Ni, Co, or Fe is subjected to temperature ≤ 700 °C to dewet the catalyst thin film on substrate. Later, a carbon source such as CH4 or C2H2 along with reducing agent such as NH3 or H2 are introduced in the reactor. Aided by the presence of catalyst particles, the hydrocarbon undergoes thermal dissociation and the resulting carbon species precipitates on the catalyst particles. If the areal density of particles on the substrate is high, van der Waal force among CNTs can facilitate vertical self-alignment during growth.

Figure 2.14. (a) Base growth and (b) tip growth of CNT on substrate resulting from catalyst- assisted dissociation of gaseous hydrocarbon source [10].

PECVD process is similar to CVD with a key difference being in the mechanism to disassociate hydrocarbon, which is done using an electric field applied in capacitive

Chapter 2 coupled plasma reactor to produce radicals. The resulting carbon radicals then precipitates on the catalyst sites where CNT growth occurs. The reducing agent facilitates etching excess carbon from the reactor walls and amorphous carbon from coating the catalyst sites so that continuous CNT growth can be sustained. The applied electric field ensures vertical alignment during CNT growth. In either CVD method, if the carbon species precipitates on the surface of the catalyst particle, then it results in CNT growth on top of the particle, referred to as base growth. If the carbon species precipitates below the catalyst resulting in the particle on the CNT tip, it is called tip growth. The base and tip growth processes are shown schematically in Fig. 2.14. Such growth generally depends on the wettability of catalyst film to the underlayer, as well as that between CNT and catalyst. Meyyappan [87] and Sun [92] reported that catalyst exhibiting strong wettability to underlayer resulted in base growth due to adherence of catalyst to underlayer, and that tip growth for catalyst with poor wettability. For interconnects, it is desirable to have CNT in direct contact with underlayer metal. Therefore tip growth is preferred so that post-growth contact engineering can be performed to improve the top contact [93].

2.5.2. CNT growth process development

PECVD with Ni catalyst is the method employed in this work to grow CNT in vias as it has been shown to result in tip growth on Ti, Cr, and oxide [87]. Sun [92] conducted extensive experiments on effect of underlayer and catalyst thicknesses on CNT growth. The results are summarized in Fig. 2.15. One can conclude that for Ni/Ti system, 10 nm Ni is the critical thickness below which sparse growth of CNTs results, attributed to catalyst particles embedded in the underlayer metal grain boundaries [87]. Wilhite [94] developed a CNT growth process for an optimized combination of Ni catalyst and Cr underlayer thicknesses. It was demonstrated from blanket growth on unpatterned substrate that the columnar grain structure of Cr resulted in high CNT areal density ~1011 cm2, for Ni film thickness down to 4 nm [94]. Aside from yielding a high areal density, Cr has been reported to be an excellent etch stop layer to reactive ion etching (RIE) process, a key requirement in patterning vias [95]. Ti readily reacts with halogens and oxygen radicals which are the primary ingredients of RIE process [96]. Therefore, Ti film can be physically damaged or oxidized during via etch by RIE, resulting in either a

Chapter 2 discontinuous or oxidized underlayer for subsequent CNT growth in vias. Thus the Ni/Cr combination is used in this work for CNT growth inside patterned vias.

Figure 2.15. Effect of catalyst thickness and underlayer combination on CNT growth [92].

The CNT growth process was developed on an oxide-covered Si substrate with a blanket Cr film serving as the metal underlayer [94]. The objective is to achieve smallest possible average CNT diameter with narrow distribution and highest possible areal density, key requirements for interconnect application in order to yield low resistance. The first stage of the process is catalyst film dewetting which determines the diameter distribution and CNT areal density. To achieve the optimum diameter and CNT areal density, various experiments were conducted by varying Ni catalyst thickness (4 – 18 nm), temperature ramp rate (250°C – 325°C), and annealing time (0 – 4 minutes), with growth time fixed at

5 minutes and gas flow rates fixed at 125 sccm and 31 sccm for NH3 and C2H2, respectively [87]. The objective was to identify conditions that would yield the desirable outcomes for CNTs grown at 700°C. SEM analysis of samples revealed that the average or median diameter of CNT is primarily determined by catalyst film thickness and annealing time. Longer annealing time resulted in coalescence of some nucleation sites, known as Ostwald ripening mechanism [97], and yielded CNTs with wide diameter distribution and sparse density. Therefore, the growth recipe we use contained no annealing and the highest ramp rate allowed by the deposition system, 325°C/min, to achieve narrow CNT diameter distribution and high areal density. Top-view SEM images of samples with and without annealing are shown in Fig. 2.16.

Chapter 2

8 2 10 2 (a) Areal density = 3 x 10 /cm (b) Areal density = 5 x 10 /cm Median diameter = 60 nm Median diameter = 25 nm

Figure 2.16. (a) CNT growth after 5 min annealing in ammonia ambient. (b) CNT growth without annealing. Both samples grown using 12 nm Ni film.

Using the optimized ramp rate and no annealing, further CNT growth experiments are conducted with Ni film thicknesses 4 nm, 6 nm, 12 nm, and 18 nm. The diameter distribution for each samples is shown in Figure 2.17. A direct correlation can be observed between median diameter and catalyst thickness. The sample with 4 nm Ni yields an

11 2 Areal density = 4 x 10 /cm 30 Median diameter = 13 nm

NumberCNTs of 10

0 0 10 20 30 40 50 60 70 80 90 100 110 Diameter (nm)

18 nm Ni 12 nm Ni 6 nm Ni 4 nm Ni

Figure 2.17. Effect of catalyst thickness on CNT diameter distribution. (Inset) Top-view SEM images of CNTs grown on unpatterned Cr substrate with 4 nm Ni catalyst.

Chapter 2 areal density of 4 x 1011/cm2 with median CNT diameter 13 nm, which is the smallest with the narrowest diameter distribution in the experimental set. Therefore, the process with 4 nm Ni catalyst on Cr underlayer is selected for CNT growth in vias.

TEM imaging and analysis are performed to examine the cross-sections of CNTs grown with PECVD process, as shown in Fig. 2.18. The TEM image revealed a bamboo-like structure with non-uniform diameter from base to tip. From the discussions on CNT structure and properties in sections 2.3 and 2.4, the variation in diameter and sidewall kinks along the length of CNT infers that changes in chiral and translation vectors occur along the length and among the shells. Further, the abrupt in-plane terminations of shells could result in discontinuous conducting channels. Therefore, CNTs obtained from PECVD with Ni catalyst cannot be expected to exhibit near-ballistic transport due to such defects in its structure. The resulting electron mean free path is thus much less than the typical CNT length and the transport is most likely ohmic. Further analysis of defects using optical characterization technique is discussed in Chapter 4 and electrical measurement results are presented in Chapter 5 to demonstrate ohmic transport.

50 nm

Figure 2.18 TEM image of CNTs grown using PECVD with Ni catalyst [76], revealing bamboo- like structure and variation in diameter along CNT length.

Chapter 2

A step-by-step description of the CNT growth process used in this work is given in Table 2.2 and a plot of the key process parameters for a typical CNT growth experiment is shown in Figs. 2.19 and 2.20. This process is used for CNT growth inside patterned vias to achieve similar CNT areal density in vias, and the results are discussed in Chapter 4 after the narrative on via fabrication.

Table 2.2. Steps for CNT growth process. Step Description Key parameter values Pressure = 1000 mbar, 1 Vent chamber for sample transfer Temperature ~ 200°C, gas flow = 0 sccm, Plasma = 0 V. Pressure = 2 µbar, Evacuate chamber until it reaches 2 Temperature ~ 200°C, gas flow = 0 base pressure (2 µbar) sccm, Plasma = 0 V.

Temperature ramp in NH3 Pressure = 2 mbar, NH3 = 100 sccm 3 ambient to 700°C for Ni film Temperature Ramp rate 325°C/min dewetting

Once temperature reaches 700°C, Pressure = 2 mbar, NH3 = 125 sccm,

4 strike plasma and introduce C2H2 C2H2 = 31 sccm, Temperature ~700-

along with NH3 in chamber 800°C, Plasma = 800 V.

Pressure = 2 mbar, NH3 = 125 sccm,

5 CNT growth step C2H2 = 31 sccm, Temperature ~700- 800°C, Plasma = 800 V, time = 5 mins

Pressure = 2 mbar, NH3 = 0 sccm, C2H2 Stop gas flows and heater power 6 = 0 sccm, Temperature 700-800°C, off Plasma = 0 V

Pressure = 15 mbar, NH3 = 0 sccm, Ar

7 Cooling step = 2000 sccm, C2H2 = 0 sccm, Temperature < 700°C, Plasma = 0 V Pressure = 1000 mbar, gas flows = 0 8 Retrieve sample from chamber sccm, plasma = 0 V, Temperature < 200°C

Chapter 2

1200 Sample transfer 1000 Temperature ramp CNT growth step 800

600

400 Cooling step Process Process Parameter magnitude 200

0 3500 4500 5500 6500 7500 8500 9500 10500 11500 Time (s) Pressure(mbar) Global temp SP(°C) Global temp PV(°C) Plasma voltage SP(V) Plasma voltage PV(V)

Figure 2.19 Typical variations of process parameters versus time before, during, and after CNT growth. SP denotes setpoint and PV for parameter value.

2500

2000 Cooling step

1500 CNT growth step

1000 Glas Glas flow (sccm)

500

0 3500 4500 5500 6500 7500 8500 9500 10500 11500 TIme (s)

MFC1 SP(sccm) MFC1 PV(sccm) MFC2 SP(sccm) MFC2 PV(sccm) MFC3 SP(sccm) MFC3 PV(sccm)

Figure 2.20 Gas flow rates versus time during and after CNT growth. MFC1 is for ammonia, MFC2 for argon, and MFC3 for acetylene.

Chapter 2

References

[1] M. S. Dresselhaus, G. Dresselhaus, J. C. Charlier, and E. Hernandez, "Electronic, thermal and mechanical properties of carbon nanotubes," Philosophical Transactions of the Royal Society a-Mathematical Physical and Engineering Sciences, vol. 362, pp. 2065-2098, Oct 2004. [2] M. S. Dresselhaus, G. Dresselhaus, and M. Pimenta, "The remarkable properties of carbon nanotubes as nanoclusters," European Physical Journal D, vol. 9, pp. 69-75, Dec 1999. [3] R. Saito, G. Dresselhaus, and M. S. Dresselhaus, Physical properties of carbon nanotubes, Imperial College Press, 1998. [4] F. Banhart, "Chains of carbon atoms: A vision or a new nanomaterial?," Beilstein Journal of Nanotechnology, vol. 6, pp. 559-569, Feb 2015. [5] N. Camara, G. Rius, J. R. Huntzinger, A. Tiberj, N. Mestres, P. Godignon, and J. Camassel, "Selective epitaxial growth of graphene on SiC," Applied Physics Letters, vol. 93, Sep 2008. [6] Y. S. Li and A. Hirose, "Controlled synthesis of diamond and carbon nanotubes on Ni-base alloy," Applied Surface Science, vol. 255, pp. 2251-2255, Dec 2008. [7] A. Hazeghi, K. Saraswat, H.-S. P. Wong, and D. Goldhaber-Gordon, Carbon Nanotube Electronics: Stanford University, 2011. [8] T. J. Booth, F. Pizzocchero, H. Andersen, T. W. Hansen, J. B. Wagner, J. R. Jinschek, R. E. Dunin-Borkowski, O. Hansen, and P. Boggild, "Discrete Dynamics of Nanoparticle Channelling in Suspended Graphene," Nano Letters, vol. 11, pp. 2689-2692, Jul 2011. [9] A. C. Neto, F. Guinea, N. M. Peres, K. S. Novoselov, and A. K. Geim, "The electronic properties of graphene," Reviews of modern physics, vol. 81, p. 109-164, June 2009. [10] S. Hermann, "Growth of carbon nanotubes on different support/catalyst systems for advanced interconnects in integrated circuits," 2011. [11] B. Partoens and F. M. Peeters, "From graphene to graphite: Electronic structure around the Kpoint," Physical Review B, vol. 74, pp. 075404-4, Aug 2006. [12] J. A. Garlow, L. K. Barrett, L. Wu, K. Kisslinger, Y. Zhu, and J. F. Pulecio, "Large-area growth of turbostratic graphene on Ni (111) via physical vapor deposition," Scientific reports, vol. 6, June 2016. [13] K. S. Novoselov, "Nobel Lecture: Graphene: Materials in the Flatland," Reviews of Modern Physics, vol. 83, pp. 837-849, Aug 2011. [14] K. S. Novoselov, V. I. Fal'ko, L. Colombo, P. R. Gellert, M. G. Schwab, and K. Kim, "A roadmap for graphene," Nature, vol. 490, pp. 192-200, Oct 2012. [15] M. Sprinkle, D. Siegel, Y. Hu, J. Hicks, A. Tejeda, A. Taleb-Ibrahimi, P. Le Fevre, F. Bertran, S. Vizzini, and H. Enriquez, "First direct observation of a nearly ideal graphene band structure," Physical review letters, vol. 103, p. 226803-4, Nov 2009. [16] L. Radushkevich and V. Lukyanovich, "O strukture ugleroda, obrazujucegosja pri termiceskom razlozenii okisi ugleroda na zeleznom kontakte," Zurn Fisic Chim, vol. 26, pp. 88-95, Jan 1952. [17] S. Iijima, "Carbon nanotubes: past, present, and future," Physica B-Condensed Matter, vol. 323, pp. 1-5, Oct 2002. [18] S. Iijima, "Structural flexibility of carbon nanotubes," Journal of Japanese Society of Tribologists, vol. 41, pp. 724-729, Feb 1996.

Chapter 2

[19] S. Iijima, "Tem Study of Carbon Nanotubes," Zoological Studies, vol. 34, pp. 170-172, Apr 1995. [20] S. Iijima, "Carbon Nanotubes," Mrs Bulletin, vol. 19, pp. 43-49, Nov 1994. [21] S. Iijima, "Growth of Carbon Nanotubes," Materials Science and Engineering B-Solid State Materials for Advanced Technology, vol. 19, pp. 172-180, Apr 1993. [22] C. Guerret-Piecourt, Y. Lebouar, A. Loiseau, and H. Pascard, "Relation between Metal Electronic-Structure and Morphology of Metal-Compounds inside Carbon Nanotubes," Nature, vol. 372, pp. 761-765, Dec 1994. [23] M. Q. Liu and J. M. Cowley, "Structures of the Helical Carbon Nanotubes," Carbon, vol. 32, pp. 393-403, Dec 1994. [24] X. K. Wang, X. W. Lin, M. Mesleh, M. F. Jarrold, V. P. Dravid, J. B. Ketterson, and R. P. H. Chang, "The Effect of Hydrogen on the Formation of Carbon Nanotubes and Fullerenes," Journal of Materials Research, vol. 10, pp. 1977-1983, Aug 1995. [25] A. A. Setlur, J. M. Lauerhaas, J. Y. Dai, and R. P. H. Chang, "A method for synthesizing large quantifies of carbon nanotubes and encapsulated copper nanowires," Applied Physics Letters, vol. 69, pp. 345-347, Jul 1996. [26] J. Cook, J. Sloan, R. J. R. Heesom, J. Hammer, and M. L. H. Green, "Purification of rhodium- filled carbon nanotubes using reversed micelles," Chemical Communications, pp. 2673-2674, Dec 1996. [27] Z. J. Shi, X. H. Zhou, Z. X. Jin, Z. N. Gu, J. Wang, S. Q. Feng, X. L. Xu, and Z. Q. Liu, "High yield synthesis and growth mechanism of carbon nanotubes," Solid State Communications, vol. 97, pp. 371-375, Feb 1996. [28] K. Hernadi, A. Fonseca, J. B. Nagy, D. Bernaerts, and A. A. Lucas, "Fe-catalyzed carbon nanotube formation," Carbon, vol. 34, pp. 1249-1257, Dec 1996. [29] H. M. Cheng, F. Li, G. Su, H. Y. Pan, L. L. He, X. Sun, and M. S. Dresselhaus, "Large-scale and low-cost synthesis of single-walled carbon nanotubes by the catalytic pyrolysis of hydrocarbons," Applied Physics Letters, vol. 72, pp. 3282-3284, June 1998. [30] C. Journet and P. Bernier, "Production of carbon nanotubes," Applied Physics a-Materials Science & Processing, vol. 67, pp. 1-9, July 1998. [31] W. K. Maser, E. Munoz, A. M. Benito, M. T. Martinez, G. F. de la Fuente, Y. Maniette, E. Anglaret, and J. L. Sauvajol, "Production of high-density single-walled nanotube material by a simple laser-ablation method," Chemical Physics Letters, vol. 292, pp. 587-593, Aug 1998. [32] Z. F. Ren, Z. P. Huang, D. Z. Wang, J. G. Wen, J. W. Xu, J. H. Wang, L. E. Calvet, J. Chen, J. F. Klemic, and M. A. Reed, "Growth of a single freestanding multiwall carbon nanotube on each nanonickel dot," Applied Physics Letters, vol. 75, pp. 1086-1088, Aug 1999. [33] R. Martel, T. Schmidt, H. R. Shea, T. Hertel, and P. Avouris, "Single- and multi-wall carbon nanotube field-effect transistors," Applied Physics Letters, vol. 73, pp. 2447-2449, Oct 1998. [34] I. Stemmler and C. Backes, "Absorption Spectroscopy as a Powerful Technique for the Characterization of Single-Walled Carbon Nanotubes," ed: White paper, PerkinElmer, 2013. [35] S. Iijima and T. Ichihashi, "Single-Shell Carbon Nanotubes of 1-Nm Diameter," Nature, vol. 363, pp. 603-605, Jun 1993.

Chapter 2

[36] M. Cantoro, S. Hofmann, S. Pisana, V. Scardaci, A. Parvez, C. Ducati, A. C. Ferrari, A. M. Blackburn, K. Y. Wang, and J. Robertson, "Catalytic chemical vapor deposition of single- wall carbon nanotubes at low temperatures," Nano Letters, vol. 6, pp. 1107-1112, Jun 2006. [37] P. B. Amama, S. Lim, D. Ciuparu, Y. H. Yang, L. Pfefferle, and G. L. Haller, "Synthesis, characterization, and stability of Fe-MCM-41 for production of carbon nanotubes by acetylene pyrolysis," Journal of Physical Chemistry B, vol. 109, pp. 2645-2656, Feb 2005. [38] M. Monthioux, B. W. Smith, B. Burteaux, A. Claye, J. E. Fischer, and D. E. Luzzi, "Sensitivity of single-wall carbon nanotubes to chemical processing: an electron microscopy investigation," Carbon, vol. 39, pp. 1251-1272, July 2001. [39] H. Busta, Z. Tolt, J. Montgomery, and A. Feinerman, "Field emission from teepee-shaped carbon nanotube bundles," Journal of Vacuum Science & Technology B, vol. 23, pp. 676-679, Mar 2005. [40] M. Ishigami, J. Cumings, A. Zettl, and S. Chen, "A simple method for the continuous production of carbon nanotubes," Chemical Physics Letters, vol. 319, pp. 457-459, Mar 2000. [41] R. A. Jishi, D. Inomata, K. Nakao, M. S. Dresselhaus, and G. Dresselhaus, "Electronic and Lattice Properties of Carbon Nanotubes," Journal of the Physical Society of Japan, vol. 63, pp. 2252-2260, Jun 1994. [42] N. Wang, K. K. Fung, W. Y. Lu, and S. H. Yang, "Structural Characterization of Carbon Nanotubes and Nanoparticles by High-Resolution Electron-Microscopy," Chemical Physics Letters, vol. 229, pp. 587-592, Nov 1994. [43] M. Q. Liu and J. M. Cowley, "Growth-Behavior and Growth Defects of Carbon Nanotubes," Materials Science and Engineering a-Structural Materials Properties Microstructure and Processing, vol. 185, pp. 131-140, Sep 1994. [44] P. H. Tan, S. L. Zhang, K. T. Yue, F. M. Huang, Z. J. Shi, X. H. Zhou, and Z. N. Gu, "Comparative Raman study of carbon nanotubes prepared by dc arc discharge and catalytic methods," Journal of Raman Spectroscopy, vol. 28, pp. 369-372, May 1997. [45] G. G. Samsonidze, A. R. Saito, D. A. Jorio, E. Pimenta, F. Souza, F. A. Grüneis, D. G. Dresselhaus, and M. Dresselhausa, "The concept of cutting lines in carbon nanotube science," Journal of nanoscience and nanotechnology, vol. 3, pp. 431-458, Dec 2003. [46] K. Grove-Rasmussen, "Electronic Transport in Single Wall Carbon Nanotubes," Ph.D. thesis, University of Copenhaguen, 2006, pp. 48-59, May 2006. [47] B. Zhen, C. W. Hsu, Y. Igarashi, L. Lu, I. Kaminer, A. Pick, S.-L. Chua, J. D. Joannopoulos, and M. Soljačić, "Spawning rings of exceptional points out of Dirac cones," Nature, vol. 525, pp. 354-358, Sep 2015. [48] P. Avouris, "Carbon nanotube electronics," Chemical Physics, vol. 281, pp. 429-445, Aug 2002. [49] P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, "Carbon nanotube electronics," Proceedings of the Ieee, vol. 91, pp. 1772-1784, Nov 2003. [50] J.-C. Charlier, X. Blase, and S. Roche, "Electronic and transport properties of nanotubes," Reviews of modern physics, vol. 79, p. 677, May 2007. [51] S. Reich, C. Thomsen, and J. Maultzsch, Carbon nanotubes: basic concepts and physical properties, John Wiley & Sons, 2008.

Chapter 2

[52] B. Chandra, R. Caldwell, M. Huang, L. Huang, M. Y. Sfeir, S. P. O'Brien, T. F. Heinz, and J. Hone, "Electrical transport measurements of nanotubes with known (n, m) indices," physica status solidi (b), vol. 243, pp. 3359-3364, Nov 2006. [53] J. W. Mintmire and C. T. White, "Universal density of states for carbon nanotubes," Physical Review Letters, vol. 81, pp. 2506-2509, Sep 1998. [54] J. W. Mintmire and C. T. White, "Electronic and Structural-Properties of Carbon Nanotubes," Carbon, vol. 33, pp. 893-902, Dec 1995. [55] A. Naeemi and J. D. Meindl, "Compact physical models for multiwall carbon-nanotube interconnects," IEEE Electron Device Letters, vol. 27, pp. 338-340, May 2006. [56] A. A. Vyas, C. Y. Yang, P. Wang, C. Zhou, and Y. Chai, "Contact resistance and reliability of 40 nm carbon nanotube vias," IEEE International Interconnect Technology Conference/Advanced Metallization Conference, pp. 203-205, May 2016. [57] A. Vyas, P. Wang, C. Zhou, M. Chan, and C. Y. Yang, "Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias," IEEE International Interconnect Technology Conference, pp. 203- 205, May 2016. [58] Y. H. Kim and H. S. Kim, "Anomalous length scaling of carbon nanotube-metal contact resistance: An ab initio study," Applied Physics Letters, vol. 100, May 2012. [59] M. Karita, K. Asaka, H. Nakahara, and Y. Saito, "In situ TEM study on the improvement of contact resistance between a carbon nanotube and metal electrodes by local melting," Surface and Interface Analysis, vol. 44, pp. 674-677, Jun 2012. [60] Y. A. Kim, S. Aoki, K. Fujisawa, Y. I. Ko, K. S. Yang, C. M. Yang, Y. C. Jung, T. Hayashi, M. Endo, M. Terrones, and M. S. Dresselhaus, "Defect-Assisted Heavily and Substitutionally Boron-Doped Thin Multiwalled Carbon Nanotubes Using High-Temperature Thermal Diffusion," Journal of Physical Chemistry C, vol. 118, pp. 4454-4459, Feb 2014. [61] Y. J. Wei, J. T. Wu, H. Q. Yin, X. H. Shi, R. G. Yang, and M. Dresselhaus, "The nature of strength enhancement and weakening by pentagon-heptagon defects in graphene," Nature Materials, vol. 11, pp. 759-763, Sep 2012. [62] P. T. Araujo, M. Terrones, and M. S. Dresselhaus, "Defects and impurities in graphene- like materials," Materials Today, vol. 15, pp. 98-109, Mar 2012. [63] M. Kalbac, Y. P. Hsieh, H. Farhat, L. Kavan, M. Hofmann, J. Kong, and M. S. Dresselhaus, "Defects in Individual Semiconducting Single Wall Carbon Nanotubes: Raman Spectroscopic and in Situ Raman Spectroelectrochemical Study," Nano Letters, vol. 10, pp. 4619-4626, Nov 2010. [64] M. S. Dresselhaus, A. Jorio, A. G. Souza, and R. Saito, "Defect characterization in graphene and carbon nanotubes using Raman spectroscopy," Philosophical Transactions of the Royal Society a-Mathematical Physical and Engineering Sciences, vol. 368, pp. 5355-5377, Dec 2010. [65] G. H. Zhu, H. Lee, Y. C. Lan, X. W. Wang, G. Joshi, D. Z. Wang, J. Yang, D. Vashaee, H. Guilbert, A. Pillitteri, M. S. Dresselhaus, G. Chen, and Z. F. Ren, "Increased Phonon Scattering by Nanograins and Point Defects in Nanostructured Silicon with a Low Concentration of Germanium," Physical Review Letters, vol. 102, May 2009. [66] S. Vollebregt, A. N. Chiaramonti, R. Ishihara, H. Schellevis, and K. Beenakker, "Contact resistance of low-temperature carbon nanotube vertical interconnects," 12th IEEE Conference on Nanotechnology pp. 1-5. Feb 2012.

Chapter 2

[67] M. H. van der Veen, B. Vereecke, C. Huyghebaert, D. J. Cott, M. Sugiura, Y. Kashiwagi, L. Teugels, R. Caluwaerts, N. Chiodarelli, P. M. Vereecken, G. P. Beyer, M. M. Heyns, S. De Gendt, and Z. Tokei, "Electrical characterization of CNT contacts with Cu Damascene top contact," Microelectronic Engineering, vol. 106, pp. 106-111, Jun 2013. [68] N. Chiodarelli, A. Fournier, H. Okuno, and J. Dijon, "Carbon nanotubes horizontal interconnects with end-bonded contacts, diameters down to 50 nm and lengths up to 20 mu m," Carbon, vol. 60, pp. 139-145, Aug 2013. [69] N. Chiodarelli, A. Fournier, and J. Dijon, "Impact of the contact's geometry on the line resistivity of carbon nanotubes bundles for applications as horizontal interconnects," Applied Physics Letters, vol. 103, Jul 2013. [70] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, p. 085302, Feb 2011. [71] N. Chiodarelli, Y. L. Li, D. J. Cott, S. Mertens, N. Peys, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration and electrical characterization of carbon nanotube via interconnects," Microelectronic Engineering, vol. 88, pp. 837-843, May 2011. [72] N. Chiodarelli, K. Kellens, D. J. Cott, N. Peys, K. Arstila, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration of Vertical Carbon Nanotube Bundles for Interconnects," Journal of the Electrochemical Society, vol. 157, pp. K211-K217, Oct 2010. [73] C. Zhang, D. Cott, N. Chiodarelli, P. Vereecken, J. Robertson, and C. M. Whelan, "Growth of carbon nanotubes as horizontal interconnects," Physica Status Solidi B-Basic Solid State Physics, vol. 245, pp. 2308-2310, Oct 2008. [74] S. Maeda, P. Wilhite, N. Kanzaki, T. Yamada, and C. Y. Yang, "Change in carbon nanofiber resistance from ambient to vacuum," Aip Advances, vol. 1, pp.022102-3, Jun 2011. [75] B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and current carrying capacity of carbon nanotubes," Applied Physics Letters, vol. 79, pp. 1172-1174, Aug 2001. [76] P. Wilhite, A. A. Vyas, J. Tan, J. Tan, T. Yamada, P. Wang, J. Park, and C. Y. Yang, "Metal– nanocarbon contacts," Semiconductor Science and Technology, vol. 29, p. 054006-16, April 2014. [77] A. P. Graham, G. S. Duesberg, W. Hoenlein, F. Kreupl, M. Liebau, R. Martin, B. Rajasekharan, W. Pamler, R. Seidel, W. Steinhoegl, and E. Unger, "How do carbon nanotubes fit into the semiconductor roadmap?," Applied Physics a-Materials Science & Processing, vol. 80, pp. 1141-1151, Mar 2005. [78] A. P. Graham, G. S. Duesberg, R. Seidel, M. Liebau, E. Unger, F. Kreupl, and W. Honlein, "Towards the integration of carbon nanotubes in microelectronics," Diamond and Related Materials, vol. 13, pp. 1296-1300, Apr-Aug 2004. [79] A. P. Graham, G. S. Duesberg, R. V. Seidel, M. Liebau, E. Unger, W. Pamler, F. Kreupl, and W. Hoenlein, "Carbon nanotubes for microelectronics?," Small, vol. 1, pp. 382-390, Apr 2005. [80] "International Technology Roadmap for Semiconductors," 2013. [81] S. Vollebregt, R. Ishihara, F. D. Tichelaar, Y. Hou, and C. I. M. Beenakker, "Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers," Carbon, vol. 50, pp. 3542-3554, Aug 2012.

Chapter 2

[82] N. Patil, A. Lin, E. R. Myers, K. Ryu, A. Badmaev, C. W. Zhou, H. S. P. Wong, and S. Mitra, "Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes," Ieee Transactions on Nanotechnology, vol. 8, pp. 498-504, Jul 2009. [83] Y. Awano, S. Sato, M. Nihei, T. Sakai, Y. Ohno, and T. Mizutani, "Carbon Nanotubes for VLSI: Interconnect and Transistor Applications," Proceedings of the IEEE, vol. 98, pp. 2015- 2031, Dec 2010. [84] R. Bhowmick, B. M. Clemens, and B. A. Cruden, "Parametric analysis of chirality families and diameter distributions in single-wall carbon nanotube production by the floating catalyst method," Carbon, vol. 46, pp. 907-922, May 2008. [85] N. Arora and N. Sharma, "Arc discharge synthesis of carbon nanotubes: Comprehensive review," Diamond and Related Materials, vol. 50, pp. 135-150, Nov 2014. [86] W.-W. Liu, S.-P. Chai, A. R. Mohamed, and U. Hashim, "Synthesis and characterization of graphene and carbon nanotubes: A review on the past and recent developments," Journal of Industrial and Engineering Chemistry, vol. 20, pp. 1171-1185, Jul 2014. [87] M. Meyyappan, "A review of plasma enhanced chemical vapour deposition of carbon nanotubes," Journal of Physics D-Applied Physics, vol. 42, Nov 2009. [88] S. Vollebregt, F. D. Tichelaar, H. Schellevis, C. I. M. Beenakker, and R. Ishihara, "Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 degrees C," Carbon, vol. 71, pp. 249-256, May 2014. [89] M. Katagiri, Y. Yamazaki, N. Sakuma, M. Suzuki, T. Sakai, M. Wada, N. Nakamura, N. Matsunaga, S. Sato, and M. Nihei, "Fabrication of 70-nm-diameter carbon nanotube via interconnects by remote plasma-enhanced chemical vapor deposition and their electrical properties," IEEE International Interconnect Technology Conference, pp. 44-46, May 2009 [90] S. Vollebregt, A. N. Chiaramonti, J. van der Cingel, K. Beenakker, and R. Ishihara, "Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits," Japanese Journal of Applied Physics, vol. 52, pp.04CB02-4, Apr 2013. [91] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Thermal conductivity of low temperature grown vertical carbon nanotube bundles measured using the three-omega method," Applied Physics Letters, vol. 102, May 2013. [92] X. H. Sun, K. Li, R. Wu, P. Wilhite, T. Saito, J. Gao, and C. Y. Yang, "The effect of catalysts and underlayer metals on the properties of PECVD-grown carbon nanostructures," Nanotechnology, vol. 21, Jan 2010. [93] S. C. Lim, J. H. Jang, D. J. Bae, G. H. Han, S. Lee, I. S. Yeo, and Y. H. Lee, "Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability," Applied Physics Letters, vol. 95, Dec 2009. [94] P. Wilhite, A. Vyas, J. Tan, C. Y. Yang, P. Wang, J. Park, H. Ai, and M. Narasimhan, "Electrical and structural analysis of CNT–metal contacts in via interconnects," in Proc. 7th Int. Conf. Quantum, Nano, Micro Technol, pp. 41-43, Aug 2013. [95] H. H. Solak, C. David, J. Gobrecht, V. Golovkina, F. Cerrina, S. Kim, and P. Nealey, "Sub-50 nm period patterns with EUV interference lithography," Microelectronic Engineering, vol. 67, pp. 56-62, Jun 2003. [96] R. d’Agostino, F. Fracassi, C. Pacifico, and P. Capezzuto, "Plasma etching of Ti in fluorine‐ containing feeds," Journal of applied physics, vol. 71, pp. 462-471, Jan 1992.

Chapter 2

[97] D. Alloyeau, G. Prevot, Y. Le Bouar, T. Oikawa, C. Langlois, A. Loiseau, and C. Ricolleau, "Ostwald Ripening in Nanoalloys: When Thermodynamics Drives a Size-Dependent Particle Composition," Physical Review Letters, vol. 105, pp. 255901-4, Dec 2010.

3 Carbon Nanotubes as Horizontal Interconnects

An overview of CNTs as horizontal interconnects is presented. We begin with a summary of work on fabricating horizontal SWCNT and MWCNT on a substrate, followed by a narrative on DC characteristics of horizontal CNT interconnects with various contact configurations to realize low contact resistance. For tungsten-deposited contacts, RF characteristics of horizontal CNT interconnects reveal that CNT behaves as a virtual frequency-independent resistor up to 50 GHz.

Chapter 3

3.1 Overview of Horizontal CNT Interconnects

Carbon nanotube in horizontal configuration has been extensively evaluated as FET channel [1-7] and interconnect [8-13]. In interconnect applications, experimental foci have been on the horizontal growth of CNTs, metal-CNT side-bonded and end-bonded contacts [14], electrical characterization[15-17], and circuit integration [18]. In most of the experiments reported, CNTs were grown vertically on another substrate and transferred onto pre-fabricated test structures by drop-casting or using a polymer sheet. However, there have been successful attempts to grow and characterize CNTs in horizontal configurations [19-24]. A typical example of SWCNTs grown in horizontal configuration on a quartz substrate is shown in Fig. 3.1, with a packing density of 1~2 CNTs/µm.

Figure 3.1 SEM images of CNTs grown on quartz substrate using different catalysts [25].

In recent years, significant progress has been made on wafer-scale methods to grow horizontally aligned CNTs with high packing density. Patil [26] reported the first wafer- scale growth of aligned SWCNTs on a 4-inch quartz wafer, with a packing density of 67 CNTs/µm, as shown in Fig. 3.2. Hu [27] reported a wafer-scale growth of SWCNTs with a median diameter of 0.9 nm and packing density of 130 CNTs/µm. In comparison, for 1 nm half-pitch, a packing density of 501 CNTs/µm is required. Therefore, ~4× improvement in wafer-scale packing density of CNTs is needed. It is also essential to control the chirality of CNTs grown on wafer as it determines the conduction property. Recently, Yang [28] reported chirality-controlled synthesis of metallic SWCNTs with chirality of (12,6) and a 92% yield of metallic nanotubes. Further improvement of

Chapter 3 chirality-controlled synthesis with high yield (>99%) can eventually result in integrating SWCNTs as FET channel and/or on-chip interconnects in integrated circuits.

Figure 3.2 SEM images of horizontally aligned SWCNTs grown on quartz substrate [26].

In contrast, the growth of horizontally aligned MWCNTs at lithographically specified locations has been a challenge. Vertical alignment of MWCNTs can be achieved with van der Waals force or with a vertical electric field. However, applying a horizontal electric field between two metal electrodes on a substrate can be challenging. Santini [29] and Yan [30] have demonstrated the growth of horizontal MWCNTs between metal electrodes and between sidewalls of a trench, respectively, as shown in Fig. 3.3. Significant process development is required to achieve high-density array of MWCNTs at pre-defined locations and ultimately on a fully integrated IC. Nonetheless, MWCNTs have been extensively evaluated for horizontal interconnect applications. In particular, experiments have been conducted to study DC and RF characteristics, contact resistance, and current-carrying capacity of individual CNTs in horizontal configurations. Findings of these studies are summarized in the following sections.

Chapter 3

(b)

Figure 3.3 (a) Top-view SEM image of a single MWCNT grown between two metal electrodes [29]. (b) Cross-sectional SEM images of a bundle of MWCNTs grown between sidewalls of a trench [30].

3.2 CNT Resistance and Metal-CNT Contacts

In general, extensive electrical characterization of CNTs can yield resistivity, electron mean free path, contact resistance, and current-carrying capacity. These parameters are related to the CNT nanostructure and thus can be used in further tuning the fabrication process to improve performance as well as reliability. The subsequent discussion focusses mainly on individual MWCNTs and CNFs only as the experiments reported were performed on these materials. Early experiments by Berger [31] on MWCNTs produced by arc-discharge method resulted in electron mean free path of 30 µm. In another experiment, Li [32] reported electron mean free path of 25 µm and resistance 34.4 Ω for an individual MWCNT with diameter 100 nm. Wei [33] demonstrated that an arc- discharge-grown CNT exhibits current-carrying capacity of 10 GA/cm2. As alluded to in Section 2.5, arc-discharged CNTs are generally of the highest quality. However, as the CNT growth temperature is lowered to below 1000°C using other techniques such as chemical vapor deposition (CVD), defects are introduced, which degrade electrical conduction and current-carrying capacity. Chai [34] conducted a comprehensive characterization to analyze electron mean free path and contact resistance of horizontally grown MWCNTs at 850°C on a SiO2 substrate using PECVD, where CNTs with three different diameter distributions were produced by varying catalyst thickness. The reported results are highlighted in Fig. 3.4 [34].

Chapter 3

Figure 3.4(a) (a) Resistance of MWCNT as a function of length. (b) Mean free path and contact resistance (excluding quantum resistance) of MWCNT as a function of diameter [34].

The results of length dependence of MWCNT resistance given in Fig. 3.4(a) are consistent with ohmic conduction. Fig. 3.4(b) shows an electron mean free path of 0.55 µm for MWCNTs with diameters around 30 nm, compared with 25 µm for a 100 nm diameter MWCNT produced by arc-discharge method [28]. The CNT contact resistance given in Fig. 3.4 (b) has an expected diameter dependence. These results strongly suggest that the MWCNTs used in this experiment exhibited ohmic transport as opposed to near-ballistic transport, which can be attributed to structural degradation due to lower growth temperature. For MWCNTs with diameters around 12 nm, the total contact resistance from Fig. 3.4(a) is ~27 kΩ, which is 60~70% of the total CNT resistance. Therefore, it is critical to understand CNT contact resistance and factors contributing to it in order to enhance CNT interconnect performance. A SWCNT with ballistic conduction and no scattering or tunneling at SWCNT-Metal interface exhibits contact resistance equal to the quantum resistance R0 = h/2e2 = 6.45 kΩ at each contact [35], where h is Planck’s constant and e electronic charge. However, in a real system, contact resistance depends on work- function difference between CNT and contact metal, contact configuration (end-contact versus side-contact) [36], wettability of contact metal[37] , and interface nanostructure [37].

Matsuda [36] simulated the effect of “end-contact” [36] and “side-contact” [38] on a single CNT shell using density functional theory (DFT). Fig. 3.5 shows the end-contact and side- contact configurations. The simulations were carried out on metal-graphene interface for the two configurations and then normalized to contact resistance per unit C atom at the CNT-metal interface for each configuration. The end-contacted configurations for Au,

Chapter 3

Cu, Pd, Pt, and Ti as contact metals used in the simulations are illustrated in Fig. 3.6. Quantum mechanical (QM) calculations were carried our using SEQQUEST simulation tool [36], a fully self-consistent Gaussian-based linear combination of atomic orbitals (LCAO) DFT method, for energies around the Fermi level to obtain I-V characteristics and interface resistance [36]. Fig. 3.7 shows the I-V behavior and resistance at metal- graphene interface for the end-contact configuration.

(a) (b)

Figure 3.5 (a) End-contacted CNT-metal interface. (b) Side-contacted CNT-metal interface [37].

Chapter 3

Figure 3.7 (a) I-V behavior for end-contacted metal-graphene interfaces. (b) Resistance versus voltage plot for the same interfaces [36].

Simulations of side-contacted metal-graphene interface were carried for Au, Cu, Pd, Pt, and Ti [38]. The model consists of a unit cell of graphene with metal atoms placed on it, as illustrated in Fig. 3.8(a). As for the end-contact configuration, the LCAO DFT method was used to calculate the binding energy versus metal-graphene distance and interface resistance, as shown in Figs. 3.8(b) and 3.8(c). From these results, one can conclude that Ti and Pd have the strongest bonding to graphene and, not surprisingly, the lowest contact resistance. Based on these results on metal-graphene interface, properties of the side-contacted metal-SWCNT interface are obtained as follows.

(d)

Chapter 3

More realistic metal-nanotube atomic clusters were used to simulate the side-contacted metal-SWCNT interface. The models chosen for Ti and Pd [38] consist of a metallic (7,7) CNT, with diameter of 9.6 Å, and a semiconducting (13, 0) CNT, with diameter 10 Å, each sandwiched between a pair of metal triple layers (Ti or Pd). The periodicity of each metal layer is preserved, as well as the optimized geometry and minimum-energy distance obtained from the metal-graphene calculations, as illustrated in Fig. 3.8(a) and (b). However, 1D periodic boundary condition is imposed on the metal-CNT system as opposed to 2D for graphene. The schematic and calculation results are shown in Fig. 3.9. As in the metal-graphene case, Ti has the lowest resistance to side-contacted metallic SWCNT (7, 7) and the conduction is ohmic as demonstrated by the linear I-V behavior.

(e) (f)

Figure 3.9 (a)-(d) Cross-sectional schematic of models for Ti-(7, 7)CNT, Pd-(7, 7)CNT, Ti-(13, 0)CNT, and Pd-(13, 0)CNT interfaces. (e) Calculated I-V behaviors. (f) Contact resistance per nm of CNT [38].

Chapter 3

From calculations of contact resistances for both configurations of metal-graphene interface, the contact resistance values normalized per surface C atom at the interface were obtained and used to calculate the contact resistance of metal-CNT interface [36]. The values given in Table 3.1 predict that end-contacted Ti-CNT interface has in the lowest contact resistance overall.

Table 3.1 Normalized contact resistance per surface C atom [36]. Contact configuration Ti Pd Pt Cu Au “end-contacted” 13.3 17.8 18.6 31.7 23.3 per unit cell (kΩ) “end-contacted” 106.5 142.4 148.5 253.5 186.8 per C atomb (kΩ) “side-contacted” 938 8566 34689 630352 1261002 per C atomc (kΩ) a For comparison, the contact resistance is averaged over the C atoms (eight atoms) at the interface. b Per surface C atom (16 atoms) at the interface. c Per surface C atom

However, it is not realistic to expect a perfect end-contact to be experimentally fabricated. Therefore, Matsuda [36, 38] proposed a hybrid form of contact in which a small area on the side of CNT is in contact with metal. The total contact resistance is obtained by parallel circuit resistance summation which is dominated by the lower of the two resistances. Fig. 3.10 shows the hybrid contact configuration in which d is the length of side contact between metal and CNT.

Figure 3.10. Hybrid contact configuration proposed by Matsuda where d is the length of side- contact between metal and CNT [36].

As an example to demonstrate the minimal impact of such hybrid configuration on contact resistance of metal-CNT, Matsuda [36] carried out a calculation for a (10, 10) CNT 80

Chapter 3 in contact with Pd. A (10, 10) CNT has 40 atoms at its end and 162 atoms on the side with length 1 µm, diameter 1.4 nm, and side-contact length d = 10 nm. Using the normalized contact resistance values from Table 3.1, a total contact resistance of 3.3 kΩ is obtained for the hybrid configuration, compared to 3.5 kΩ for end-contact and 52.87 kΩ for side- contact for the Pd - (10, 10) CNT interface [36]. Thus, hybrid-contact seems to be a reasonable description as well as experimentally feasible solution for metal to make contact with CNT.

Lim [37] fabricated hybrid top- and side-contacts on a bundle of vertically aligned MWCNTs in via test structures to analyze effect of contact metal work function and wettability on contact resistance of CNT. The test structure is an array of vias with diameter 100 nm and aspect ratio 2. Bottom electrode consists of a stack of Ti (10 nm)/ TiN (100 nm) layer as Ti yields a low-resistance ohmic contact with CNT [36, 38]. CNTs were grown on Ti using 3 nm Ni film as catalyst in PECVD process at 600°C. Thus, the as-grown base contact of all CNTs is end-bonded with Ti [37]. For top contact, a number of metals were selected with work functions ranging from ~4.0 eV to 5.7 eV, covering that of CNT between 4.5 eV and 5.1 eV. The list of metals is given in Fig. 3.11(a). Each of these metals was deposited as top contacts on CNT vias using e-beam evaporation [37]. Electrical characterization was first conducted on vias with Ti top contact to extract the CNT-Ti base contact resistance, which was then subtracted from the contact resistance of other metal-CNT-underlayer Ti contact resistance to yield the metal-CNT top-contact resistance. Figs. 3.11(a) and (b) show the extracted metal-CNT contact resistance versus the metal work function. The range of CNT work function is marked by the grey-shaded area. Overall, the data in Fig. 3.11(a) do not suggest a clear correlation between contact resistance and work function difference between metal and CNT.

At first glance, metals with small work function difference with CNT seem to yield relatively lower contact resistance, as shown in Fig 3.11(a) and (b). However, there are exceptions, such as Ag and Pd, with metal-CNT work function differences about the same as Ti, but a much higher contact resistances [37]. Thus, work function difference is probably not the primary factor contributing to contact resistance, while other factors such as wettability, bonding at interface, and presence of interfacial layer might be more important. Based on the schematics shown in Figs. 3.11(c) and (d), Lim [37] studied the wettability of metals to CNTs using experimental findings by Zhang [39], in which wettability of Ti, Ni, Pd, Au, Al, and Fe on SWCNTs, grown using CVD at 900°C, were 81

Chapter 3 analyzed using e-beam evaporation and TEM. Metals which form continuous coating on SWCNT surface exhibit good wettability and the metals forming non-continuous or grainy deposits have poor wettability, as illustrated in Fig. 3.12.

Figure 3.11 (a) Measured metal-CNT contact resistance versus metal work-function [37]. (b) Metal-CNT contact resistance versus work function of selected metals with work functions between 4.2 – 5.7 eV [37]. (c) Schematics of good wettability metal-CNT contact [37]. (d) Schematics of poor-wettability metal-CNT contact [37].

Figure 3.12 TEM images of 5 nm metal films deposited on surface of SWCNT [39]. Ti is observed to have best wettability on SWCNT surface among all other metals, as shown in Fig. 3.12. Ni and Pd exhibit moderate wettability, while Au, Al, and Fe show poor wettability on SWCNT. Wettability is used to analyze performance of side contacts

Chapter 3 formed by adhesion of metal to SWCNT surface due to van der Waal force. On the other hand, end contacts are formed by chemical bonding between carbon and metal atoms. The affinity of metal to form a covalent bond with carbon is correlated with the number of d-orbital vacancies in metal [39]. Au, Ag, and Cu have one d-orbital vacancy each and negligible affinity to bond with carbon [39]. Ni and Fe, with 2 and 4 d-orbital vacancies, respectively, have finite solubility in carbon over a selected temperature range and exhibit moderate affinity for carbon [39]. Ti, Nb, and Cr, with 8, 7, and 6 d-orbital vacancies, respectively, form metal carbides with stable covalent bonds [39]. Thus, for a metal to yield a low-resistance ohmic contact to SWCNT, the data seem to point to good wettability, high d-orbital vacancies, and stable bonding with carbon [39].

Based on Zhang’s [39] experimental findings on SWCNTs, Lim [37] analyzed wettability and chemical bonding at metal-MWCNT contacts using his results on contact resistance versus metal work function. Table 3.2 lists the properties of metals from Fig. 3.11(b), in ascending order of highest valence d-orbitals. One should note that Lim’s data were for end contacts, where d-orbital vacancy might play a role, while Zhang’s data were for side contacts. Ti, with 8 d-orbital vacancies, good wettability, and a work function difference of 0.22 eV, forms a stable bond at CNT end contact. And Ti yields the lowest contact resistance to CNT as shown in Fig. 3.11(b), similar to Cr, with 6 d-orbital vacancies and 0.05 eV work function difference. Whereas, Cu and Au have only one d-orbital vacancy each, poor wettability, and weak or no bonding to CNT. Their work functions lie in the range of CNT work function and they exhibit similar contact resistance to CNT, as shown in Fig 3.11(b), but higher than those for Ti and Cr. Pd, Pt, and Ni have two d-orbital vacancies each and moderate wettability to carbon. Their work functions are higher than that of CNT and they exhibit a nearly linear dependence of contact resistance on work function, as shown in Fig 3.11(b), but higher than those for Cu and Au, with one extra d- orbital vacancy. Hf has 8 unoccupied d-orbitals (same as Ti) but a relatively large work function difference of 0.65 eV with CNT, yielding the highest contact resistance among all the metals shown in Fig. 3.11(a). Mn and Nb have 5 and 7 unoccupied d-orbitals, respectively, and small work function difference with CNT. But they both exhibit much higher contact resistance than Ti and Cr. Fe has 4 d-orbital vacancies and shows poor wettability, but with a negligible work function difference with CNT a contact resistance comparable to Ti. Therefore, based on Lim’s findings [37], there does not seem to be a direct correlation among d-orbital vacancy, wettability, work function difference, and contact resistance for metal-MWCNT contacts, with the notable exceptions of Ti and Cr. 83

Chapter 3

Perhaps one should carry out separate analyses for side and end contacts. In the former cases, wettability can be used to contrast ohmic and tunneling contacts, as schematically illustrated in Fig. 3.11(c) and (d). Metals with good wettability form ohmic contact with CNT surface (side contact), while metals with poor wettability result in electron tunneling across the interface and yield relatively high contact resistance. Whereas for end contacts, d-orbital vacancy and work function difference could be the major contributing factors to various degrees.

Table 3.2 d-orbital vacancies and work functions of various transition and noble metals [37].

Element Outermost orbital Number of d orbital vacancies Work function (eV) Ti 3d 8 4.33 Cr 3d 6 4.5 Mn 3d 5 1.1 Fe 3d 4 4.5 Ni 3d 2 5.15 Cu 3d 1 4.65 Nb 4d 7 4.3 Pd 4d 2 5.25 Ag 4d 1 4.26 Hf 5d 8 3.9 Pt 5d 2 5.65 Au 5d 1 5.1

Lim [37] evaluated various contact metals to CNT including Cu which is a conventional IC interconnect material [40]. However, he did not include another important interconnect material, W [41], which has a work function of 4.65 eV, 6 unoccupied 5d- orbitals [42], good wettability [43], and forms a stable covalent bond with carbon [44]. Following Lim’s analysis [37] on work function difference and d-orbital vacancies, W is expected to form a low-resistance ohmic contact to CNT. Li [32] and Wei [33] studied experimentally the resistance and reliability of W contacts to CNT. The device consists of end-contacted electrical nanoprobes to an individual MWCNT prepared by arc-discharge method. It yielded a total resistance of 34.4 Ω and current-carrying capacity of 10 GA/cm2 for a 2.5 µm long MWCNT with diameter 50 nm. Arc-discharged CNT is expected to be

Chapter 3 of the highest quality compared with those grown with CVD methods, consistent with ohmic W contacts and the measured low total resistance.

3.3 DC Characteristics

Saito [45] reported a comprehensive electrical characterization of horizontal CNF (a form of MWCNT as described in Chapter 2) interconnect with W-deposited contacts on Au electrodes. Resistance and current-carrying capacity are characterized on four test configurations, suspended/supported CNF with/without W contacts. CNFs were grown on oxide substrate using Ni catalyst in PECVD process at 700°C with recipe described in section 2.4. After growth, CNFs were removed from substrate, suspended in iso-propyl alcohol (IPA), and subjected to sonication. This solution was drop-casted on an oxide substrate consisting of pre-fabricated patterned array of Au electrodes separated by various spacings [45]. Devices with only one single CNF bridging the Au pads were selected for this experiment. W was then selectively deposited on contacts using focused- ion-beam (FIB) with W(CO)6 as precursor on one set of supported and one set of suspended configurations [45]. Fig. 3.13 shows the schematic and corresponding SEM images of the four test-configurations described below.

Configuration 1: CNF suspended between two planar Au pads patterned on SiO2/Si substrate. The SEM image and schematic for resistance and current stressing measurements are shown in Fig. 3.13(a).

Configuration 2: CNF supported on SiO2 between two planar Au pads patterned on

SiO2/Si substrate. The SEM image and schematic for resistance and current stressing measurements are shown in Fig. 3.13(b).

Configuration 3: CNF suspended between two planar Au pads patterned on SiO2/Si substrate. The contacts of CNF on Au pads consist of W deposited with FIB. The SEM image and schematic for resistance and current stressing measurements are shown in Fig. 3.13(c). The SEM image shows a conformal coating of W on CNF with part of it in direct contact with the Au pad. Zhang [39] demonstrated that Au has poor wettability to CNT surface. Therefore, the total contact resistance is expected to come most from W-CNT contact. Further, from Lim’s findings [37], the CNT-Au interface, regardless of its quality, is not expected to impact the device performance.

Configuration 4: CNF supported between two planar Au pads patterned on SiO2/Si substrate. The contacts of CNF on Au pads consist of W deposited with FIB. The SEM 85

Chapter 3 image and schematic for resistance and current stressing measurements are shown in Fig. 3.13(d). As in Configuration 3, the contact resistance is due primarily to the W-CNF contacts.

Figure 3.13 Current-stressing experiments. (a) Configuration 1: CNF suspended on Au electrodes. (b) Configuration 2: CNF supported by SiO2 substrate. (c) Configuration 3: CNF suspended with W deposited on contacts. (d) Configuration 4: CNF supported by SiO2 substrate with W deposited on contacts. Upper frame in each figure shows SEM image of device from 75° tilted-angle view, and lower frame is electrical measurement schematic [45].

Initial electrical measurements were conducted to study the effect of W contacts on electrical characteristics of CNF test device. I-V sweep was carried out on devices with and without W contacts, as shown in Fig. 3.14. Zhang [39] and Lim [37] demonstrated that Au results in poor wettability to CNT surface and Yamada [46] confirmed tunneling

Chapter 3 at the CNF-Au interface. Both findings are consistent with the I-V behavior shown in Fig. 3.14(a). Fig. 3.14(b) shows ohmic characteristics for the CNF device with W-deposited contacts. Following Lim’s [37] analysis of wettability and work function along with Wei’s [32] experimental data, ohmic conduction across the W-CNF contact was successfully demonstrated.

Figure 3.14 (a) Typical I-V characteristics for Configuration 1 measured before current stressing. (b) Typical I-V characteristics for Configuration 3 measured before current stressing [45].

After confirming contact improvement with W depositions, multiple devices of each configuration were subjected to current stressing in a SEM chamber with base pressure of 10-6 Torr [45]. Constant current is applied in incremental progression and resistance of device is recorded after each stress cycle until CNF breakdown occurs. The resulting total device resistance versus stress current behavior before breakdown is shown in Fig. 3.15. For CNF without W contacts, the substantial decrease in total resistance from current stressing is due to contact resistance reduction, which can be attributed to physical changes in the nanostructure at the CNF-Au interfaces. After drop-cast, the initial interfacial geometry is expected to be rough due to weak attractive forces and poor wettability between CNF and Au, yielding an initial resistance over 1 MΩ. Current stressing supplies Joule heat to the materials, equivalent to thermal annealing, results in improved interfacial geometry and an effective decrease in tunneling barrier height. The experimental findings supports the tunneling barrier height reduction trend predicted by Yamada’s model [46]. CNF devices with W contacts are expected to show stable ohmic

Chapter 3 contacts and no change was observed for these devices with current stressing, as shown in Fig. 3.15(b). W deposition at CNF contacts yields fully optimized contacts, hence no further improvement by Joule heating stressing occurred. The results of Saito’s experiments [45] further support the metal work function and wettability analysis of metal-CNT contacts by Lim [37] and demonstrate that W is a suitable contact metal for ohmic conduction in nanocarbon interconnects.

Figure 3.15 (a) Resistance of CNF devices without W deposition as a function of stressing current after each stress cycle. Each symbol represents an individual device [45, 47]. (b) Resistance of CNF devices with W-deposited contacts as a function of stressing current after each stress cycle [45].

To study the effect of contact improvement on the reliability of suspended and supported CNF test devices, Saito [45] recorded the maximum current density at which CNF breakdown occurred. Constant current stressing was applied to 36 devices in all four configurations with various CNF lengths, and the results are shown in Fig. 3.16. The plot shows the maximum current-carrying density versus reciprocal CNF length for all four configurations. Generally, longer CNFs are prone to more defects in their nanostructure, which limit their current-carrying capacity. Another critical factor is dissipation of Joule heat [48]. Test devices in Configurations 1 and 3 are suspended and the overall heat dissipation is inferior to that in Configurations 2 and 4, where the oxide substrate in contact with the CNF provides an added path for the Joule heat to escape. Thus the current capacities of all supported devices are higher than those of suspended ones, as shown in Fig. 3.16, with the largest value 7 MA/cm2. Using a simple thermal transport model for analyzing measured data (indicated by solid black circles in Fig. 3.16), Kitsuki 88

Chapter 3

[47] determined that for suspended devices, breakdown occurred at the midpoint of the CNF between the Au electrodes, where the highest temperature is reached, was recorded [47]. The current-carrying capacity of supported CNFs can be further improved by employing a support material with higher thermal conductivity than SiO2 (1.3 W/mK)

[49], such as Al2O3 (12 W/mK) [49]. In summary, Saito’s results [45] demonstrated that the DC performance and reliability of horizontal CNF interconnects can be enhanced by improved contacts.

Following up on Saito’s work [45], Wilhite [43] conducted further studies on CNF interconnects with W contacts deposited using two different techniques. Sample preparation was the same as that described by Saito [45]. Side-bonded W contacts CNF bridging Au electrodes were formed using ion-beam-induced deposition (IBID) using a FIB system as in [45] and electron-beam-induced deposition (EBID) [43], respectively. The

W source for the former was W(CO)6, and for the latter WF6 precursor was introduced inside a SEM chamber [43]. The higher ambient pressure in the SEM chamber than that in FIB system can result in more impurities during depositions. The two types of W- deposited devices along with a reference Au/CNF device were subjected to current stressing to reveal the effect of W-deposited contacts. Fig. 3.17 shows a summary of results for three devices and the circuit model in the inset shows the resistance 89

Chapter 3 contributions from various interfaces present in the device structure [43]. The reference and IBID-W/CNF devices showed the same trends as that obtained by Saito [45], while similar resistance improvement in the EBID-W/CNF device was achieved by further current stressing [43].

Figure 3.17. Comparison of resistances of three CNF test devices under current stressing in vacuum. [43].

Devices with EBID-W and IBID-W contacts were subjected to TEM analysis to study the nanostructures at the W-CNF interfaces, with results shown in Fig 3.18. Device with IBID- W-deposited contacts displayed high purity W and abrupt interface as confirmed by energy dispersive spectroscopy (EDS) analysis shown in Fig. 3.18(b), with a small trace of Ga from the ion beam. On the other hand, the EBID-W-deposited device shown in Fig. 3.18(c) revealed small W grains and a much less abrupt interface, as well as significant concentrations of C and O impurities, attributed to high base pressure inside the SEM chamber. However, current stressing results in reduction of these impurities and increasing W grain size, as shown in Fig. 3.18(d). Nevertheless, W-deposited contacts by either technique resulted in contiguous W-CNF interfaces, confirming that W has a good wettability to CNF surface.

Chapter 3

3.4 RF Characteristics

From DC measurements, resistance of horizontal CNF interconnect can be obtained as described in the previous section. But interconnect performance is dependent on both resistance and capacitance [50]. In an IC, the interconnect network consists of conductors surrounded and separated by dielectric materials, giving rise to capacitance [50]. Further, at high frequencies, both capacitive and inductive behaviors could contribute to the overall interconnect impedance [51, 52]. Therefore, it is critical to characterize CNT and CNF interconnects in the RF range as well as DC.

RF transmission through a nanostructure requires a suitably designed test structure in which parasitic contributions are minimal, as signal transmission through the device under test (DUT) can be rather small. To achieve this, Madriz [53] designed and fabricated a two-port ground-signal-ground (GSG) test structure which was optimized for minimum parasitics to allow a precise study of signal transmission through the DUT. Further, S-parameter measurements without DUT (open test structure) were carried out prior to introducing the CNF along the signal path and repeating the measurements. Analysis of the de-embedded results were then performed [53-55]. The test structure layout shown in Fig. 3.19(a) was similar to that of Saito [45] but the ground plane was separated by oxide to minimize signal-to-ground coupling [53].

The test devices were obtained by drop-casting [45], followed by W deposition on contacts of devices having only a single CNF bridging the signal pads. SEM images of devices before and after W deposition are shown in Fig. 3.19(b) and (c), respectively. Either device was subjected to current stressing to minimize the total DC resistance as in [45]. Cross-sectional TEM analysis of W contacts shown in Fig. 3.18(b) revealed a conformal deposition of IBID-W on CNF surface, and together with robust DC behavior, suggesting that good wettability at the W-CNF interface can improve RF characteristics as well.

Chapter 3

(a) (b) (c)

Figure 3.19 (a) Schematics of layout and cross-section of GSG test structure. All labeled spacings in µm. D indicates pad-to-pad spacing ranging from 1 µm to 10 µm [54, 55]. (b) Drop-casted CNF bridging Au inner pads. (c) Test device after contact metallization with IBID-W.

RF measurements were conducted using a vector network analyzer (VNA) connected to customized GSG RF probes. A Line-Reflect-Reflect-Match (LRRM) calibration of the open test structure is carried out to remove any parasitics present in the VNA [56-58]. Following the approach used by Madriz [55], two port S-parameters of the open test structure are measured and a circuit model is constructed, as shown in Fig. 3.20(a). CPG is the capacitance between signal pad and ground, RPG represents conduction between signal pad and ground, as well as any other loss mechanisms in the SiO2 layer, CPP is the capacitance between signal pads, and RPP accounts for conduction and losses between signal pads, corresponding to the layout shown in Fig. 3.19(a). The extracted parameter versus frequency behaviors of the open test structure are shown in Fig. 3.20(b) and (c).

Below ~30 GHz, CPP and CPG are both nearly independent of frequency. Above 30 GHz, however, both decrease monotonically with frequency, suggesting that the test structure may contain an inductive component, perhaps from the signal pads, that has been

“lumped” into CPP and CPG.

(a) (b) (c)

Figure 3.20 (a) Circuit model of open test structure without CNF [53]. (b) Capacitive components in open test structure (c) Resistive components in open test structure.

Chapter 3

Figure 3.21 3D schematic of entire test structure showing various components and their corresponding model circuit elements.

The two-port S-parameters of the test structure with CNF bridging the signal pads and the corresponding circuit model are shown in Fig. 3.21, with CNF and its contacts represented by an admittance y(ω) = GF(ω) + jωCF(ω), where GF and CF are CNF conductance and capacitance, respectively, and GF  1/RF. Thus, y(ω) can be obtained by de-embedding using Y-parameters Y21OpenCircuit(ω) and Y21Total(ω), which are extracted from measured S-parameters of the test structures without and with CNF [54], respectively.

y(ω) = GF(ω) + jωCF(ω) = Y21OpenCircuit(ω) – Y21Total(ω) (3.1)

This procedure is repeated for CNF with W-deposited contacts.

The extracted CNF resistance and capacitance behaviors up to 50 GHz are shown in Fig. 3.22(b), with the corresponding DC I-V plots shown in Fig. 3.22(a) as reference. The impedance of CNF without W-deposited side contacts varies up to 70% across the frequency range from its DC value. Whereas CNF with W contacts yields a nearly constant resistance and a vanishingly small capacitance up to 50 GHz. Thus the impedance of the CNF device without W-deposited contacts shows significant variation with frequency, while the one with W-deposited contacts behaves like a constant resistor up to 50 GHz. This result demonstrates that the RF characteristics of the CNF test device are highly sensitive to the integrity of its contacts. W deposition at contacts results in stabilizing the contact by improving at CNF-electrode interface as demonstrated previously [43, 45], reducing the total DC resistance and virtually eliminating the frequency dependence of its impedance up to 50 GHz. Therefore, a CNF horizontal

Chapter 3 interconnect with W-deposited contacts can be modeled up to 50 GHz using a frequency- independent impedance consisting of only a constant resistive component with the device’s DC value.

Following Lim’s [37] and Zhang’s [39] analyses on work function difference, d-orbital vacancy, and wettability in section 3.2, along with Saito’s results [45] on contact improvement in Section 3.3, the RF behavior obtained here further confirms that W- deposition is suitable to form robust ohmic side contacts with horizontal CNF and thus enhances the performance of CNF/CNT interconnects for DC and RF applications. The following chapters will focus on experiments on CNT vias and metal-CNT end contacts, with analyses based on those presented in this chapter.

References

[1] J. Guo, M. Lundstrom, and S. Datta, "Performance projections for ballistic carbon nanotube field-effect transistors," Applied Physics Letters, vol. 80, pp. 3192-3194, Apr 2002. [2] P. Avouris, "Molecular electronics with carbon nanotubes," Accounts of Chemical Research, vol. 35, pp. 1026-1034, Dec 2002. [3] P. Avouris, "Carbon nanotube electronics," Chemical Physics, vol. 281, pp. 429-445, Aug 2002. [4] P. Avouris, R. Martel, V. Derycke, and J. Appenzeller, "Carbon nanotube transistors and logic circuits," Physica B-Condensed Matter, vol. 323, pp. 6-14, Oct 2002.

Chapter 3

[5] W. Hoenlein, F. Kreupl, G. S. Duesberg, A. P. Graham, M. Liebau, R. Seidel, and E. Unger, "Carbon nanotubes for microelectronics: status and future prospects," Materials Science & Engineering C-Biomimetic and Supramolecular Systems, vol. 23, pp. 663-669, Dec 15 2003. [6] P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, "Carbon nanotube electronics," Proceedings of the Ieee, vol. 91, pp. 1772-1784, Nov 2003. [7] A. Javey, J. Guo, D. B. Farmer, Q. Wang, D. W. Wang, R. G. Gordon, M. Lundstrom, and H. J. Dai, "Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics," Nano Letters, vol. 4, pp. 447-450, Mar 2004. [8] R. H. Baughman, A. A. Zakhidov, and W. A. de Heer, "Carbon nanotubes--the route toward applications," Science, vol. 297, pp. 787-792, Aug 2 2002. [9] Y. Chai, J. F. Gong, K. Zhang, P. C. H. Chan, and M. M. F. Yuen, "Flexible transfer of aligned carbon nanotube films for integration at lower temperature," Nanotechnology, vol. 18, Sep 2007. [10] S. C. Jun, J. H. Choi, S. N. Cha, C. W. Baik, S. Lee, H. J. Kim, J. Hone, and J. M. Kim, "Radio- frequency transmission characteristics of a multi-walled carbon nanotube," Nanotechnology, vol. 18, Jun 2007. [11] G. F. Close, S. Yasuda, B. Paul, S. Fujita, and H. S. P. Wong, "A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors," Nano Letters, vol. 8, pp. 706-709, Feb 2008. [12] N. Chiodarelli, A. Fournier, and J. Dijon, "Impact of the contact's geometry on the line resistivity of carbon nanotubes bundles for applications as horizontal interconnects," Applied Physics Letters, vol. 103, Jul 2013. [13] A. A. Vyas, F. Madriz, N. Kanzaki, P. Wilhite, X. H. Sun, T. Yamada, and C. Y. Yang, "Carbon Nanofiber Interconnect RF Characteristics Improvement with Deposited Tungsten Contacts," Journal of Nanoscience and Nanotechnology, vol. 14, pp. 2683-2686, Mar 2014. [14] Q. Cao, S.-J. Han, J. Tersoff, A. D. Franklin, Y. Zhu, Z. Zhang, G. S. Tulevski, J. Tang, and W. Haensch, "End-bonded contacts for carbon nanotube transistors with low, size- independent resistance," Science, vol. 350, pp. 68-72, Oct 2015. [15] A. G. Fedorov, S. Kim, M. Henry, D. Kulkarni, and V. V. Tsukruk, "Focused-electron-beam- induced processing (FEBIP) for emerging applications in carbon nanoelectronics," Applied Physics a-Materials Science & Processing, vol. 117, pp. 1659-1674, Dec 2014. [16] W. Mu, S. X. Sun, D. Jiang, Y. F. Fu, M. Edwards, Y. Zhang, K. Jeppson, and J. Liu, "Tape- Assisted Transfer of Carbon Nanotube Bundles for Through-Silicon-Via Applications," Journal of Electronic Materials, vol. 44, pp. 2898-2907, Aug 2015. [17] N. Srivastava, H. Li, F. Kreupl, and K. Banerjee, "On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects," IEEE Transactions on Nanotechnology, vol. 8, pp. 542-559, Jul 2009. [18] M. M. Shulaker, G. Hills, N. Patil, H. Wei, H.-Y. Chen, H.-S. P. Wong, and S. Mitra, "Carbon nanotube computer," Nature, vol. 501, pp. 526-530, Sep 2013. [19] S. M. Huang, X. Y. Cai, and J. Liu, "Growth of millimeter-long and horizontally aligned single-walled carbon nanotubes on flat substrates," Journal of the American Chemical Society, vol. 125, pp. 5636-5637, May 2003.

Chapter 3

[20] L. M. Huang, X. D. Cui, B. White, and S. P. O'Brien, "Long and oriented single-walled carbon nanotubes grown by ethanol chemical vapor deposition," Journal of Physical Chemistry B, vol. 108, pp. 16451-16456, Oct 2004. [21] D. Phokharatkul, Y. Ohno, H. Nakano, S. Kishimoto, and T. Mizutani, "High-density horizontally aligned growth of carbon nanotubes with Co nanoparticles deposited by arc- discharge plasma method," Applied Physics Letters, vol. 93, Aug 2008. [22] T. Watanabe, E. S. Sadki, T. Yamaguchi, and Y. Takano, "Electrical transport properties of small diameter single-walled carbon nanotubes aligned on ST-cut quartz substrates," Nanoscale Research Letters, vol. 9, Jul 2014. [23] L. X. Kang, Y. Hu, L. L. Liu, J. X. Wu, S. C. Zhang, Q. C. Zhao, F. Ding, Q. W. Li, and J. Zhang, "Growth of Close-Packed Semiconducting Single-Walled Carbon Nanotube Arrays Using Oxygen-Deficient TiO2 Nanoparticles as Catalysts," Nano Letters, vol. 15, pp. 403-409, Jan 2015. [24] T. Inoue, D. Hasegawa, S. Chiashi, and S. Maruyama, "Chirality analysis of horizontally aligned single-walled carbon nanotubes: decoupling populations and lengths," Journal of Materials Chemistry A, vol. 3, pp. 15119-15123, Apr 2015. [25] D. N. Yuan, L. Ding, H. B. Chu, Y. Y. Feng, T. P. McNicholas, and J. Liu, "Horizontally aligned single-walled carbon nanotube on quartz from a large variety of metal catalysts," Nano Letters, vol. 8, pp. 2576-2579, Aug 2008. [26] N. Patil, A. Lin, E. R. Myers, K. Ryu, A. Badmaev, C. W. Zhou, H. S. P. Wong, and S. Mitra, "Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes," Ieee Transactions on Nanotechnology, vol. 8, pp. 498-504, Jul 2009. [27] Y. Hu, L. Kang, Q. Zhao, H. Zhong, S. Zhang, L. Yang, Z. Wang, J. Lin, Q. Li, and Z. Zhang, "Growth of high-density horizontally aligned SWNT arrays using Trojan catalysts," Nature communications, vol. 6, 2015. [28] F. Yang, X. Wang, D. Q. Zhang, J. Yang, D. Luo, Z. W. Xu, J. K. Wei, J. Q. Wang, Z. Xu, F. Peng, X. M. Li, R. M. Li, Y. L. Li, M. H. Li, X. D. Bai, F. Ding, and Y. Li, "Chirality-specific growth of single-walled carbon nanotubes on solid alloy catalysts," Nature, vol. 510, pp. 522- 524, Jun 2014. [29] C. A. Santini, A. Volodin, C. Van Haesendonck, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Carbon nanotube-carbon nanotube contacts as an alternative towards low resistance horizontal interconnects," Carbon, vol. 49, pp. 4004-4012, Oct 2011. [30] F. Yan, C. Zhang, D. Cott, G. Zhong, and J. Robertson, "High-density growth of horizontally aligned carbon nanotubes for interconnects," Physica Status Solidi B-Basic Solid State Physics, vol. 247, pp. 2669-2672, Dec 2010. [31] C. Berger, Y. Yi, Z. L. Wang, and W. A. de Heer, "Multiwalled carbon nanotubes are ballistic conductors at room temperature," Applied Physics a-Materials Science & Processing, vol. 74, pp. 363-365, Mar 2002. [32] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, "Multichannel ballistic transport in multiwall carbon nanotubes," Physical Review Letters, vol. 95, Aug 2005. [33] B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and current carrying capacity of carbon nanotubes," Applied Physics Letters, vol. 79, pp. 1172-1174, Aug 2001.

Chapter 3

[34] Y. Chai, Z. Xiao, and P. C. Chan, "Horizontally aligned carbon nanotube bundles for interconnect application: diameter-dependent contact resistance and mean free path," Nanotechnology, vol. 21, p. 235705-8, May 2010. [35] J. Tersoff, "Contact resistance of carbon nanotubes," Applied Physics Letters, vol. 74, pp. 2122- 2124, Apr 1999. [36] Y. Matsuda, W.-Q. Deng, and W. A. Goddard III, "Contact Resistance for “End-Contacted” Metal− Graphene and Metal− Nanotube Interfaces from Quantum Mechanics," The Journal of Physical Chemistry C, vol. 114, pp. 17845-17850, Sep 2010. [37] S. C. Lim, J. H. Jang, D. J. Bae, G. H. Han, S. Lee, I. S. Yeo, and Y. H. Lee, "Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability," Applied Physics Letters, vol. 95, pp. 264103-3, Dec 2009. [38] Y. Matsuda, W.-Q. Deng, and W. A. Goddard, "Contact resistance properties between nanotubes and various metals from quantum mechanics," The Journal of Physical Chemistry C, vol. 111, pp. 11113-11116, July 2007. [39] Y. Zhang, N. W. Franklin, R. J. Chen, and H. J. Dai, "Metal coating on suspended carbon nanotubes and its implication to metal-tube interaction," Chemical Physics Letters, vol. 331, pp. 35-41, Nov 2000. [40] R. Rosenberg, D. C. Edelstein, C. K. Hu, and K. P. Rodbell, "Copper metallization for high performance silicon technology," Annual Review of Materials Science, vol. 30, pp. 229-262, Aug 2000. [41] D. W. Niles, W. Dauksher, and R. W. Kee, "Understanding and Modeling the Resistance of High Aspect Ratio FIB-Fabricated Tungsten Vias," Journal of Materials Engineering and Performance, vol. 19, pp. 900-905, Aug 2010. [42] E. W. Müller, "Work function of tungsten single crystal planes measured by the field emission microscope," Journal of Applied Physics, vol. 26, pp. 732-737, June 1955. [43] P. Wilhite, H. S. Uh, N. Kanzaki, P. Wang, A. Vyas, S. Maeda, T. Yamada, and C. Y. Yang, "Electron-beam and ion-beam-induced deposited tungsten contacts for carbon nanofiber interconnects," Nanotechnology, vol. 25, p. 375702-9, Sep 2014. [44] S. J. Wang, H. Y. Tsai, S. C. Sun, and M. H. Shiao, "Thermal stability of sputtered tungsten carbide as diffusion barrier for copper metallization," Journal of the Electrochemical Society, vol. 148, pp. G500-G506, Sep 2001. [45] T. Saito, T. Yamada, D. Fabris, H. Kitsuki, P. Wilhite, M. Suzuki, and C. Y. Yang, "Improved contact for thermal and electrical transport in carbon nanofiber interconnects," Applied Physics Letters, vol. 93, pp. 102108-3, Sep 2008. [46] T. Yamada, T. Saito, M. Suzuki, P. Wilhite, X. H. Sun, N. Akhavantafti, D. Fabris, and C. Y. Yang, "Tunneling between carbon nanofiber and gold electrodes," Journal of Applied Physics, vol. 107, pp. 044304-5, Feb 2010. [47] H. Kitsuki, T. Yamada, D. Fabris, J. R. Jameson, P. Wilhite, M. Suzuki, and C. Y. Yang, "Length dependence of current-induced breakdown in carbon nanofiber interconnects," Applied Physics Letters, vol. 92, p.173110-3, Apr 2008. [48] J. Yu, G. Liu, A. V. Sumant, V. Goyal, and A. A. Balandin, "Graphene-on-diamond devices with increased current-carrying capacity: carbon sp2-on-sp3 technology," Nano letters, vol. 12, pp. 1603-1608, Feb 2012.

Chapter 3

[49] S.-M. Lee, D. G. Cahill, and T. H. Allen, "Thermal conductivity of sputtered oxide films," Physical Review B, vol. 52, pp. 253-256, July 1995. [50] International Technology Roadmap for Semiconductors, 2013 edition, available at www.itrs2.net. [51] E. Fayneh, M. Yuffe, E. Knoll, M. Zelikson, M. Abozaed, Y. Talker, Z. Shmuely, and S. A. Rahme, "4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance," IEEE International Solid-State Circuits Conference, pp. 72-73. Jan 2016. [52] T. Yamada, F. R. Madriz, and C. Y. Yang, "Inductance in One-Dimensional Nanostructures," IEEE Transactions on Electron Devices, vol. 56, pp. 1834-1839, Sep 2009. [53] F. R. Madriz, J. R. Jameson, S. Krishnan, X. Sun, and C. Y. Yang, "Test structure to extract circuit models of nanostructures operating at high frequencies," IEEE International Conference on Microelectronic Test Structures, pp. 36-38, Mar 2008. [54] F. R. Madriz, T. Yamada, X. H. Sun, J. G. Nickel, and C. Y. Yang, "Frequency-Independent RC Circuit Model for One-Dimensional Carbon Nanostructures," IEEE Electron Device Letters, vol. 31, pp. 263-265, Apr 2010. [55] F. R. Madriz, J. R. Jameson, S. Krishnan, X. H. Sun, and C. Y. Yang, "Circuit Modeling of High-Frequency Electrical Conduction in Carbon Nanofibers," IEEE Transactions on Electron Devices, vol. 56, pp. 1557-1561, Aug 2009. [56] F. Purroy and L. Pradell, "New theoretical analysis of the LRRM calibration technique for vector network analyzers," IEEE Transactions on Instrumentation and Measurement, vol. 50, pp. 1307-1314, Oct 2001. [57] J. Pence, "Verification of LRRM calibrations with load inductance compensation for CPW measurements on GaAs substrates," ARFTG Conference Digest, 4pp, Nov 1993. [58] A. Davidson, K. Jones, and E. Strid, "LRM and LRRM calibrations with automatic determination of load inductance," ARFTG Conference Digest-Fall, pp. 57-63, Nov 1990.

4 Carbon Nanotube Vias: Test Structure Fabrication and Nanostructure Characterization

This chapter covers design considerations, layout, and fabrication of via test structures, as well as their nanostructure characterization. We begin with a narrative on design of experiment to extract performance and reliability parameters, literature survey, and issues related to fabrication and metrology equipment. This is followed by a step-by- step description of via test structure fabrication, CNT growth in vias, inter-CNT filler dielectric deposition, and polishing for subsequent top-contact metallization. High- resolution TEM and Raman analyses are employed to examine the nanostructures of CNT vias and individual CNTs, respectively.

100

Chapter 4

4.1 Test structure design considerations

The primary focus of this work is study of the performance and reliability of CNT vias with widths in range of 40 – 150 nm under DC operation. Based on the overview of interconnects presented in Chapter 1 and investigation of CNT horizontal interconnects along with metal-CNT contacts in Chapter 3, the DC performance of CNT vias can be defined by three fundamental electrical parameters – via resistance, CNT resistivity, and contact resistance. Via reliability is quantified using the maximum current-carrying capacity of the CNT-filled via [1]. The most commonly used test structure and methodology to characterize performance and reliability of a via is a cross-bridge Kelvin resistor (CBKR) and four-point probe (4PP) method, respectively [2], as shown in Fig. 4.1(a). 4PP measurement on a device under test (DUT) with CBKR is carried out by passing a constant current through the DUT using one pair of contacts and measuring the voltage across it using another pair of contacts. High-resistance voltage probes are used to minimize the current drawn by the probes. The ratio of measured voltage to applied current yields an accurate DUT resistance. The key in realizing such a structure is that the voltage is measured at the contacts directly across the DUT to eliminate contributions from stray series resistance. The CBKR test structure can also be used to determine the maximum current-carrying capacity.

Vollebregt [3-9] studied the performance and reliability of CNT vias with widths 13 µm using a CBKR test structure, where the experimental focus was growth of CNTs inside vias at BEOL-compatible temperatures. For CNT vias with sub-micron linewidths, fabricating such test structure would be difficult due to lithography and alignment challenges. Therefore, Chiodarelli [10-12] and van der Veen [13, 14] characterized sub-200 nm CNT vias using 4PP and a different measurement configuration, as shown in Fig. 4.2(b). The setup consists of measuring the voltage across two adjacent CNT vias using two probes, while passing a constant current through the same two vias. Assuming the vias are identical, the resistance of each via is obtained. However, the method is prone to errors as the CNT areal density and diameter distribution vary among vias and the contributions from via base contacts and metal underlayer are included in the measured resistance. Thus it is not suitable for via dimensions used in this work. Instead, we use a simple two-point probe (2PP) setup with a nanoprober on patterned vias, the schematic and SEM image of which are shown

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Chapter 4 in Fig 4.1(c) and (d), respectively. However, a 2PP structure inevitably consists of contributions from the nanoprobes, metal underlayer, and contacts between probes and metal pads, as well as CNT contacts and CNTs. Each of these contributions is addressed in both the test structure design and the method to analyze the measured results.

(a) (b) Voltage Voltage Voltage DUT Voltage CNT via Current Current Current Current

(c)

Ground Probe

CNT via

Via top Contact Probe

Figure 4.1 (a) Schematic of 4PP CBKR test structure [3]. (b) SEM image of 4PP measurement on a pair of metallized CNT vias [12]. (c) Schematic of 2PP measurement setup for direct probing of a single CNT via [15] and SEM image of the 2PP setup.

In an IC, a via connects two horizontal interconnect lines on adjacent levels separated by dielectric. Thus, a via and its top and bottom electrical contacts constitute the fundamental building block of BEOL architecture. A 2PP CNT via test structure is designed to resemble vias in an IC, where each via connects the underlayer metal to the top contact. As discussed in Chapter 2, a CNT via test structure with Cr underlayer yields CNT areal density ~5 x 1011/cm2 and narrow diameter distribution with median diameter of 13 nm. Therefore, a 300 nm Cr film is used as the underlayer to yield high CNT areal density with little contribution to the total resistance in the 2PP measurement.

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The choice of top-contact metal and contact configuration is critical to achieve low contact resistance. From discussion in Section 3.2, Matsuda [16, 17] and Lim [18] concluded that Ti in “end-bonded” or “hybrid-contact” configuration was the best contact metal for CNT due to their small work function difference, suitable wettability, and formation of stable metal-carbon bond at the interface. However, Ti tends to oxidize easily, giving rise to changes at the Ti surface and Ti-CNT interface that results in high contact resistance. Therefore, among the candidate metals examined in Section 3.2 and considering the process available to us, Pt is selected for via top-contact metallization, as it does not oxidize in air at room temperature [19] during sample transfer from metal deposition to nanoprobing. Powell [19] reported that Pt oxidizes in the 500°C to 1100°C range in the presence of oxygen. And the temperature of Pt contacts can significantly increase during current stressing measurements. This problem is mitigated by carrying out nanoprobing in a high-vacuum SEM chamber (base pressure 10-7 Torr) to minimize oxygen content in the ambient. Also as demonstrated by Matsuda [16, 17], the end-bonded contact configuration generally yields lower resistance than side-bonded contact. As shown in the Section 4.5, the Pt-metallized via top contacts indeed form end-bonded contacts to exposed CNTs inside the via, and together with the Cr underlayer and the CNTs, constitute a realistic model for the building block of an on-chip 3D interconnect network. Direct probing of individual CNT vias with different heights and widths allows us to analyze the measured resistance data to accurately extract various resistance contributions, as presented in Chapter 5. Thus, the 2PP method used in our work, with a simple test structure design and fabrication process, is well suited for the study of performance and reliability of CNT interconnect vias.

The choice of dielectric material in which CNT vias are patterned is critical to ensure structural and electrical integrity of CNT vias. CNT growth process, described in Section 2.5, is carried out at 700°C in ammonia plasma ambient. The dielectric material should be able to withstand ion bombardment in plasma and prevent diffusion of the underlayer Cr into the dielectric during CNT growth. Structural damage and/or diffusion of Cr into the dielectric compromises the electrical measurements of CNT vias by providing alternative conduction path. Graham [20, 21] and Vollebregt [3, 6-9] have reported that SiO2 can withstand ion bombardment in plasma and temperature up to

800°C. Therefore, SiO2 is employed as the dielectric surrounding the vias.

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Finally, to ensure that all CNTs inside each via make contact with the metal underlayer and can potentially participate in electrical conduction, it is critical to suppress any CNT growth from the dielectric sidewalls of via as such growth would limit the growth of CNTs from via base by reducing the diffusion of carbon precursors deep into the via. Therefore, a key design consideration is patterning vias with vertical sidewalls and using directional catalyst deposition to minimize deposition on via sidewalls.

Based on all these considerations, a test structure consisting of vias with square cross- sections and widths 150 nm, 120 nm, 90 nm, 60 nm, and 40 nm are designed, and the resulting fabricated mask for patterned via arrays is shown in Fig. 4.2.

150 nm

120 nm

90 nm

60 nm

40 nm

4.2 Via test structure fabrication

Standard silicon IC fabrication techniques such as vapor deposition, reactive etching, and lithography are employed in the test structure fabrication, with its process flow shown in Fig. 4.3. Such process flow was jointly developed with Zhou [22] and the fabrication was carried out at the Nanosystem Fabrication Facility (NFF) of Hong Kong University of Science and Technology. We start with a 100 mm diameter lightly doped

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Si wafer on which a 200 nm thermal oxide is grown in a furnace at 900°C. The oxide layer is used to isolate the via structure from the Si substrate. Subsequently, a 300 nm Cr film is evaporated on the oxide, which serves as the underlayer for CNT growth and also as the base electrode in 2PP measurements. The Cr evaporation is performed at 3 kW e-beam power in N2 ambient, with a base pressure of 10-8 Torr to ensure high-purity deposits. Top-view SEM image of Cr film after evaporation is shown in Fig. 4.4(a), revealing a grainy surface. The Cr film is then subjected to thermal annealing at 400°C in N2 ambient to reduce the film roughness by fusing some Cr grains. Voids between grain boundaries in the underlayer can result in catalyst diffusion into underlayer and suppress CNT growth. SEM image of the Cr surface after annealing in Fig. 4.4(b) shows improvement which is confirmed by reduction in overall sheet resistance from 3.6 Ω/□ before annealing to 3.1 Ω/□ after annealing.

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Figure 4.3 Process flow for via test structure fabrication.

(a) (b)

Figure 4.4 Top-view SEM images of Cr underlayer (a) after deposition and (b) after annealing at 400°C.

The next step is deposition of a 150 nm SiO2 film using PECVD process with SiH4 and

O2 precursors at 425°C, 110 mTorr pressure, and 100 W plasma power. The film thickness is chosen to yield the smallest height to width aspect ratio of 1 for vias with the largest width of 150 nm. Previous reports by Awano [23] on vias with similar dimensions had an aspect ratio of less than 1, which is not representative of IC dimensions with aspect ratios in the 15 range [1]. The mask shown in Fig. 4.2 is then used to pattern the vias with Process 1a shown in the flow diagram in Fig. 4.3 and described as follows. In first step, an e-beam lithographic technique is used to transfer the pattern on resist, which is then used as a mask to etch vias in the dielectric. A 300

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Chapter 4 nm resist film is spin-coated on the entire wafer and subjected to baking at 180°C for 2 minutes to evaporate the excess resist. After baking, the resist film is irradiated by the e- beam using the mask shown in Fig. 4.2, where the area of resist under each patterned via is exposed to e-beam, weakening the resist polymer and making it soluble in organic solvents. The wafer is then soaked in amyl acetate solution to etch the resist from e- beam exposed regions. This process transfers the via pattern from mask to the resist film, to be used as a mask for subsequent via etching in the SiO2 layer underneath. The cross-section of resist film at the end of this process is shown in Fig. 4.5(a).

(a) (b)

Figure 4.5 (a) Cross-sectional SEM image of resist film after developing. (b) Cross-sectional SEM image of a 60 nm CNT via with tapered profile.

Etching of vias in the dielectric is carried out using reactive ion etching (RIE) with CHF3 and O2 as reactants and at 935 W plasma power and 130 W substrate bias power. The etch selectivity ratio of resist to oxide is 1.36. Therefore, the reactants etch the resist mask faster than the dielectric and results in the top region of vias getting overexposed to reactants and causing lateral etching. This results in vias with tapered sidewalls as shown in the cross-sectional SEM image in Fig. 4.5(b). Tapered sidewalls are in violation of our design criterion set forth in Section 4.1, as catalyst film can easily coat the tapered sidewalls during the deposition process, resulting in CNT growth from the sidewalls. In order to achieve a vertical via profile, a layer of a-Si which has etch selectivity ratio of 1:20 to oxide is used as a hard mask to prevent overexposure of the top region of vias to reactants, is employed in Process 1b illustrated in Fig. 4.3 and described below.

A 50 nm a-Si film is deposited on top of a 100 nm SiO2 layer to maintain a 150 nm total thickness of dielectric and hard mask stack. After resist transfer as in Process 1a, the e- beam resist is first used as a mask for a-Si etching, using ICP with SF6 and O2 as etchants at 900 W plasma power and 100 W substrate bias. Subsequently, SiO2 etching is performed using the same recipe as in Process 1a. The cross-sectional SEM images of 60 nm and 40 nm vias are shown in Fig 4.6. By introducing a-Si layer which prevents

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Chapter 4 overexposure of top region of via to etchants, vertical profiles are obtained for vias with width 150 nm to 60 nm. The resulting via height is ~ 130 nm implying that a 20 nm layer of a-Si is consumed during oxide etching. However, some 40 nm vias cannot be fully etched down to the Cr underlayer, as shown in section 4.6(b). To overcome such under- etching, another sample is prepared with a thinner SiO2 layer (50 nm) and reduced a-Si thickness (40 nm) to fabricate 40 nm vias on a separate wafer. Same etch process is used on this sample which yielded 40 nm vias with 80 nm high vertical sidewalls, as confirmed by the cross-sectional TEM images presented in Section 4.6.1. All samples with patterned vias are subjected to HF rinse to remove any native oxidation on exposed underlayer Cr before catalyst deposition.

A Ni film is deposited on the entire sample using e-beam evaporation with base pressure of 10-7 Torr and 6 kW e-beam power. The optimized recipe for CNT growth in Section 2.5 using 4 nm thick Ni film is used for both the 60 ~ 150 nm (A) and 40 nm via (B) samples. A summary of the two via samples is presented in Table 4.1.

(a) (b)

a-Si

Figure 4.6 (a) Cross-sectional SEM image of 60 nm vias showing vertical sidewalls. (b) Cross- sectional SEM image of an under-etched 40 nm via.

Table 4.1. Summary of via samples prepared for CNT growth. Specification Sample A Sample B Via height or depth 130 nm 80 nm Via width(s) 60 nm, 90 nm, 120 nm, 150 nm 40 nm Catalyst, film thickness (nm) Ni, 4 nm Ni, 4 nm

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4.3 CNT growth in vias

CNTs are grown in the via structure using the optimized PECVD recipe developed on unpatterned substrates, as discussed in Section 2.5. The duration for CNT growth in vias is determined using the CNT growth rate on an unpatterned Cr substrate. A blanket Ni/Cr film stack is deposited using a magnetron sputtering system prior to CNT growth with PECVD for 10 minutes. The cross-sectional SEM image of a typical growth is shown in Fig. 4.7(a), revealing an average CNT height ~1 µm which corresponds to CNT growth rate of ~100 nm/min. Using this growth rate obtained from unpatterned substrate, the time for CNT growth inside vias is adjusted to 90 seconds to target 150 nm CNT height in sample A (60150 nm wide vias) and 60 seconds for 100 nm height in sample B (40 nm vias). Targeting CNT length taller than via depth ensures that CNTs inside vias are exposed after polishing to remove stray CNTs grown on the oxide surrounding vias. And the exposed CNTs can then make end-bonded contact with metal subsequently deposited on top of the via.

(a) (b) (c)

0.9~1 µm

Top-view SEM images of samples A and B after CNT growth are shown in Fig. 4.7(b) and (c), respectively. CNT growth occurs in vias and on top of oxide as Ni is uniformly evaporated across the entire sample including inside vias. Top-view SEM images reveal the presence of voids between CNT vias. To ensure robustness and vertical alignment of CNTs, the voids need to be filled with an electrically insulating material, which also serves to prevent diffusion of metal inside the via to avoid electrical short of top contact with the Cr underlayer. Dielectric filler also provides mechanical stability for CNTs in via so that they can withstand subsequent ion milling/polishing. The process to deposit dielectric and surface polishing is discussed in the next section.

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4.4 Dielectric fill and polish

Deposition of dielectric to fill the vias after CNT growth is a key step in the via fabrication process, and has a direct impact on the performance, reliability, and integrity of the subsequent electrical measurements. Dielectric filling in CNT vias serves multiple purposes such as filling the voids in CNT vias to provide a barrier to metal diffusion during top-contact metal deposition, creating support and adhesion to CNTs inside vias for them to withstand polishing, and facilitating dissipation of heat generated from Joule heating of CNTs during current stressing. Taking these purposes into accounts, we considered using either spin-on-glass (SOG) [20, 21] or aluminum oxide (Al2O3) [24], which have been widely reported as dielectrics in CNT vias. Al2O3 has a thermal conductivity of 13 W/mK compared to 1.2 W/mK for SOG. And Chiodarelli [10] and van der Veen [13] have successfully demonstrated conformal deposition of Al2O3 in CNT vias using atomic layer deposition (ALD) process.

Therefore, Al2O3 is chosen for as the via filler material for this work.

The CNT vias in samples A and B are subjected to an ALD process in a thermal CVD reactor with trimethylaluminum (TMA) as the Al precursor and distilled water as the

O2 precursor at 300°C substrate temperature. TMA and O2 are introduced and evacuated from the reactor in a cyclical manner, with a resulting Al2O3 deposition rate of ~1 Å/cycle [25]. Top-view SEM images shown in Figs. 4.7(b) and (c) reveal an average void width of 15 nm between adjacent CNTs. ALD process results in conformal deposition and hence an Al2O3 layer thickness of at least half the void width, 7.5 nm, can completely fill the void. However, to ensure that the voids in all vias are completely filled, a 10 nm target thickness is chosen for 100 ALD cycles to deposit Al2O3 on the two samples. Top-view SEM and cross-sectional TEM images of the resulting CNT vias are shown in Fig. 4.8, revealing void free structures. The TEM image in Fig. 4.8(b) also show that the Cr underlayer protrudes into the via during the CNT growth process at 700°C, further justifying the need for dielectric filler before metallization and electrical characterization.

The images in Fig. 4.8 also reveal that the as-grown CNTs are taller than the via height and covered with Al2O3. A polishing process is then needed to planarize the sample surface and to remove the excess Al2O3 as well as to expose the CNTs inside vias. These CNTs, having exposed graphitic shells from the removal of catalyst particles at their tips, can make contacts with nanoprobes directly or through deposited metal in an end-

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Chapter 4 bonded configuration. Sample A consisting of vias with various widths will be electrically characterized to reveal width dependence on CNT via resistance, whereas sample B containing only 40 nm wide vias will undergo measurements to determine resistance dependence on via height to yield contact resistance and resistivity. Therefore, sample A is polished using ion milling at a glancing angle to prepare CNT vias with a fixed height. Ion milling is carried out in high-vacuum with 10-7 Torr base pressure in a dual-beam SEM/FIB chamber. The accelerating voltage of FIB is maintained at 10 kV with a beam current of 1.7 nA for milling the sample surface. The top-view SEM images of CNT vias after ion milling are shown in Fig. 4.9, with exposed CNTs inside vias visible in the image in Fig. 4.9(b).

(a) (b)

a-Si hard mask

SiO2 Al2O3 sidewall

Figure 4.8 (a) SEM image of CNT vias in sample A after Al2O3 filling. (b) Cross-sectional TEM image of a 60 nm CNT via after deposition of a 10 nm Al2O3 layer.

(a) (b)

Ion milled Patch of vias

Figure 4.9 (a) Low-magnification view of sample A. (b) Top-view SEM image of an array of 60 nm via after ion milling.

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Sample B is subjected to mechanical polishing at an angle to fashion a wedge structure with a ~1° angle. It creates vias of multiple heights on the same sample which can then be measured to yield the height dependence of CNT via resistance. Mechanical polishing is performed using SiO2 nanoparticles as slurry. The cross-sectional schematic and top-view SEM image of sample B after polishing are shown in Fig. 4.10. Both samples are now ready for nanoprobing directly or for top-contact metallization as presented in the next section.

(b) (a)

Figure 4.10 (a) Cross-sectional schematic of CNT via wedge structure with varying height h. (b) Top-view SEM image of 40 nm CNT vias on wedge structure with arrow indicating direction of wedge.

4.5 CNT via top contact metallization

The final step in CNT via fabrication process is metal deposition on vias to realize end- bonded contacts for CNTs inside vias. From design considerations in Section 4.1, Pt is chosen as the top via contact material. Selective deposition of Pt contacts on individual CNT vias is made using electron-beam-induced deposition (EBID) process carried out in a SEM chamber. The most common precursors reported for Pt deposition are

Trimethyl(methylcyclopentadienyl)platinum(IV) (MCP) C9H16Pt and chloroplatinic acid

(CPA) H2PtCl6 [26]. CPA is a solution and its dissociation by e-beam can result in HCl byproduct which can cause erosion of sample and also damage the internal surface of the deposition chamber. MCP is an organometallic precursor and can result in stray a-C byproduct deposition. Therefore, to avoid damage to the sample, MCP is chosen for the EBID-Pt process.

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Each of samples A and B is introduced in the SEM chamber and allowed to degas to remove air molecules adsorbed on the surface. The chamber is then subjected to sub- atmospheric air plasma to remove stray a-C from the sample surface and chamber walls. The plasma cleaning process can be augmented by irradiating an area on the sample with e-beam for a few minutes to ensure no residual a-C remains. Subsequently, EBID-Pt depositions are made on 60 nm vias on sample A, and on 40 nm vias on sample B at five different heights along the wedge. Deposition areas of 90 x 90 nm and 70 x 70 nm are targeted for 60 nm and 40 nm vias, respectively. EBID-Pt deposits are formed at 10 kV accelerating voltage by using the e-beam to dissociate the precursor molecules and to guide the dissociated products to pre-defined locations. SEM images of selective deposited contacts on individual CNT vias are shown in Fig. 4.11(a)-(d), which confirm that Pt contacts are indeed made selectively on individual vias and each deposit is confined at the target without overlapping adjacent vias.

(a) (b)

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4.6 Nanostructure characterization

After top-contact metallization, the nanostructure of CNT vias is characterized to confirm their structural integrity, as well as to examine the metal-CNT interfaces. Cross- sectional TEM and energy-dispersive x-ray spectroscopy (EDS) are used to study CNT via nanostructure, while Raman spectroscopy is employed to quantify defects and to estimate the electron mean free path, which can infer the type of electron transport mechanism through CNTs.

4.6.1 Electron microscopic analyses

Cross-sectional TEM imaging is performed on vias with and without top-contact metallization to analyze their nanostructure. TEM image for a 60 nm via after Al2O3 deposition shown in Fig. 4.12(a) reveals that the Cr protrusion is limited to less than half the via height. The Al2O3 layer is shown to be uniformly and conformally deposited around CNTs and fills the inter-CNT voids. As a result, diffusion of Pt inside the via is not evident from the TEM image shown in Fig. 4.12(b), which also reveal a CNT embedded in Al2O3 filler making contact with the Pt cap. Thus, CNTs inside via form end-bonded via top contact with Pt and via base contact with Cr. Such contacts with metals were demonstrated by Matsuda [16, 17] and Lim [18] to yield lower contact resistance compared to side-bonded contacts.

(a) (b)

EBID-Pt CNTs Al2O3 Al2O3

a-Si a-Si a-Si a-Si SiO2 SiO2 SiO2 SiO2 CNT

60 nm Cr 40 nm Cr

Figure 4.12 (a) Cross-sectional TEM image of 60 nm vias before polishing. (b) Cross-sectional TEM image of 40 nm via with EBID-Pt “end-bonded” top contact.

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Fig. 4.12(a) shows that the a-Si region is grainy as opposed to as-deposited amorphous structure evident in Fig. 4.6(a). It has been reported that a-Si undergoes recrystallization at temperatures > 500°C [27], which is experienced by both samples A and B during CNT growth at 700°C. Therefore, the grainy region is likely to be polycrystalline Si formed due to recrystallization of a-Si. Polycrystalline Si has been reported to readily react with Ni to form electrically conductive NiSi [28, 29] which can compromise the electrical integrity of the test structure. Further, it is unclear if the CNT base is on the surface of the protruded Cr or at the bottom of the via. Therefore, elemental analysis is needed to determine the locations of various components inside the via. Energy dispersive x-ray spectroscopy (EDS) is carried out on the cross-section of a 60 nm via, with results shown in Fig. 4.13. The elemental maps confirm that Ni is detected only inside the via in the form of catalyst particles on CNT tips, and not in the Si or oxide regions, thus ruling out any NiSi formation. The elemental map of Cr shows that Cr is confined below the SiO2 layer outside the via and below CNTs inside. Thus no Cr diffusion into either SiO2 or Al2O3 occurs. Carbon signal is traced all the way down to the via bottom through the protruded Cr, which confirms that the CNT base is not on the surface of the protruded Cr underlayer. This last finding is critical to an accurate determination of CNT height inside via, which can now be equated to the via height. Based on these results, a model of CNT growth inside vias is given in Figure 4.14.

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Fig. 4.14 Model for CNT growth inside via. The substrate temperature is ramped up to 650°C, at which carbon precursor C2H2 is introduced. Prior to flow of C2H2 at 650°C (Stage I), the deposited Ni film is dewetted forming catalytic particles for the reaction. In Stage IIa, when the temperature is being ramped up to 700°C, the Cr underlayer softens and rises inside the via due to capillary force while tip-growth of CNTs continues (Stages IIb). Such CNT growth through the protruded Cr is somewhat similar to the Ni/Cr liftoff during growth observed by Hermann [30-33].

TEM analyses can also reveal the nanostructure of CNTs inside vias and suggest possible electron transport mechanism based on it. From Fig. 4.12(a), the internal structure of CNTs show a “bamboo-shaped” configuration, typical of CNFs and similar to the one observed on unpatterned substrate, as presented in Section 2.5. Therefore, based on the understanding of CNT nanostructures outlined in Section 2.3, such apparent structural discontinuities could lead to variations in chiral and translational vectors along the CNT length [34], hence introducing more scattering events for electron transport. Thus the resulting electron mean free path is expected to be significantly smaller than the CNT length, and ohmic conduction most likely occurs. To quantify electron mean free path, analysis of Raman spectra is presented next.

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4.6.2 Raman spectral analysis

Raman spectroscopy has emerged as an effective technique in analyzing the structure of nanocarbons. Dressellhaus [35-43] and Vollebregt [44] have extensively characterized CNTs using Raman spectroscopy to reveal long-range order and determine electron mean free path. To obtain similar knowledge for our as-grown CNTs, Raman analysis is performed for samples prepared at three different growth temperatures.

The normalized spectra of CNTs with respect to G-band is shown in Fig. 4.15, where G- band corresponds to the active mode of graphitic material, D-band indicates presence of defects, and G’ is the second harmonic of D-band. The physical origin of the D-band is attributed to graphitic shell terminations on the CNT outermost wall that result in the bamboo-like structure shown in Fig. 4.12(a) [44-57], missing C atoms, and presence of heptagons in hexagonal honeycomb lattice [35,58-60]. These defects contribute to electron scattering and result in reduction of electron mean free path. The intensity ratio of D-band to G-band can be used to estimate the defect density and electron mean free path inside the CNT [3,5,8,44]. A similar approach is employed here to estimate the electron mean free path of our as-grown CNTs on unpatterned substrates.

Fig. 4.15 Raman spectra of CNTs grown at three different temperatures. The signal intensity in each plot is normalized to the G-band peak.

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From the intensity of D and G peaks, electron mean free path can be obtained [8].

퐼퐷 퐶(휆) = , (4.1) 퐼퐺 퐿푎

where C(λ) = 4.4 nm is a fitting parameter for graphite and La is a measure of long-range order in the material or equivalently, its electron mean free path. La is obtained for CNTs grown at the three temperatures with results summarized in Table 4.2.

Table 4.2 Electron mean free paths for as-grown CNTs from their Raman data.

CNT growth temperature (°C) ID/IG ratio La (nm) 500 0.98 4.4 600 0.90 4.8 700 0.85 5.2

As expected, the results given in Table 4.2 reveal that the mean free path decreases with lower growth temperature. For CNTs grown in vias at 700°C, an electron mean free path of 5.2 nm is significantly smaller than via heights of 130 nm (sample A) and 80 nm (sample B). Therefore, combining with analyses of TEM and Raman results and based on understanding of CNT nanostructures, we conclude that ohmic transport is the predominant conduction mechanism. Such conclusion allows us to model a CNT via as a resistor consisting of various components including contact resistance, and validates the analyses of measured resistance versus via width and height data [61], to be presented in the following chapter.

References

[1] International Technology Roadmap for Semiconductors, 2013 edition, available at www.itrs2.net. [2] K. Ohuchi, N. Kusunoki, and F. Matsuoka, "Accurate Measurement of Silicide Specific Contact Resistivity by Cross Bridge Kelvin Resistor for 28nm Complementary Metal- Oxide-Semiconductor Technology and Beyond," Japanese Journal of Applied Physics, vol. 50, pp. 04DA03-4, Apr 2011. [3] S. Vollebregt, F. D. Tichelaar, H. Schellevis, C. I. M. Beenakker, and R. Ishihara, "Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 degrees C," Carbon, vol. 71, pp. 249-256, May 2014.

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[4] S. Vollebregt, S. Banerjee, A. N. Chiaramonti, F. D. Tichelaar, K. Beenakker, and R. Ishihara, "Dominant thermal boundary resistance in multi-walled carbon nanotube bundles fabricated at low temperature," Journal of Applied Physics, vol. 116, pp. 023514-5, Jul 2014. [5] S. Vollebregt, A. N. Chiaramonti, J. van der Cingel, K. Beenakker, and R. Ishihara, "Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits," Japanese Journal of Applied Physics, vol. 52, pp. 04CB02-4, Apr 2013. [6] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Thermal conductivity of low temperature grown vertical carbon nanotube bundles measured using the three-omega method," Applied Physics Letters, vol. 102, pp. 191909-3, May 2013. [7] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Size-Dependent Effects on the Temperature Coefficient of Resistance of Carbon Nanotube Vias," IEEE Transactions on Electron Devices, vol. 60, pp. 4085-4089, Dec 2013. [8] S. Vollebregt, A. N. Chiaramonti, R. Ishihara, H. Schellevis, and K. Beenakker, "Contact resistance of low-temperature carbon nanotube vertical interconnects," Nanotechnology (IEEE-NANO), 12th IEEE Conference on, pp. 1-5, Aug 2012. [9] S. Vollebregt, J. Derakhshandeh, R. Ishihara, M. Y. Wu, and C. I. M. Beenakker, "Growth of High-Density Self-Aligned Carbon Nanotubes and Nanofibers Using Palladium Catalyst," Journal of Electronic Materials, vol. 39, pp. 371-375, Apr 2010. [10] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, pp. 085302-6, Feb 2011. [11] N. Chiodarelli, Y. L. Li, D. J. Cott, S. Mertens, N. Peys, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration and electrical characterization of carbon nanotube via interconnects," Microelectronic Engineering, vol. 88, pp. 837-843, May 2011. [12] N. Chiodarelli, K. Kellens, D. J. Cott, N. Peys, K. Arstila, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration of Vertical Carbon Nanotube Bundles for Interconnects," Journal of the Electrochemical Society, vol. 157, pp. K211-K217, Oct 2010. [13] M. H. van der Veen, Y. Barbarin, Y. Kashiwagi, and Z. Tokei, "Electron mean-free path for CNT in vertical interconnects approaches Cu," in Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), IEEE International, 2014, pp. 181- 184, May 2014. [14] M. H. van der Veen, B. Vereecke, C. Huyghebaert, D. J. Cott, M. Sugiura, Y. Kashiwagi, L. Teugels, R. Caluwaerts, N. Chiodarelli, P. M. Vereecken, G. P. Beyer, M. M. Heyns, S. De Gendt, and Z. Tokei, "Electrical characterization of CNT contacts with Cu Damascene top contact," Microelectronic Engineering, vol. 106, pp. 106-111, Jun 2013. [15] C. J. Zhou, A. A. Vyas, P. Wilhite, P. Wang, M. S. Chan, and C. Y. Yang, "Resistance Determination for Sub-100-nm Carbon Nanotube Vias," IEEE Electron Device Letters, vol. 36, pp. 71-73, Jan 2015. [16] Y. Matsuda, W.-Q. Deng, and W. A. Goddard III, "Contact Resistance for “End-Contacted” Metal− Graphene and Metal− Nanotube Interfaces from Quantum Mechanics," The Journal of Physical Chemistry C, vol. 114, pp. 17845-17850, Sep 2010.

119

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[17] Y. Matsuda, W.-Q. Deng, and W. A. Goddard, "Contact resistance properties between nanotubes and various metals from quantum mechanics," The Journal of Physical Chemistry C, vol. 111, pp. 11113-11116, Jul 2007. [18] S. C. Lim, J. H. Jang, D. J. Bae, G. H. Han, S. Lee, I. S. Yeo, and Y. H. Lee, "Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability," Applied Physics Letters, vol. 95, pp. 264103-3, Dec 2009. [19] A. Powell, "Behaviour of the Platinum Metals at High Temperatures," Platinum Metals Review, vol. 2, pp. 95-98, Jul 1958. [20] A. P. Graham, G. S. Duesberg, R. V. Seidel, M. Liebau, E. Unger, W. Pamler, F. Kreupl, and W. Hoenlein, "Carbon nanotubes for microelectronics?," Small, vol. 1, pp. 382-390, Apr 2005. [21] A. P. Graham, G. S. Duesberg, W. Hoenlein, F. Kreupl, M. Liebau, R. Martin, B. Rajasekharan, W. Pamler, R. Seidel, W. Steinhoegl, and E. Unger, "How do carbon nanotubes fit into the semiconductor roadmap?," Applied Physics a-Materials Science & Processing, vol. 80, pp. 1141-1151, Mar 2005. [22] C. Zhou, A. A. Vyas, P. Wilhite, P. Wang, M. Chan, and C. Y. Yang, "Resistance determination for sub-100-nm carbon nanotube vias," IEEE Electron Device Letters, vol. 36, pp. 71-73, Jan 2015. [23] Y. Awano, S. Sato, M. Nihei, T. Sakai, Y. Ohno, and T. Mizutani, "Carbon Nanotubes for VLSI: Interconnect and Transistor Applications," Proceedings of the IEEE, vol. 98, pp. 2015- 2031, Dec 2010. [24] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. L. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, pp. 085302-8, Feb 2011. [25] N. Al Dahoudi, Q. Zhang, and G. Cao, "Alumina and hafnia ald layers for a niobium- doped titanium oxide photoanode," International Journal of Photoenergy, vol. 2012, Dec 2012. [26] P. Reyes, M. Oportus, G. Pecchi, R. Frety, and B. Moraweck, "Influence of the nature of the platinum precursor on the surface properties and catalytic activity of alumina-supported catalysts," Catalysis letters, vol. 37, pp. 193-197, Sep 1996. [27] G. Olson and J. Roth, "Kinetics of solid phase crystallization in amorphous silicon," Materials Science Reports, vol. 3, pp. 1-77, Dec 1988. [28] A. P. Peter, J. Meersschaut, O. Richard, A. Moussa, J. Steenbergen, M. Schaekers, Z. Tokei, S. Van Elshocht, and C. Adelmann, "Phase Formation and Morphology of Nickel Silicide Thin Films Synthesized by Catalyzed Chemical Vapor Reaction of Nickel with Silane," Chemistry of Materials, vol. 27, pp. 245-254, Jan 2015. [29] J. Y. Lin, H. M. Hsu, and K. C. Lu, "Growth of single-crystalline nickel silicide nanowires with excellent physical properties," Crystengcomm, vol. 17, pp. 1911-1916, Jan 2015. [30] S. Hermann, "Growth of carbon nanotubes on different support/catalyst systems for advanced interconnects in integrated circuits," May 2011. [31] S. Hermann, S. Schulze, R. Ecke, A. Liebig, P. Schaefer, D. R. T. Zahn, M. Albrecht, M. Hietschold, S. E. Schulz, and T. Gessner, "Growth of carbon nanotube forests between a bi-

120

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metallic catalyst layer and a SiO2 substrate to form a self-assembled carbon-metal heterostructure," Carbon, vol. 50, pp. 4765-4772, Nov 2012. [32] S. Hermann, B. Pahl, R. Ecke, S. E. Schulz, and T. Gessner, "Carbon nanotubes for nanoscale low temperature flip chip connections," Microelectronic Engineering, vol. 87, pp. 438-442, Mar 2010. [33] S. Hermann, R. Ecke, S. Schulz, and T. Gessner, "Controlling the formation of nanoparticles for definite growth of carbon nanotubes for interconnect applications," Microelectronic Engineering, vol. 85, pp. 1979-1983, Oct 2008. [34] R. Saito, G. Dresselhaus, and M. S. Dresselhaus, Physical properties of carbon nanotubes vol. 35: World Scientific, 1998. [35] M. S. Dresselhaus, A. Jorio, A. G. Souza, and R. Saito, "Defect characterization in graphene and carbon nanotubes using Raman spectroscopy," Philosophical Transactions of the Royal Society a-Mathematical Physical and Engineering Sciences, vol. 368, pp. 5355-5377, Dec 2010. [36] M. S. Dresselhaus, A. Jorio, and R. Saito, "Characterizing Graphene, Graphite, and Carbon Nanotubes by Raman Spectroscopy," Annual Review of Condensed Matter Physics, vol. 1, pp. 89-108, Aug 2010. [37] M. S. Dresselhaus, A. Jorio, M. Hofmann, G. Dresselhaus, and R. Saito, "Perspectives on carbon nanotubes and graphene Raman spectroscopy," Nano Lett, vol. 10, pp. 751-758, Mar 2010. [38] M. S. Dresselhaus, G. Dresselhaus, and M. Hofmann, "Raman spectroscopy as a probe of graphene and carbon nanotubes," Philosophical Transactions of the Royal Society a- Mathematical Physical and Engineering Sciences, vol. 366, pp. 231-236, Jan 2008. [39] M. S. Dresselhaus, G. Dresselhaus, and A. Jorio, "Raman spectroscopy of carbon nanotubes in 1997 and 2007," Journal of Physical Chemistry C, vol. 111, pp. 17887-17893, Dec 2007. [40] M. S. Dresselhaus, G. Dresselhaus, and M. Hofmann, "The big picture of Raman scattering in carbon nanotubes," Vibrational Spectroscopy, vol. 45, pp. 71-81, Nov 2007. [41] M. S. Dresselhaus, G. Dresselhaus, R. Saito, and A. Jorio, "Raman spectroscopy of carbon nanotubes," Physics Reports, vol. 409, pp. 47-99, Mar 2005. [42] M. S. Dresselhaus, G. Dresselhaus, A. M. Rao, A. Jorio, A. G. Souza, G. G. Samsonidze, and R. Saito, "Resonance Raman scattering on one-dimensional systems," Indian Journal of Physics and Proceedings of the Indian Association for the Cultivation of Science-Part B, vol. 77B, pp. 75-99, Feb 2003. [43] M. S. Dresselhaus, G. Dresselhaus, A. Jorio, A. G. Souza, and R. Saito, "Raman spectroscopy on isolated single wall carbon nanotubes," Carbon, vol. 40, pp. 2043-2061, Dec 2002. [44] S. Vollebregt, R. Ishihara, F. D. Tichelaar, Y. Hou, and C. I. M. Beenakker, "Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers," Carbon, vol. 50, pp. 3542-3554, Aug 2012. [45] Q. Ngo, D. Petranovic, S. Krishnan, A. M. Cassell, Q. Ye, J. Li, M. Meyyappan, and C. Y. Yang, "Electron transport through metal-multiwall carbon nanotube interfaces," IEEE Transactions on Nanotechnology, vol. 3, pp. 311-317, Jun 2004.

121

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[46] Z. F. Zhao, Y. S. Zhou, C. Q. Zhang, and Z. Y. Wang, "Thermoset composites functionalized with carbon nanofiber sheets for EMI shielding," Journal of Applied Polymer Science, vol. 132, May 2015. [47] X. P. Zhang, D. Liu, L. B. Li, and T. Y. You, "Direct Electrochemistry of Glucose Oxidase on Novel Free-Standing Nitrogen-Doped Carbon Nanospheres@Carbon Nanofibers Composite Film," Scientific Reports, vol. 5, May 2015. [48] L. C. Zeng, Y. Jiang, J. Xu, M. Wang, W. H. Li, and Y. Yu, "Flexible copper-stabilized sulfur-carbon nanofibers with excellent electrochemical performance for Li-S batteries," Nanoscale, vol. 7, pp. 10940-10949, May 2015. [49] S. Yu, J. W. Jung, and I. D. Kim, "Single layers of WS2 nanoplates embedded in nitrogen- doped carbon nanofibers as anode materials for lithium-ion batteries," Nanoscale, vol. 7, pp. 11945-11950, Jun 2015. [50] Y. Yaakob, M. Z. M. Yusop, C. Takahashi, M. S. Rosmi, G. Kalita, and M. Tanemura, "In situ transmission electron microscopy of Ag-incorporated carbon nanofibers: the effect of Ag nanoparticle size on graphene formation," RSC Advances, vol. 5, pp. 5647-5651, Jan 2015. [51] S. B. Xu, A. Akchurin, T. Liu, W. Wood, X. W. Tangpong, I. S. Akhatov, and W. H. Zhong, "Thermal properties of carbon nanofiber reinforced high-density polyethylene nanocomposites," Journal of Composite Materials, vol. 49, pp. 795-805, Mar 2015. [52] W. Wang, Y. Sun, B. Liu, S. G. Wang, and M. H. Cao, "Porous carbon nanofiber webs derived from bacterial cellulose as an anode for high performance lithium ion batteries," Carbon, vol. 91, pp. 56-65, Sep 2015. [53] M. S. Wang, W. L. Song, J. Wang, and L. Z. Fan, "Highly uniform silicon nanoparticle/porous carbon nanofiber hybrids towards free-standing high-performance anodes for lithium-ion batteries," Carbon, vol. 82, pp. 337-345, Feb 2015. [54] E. Tsuji, T. Yamasaki, Y. Aoki, S. G. Park, K. Shimizu, and H. Habazaki, "Highly durable platelet carbon nanofiber-supported platinum catalysts for the oxygen reduction reaction," Carbon, vol. 87, pp. 1-9, Jun 2015. [55] X. Tang, Z. Y. Xie, Q. Z. Huang, G. F. Chen, M. Hou, and B. L. Yi, "Mass-transport- controlled, large-area, uniform deposition of carbon nanofibers and their application in gas diffusion layers of fuel cells," Nanoscale, vol. 7, pp. 7971-7979, May 2015. [56] K. X. Tang, Y. P. Li, H. B. Cao, F. Duan, J. Zhang, Y. Zhang, and Y. Wang, "Integrated electrospun carbon nanofibers with vanadium and single-walled carbon nanotubes through covalent bonds for high-performance supercapacitors," RSC Advances, vol. 5, pp. 40163-40172, Apr 2015. [57] A. Simon, M. Seyring, S. Kamnitz, H. Richter, I. Voigt, M. Rettenmayr, and U. Ritter, "Carbon nanotubes and carbon nanofibers fabricated on tubular porous Al2O3 substrates," Carbon, vol. 90, pp. 25-33, Aug 2015. [58] Y. J. Wei, J. T. Wu, H. Q. Yin, X. H. Shi, R. G. Yang, and M. Dresselhaus, "The nature of strength enhancement and weakening by pentagon-heptagon defects in graphene," Nature Materials, vol. 11, pp. 759-763, Sep 2012. [59] P. T. Araujo, M. Terrones, and M. S. Dresselhaus, "Defects and impurities in graphene- like materials," Materials Today, vol. 15, pp. 98-109, Mar 2012.

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[60] M. Kalbac, Y. P. Hsieh, H. Farhat, L. Kavan, M. Hofmann, J. Kong, and M. S. Dresselhaus, "Defects in Individual Semiconducting Single Wall Carbon Nanotubes: Raman Spectroscopic and in Situ Raman Spectroelectrochemical Study," Nano Letters, vol. 10, pp. 4619-4626, Nov 2010. [61] K. C. Huang, D. B. Janes, K. J. Webb, and M. R. Melloch, "A transfer length model for contact resistance of two-layer systems with arbitrary interlayer coupling under the contacts," IEEE Transactions on Electron Devices, vol. 43, pp. 676-684, May 1996.

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5 Carbon Nanotube Vias - Electrical Characterization

This chapter covers an extensive electrical characterization of CNT vias to determine their performance and reliability as well as the impact of improved performance on reliability. We begin with an overview of a nanoprobing system used for in situ electrical measurements on 2PP CNT via test structure, followed by a narrative on measured resistance of CNT vias to study its dependence on via width, and to extract resistivity and contact resistance from resistance versus via height data. The reliability of CNT vias is examined using current stressing method to determine their maximum current-carrying capacity. A voltage-sweep technique with incremental current compliance is used to independently verify the maximum current-carrying capacity of CNT vias obtained from current stressing.

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5.1 Overview of nanoprobing system

The design considerations for test structure listed in section 4.1 suggest that CNT vias can be accurately characterized with a 2PP method by minimizing the stray resistance contribution, primarily from underlayer and probes. Towards this end, a 300 nm thick Cr layer serves as an underlayer in CNT via test structure to minimize its resistance contribution. Stray resistance contribution from the nanoprobing system is minimized by employing a low-resistance nanoprobe system shown in Fig. 5.1, with its configuration and measurement of its intrinsic resistance described as follows.

Nanoprobe

Sample location

Figure 5.1. Photo of nanoprobing system consisting of four probes. The setup is made to rest on SEM sample stage which allows in situ imaging and probing of nanoscale devices.

The nanoprober is installed inside the SEM chamber with sample resting at the center of the nanoprober stage. The system is allowed to evacuate for 4 hours to allow outgassing of air molecules adsorbed on nanoprober and sample. Achieving high vacuum (~10-7 Torr) is key to achieve accurate measurements as stray oxygen can have an adverse effect on both performance and reliability determinations [1]. The resistances of the nanoprobing system, probe-metal contact, and underlayer resistance are measured in situ under high vacuum. The intrinsic resistance of the nanoprobing system which appears as a parasitic series resistance in 2PP measurements is obtained by electrically shorting

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Chapter 5 two probes which forms a short circuit across the nanoprobing system. The SEM image of two probes in contact is shown in Fig. 5.2(a) and the corresponding I-V and resistance behaviors are shown in Fig. 5.2(b). The contribution from the nanoprobing system is 5 Ω.

(a) (b)

5 Ω

Bias Ground

Figure 5.2 (a) SEM image of shorting two nanoprobes. (b) Resulting I-V and resistance behaviors.

Next, the combined probe-metal contacts and underlayer resistance is extracted by first applying 2.5 V initially between the two probes with a current compliance of 50 nA, while both probes land firmly on an exposed area of the Cr underlayer, serving as the ground. Once both probes make contact with Cr, the voltage drops and the current reaches its maximum value set by the compliance, as shown in Fig. 5.3(a). The resulting I-V and resistance behaviors are given in Fig. 5.3(b).

(a) (b) After contact Before contact Bias 9 Ω Ground

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As shown in Fig. 5.3(b), the total contribution from the nanoprobing system, probe-metal contacts, and underlayer is 9 Ω, out of which 5 Ω is from the nanoprobing system. Resistances of CNT vias for widths 30 – 200 nm were reported to be in the 1-5 kΩ range [2-5]. Assuming similar resistances for our samples A and B, the error introduced by neglecting all series parasitic resistances in 2PP measurements is at most 1%. Thus, the use of 2PP to measure CNT via resistance as discussed in Section 4.1 is validated. We now proceed to describe the results of such measurements and how they are used to study CNT via performance and reliability.

5.2 CNT via resistance measurements

Resistance measurements are carried out on samples A and B introduced in Chapter 4, and their specifications are summarized in Table 5.1. Descriptions of these measurements and their results are presented in this and the next sections.

Table 5.1. Summary of CNT via sample parameters and resistance measurements.

Parameter/Task Sample A Sample B Description Obtained from via etching Via height (nm) 130 (fixed) 80 (wedge) during fabrication process Targeted linewidths for Via width(s) (nm) 60, 90, 120, 150 40 end-of-roadmap nodes Top-contact Vias with and without Vias with and without Effect of metallized top metallization EBID-Pt EBID-Pt contact Determine I-V linearity and I-V I-V via resistance Resistance projection for Resistance vs via width NA sub-60 nm linewidths Electrical Extract contact resistance NA Resistance vs via height measurements and and resistivity analyses Determine current-carrying Current stressing Current stressing capacity Voltage sweep with Verify current-carrying NA incremental current capacity compliance

We begin with sample A by measuring the I-V behavior of at least 10 vias for each linewidth. The total via resistance is then determined by taking the reciprocal slope of the I-V plot at zero voltage. The data for the four via widths are then analyzed to project sub- 60 nm via resistance. Contact improvement for each via is achieved by current stressing

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Chapter 5 prior to recording its resistance value. Sample B also undergoes I-V measurements to determine resistance for 40 nm CNT vias at five different heights along the wedge. CNT vias with and without EBID-Pt contacts are measured to extract their contact resistance and resistivity. Finally, current-carrying capacities for 60 nm and 40 nm vias are characterized.

The cross-sectional schematic of 2PP I-V measurement setup is shown in Fig. 5.4(a). One nanoprobe lands on the Cr underlayer serving as ground and another makes a mechanically robust contact, as illustrated in the SEM image shown in Fig. 5.4(b) for a 60 nm CNT via. Initial contact between nanoprobe and un-metallized via top contact yields high resistance, which is improved by current stressing and the final value is recorded when no further reduction in resistance occurs. A typical CNT via I-V plot is shown in Fig. 5.4(c). Linearity of the I-V behavior confirms ohmic transport suggested by TEM and Raman analyses presented in Section 4.5.

(a) (b) (c) 12.5 kΩ

I-V measurements on vias without metallized top contacts in sample A are conducted. The purpose is to project via resistance in the sub-60 nm regime from statistical analysis of resistance versus width data for 60 nm to 150 nm vias. Such projection is useful for assessing the potential of CNT as an interconnect material for the current interconnect pitch [6]. With the 2PP setup in Fig. 5.4(a), the measured resistance of a single CNT via is given by

푅푣𝑖푎 = 푅퐶푟 + 푅푝푟표푏푒 + 푅푝푟표푏푒−퐶푟 + 푅푝푟표푏푒−퐶푁푇 + 푅퐶푟−퐶푁푇 + 푅퐶푁푇 (5.1)

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RCr, Rprobe, and Rprobe-Cr denote the resistances of the Cr underlayer, nanoprobes, and probe-

Cr contact resistance, respectively. Their sum RM is estimated (see Section 5.1) to be ~9 Ω.

RCr-CNT and Rprobe-CNT are lumped together to represent the total contact resistance RC, and

RCNT is the intrinsic CNT resistance. The total CNT via resistance becomes

푅푣𝑖푎 = 푅푀 + 푅퐶 + 푅퐶푁푇 . (5.2)

RC is estimated by dividing RCi, contact resistance of a single CNT, by an average number of CNTs inside via making contact with nanoprobe, which is the product of average CNT areal density NCNT and via cross-sectional area w2. The CNT resistance can then be expressed in terms of CNT resistivity and via dimensions, assuming ohmic conduction along the CNT height.

푅퐶푖 휌퐶푁푇 ×ℎ 푅푣𝑖푎 = 푅푀 + 2 + 2 (5.3) 푁퐶푁푇 ×푤 푁퐶푁푇×푤 ×퐴퐶푁푇

ρCNT is the CNT resistivity, h the CNT height, and ACNT the average total CNT cross- sectional area inside the via.

The via resistance versus width plot is shown in Fig. 5.5, with the mean and standard deviation for each width given in the inset. We note that the standard deviation significantly increases for sub-100 nm linewidths, suggesting large variations at the probe-CNT interface among vias. Such variations among vias with the same width are mostly due to differences in interface morphology between the nanoprobe and CNT tips, resulting in different numbers of graphene shells making contact with the probe. For via top contact, it is essential that the metal (nanoprobe or contact metal layer) creates a current path through as many CNT walls as possible. We use a nanoprobe with W tip which can be softened by current annealing, effectively increasing the contact area and resulting in carrier flow through the maximum number of CNT walls. Based on such considerations and for the average areal density obtained from our CNT growth, if all process and probing steps are approaching optimum, the via resistance can be as low as 150 Ω for a 60 nm via as shown in Fig. 5.5. However, variations in contacts (both base and top) among vias, coupled with the fact that a different percentage of CNTs reaching the top of each via, create a substantial scatter in the measured data. Nevertheless, by measuring multiple devices and performing a standard statistical analysis, we can

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Chapter 5 systematically study the downward scaling trend of CNT via resistance, which in turn provides a reasonable projection for future technology nodes.

Since RM is at least an order of magnitude lower than Rvia in all cases, it is neglected in rewriting Eq 5.3 as

푅퐶푖 휌퐶푁푇 ×ℎ 푅푣𝑖푎 = 2 + 2 (5.4) 푁퐶푁푇 ×푤 푁퐶푁푇×푤 ×퐴퐶

Now, taking logarithm of both sides of Eq. 5.4, we obtain

푅푐푖 휌퐶푁푇 × ℎ log10(푅푣𝑖푎) = log10 ( + ) − 2 × log10 푤 . (5.5) 푁퐶푁푇 푁퐶푁푇 × 퐴퐶

Based on Eq. 5.5 and statistical linear regression analysis of the measured data plotted in a log-log scale, the slope of the fitted line is -1.9, compared to the ideal case of −2 where

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NCNT, ACNT, and ρCNT are width-independent, thus supporting this analysis for examining the downward scaling trend of via performance. This result also suggests that the dependence of NCNT, ACNT, and ρCNT on w may not be significant, which further attests to uniformity in CNT growth. By extrapolating the fitted line, the projected resistance for a 30 nm CNT via with a height of 130 nm is 6.3 kΩ, and can be as low as 295 Ω in the best (or minimum resistance) case.

To examine the contributions of the contact resistance RC and the intrinsic CNT resistance RCNT, we have computed the CNT areal density by directly counting the numbers of CNTs inside a large number of vias of different widths, yielding an average of ∼2 × 1011/cm2. Using Rci = 300 Ω [8], RC is estimated to be 42 Ω for a 60 nm via. By including RM = 9 Ω and the best measured Rvia value of 150 Ω for a 60 nm via, RCNT = 99 Ω for the 60 nm via. Although there are considerable differences among literature reports in fabrication processes, measurement techniques, and data analysis methods, our best result of 150 Ω for a 60 nm via represents the lowest reported measured resistance for sub-100 nm CNT vias [2, 9-14] to date, albeit at a relatively high CNT growth temperature.

The effect of top-contact metallization on Rvia is examined by conducting I-V measurements on two sets of twenty each 60 nm CNT vias with and without metallized top contacts, as it is the smallest width on sample A comparable to the linewidth in the current technology node size [6]. The measured resistances on a cumulative frequency distribution (CFD) plot are shown in Fig. 5.6. The resulting median Rvia value and coefficient of variation (CV) for each set reveal 65% and 20% decreases, respectively, confirming significant improvement of via resistance by top-contact metallization.

Resistance distribution of 60 nm vias 100.00% 90.00% 65% reduction 80.00% in median Coeff. of Variation = 40.5% 70.00% via resistance Coeff. of Variation = 19.66% 60.00% 50.00%

CFD (%) CFD 40.00% EBID-Pt Cap 30.00% 20.00% w/o Cap 10.00% 0.00% 1000 R (Ω) 10000 100000 via

Figure 5.6. Cumulative frequency distribution plot for 60 nm CNT via resistance with and without EBID-Pt top contacts.

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Top-contact metallization serves to reduce the contribution of nanoprobe-via contact to the via resistance as suggested by the CFD plot in Fig. 5.6. Since the analysis of data shown in Fig. 5.5 is consistent with the assumption that the dependence of NCNT, ACNT, and

ρCNT on w is not significant, the improvement in via resistance shown in Fig. 5.6 lends further support for the conclusion that variations in nanoprobe-via contacts among vias are principally responsible for the large scatter in measured resistance data. The other component of RC, from the via base contact between Cr and CNTs inside via formed during CNT growth, is not expected to have significant variations among vias due to uniformity of CNT growth. Another source for the data spread is from height variations among vias, which can be attributed to non-uniformity in the polishing process and/or imperfect CNT alignments inside via. Nevertheless, the data shown in Figs. 5.5 and 5.6 provide strong evidence to support the finding that improved via top contact enhances the overall CNT via performance.

For sample B, I-V measurements are carried out on 40 nm CNT vias along the wedge, as summarized in Fig. 5.7, with identical techniques used for sample A. A typical CNT via I-V plot is shown in Fig. 5.7(d). Linearity of the I-V behavior confirms ohmic transport suggested by TEM and Raman analyses presented in Section 4.5. Resistance of at least ten vias for each of the five different via heights are obtained using the technique illustrated in the schematic in Fig. 5.7(f), with the results shown in Fig. 5.8.

The range of via heights is selected such that the shortest height is at least half the maximum via height in order to avoid accidental shorting of the top and bottom electrodes. Since the via height range is 48–80 nm, and the electron mean free path in as- grown CNTs estimated from analysis of Raman spectra (see Section 4.6) is about 5 nm, the assumption of ohmic transport is still valid. Thus, each via resistance Rvia can be expressed as

휌퐶푁푇 ×ℎ 푅푣𝑖푎 = 푅푀 + 푅퐶 + . (5.6) 퐴퐶푁푇

As in the analysis of sample A data, RM represents the total resistance contributions from the Cr underlayer, probes, and probe-Cr contacts, and its value is estimated by landing both nanoprobes on the exposed Cr area, as described previously. A typical value obtained is 9 Ω, which is less than 0.2% of the lowest measured Rvia. Hence, RM can be neglected in the subsequent analysis. RC is the total contact resistance of the via and varies among vias according to the number and diameter of the CNTs inside each via, as well

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as the nanoprobe-via contact. ACNT is the total CNT cross-sectional area inside via and also varies among vias.

(c)

Figure 5.7 (a) Top-view SEM images of 40 nm vias after CNT growth. (b) CNT vias of 40 nm after Al2O3 filling and polishing. (c) Top-view of wedge formed after polishing and before EBID-Pt deposition. The arrow indicates the direction of the wedge from low to high. (d) Typical measured I–V behavior that yields via resistance Rvia before EBID-Pt top-contact metallization. (e) Glancing view of CNT vias after EBID-Pt. Alternate vias are selectively metallized in order to avoid overlaps. (f) Cross-sectional schematic of wedge with nanoprobing setup showing varying via height h used for contact resistance extraction. The arrow indicates the direction of the wedge as in (c) [15].

Such variations are manifested in the data spread for each via height shown in Fig. 5.8. The via height h is fixed among vias of the same height using the wedge structure shown in Fig. 5.7(f), assuming uniformity in the wedge formation process. The CNT resistivity

ρCNT depends on the number of defects in the graphitic structure and the number of walls.

Relative to the variations of ACNT and RC among vias (to be addressed in the ensuing paragraph), and considering the small range of via heights used, the variation of ρCNT is expected to be small and an average value for the sample is assumed in the analysis. Thus, in using Eq. 5.6 to extract the contact resistance from the Rvia versus h data, the resistance intercept of the statistical linear fit amounts to an average RC that takes into account all variations among vias.

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(a)

No metal cap EBID-Pt cap

(Ω)

via

(b) 25

) 15 Ω 2 (k R = 0.92

via 10 R

5 R2 = 0.91

0 40 45 50 55 60 65 70 75 80 85 Via height (nm)

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The fitted straight line in Fig. 5.8(a) yields a slope of 142.5 Ω·nm−1 and 61 Ω·nm−1 for CNT vias without and with metallized top contacts. The coefficient of determination R2 exceeds 0.9 in either case, supporting the assumption that conduction through the entire

CNT via structure is indeed ohmic, with an average CNT linear resistivity ρCNT/ACNT = 142.5 Ω·nm−1 and 61 Ω·nm−1 for un-metallized and metallized CNT vias, respectively. The mean Rvia and standard deviation for each height are given in Fig. 5.8(b).

Therefore, despite significant variations among vias, such statistical analysis can be employed to extract an average via contact resistance and an average CNT resistivity, with RC = 4.1 kΩ and ρCNT = 4.3 mΩ·cm for un-metallized CNT vias, and RC = 2.8 kΩ and

ρCNT = 1.8 mΩ·cm for metallized ones, showing a significant improvement in contact resistance and resistivity. For this calculation, an average ACNT ∼ 300 nm2 is obtained from SEM image analysis of eight un-metallized 40 nm vias in the vicinity of the ones which undergo electrical measurements. A sample set of vias used in such image analysis is shown in Fig. 5.9. The resistivity value extracted for either data set is about an order of magnitude lower than the ones obtained for the lower CNT growth temperature[16], but still more than two orders of magnitude higher than those of Cu and W with similar linewidths [16].

Total Area of CNTs inside via

2 2 ACNT = 229 nm ACNT = 266 nm 2 ACNT = 495 nm

50 nm

Figure 5.9 SEM images of vias used to estimate average total area of CNTs inside 40 nm via.

To examine the variations among vias further, a statistical analysis is performed on the variations in the diameter and number of CNTs inside each via, as well as the resulting variations in the extracted contact resistance. The diameters and number of CNTs making contacts with the top and bottom electrodes define the total conducting cross-sectional

135

Chapter 5 area in a via, and variations in that area among the vias manifest themselves in variations in the measured Rvia and extracted RC. For the set of vias used in this experiment, the mean (μ), standard deviation (σ), and coefficient of variation (CV) for each of these parameters are summarized in Table 5.2. For CNT vias exhibiting ohmic conduction described by Eq.

5.6, both contact resistance and total CNT resistance are inversely proportional to ACNT.

Thus, one would expect the extracted RC to have variations similar to those for ACNT.

However, for CNT via with un-metallized contacts, RC has an additional variation from

Rprobe-CNT, which as we have demonstrated for 60 nm vias, is principally responsible for the resistance variations among vias of the same geometry. If we were to use the average CNT diameter and average number of CNTs inside via given in Table 5.2 to deduce the average ACNT, it would be ∼1000 nm2. This value is clearly an overestimation as both the SEM image of the unpolished vias in Fig. 5.7(a) reveal CNTs with lengths lower than the via heights, which do not contribute to conduction. On the other hand, the presence of oxide surrounding the vias as well as the exposed dielectric filler material in the polished sample results in insufficient contrast for accurate individual CNT diameter and number determination, but probably adequate for total area estimation. The resulting ACNT statistics given in Table 5.2 correlate well those for RC for metallized CNT vias, thus supporting the analysis used to extract the latter. Despite the fact that RC varies inversely as ACNT, in the range of ACNT obtained for 40 nm vias, the magnitudes of RCNT and ACNT variations are approximately linearly related. Thus, correlation of CV data between these two parameters given in Table 5.2 can be justified.

Table. 5.2. Statistics of 40 nm CNT via parameters which contribute to variations in measured via resistance and extracted contact resistance. For diameter and number of CNTs, the data are obtained from SEM images of unfilled and unpolished vias such as those in Fig. 5.7(a), whereas the total CNT area in via is obtained from SEM images of polished samples shown in Fig. 5.7(b). For each parameter, the mean µ, standard deviation σ, and coefficient of variation CV are obtained, showing similarities in variations for ACNT and RC in metallized vias.

Parameter in a set of 40 nm CNT vias µ σ CV(%) CNT diameter across the entire set (nm) 9.03 3.62 40.1 Number of CNTs in via, NCNT 16 2 12.5 2 Total area of CNTs in via, ACNT (nm ) 310 101 32.6 Extracted RC (kΩ) for metallized CNT vias from Fig. 5.8(a) 2.84 0.8 28.6 Extracted RC (kΩ) for un-metallized CNT vias from Fig. 5.8(a) 4.1 4.05 98.7

The understanding gained from the preceding analysis of via resistance data is applied to the study of via reliability in the next section.

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5.3 Current-carrying capacity measurements

Reliability of CNT vias can be quantified by measuring their current-carrying capacities

JMAX. As long as JMAX remains higher than the required current density for interconnects, they can operate without degradation in performance. We have recently demonstrated [15, 17] the advantage of growing CNTs at temperatures higher than those considered to be acceptable for IC manufacturing [6], where the resulting high CNT quality leads to lower resistivity and higher current-carrying capacity [18]. To obtain JMAX for CNT vias, two complementary methods are employed as discussed in the following subsections

5.3.1 Current stress test

For the first method, a constant current is applied to the via in incremental steps and the resistance is recorded after each stress cycle until device breakdown. This is similar to studies for horizontal CNT interconnects discussed in Section 3.3. The resistance versus stress current behavior for 40 nm and 60 nm CNT vias with and without metallized top contacts are shown in Fig. 5.10. It is observed that in either case, the vias with Pt top contacts can carry much higher current than those without, and with much lower resistance prior to breakdown. The Pt contact allows all the exposed CNT tips and the graphene shells inside each CNT to interface with the deposited metal, whereas for vias without the metallized top-contact, via resistance is very sensitive to variations in probe- via contact, which generally does not cover all the CNTs inside the via, resulting in higher contact resistance and increased Joule heating from current stressing. Furthermore, heat dissipation from the CNTs under current stressing is less efficient without the top-contact metal, and hence the via breaks down at a lower current density. An additional benefit of metallized top contact is further improvement of the top and base contacts by Joule heat from current stressing, which facilitates fusion of nanocrystalline grains in the metal, as observed by Wilhite [19, 20] for EBID-W contacts and reported by Wang [21] for EBID- Pt nanocrystals. Thus, current stressing provides local annealing of individual vias instead of having to thermally anneal the entire sample.

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14 MA/cm2

330 MA/cm2

10 MA/cm2

17 MA/cm2

170 MA/cm2

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Study of the horizontal CNT interconnects using end-bonded contacts after CNT growth was reported by Chiodarelli [22], showing similar improvement as in the case of horizontal carbon nanofibers after contact metallization. Fig. 5.10(a) shows the resistance behavior versus stress current for two 40 nm vias, each with breakdown at 1 mA. Using

ACNT ∼ 300 nm2 obtained for 40 nm vias, JMAX ∼ 330 MA cm−2. For the 60 nm via data in

Fig. 5.10(b), with ACNT ∼ 700 nm2, JMAX ∼ 170 MA cm−2. These via current-carrying capacities are more than two orders of magnitude higher than those for Cu and W with similar dimensions and are consistent with reported values [16]. The improvements in both via resistance and current-carrying capacity are evident for each linewidth. The breakdown in CNTs tends to occur at defect sites and can be exacerbated by ambient oxygen adsorption. Therefore, the improvement of long-range order in CNTs by reducing defects and using non-oxide-based dielectric fillers can result in further enhancement in

JMAX as well as a reduction in via resistance. Nonetheless, the JMAX values obtained in this experiment and reported by others [14, 18, 23, 24] are more than sufficient for functionalized on-chip CNT interconnects to last through to the end of semiconductor technology nodes, if the line resistance can be reduced to approach its Cu and W counterparts.

5.3.2 Voltage-sweep test

To independently verify the current-carrying capacity of the CNT vias obtained with current stressing experiment described in the previous sub-section, a second test is conducted. The voltage across each via is swept between a pre-defined or compliance range of currents. If a continuous linear I–V is obtained, it implies that the CNTs inside the via remain intact. An array of Pt-metallized vias after the voltage sweep is shown in Fig. 5.11(a). At the outset, a current compliance range of ±1 mA is used with a voltage sweep from −4 V to 4 V. As shown in Fig. 5.11(b), continuous I–V behavior is obtained for this compliance range. The via meeting this compliance remains intact, while those with higher compliance ranges break down as shown in Fig. 5.11(a). Thus, the current-carrying capacity shown in Fig. 5.10(a) is verified.

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(a) (b)

Compliance range

1 mA 300 nm

Finally, it is important to know how the latest results for CNT vias compare with the vias made of the conventional materials, Cu and W, with similar dimensions, and with pertinent results reported by others. A comparison of the Rvia and JMAX of CNT, Cu, and W vias is given in Table 5.3. The data clearly reveal how CNT areal density correlates with via current-carrying capacity. However, in order to achieve higher areal density, smaller CNT diameters are needed to pack more of them into a via, which could increase the overall via resistance. Also, defects in CNTs can limit the via current-carrying capacity. As reported in Section 4.6 that even for 700°C growth, the defect ratio (ID/IG) from Raman analysis is 0.85. Therefore, taller vias are susceptible to reduced current- carrying capacity as more defects are present along the CNT length, consistent with the data obtained in this work and by others given in Table 5.3.

As in horizontal CNT interconnects discussed in Chapter 3, dissipation of Joule heat from current stressing is less efficient for a taller via, contributing to variations in JMAX among vias with different heights. Katagiri [28] reported a resistance of 11 kΩ and a current- carrying capacity of 100 MA/cm 2 for a 70 nm wide via with CNT growth at 450°C, while an extensive study by Vollebregt [9, 36] conclusively demonstrated that the number of defects in CNTs increases as the growth temperature was reduced. Graham [14, 26] reported that 700°C CNT growth and subsequent annealing resulted in a current-carrying capacity of 400 MA/cm2 for a 30 nm via with a CNT areal density of 1.5 × 1011 cm−2. This higher JMAX is probably due to a multi-walled structure with a hollow interior, as evident

140

Chapter 5 in the cross-sectional TEM image of a CNT in [26], whereas the CNTs in our vias mostly have a “bamboo” structure, where interlayer defects can lower their JMAX. In all cases, while the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, via resistance to approach those of Cu and W remain a daunting challenge, though our results suggest that further innovations in contact engineering and improving the long-range order could begin to overcome such challenge.

Table 5.3 Comparison of properties of CNT vias studied here and reported by others, and with Cu and W vias of similar dimensions.

CNT Via CNT Current- Via CNT Contact Growth Dimensions Areal carrying Resistance Resistivity Resistance Temperature (width × Density Capacity (Ω) (mΩ·cm) (Ω) (°C) height) (#/cm2) (MA/cm2) 40 nm × 700 7500 1.8 2800 ~1012 330 This work 80 nm [7, 15, 17, 25] 60 nm × 700 2795 NA NA 2 × 1011 170 130 nm Graham 30 nm × 700 7800 NA NA ~ 1011 400 [14, 24, 26, 27] 150 nm Katagiri 70 nm × 400 11000 NA NA 5 × 1011 100 [11, 23, 28] 100 nm 160 nm × Awano [13] 400 63 NA NA 3 × 1011 5 120 nm 100 nm × Wada [29] 425 1400 NA NA ~1011 NA 190 nm 100 nm × Ngo [30] 700 9000 0.44 NA 8 × 108 7 4000 nm 100 nm × Lim [2] 600 NA NA 3100 (Pt) 4 × 1011 NA 200 nm 100 nm × Li [31] 750 300 NA NA 1.6 × 109 10000 2000 nm Hermann 1000 nm × 600 NA NA 6 2 × 1011 NA [12, 32-34] 5500 nm 150 nm × Marleen [35] 540 2200 5.1 500 ~1011 NA 400 nm Chiodarelli 300 nm × 470 9500 3.7 1160 2 × 1011 NA [3-5, 22] 450 nm Vollebregt 2000 nm × 350 25 10 8 × NA [9, 36-38] 3000 nm 30 nm × Copper [16] NA 25 0.007 15 NA 2.5 130 nm 30 nm × Tungsten [16] NA 60 0.038 5 NA 1 130 nm

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In this chapter, the first and only comprehensive electrical characterization of CNT vias is reported for sub-50 nm linewidths, and significant improvement in resistance and current-carrying capacity for such integrated CNT vias is achieved with contact engineering, albeit at relatively high CNT growth temperature.

References

[1] S. Maeda, P. Wilhite, N. Kanzaki, T. Yamada, and C. Y. Yang, "Change in carbon nanofiber resistance from ambient to vacuum," Aip Advances, vol. 1, pp. 022102-6, Jun 2011. [2] S. C. Lim, J. H. Jang, D. J. Bae, G. H. Han, S. Lee, I. S. Yeo, and Y. H. Lee, "Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability," Applied Physics Letters, vol. 95, pp.0650221-3, Dec 2009. [3] N. Chiodarelli, K. Kellens, D. J. Cott, N. Peys, K. Arstila, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration of Vertical Carbon Nanotube Bundles for Interconnects," Journal of the Electrochemical Society, vol. 157, pp. K211-K217, 2010. [4] N. Chiodarelli, Y. L. Li, D. J. Cott, S. Mertens, N. Peys, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration and electrical characterization of carbon nanotube via interconnects," Microelectronic Engineering, vol. 88, pp. 837-843, May 2011. [5] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, p. 085302-8, Feb 25 2011. [6] International Technology Roadmap for Semiconductors, 2013 edition, available at www.itrs2.net. [7] C. J. Zhou, A. A. Vyas, P. Wilhite, P. Wang, M. S. Chan, and C. Y. Yang, "Resistance Determination for Sub-100-nm Carbon Nanotube Vias," IEEE Electron Device Letters, vol. 36, pp. 71-73, Jan 2015. [8] P. Wilhite, A. Vyas, J. Tan, C. Y. Yang, P. Wang, J. Park, H. Ai, and M. Narasimhan, "Electrical and structural analysis of CNT–metal contacts in via interconnects," Proc. 7th Int. Conf. Quantum, Nano, Micro Technol, 2013, pp. 41-43, Aug 2013. [9] S. Vollebregt, A. N. Chiaramonti, J. van der Cingel, K. Beenakker, and R. Ishihara, "Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits," Japanese Journal of Applied Physics, vol. 52, pp. 04CB02-4, Apr 2013. [10] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Size-Dependent Effects on the Temperature Coefficient of Resistance of Carbon Nanotube Vias," IEEE Transactions on Electron Devices, vol. 60, pp. 4085-4089, Dec 2013. [11] M. Katagiri, Y. Yamazaki, M. Wada, M. Kitamura, N. Sakuma, M. Suzuki, S. Sato, M. Nihei, A. Kajita, T. Sakai, and Y. Awano, "Improvement in Electrical Properties of Carbon Nanotube Via Interconnects," Japanese Journal of Applied Physics, vol. 50, pp. 05EF01-5, May 2011.

142

Chapter 5

[12] S. Hermann, "Growth of carbon nanotubes on different support/catalyst systems for advanced interconnects in integrated circuits," 2011. [13] Y. Awano, S. Sato, M. Nihei, T. Sakai, Y. Ohno, and T. Mizutani, "Carbon Nanotubes for VLSI: Interconnect and Transistor Applications," Proceedings of the Ieee, vol. 98, pp. 2015- 2031, Dec 2010. [14] A. P. Graham, G. S. Duesberg, R. V. Seidel, M. Liebau, E. Unger, W. Pamler, F. Kreupl, and W. Hoenlein, "Carbon nanotubes for microelectronics?," Small, vol. 1, pp. 382-390, Apr 2005. [15] A. A. Vyas, C. Zhou, Y. Chai, P. Wang, and C. Y. Yang, "Effect of improved contact on reliability of sub-60 nm carbon nanotube vias," Nanotechnology, vol. 27, p. 375202-11, Aug 2016. [16] C. Adelmann, L. G. Wen, A. P. Peter, Y. K. Siew, K. Croes, J. Swerts, M. Popovici, K. Sankaran, G. Pourtois, and S. Van Elshocht, "Alternative metals for advanced interconnects," in IEEE International Interconnect Technology Conference, pp. 173-176, May 2014. [17] A. Vyas, P. Wang, C. Zhou, M. Chan, and C. Y. Yang, "Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias," IEEE International Interconnect Technology Conference, pp. 203-205, May 2016. [18] B. Q. Wei, R. Vajtai, and P. M. Ajayan, "Reliability and current carrying capacity of carbon nanotubes," Applied Physics Letters, vol. 79, pp. 1172-1174, Aug 2001. [19] P. Wilhite, A. A. Vyas, J. Tan, J. Tan, T. Yamada, P. Wang, J. Park, and C. Y. Yang, "Metal– nanocarbon contacts," Semiconductor Science and Technology, vol. 29, p. 054006-16, 2014. [20] P. Wilhite, H. S. Uh, N. Kanzaki, P. Wang, A. Vyas, S. Maeda, T. Yamada, and C. Y. Yang, "Electron-beam and ion-beam-induced deposited tungsten contacts for carbon nanofiber interconnects," Nanotechnology, vol. 25, p. 375702-8, Sep 2014. [21] Z. L. Wang, J. M. Petroski, T. C. Green, and M. A. El-Sayed, "Shape transformation and surface melting of cubic and tetrahedral platinum nanocrystals," The Journal of Physical Chemistry B, vol. 102, pp. 6145-6151, 1998. [22] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. L. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, pp. 085302-9, Feb 2011. [23] M. Katagiri, Y. Yamazaki, N. Sakuma, M. Suzuki, T. Sakai, M. Wada, N. Nakamura, N. Matsunaga, S. Sato, and M. Nihei, "Fabrication of 70-nm-diameter carbon nanotube via interconnects by remote plasma-enhanced chemical vapor deposition and their electrical properties," Interconnect Technology Conference,IEEE International, pp. 44-46, May 2009. [24] F. Kreupl, A. P. Graham, G. S. Duesberg, W. Steinhogl, M. Liebau, E. Unger, and W. Honlein, "Carbon nanotubes in interconnect applications," Microelectronic Engineering, vol. 64, pp. 399-408, Oct 2002. [25] A. A. Vyas, C. Zhou, P. Wilhite, P. Wang, and C. Y. Yang, "Electrical properties of carbon nanotube via interconnects for 30nm linewidth and beyond," Microelectronics Reliability, vol. 61, pp. 35-42, Jun 2016.

143

Chapter 5

[26] A. P. Graham, G. S. Duesberg, W. Hoenlein, F. Kreupl, M. Liebau, R. Martin, B. Rajasekharan, W. Pamler, R. Seidel, W. Steinhoegl, and E. Unger, "How do carbon nanotubes fit into the semiconductor roadmap?," Applied Physics a-Materials Science & Processing, vol. 80, pp. 1141-1151, Mar 2005. [27] G. S. Duesberg, A. P. Graham, M. Liebau, R. Seidel, E. Unger, F. Kreupl, and W. Hoenlein, "Growth of isolated carbon nanotubes with lithographically defined diameter and location," Nano Letters, vol. 3, pp. 257-259, Feb 2003. [28] M. Katagiri, M. Wada, B. Ito, Y. Yamazaki, M. Suzuki, M. Kitamura, T. Saito, A. Isobayashi, A. Sakata, N. Sakuma, A. Kajita, and T. Sakai, "Fabrication and Characterization of Planarized Carbon Nanotube Via Interconnects," Japanese Journal of Applied Physics, vol. 51, pp. 05GF01-5, May 2012. [29] M. Wada, B. Ito, T. Saito, D. Nishide, T. Ishikura, A. Isobayashi, M. Katagiri, Y. Yamazaki, T. Matsumoto, and M. Kitamura, "Selective carbon nanotube growth in via structure using novel arrangement of catalytic metal," in IEEE International Interconnect Technology Conference, 2014. [30] Q. Ngo, A. M. Cassell, A. J. Austin, J. Li, S. Krishnan, M. Meyyappan, and C. Y. Yang, "Characteristics of aligned carbon nanofibers for interconnect via applications," Ieee Electron Device Letters, vol. 27, pp. 221-224, Apr 2006. [31] J. Li, Q. Ye, A. Cassell, H. T. Ng, R. Stevens, J. Han, and M. Meyyappan, "Bottom-up approach for carbon nanotube interconnects," Applied Physics Letters, vol. 82, pp. 2491- 2493, Apr 2003. [32] S. Hermann, S. Schulze, R. Ecke, A. Liebig, P. Schaefer, D. R. T. Zahn, M. Albrecht, M. Hietschold, S. E. Schulz, and T. Gessner, "Growth of carbon nanotube forests between a bi-metallic catalyst layer and a SiO2 substrate to form a self-assembled carbon-metal heterostructure," Carbon, vol. 50, pp. 4765-4772, Nov 2012. [33] S. Hermann, B. Pahl, R. Ecke, S. E. Schulz, and T. Gessner, "Carbon nanotubes for nanoscale low temperature flip chip connections," Microelectronic Engineering, vol. 87, pp. 438-442, Mar 2010. [34] S. Hermann, R. Ecke, S. Schulz, and T. Gessner, "Controlling the formation of nanoparticles for definite growth of carbon nanotubes for interconnect applications," Microelectronic Engineering, vol. 85, pp. 1979-1983, Oct 2008. [35] M. H. van der Veen, Y. Barbarin, Y. Kashiwagi, and Z. Tokei, "Electron mean-free path for CNT in vertical interconnects approaches Cu," in Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), IEEE International, pp. 181-184, May 2014. [36] S. Vollebregt, F. D. Tichelaar, H. Schellevis, C. I. M. Beenakker, and R. Ishihara, "Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 degrees C," Carbon, vol. 71, pp. 249-256, May 2014. [37] S. Vollebregt, S. Banerjee, A. N. Chiaramonti, F. D. Tichelaar, K. Beenakker, and R. Ishihara, "Dominant thermal boundary resistance in multi-walled carbon nanotube bundles fabricated at low temperature," Journal of Applied Physics, vol. 116, pp. 023514-7, Jul 2014.

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[38] S. Vollebregt, S. Banerjee, K. Beenakker, and R. Ishihara, "Thermal conductivity of low temperature grown vertical carbon nanotube bundles measured using the three-omega method," Applied Physics Letters, vol. 102, pp. 191909-3, May 2013.

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Conclusions and Future Work

The final chapter of the dissertation contains the conclusions of this study and suggestions for further work on nanocarbon-based on-chip interconnects. We begin with a concluding narrative based on understanding of the state-of-the-art, design and implementation of experiments presented here, and results/analyses of the findings. This is followed by recommendations on potential solutions to improve the performance of CNT interconnects, including an all-carbon 3D interconnect structure, and discussion of preliminary data on such system.

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6.1. Conclusions

The continued downward scaling of ICs following Moore’s law, which facilitated developments and manufacturing of transistors with smaller geometry, faster switching speeds, lower power consumption, and lower costs for subsequent generations of semiconductor technology nodes. However, shrinking on-chip interconnects have resulted in degraded performance and reliability, which in turn limit the IC speed and lifetime. Therefore, to sustain the continuous downward scaling, alternative materials to replace Cu and W as the interconnect conductor must be explored to meet and overcome these challenges. Among various replacement candidates such as Co, NiSi, graphene, and Ag nanowire reported in ITRS roadmap [1], CNT seems to hold special promise due to its unique electron transport and superior current-carrying capacity [2]. To evaluate the applicability of CNTs as an interconnect material, various test structures have been designed and fabricated, and their structural and electrical properties have been characterized extensively in this study. For horizontal interconnects, while lateral CNT growth and integration of a densely packed CNT bundle remains a challenge, electrical and structural characterization of drop-casted CNT interconnect test devices have been carried out. With contact engineering such as current stressing and W- deposited electrodes, the test devices yield significant improvement in its DC and RF characteristics. In fact, the horizontal structure can be modeled as a frequency- independent resistor up to 50 GHz. Structural characterization of W deposited at contacts reveals that W exhibits good wettability with carbon, a key requirement for realizing low-resistance ohmic contacts to CNT interconnects [3-5].

Much of the existing work on CNT interconnects focused on reduction of CNT growth temperature to the BEOL limit of 450°C [6] and to integrate CNT vias with conventional interconnect materials as contacts [7-10]. However, lowering the CNT growth temperature results in significant defects in CNT structure which increase its resistivity and hence the via resistance [11]. Further, an in-depth study of both performance and reliability of CNT vias with sub-50 nm linewidth and practical aspect ratios was lacking. Such a study is essential to evaluating the applicability of CNT as an interconnect material. Therefore, in this dissertation, CNT vias with lateral cross-sections 40 nm x 40 nm and 60 nm x 60 nm and aspect ratios of at least 2 have been electrically characterized to extract their resistivity, contact resistance, nanostructure, and current-carrying

147

Chapter 6 capacity. Nanostructures in CNT vias have been examined in this study using TEM and Raman analyses, which reveal vertical sidewalls inside vias with CNTs grown only from the base. They also reveal that the base contact of CNT is not an end-bonded contact made by blanket-grown CNTs with underlayer metal in an unpatterned substrate, but consists of Cr wrapping around CNTs to form a hybrid contact. On the other hand, the via top contact consists of an abrupt interface between CNTs and EBID- Pt in an end-bonded configuration. Raman analyses reveal significant reduction of defects in CNTs grown at 700°C compared to lower and more BEOL-compatible temperatures, consistent with results reported by Vollebregt [11], and yield electron mean free paths much less than CNT lengths used in our experiments. These findings justify our 700°C CNT growth temperature and the assumption of ohmic transport, respectively.

Electrical characterization of 60 nm x 60 nm CNT vias with a fixed height of 130 nm has been carried to obtain resistance and current-carrying capacity. Significant improvement in both via resistance and current-carrying capacity has been observed for 60 nm x 60 nm CNT vias after EBID-Pt top-contact deposition. Electrical measurements on 40 nm x 40 nm CNT vias on a wedge structure with EBID-Pt top contacts have yielded via resistance versus height data to extract CNT resistivity and contact resistance of 1.8 mΩ.cm and 2.8 kΩ, respectively. These values are the first reported for CNTs integrated in vias with 40 nm width. And the CNT resistivity is more than an order of magnitude less than that obtained from BEOL-compatible growth process [6]. Further, our measurements confirm that the high current-carrying capacities of CNTs are retained in the via structures, which are further enhanced by top contact engineering. While the CNT resistivity and via resistance remains two orders of magnitude higher than those of the conventional interconnect materials, Cu and W, this work has demonstrated the superior reliability of CNT vias, and that with improved CNT growth process and effective contact engineering including using other nanocarbons, the via performance can approach the point where the material can be fully integrated into chip manufacturing in end-of-roadmap technology nodes.

6.2. Future work on nanocarbon interconnects

Structural description and fabrication of CNTs in Sections 2.3 – 2.5 suggest that CNTs grown by other techniques such as arc-discharge can yield higher quality with minimal

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Chapter 6 defects. However, a hetero-interface between CNTs and conventional metal still remains at the as-grown contact. Although optimization of the as-grown interface between CNT and metal can in principle be achieved with tweaking CNT growth parameters, its implementation involves far too many variables to be practical as part of the chip manufacturing process [1]. To avoid such an interface, an all-carbon 3D interconnect structure is proposed, using graphene as horizontal interconnect with CNTs grown directly on it [12]. A schematic of this 3D structure together with an image of an existing multi-level on-chip interconnect network are shown in Fig. 6.1, and preliminary results on fabrication and characterization of test structures are presented as follows.

(a) (b)

Figure 6.1 (a) Cross-sectional SEM image of a six-level interconnect network in an IC [13]. (b) Schematic of a six-level all-carbon interconnect structure with CNT as vias and graphene as horizontal interconnects [14].

Ideally, if sp2 bonding continues from CNT into the graphene layer(s), the 3D structure shown in Fig. 6.1(b) should yield low overall resistance as well as low contact resistance compared to CNT-metal contacts. The structural and electrical characterization of such all-carbon 3D interconnect structure can be carried out to describe its behavior as a building block for a multi-level BEOL structure. Each layer of the structure in Fig. 6.1(b) consists of CNTs on graphene that can be fabricated by growing CNTs on an unpatterned substrate of graphene layers. The process flow to prepare such a 3D test structure is given in Fig. 6.2. We start with an undoped Si substrate with a layer of thermal oxide on it for electrical isolation. This is followed by evaporation of a 300 nm thick Ni layer, serving as catalyst for graphene growth. The sample is then subjected to

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annealing at 900°C in H2 ambient to increase the grain size of Ni film, which facilitates uniformity in the subsequent growth of multi-layer graphene (MLG) [12].

Figure 6.2 Process flow for CNT-graphene test structure fabrication [12].

After annealing, graphene is grown using a microwave PECVD (MPECVD) process, similar to the one described for CNT growth in Section 2.5, with methane as carbon precursor and hydrogen as reducing agent, resulting in a MLG film. To transfer the MLG to an oxide substrate for subsequent CNT growth and electrical measurements, a PMMA layer is deposited for a lift-off process [12]. CNTs are then grown on the transferred graphene using Fe and Ni as catalysts, respectively, with the same

MPECVD apparatus and CH4 or C2H2 as the carbon precursor. The CNT-graphene structures thus obtained are characterized using transmission electron microscopy with images shown in Fig. 6.3.

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Figure 6.3 Cross-sectional TEM images of CNTs grown on graphene with (a) Fe catalyst and (b) Ni catalyst. Distorted graphene is indicated near the base of the grown CNT in (a), while part of the graphene layer is missing at the interface after CNT growth in (b).

The TEM images in Fig. 6.3(a), where Fe catalyst is used, show that CNTs and graphene remain intact. Whereas, the images in Fig. 6.3(b) shows that some Ni particles remain on the surface of the substrate, with part of the graphene layer missing in the vicinity of the Ni particles. It has been previously demonstrated that Ni dissolves in carbon in the presence of H2, which can lead to etching of graphene [15].

Electrical characterization of a CNT-graphene sample prepared with Fe catalyst is carried out by first probing the graphene underlayer with 20 µm wide Au contact pads and varying separations as shown schematically in Fig. 6.4(a). The measurements confirm ohmic transport throughout the structure and yield a sheet resistance of 1821 Ω/□ and a contact resistivity of 950 Ω·µm. These values are consistent with values obtained for pristine graphene on oxide substrates [15], suggesting that the PECVD growth process and physical vapor deposition of Fe catalyst does not adversely affect the graphene.

Figure 6.4 (a) Electrical measurement schematic and resistance versus graphene length behavior after CNT growth, where W denotes the width of graphene stripe, RS the sheet resistance, and RC the contact resistivity. (b) Electrical measurement schematic and I-V characteristics of CNT- graphene heterostructure after oxide filling and polishing to expose CNT tips, where Rtotal denotes the total extracted resistance and LCNT the CNT height.

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After initial probing to inspect the graphene layer, Al2O3 is deposited using ALD to fill the voids between CNTs, similar to the process for CNT vias described in Section 4.4, and the CNT tips are exposed for subsequent direct probing, using wet etching in a buffered HF solution [15]. A cross-sectional schematic of the resulting structure is shown in Fig. 6.4(b) along with the resulting I-V plot. The I-V behavior is nonlinear, suggesting non-ohmic transport across the CNT-graphene interface, through graphene, and/or at the CNT-probe contact. Nevertheless, the extracted total resistance of 4 kΩ support the assertion of a continuous conduction path throughout the all-carbon 3D structure. From the results given in Fig. 6.4(a), each graphene stripe contributes ~3 kΩ to the total resistance. The CNT resistance is assumed to originate from two CNT vertical arrays each 1 μm high with a cross-sectional area of 2 μm× 2 μm (tip area of the probe), and estimated using the data obtained from sub-100 nm CNT vias [16-18] to be no more than 100 Ω. The remaining resistance mainly comes from the probe-CNT contacts and the CNT-graphene interface. The total resistance decreases as the applied voltage increases, due to the improved contact from Joule heating during the measurement, a well-known phenomenon for CNT-metal contacts [19]. Further experiments, such as in situ nanoprobing of individual CNTs inside a SEM chamber, are needed to extract the contact resistance of the CNT-graphene interface. Nevertheless, these electrical measurements have demonstrated the existence of both vertical and lateral conduction paths in the CNT-graphene structure. And they provide an independent support for the viability of a 3D CNT-graphene interconnect network, as well as an alternative to using conventional metals for making contact with CNTs. These findings will pave the way for further studies on 3D all-carbon interconnects.

References

[1] "International Technology Roadmap for Semiconductors," 2013. [2] W. S. Zhao, G. F. Wang, J. Hu, L. L. Sun, and H. Hong, "Performance and stability analysis of monolayer single-walled carbon nanotube interconnects," International Journal of Numerical Modelling-Electronic Networks Devices and Fields, vol. 28, pp. 456-464, Jul-Aug 2015. [3] Y. Matsuda, W.-Q. Deng, and W. A. Goddard III, "Contact Resistance for “End- Contacted” Metal− Graphene and Metal− Nanotube Interfaces from Quantum Mechanics," The Journal of Physical Chemistry C, vol. 114, pp. 17845-17850, Sep 2010. [4] Y. Matsuda, W.-Q. Deng, and W. A. Goddard, "Contact resistance properties between nanotubes and various metals from quantum mechanics," The Journal of Physical Chemistry C, vol. 111, pp. 11113-11116, Jul 2007.

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[5] S. C. Lim, J. H. Jang, D. J. Bae, G. H. Han, S. Lee, I. S. Yeo, and Y. H. Lee, "Contact resistance between metal and carbon nanotube interconnects: Effect of work function and wettability," Applied Physics Letters, vol. 95, Dec 2009. [6] S. Vollebregt, F. D. Tichelaar, H. Schellevis, C. I. M. Beenakker, and R. Ishihara, "Carbon nanotube vertical interconnects fabricated at temperatures as low as 350 degrees C," Carbon, vol. 71, pp. 249-256, May 2014. [7] N. Chiodarelli, A. Fournier, and J. Dijon, "Impact of the contact's geometry on the line resistivity of carbon nanotubes bundles for applications as horizontal interconnects," Applied Physics Letters, vol. 103, Jul 2013. [8] N. Chiodarelli, S. Masahito, Y. Kashiwagi, Y. Li, K. Arstila, O. Richard, D. J. Cott, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects," Nanotechnology, vol. 22, p. 085302, Feb 2011. [9] N. Chiodarelli, Y. L. Li, D. J. Cott, S. Mertens, N. Peys, M. Heyns, S. De Gendt, G. Groeseneken, and P. M. Vereecken, "Integration and electrical characterization of carbon nanotube via interconnects," Microelectronic Engineering, vol. 88, pp. 837-843, May 2011. [10] M. H. van der Veen, Y. Barbarin, Y. Kashiwagi, and Z. Tokei, "Electron mean-free path for CNT in vertical interconnects approaches Cu," in Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2014 IEEE International, pp. 181- 184, May 2014. [11] S. Vollebregt, R. Ishihara, F. D. Tichelaar, Y. Hou, and C. I. M. Beenakker, "Influence of the growth temperature on the first and second-order Raman band ratios and widths of carbon nanotubes and fibers," Carbon, vol. 50, pp. 3542-3554, Aug 2012. [12] C. Zhou, R. Senegor, Z. Baron, Y. Chen, S. Raju, A. A. Vyas, M. Chan, Y. Chai, and C. Y. Yang, "Synthesis and Interface Characterization of CNT on Graphene," Nanotechnology, in press. [13] L. Chen, "Metal silicides: An integral part of microelectronics," Journal of The Minerals, Metals & Materials Society, vol. 57, pp. 24-30, Sep 2005. [14] G. Dimitrakakis, G. Froudakis, and E. Tylianakis, "Designing novel carbon nanostructures for hydrogen storage," SPIE Newsroom, vol. 1451, p. 1-5, Mar 2009. [15] L. C. Campos, V. R. Manfrinato, J. D. Sanchez-Yamagishi, J. Kong, and P. Jarillo-Herrero, "Anisotropic Etching and Nanoribbon Formation in Single-Layer Graphene," Nano Letters, vol. 9, pp. 2600-2604, Jul 2009. [16] A. A. Vyas, C. Zhou, Y. Chai, P. Wang, and C. Y. Yang, "Effect of improved contact on reliability of sub-60 nm carbon nanotube vias," Nanotechnology, vol. 27, p. 375202, Aug 2016. [17] A. Vyas, P. Wang, C. Zhou, M. Chan, and C. Y. Yang, "Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias," IEEE International Interconnect Technology Conference, pp. 203-205, May 2016. [18] C. J. Zhou, A. A. Vyas, P. Wilhite, P. Wang, M. S. Chan, and C. Y. Yang, "Resistance Determination for Sub-100-nm Carbon Nanotube Vias," IEEE Electron Device Letters, vol. 36, pp. 71-73, Jan 2015.

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[19] P. Wilhite, A. A. Vyas, J. Tan, J. Tan, T. Yamada, P. Wang, J. Park, and C. Y. Yang, "Metal–nanocarbon contacts," Semiconductor Science and Technology, vol. 29, p. 054006-16, Apr 2014.

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Publications of Anshul A. Vyas

Refereed Journals

1. Anshul A. Vyas, Changjian Zhou, and Cary Y. Yang. “On-chip Interconnect Conductor Materials for End-of-Roadmap Technology Nodes.” IEEE Transactions on Nanotechnology, in press. 2. Changjian Zhou, Richard Senegor, Zachary Baron, Yihan Chen, Salahuddin Raju, Anshul A. Vyas, Mansun Chan, Yang Chai, and Cary Y. Yang. “Synthesis and Interface Characterization of CNT-Graphene Heterostructure for All-Carbon Interconnects.” Nanotechnology, in press. 3. Anshul A. Vyas, Changjian Zhou, Phillip Wang, Yang Chai, and Cary Y. Yang. “Effect of Improved Contact on Reliability of Sub-60 nm Carbon Nanotube Vias.” Nanotechnology, vol. 27, pp. 375202-11, September 2016. 4. Anshul A. Vyas, Changjian Zhou, Patrick Wilhite, Phillip Wang, and Cary Y. Yang. “Electrical properties of carbon nanotube via interconnects for 30 nm linewidth and beyond.” Microelectronics Reliability, vol. 61, pp. 35-42, June 2016. 5. Changjian Zhou, Anshul A. Vyas, Patrick Wilhite, Phillip Wang, Mansun Chan, and Cary Y. Yang. “Resistance Determination of Sub-100 nm Carbon Nanotube Vias.” IEEE Electron Device Letters, vol. 36, pp. 71-73, January 2015. 6. Patrick Wilhite, Hyung-Soo Uh, Nobuhiko Kanzaki, Phillip Wang, Anshul A. Vyas, Shushaku Maeda, Toshishige Yamada, and Cary Y. Yang. “Electron-beam and Ion- beam-induced Deposited Tungsten Contacts for Carbon Nanofiber Interconnects.” Nanotechnology, vol. 25, pp. 375702-8, August 2014. 7. Patrick Wilhite, Anshul A. Vyas, Jason Tan, Jasper Tan, Toshishige Yamada, Phillip Wang, Jeongwon Park, and Cary Y. Yang. “Metal-Nanocarbon Contacts.” Semiconductor Science and Technology, vol. 29, pp. 054006-16, July 2014 (Invited Review Paper). 8. Anshul A. Vyas, Francisco Madriz, Patrick Wilhite, Toshishige Yamada, Xuhui Sun, and Cary Y. Yang. “Carbon Nanofiber Interconnect RF Characteristics Improvement with Deposited Tungsten Contacts.” Journal of Nanoscience and Nanotechnology (Special issue in Nanospace Science and Technology), vol. 14, pp. 2683-2686, March 2014.

Patent

1. Bo Zheng, Avgerinos Gelatos, Anshul A. Vyas, Raymond Hung. “Pre-clean of Si- Ge for Pre-Metal Contact at Source, Drain, and Gate.” U.S. Patent No. 20160079062, 17 March 2016.

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Conference Proceedings

1. Anshul A. Vyas, Phillip Wang, Changjian Zhou, Yang Chai, and Cary Y. Yang. “Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias.” IEEE/AMC International Interconnect Technology Conference, San Jose, May 23-26, 2016, pp. 203- 205. 2. Richard Senegor, Zack Baron, Changjian Zhou, Yihan Chen, Anshul A. Vyas, Ayo Adesida, and Cary Y. Yang. “Carbon Nanotubes on Graphene – Interfacial and Electrical Properties.” Nanotech 2016 Conference & Expo, Washington, D.C., May 22- 25, 2016, 4 pp. 3. Chi-Nung Ni, Yi-Chiau Huang, Sungwon Jun, Shiyu Sun, Anshul A. Vyas, Fareen Khaja, Kalpatnam Vivek Rao, Shashank Sharma, Nicholas Breil, Miao Jin, Christopher Lazik, Abhilash Mayur, Jerry Gelatos, Hua Chung, Raymond Hung, Michael Chudzik, Naomi Yoshida, Nam Sung Kim. “PMOS Contact Resistance Solution Compatible to CMOS Integration for 7 nm Node And Beyond.” International Symposium on VLSI Technology, Systems and Applications, Hsinchu, April 25-27, 2016, pp. 1-2. 4. Anshul A. Vyas, Changjian Zhou, Patrick Wilhite, Phillip Wang, and Cary Y. Yang. “Carbon Nanotube Via Interconnects for 30 nm Linewidth and Beyond.” Proceedings of The 17th Takayanagi Kenjiro Memorial Symposium, Hamamatsu, November 17-18, 2015, 8 pp. (plenary paper) 5. Yusuke Abe, Anshul A. Vyas, and Cary Y. Yang. “Contact engineering for nanocarbon interconnects.” IEEE 15th International Conference on Nanotechnology, Rome, July 27-30, 2015, pp. 1194-1196. 6. Yusuke Abe, Anshul A. Vyas, Richard Senegor, and Cary Y. Yang. “Contact Engineering on Carbon Nanotube Interconnect Vias.” American Vacuum Society International Symposium and Exhibition, San Jose, October 18-23, 2015, 4 pp. 7. Yusuke Abe, Anshul A. Vyas, and Cary Y. Yang. “SEM Image Analysis of CNT Interconnect Vias.” Microscopy and Microanalysis Meeting, Portland, August 2-6, 2015, pp. 1-2. 8. Changjian Zhou, Anshul A. Vyas, Phillip Wang, and Cary Y. Yang. “Fabrication and Characterization of Carbon Nanotube Vias for Next-generation Technology Nodes.” IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, June 18-20, 2014, 2 pp. (invited paper) 9. Patrick Wilhite, Anshul A. Vyas, and Cary Y. Yang, “Metal-CNT Contacts,” Proceedings of the IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, Guilin, October 28-31, 2014, pp. 1-6. (invited paper) 10. Patrick Wilhite, Anshul A. Vyas, and C.Y. Yang, “Metal-CNT Contacts,” Extended Abstracts of 2014 International Conference on Solid State Devices and Materials, Tsukuba, September 8-11, 2014 pp. 832-833. (invited paper)

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11. Patrick Wilhite, Anshul A. Vyas, Jason Tan, Phillip Wang, Hua Ai, Murali Narasimhan, and Cary Y. Yang. “Electrical and Structural Analysis of CNT-Metal Contacts in Via Interconnects”, 7th International Conference on Quantum, Nano, and Micro Technologies, Barcelona, August 25-31, 2013, pp. 41-43. 12. Anshul A. Vyas, Jessica Koehne, Francisco Madriz, Patrick Wilhite, Phillip Wang, Changjian Zhou, Tian-Ling Ren, and Cary Y. Yang. “Electrical and Structural Characterization of Carbon Nanotube Interconnect Vias”, IEEE Nanomaterials and Device Conference, Tainan, October 7-9, 2013, Paper MP-4-9, 2 pp. 13. Anshul A. Vyas, Francisco Madriz, Nobuhiko Kanzaki, Patrick Wilhite, Xuhui Sun, and Cary Y. Yang. “RF Characteristics of One-Dimensional Nanocarbons”, International Conference on Emerging Electronics, Mumbai, December 12-17, 2012, pp.1- 3. 14. Anshul A. Vyas, Francisco Madriz, Nobuhiko Kanzaki, Patrick Wilhite, Xuhui Sun, and Cary Y. Yang. “High-frequency Behavior of One-Dimensional Nanocarbons”, IEEE International Conference on Solid-State and Integrated Circuit Technology, Xi’an, October 29 – November 1, 2012, pp. 1-4. (invited paper). 15. Anshul A. Vyas, Francisco Madriz, Nobuhiko Kanzaki, Patrick Wilhite, Jason Tan, Toshishige Yamada, and Cary Y. Yang. “Improved RF Characteristics of Carbon Nanotube Interconnects with Deposited Tungsten Contacts”, Nanotech Conference & Expo 2012, Santa Clara, June 18-21, 2012, pp. 21-22.

Conference Presentations

1. Anshul A. Vyas, Phillip Wang, Changjian Zhou, Yang Chai, and Cary Y. Yang. “Contact Resistance and Reliability of 40 nm Carbon Nanotube Vias.” 44th Electronic Materials Symposium, San Jose, May 20, 2016. 2. Yusuke Abe, Anshul A. Vyas, Richard Senegor, and Cary Y. Yang, “SEM Image Analysis of CNT Interconnect Vias,” Microscopy & Microanalysis 2015, Gottingen, September 6-11, 2015. 3. Anshul A. Vyas, Changjian Zhou, Patrick Wilhite, Mansun Chan, and Cary Y. Yang, “Carbon Nanotube Interconnect Vias,” International Conference on Materials for Advanced Technologies, Symposium Y: Reliability and Variability of Devices for Circuits and Systems, Singapore, June 28 – July 3, 2015. (invited presentation) 4. Anshul A. Vyas, Changjian Zhou, Richard Senegor, Ayo Adesida, Yusuke Abe, Phillip Wang, and Cary Y. Yang, “Carbon Nanotube On-chip Interconnect Vias,” 43rd Annual Northern California Electronic Materials Symposium, Santa Clara, May 22, 2015. 5. Anshul A. Vyas, Changjian Zhou, Richard Senegor, Ayo Adesida, Yusuke Abe, Phillip Wang, and Cary Y. Yang, “Carbon Nanotube On-chip Interconnect Vias,” IEEE SFBA Nanotechnology Council 11th Annual Symposium, Santa Clara, April 5, 2015.

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6. Anshul A. Vyas, Richard Senegor, Yusuke Abe, Ayo Adesida, Phillip Wang, Changjian Zhou, and Cary Y. Yang, “CNT Via Contact Resistance Extraction,” Materials Research Society Spring Meeting, Symposium Q: Nano Carbon Materials – 1D to 3D, San Francisco, April 6-10, 2015. 7. Yusuke Abe, Anshul A. Vyas, Changjian Zhou, Richard Senegor, Patrick Wilhite, and Cary Y. Yang, “Contact Metallization for Carbon Nanotube Interconnect Vias,” Materials Research Society Spring Meeting, Symposium BB: Innovative Interconnects/Electrodes for Advanced Devices, Flexible and Green-Energy Electronics, San Francisco, April 6-10, 2015. 8. Yihan Chen, Changjian Zhou, Anshul A. Vyas, Mansun Chan, and Cary Y. Yang, “All-Carbon Interconnects: Fabrication and Integration,” Materials Research Society Spring Meeting, Symposium BB: Innovative Interconnects/Electrodes for Advanced Devices, Flexible and Green-Energy Electronics, San Francisco, April 6-10, 2015. 9. Anshul A. Vyas, Francisco Madriz, Changjian Zhou, Bo Zheng, Jessica Koehne, Patrick Wilhite, Jerry Gelatos, Tian-Ling Ren, Mansun Chan, and Cary Y. Yang. “Carbon Nanotube Vias for End-of-Roadmap Technology Nodes,” Materials Research Society Spring Meeting and Exhibit, San Francisco, April 21-25, 2014. 10. Anshul A. Vyas, Changjian Zhou, Francisco Madriz, Jessica Koehne, Patrick Wilhite, Tian-Ling Ren, Mansun Chan, and Cary Y. Yang. “Electrical and Structural Characterization of Sub-100 nm Carbon Nanotube Vias”, 35th Annual Equipment Exhibition of American Vacuum Society, San Jose, February 20, 2014. 11. Anshul A. Vyas, Francisco Madriz, Jessica Koehne, Patrick Wilhite, and Cary Y. Yang. “Electrical and Structural Characterization of Carbon Nanotube Via Interconnects”, 41st Electronic Materials Symposium, Santa Clara, September 26, 2013. 12. Anshul A. Vyas, Changjian Zhou, Patrick Wilhite, Jessica Koehne, Phillip Wang, Tian-Ling Ren, and Cary Y. Yang. “Comparative Studies of Cu and CNT as On-chip Via Interconnect Materials”, Materials Research Society Spring Meeting and Exhibit, San Francisco, April 1-5, 2013. 13. Patrick Wilhite, Anshul A. Vyas, Jason Tan, Phillip Wang, Jeongwon Park, Hua Ai, Murali Narasimhan, and Cary Y. Yang. “Analysis of Interfaces between CNT and Metal Underlayers in Via Interconnects”, Material Research Society Spring Meeting and Exhibit, San Francisco, April 1-5, 2013. 14. Anshul A. Vyas, Francisco Madriz, Patrick Wilhite, Toshishige Yamada, and Cary Y. Yang. “RF Characteristics of Copper Vias”, Materials Research Society Spring Meeting and Exhibit, San Francisco, April 9-13, 2012. 15. Patrick Wilhite, Anshul A. Vyas, Jason Tan, Jeongwon Park, Phillip Wang, Michael Jackson, and Cary Y. Yang. “Nanostructure Characterization of Carbon Nanotube/Metal Interfaces”, Materials Research Society Spring Meeting and Exhibit, San Francisco, April 9-13, 2012.

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16. Anshul A. Vyas, Nobuhiko Kanzaki, Patrick Wilhite, Toshishige Yamada, and Cary Y. Yang. “RF Characteristics of Carbon Nanofiber with Tungsten Electrode Contacts”, 40th Electronic Material Symposium, Santa Clara, April 20, 2012. 17. Anshul A. Vyas, Francisco Madriz, Patrick Wilhite, Toshishige Yamada, and Cary Y. Yang. “Extraction of Copper-Via Impedance from RF Measurements”, 39th Electronic Materials Symposium, Santa Clara, April 15, 2011.

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