Analog Solutions for Xilinx FPGAs Product Guide

Inside:

1 Introduction 25 Design Protection Solutions for FPGAs 3 Powering Xilinx FPGAs and CPLDs Selector Guide and Tables Featured Products 29 Interfacing High-Speed DACs and ADCs to FPGAs Selector Guide and Tables Selector Guide and Tables 16 Signal Conversion Solutions for FPGAs Featured Products Selector Guide and Tables

Edition 1, April 2012 Analog Solutions for Xilinx FPGAs A message from the Corporate Vice President, Marketing, Xilinx Inc.

Dear Customers, From consumer electronics to industrial and telecom infrastructure equipment systems, sitting alongside the analog and mixed signal ICs that interface with the outside world are field programmable gate arrays (FPGAs) that deliver significant value through programmable system integration. If you are designing a system that requires integrating several key components to acquire and process data, you’re probably weighing your FPGA choices right now. So how do you determine which parts are not only the best for your design, but also work well together? Xilinx and Maxim are the winning formula to help you achieve success. For over a quarter century, both Xilinx and Maxim have specialized in integrated solutions designed to meet your most demanding system requirements. We have built our reputations as technology leaders, each with over $2 billion in revenues serving similar markets and common customers like you. Xilinx devices integrate memory, clocking, DSP functions, SerDes, and even embedded PowerPC and ARM processors within a programmable fabric to enable virtually any application. Maxim produces power management, data converters, sensors, I/O interfaces, RF, and other mixed signal functions to complete the system. So what can Xilinx and Maxim do for you? Consider ease of use. Xilinx provides programmable solutions to solve your toughest design challenges through its Targeted Design Platforms, a comprehensive and growing portfolio of development kits, complete with boards, tools, IP cores, reference designs, and FPGA Mezzanine Card (FMC) support, enabling designers to begin application development immediately. Maxim enables FPGA design with analog and digital power regulators and modules. Additionally, Maxim’s signal-chain building blocks and IP security parts perfectly complement Xilinx's FPGAs. Your design also calls for incorporating video, voice, or data. Xilinx and Maxim have those bases covered, too. As FPGAs grow in their use, so does the need for flexible and robust interfaces for the analog world around it. Maxim audio/video amplifiers and codecs, signal conditioning filters, signal integrity and protection circuits, as well as GHz DACs deliver superior performance. That's not all. You have worldwide support, which is always available to help you with your design. Leverage our solid team of field application engineers dedicated to resolving issues and design entire systems. Xilinx and Maxim also share Avnet as their primary distributor, eliminating the hassle of navigating multiple sales channels. And above all, our companies deliver innovative solutions that add value to your products, allowing you to focus on your project at hand. Xilinx and Maxim are building a future founded on expertise and innovation. In the following pages, discover more ways to use Xilinx FPGAs with Maxim ICs to realize your objectives faster.

Sincerely,

Bruce Kleinman Corporate Vice President, Marketing Xilinx Inc. Introduction

(LUTs) called field programmable world are analog in nature (temperature, Designing with gate arrays (FPGAs). In addition to pressure, sound, vision, voltage, current, Programmable Logic implementing Boolean logic and frequency, and others). Most data travel registers in the configurable logic on wires or wireless media as analog in an Analog World array, you can also use built-in features signals that need to be converted into 0s Programmable logic devices such as memory, clock management, and 1s for the FPGA to process. Making revolutionized digital design over 25 I/O drivers, high-speed transceivers, the analog world accessible to the digital years ago, promising designers a blank Ethernet MACs, DSP building blocks, and world is where Maxim shines. As one of chip to design literally any function embedded processors inside the FPGA. the top 3 players in nearly every analog and program it in the field. PLDs can function, Maxim has built a reputation Using programmable logic devices, data be low-logic density devices that use for innovation and quality. With a focus is input, processed and manipulated, nonvolatile sea-of-gates cells called on ease of use, our products simplify then output. However, this processing is complex programmable logic devices your system design allowing you to generally limited to the digital domain (CPLDs) or they can be high-density focus on your unique algorithms. devices based on SRAM look-up tables while most of the signals in the real

CONFIGURATION CLOCKS AND TIMING IP PROTECTION MEMORY

DATA CONVERTERS MULTIMEDIA

ANALOG HUMAN-MACHINE BUILDING BLOCKS INTERFACE

POWER SYSTEM MONITORING I/O INTERFACES MANAGEMENT

Figure 1. A Typical System Application Showing FPGA Working with Analog Functions

www.maxim-ic.com/xilinx 1 Power Management response authentication sequence to them from driving the voltage or current FPGAs and CPLDs require anywhere differentiate between authorized and levels required by many interface from 3 to 15 or more voltage rails. counterfeit devices, thereby protecting standards. RS-232, RS-485, CAN, IO-Link, The logic fabric is usually at the the design investment from copying Ethernet, optical, and IrDA are just a few latest process technology node that and cloning. Read about the benefits of common examples. Maxim’s portfolio determines the core supply voltage. our proprietary approach in the Design provides solutions to these interface Configuration, housekeeping circuitry, Protection Solutions for FPGAs section. problems, many including additional various I/Os, SerDes transceivers, clock Reference designs with FPGA logic are features for ESD and fault protection. In managers, and other functions have available. other cases, high-density interface ports differing requirements for voltage rails, Multimedia like 24+ port SATA and SAS transceivers sequencing/tracking, and voltage ripple can be off-loaded from the FPGA to a FPGAs are increasingly used to companion chip for optimizing costs. limits. Learn the best ways to manage process audio along with data. this complex challenge starting in the In most instances, these systems We provide power-over-Ethernet ICs to Powering Xilinx FPGAs and CPLDs section. require audio/video data converters, power devices such as security cameras, Data Converters amplifiers, filters, equalizers, signal IP phones, WiFi access points, and others through Ethernet. We can help you FPGAs in communications applications conditioners, on-screen display blocks, communicate over power lines using typically need high-speed data video decoders, and audio codecs. our power-line communication ICs. converters, while those in industrial and Maxim offers multimedia subsystem medical applications frequently require ICs, allowing the FPGA designer to Building Blocks focus on the advanced audio/video high precision and resolution. Maxim’s Maxim provides building blocks such processing stages of the design. data converter portfolio includes a as level translators, MEMS-based real- wide variety of devices that serve these Human-Machine Interface time clocks, oscillators, amplifiers, applications, including multi-GSPS Most systems interact with their human comparators, multiplexers, signal high-performance and 16-bit to 24- operators and the real world. Maxim conditioners, filters, potentiometers, bit precision A/D and D/A converters. provides a wide variety of state-of- ESD/fault protection, and other ICs to Turn to the Signal Conversion Solutions the art components to detect touch, make your design robust and reliable. for FPGAs section for information temperature, proximity, light, and System Monitoring about high-speed data converters. motion and convert those analog signals FPGAs are used in rack-mounted to the digital domain for processing IP Protection communications/computing within your FPGA. This includes devices While field programmability offers infrastructure or sensitive industrial/ suitable for high-volume consumer flexibility during the design process, medical and defense applications. For applications in addition to those built it can also expose your underlying these applications, Maxim provides a for the rugged industrial environments. IP to significant risks to reverse full spectrum of solutions for enclosure engineering and theft. Maxim provides I/O Interfaces management, thermal management, M 1-Wire secure EEPROMs that use While FPGAs include various I/O fan control, and hot-swap controllers, a single pin on the FPGA or CPLD to drivers such as LVTTL, LVCMOS, LVDS, including fault-detection/logging, secure the design implemented. The HSTL/SSTL, and multi-gigabit serial and security/authentication. secure memory uses a challenge and transceivers, process limitations preclude

2 Analog Solutions for Xilinx FPGAs Powering Xilinx FPGAs and CPLDs

Understanding FPGA Power Rails in an industrial application, and an Overview Artix Series FPGA used in a consumer M Modern PLDs have a core supply rail While Xilinx FPGAs based on SRAM application. technology offer higher logic density that powers most of the device and and consume higher power, Xilinx CPLDs consumes the highest power. With every Consider the latest FPGAs from Xilinx based on flash technology offer lower new technology node, there is a new as an example to understand the logic density and consume lower power. core supply voltage rail. Auxiliary voltage power needs better. Table 1 provides a PLD vendors use the latest process supply rails power supporting circuits summary of the key voltage rails in the technology node in every generation on a PLD such as configuration logic, Xilinx 7 series FPGAs inclusive of Virtex-7, of devices to increase the logic density clock managers, and other housekeeping Kintex-7, and Artix-7, as well as Zynq™- and integrate more features. Examples circuits. In addition, FPGAs are typically 7000 processing platform devices. While include block RAMs, clock managers, DSP used to bridge one interface standard this table shows the latest FPGAs, the functions, system interfaces, and even to another, and each I/O driver has its power-supply requirements of previous ARMM/PowerPCM processors. unique voltage rail ranging from 1.2 to generation FPGAs are quite similar. Xilinx 3.3V. Examples include LVTTL/LVCMOS, recommends a typical power-on and The integration of disparate functions LVDS, bus LVDS, mini LVDS, HSTL, SSTL, power-off sequence. The recommended and regular technology node migration and TMDS, among others. sequence for power-on is VCCINT, results in several power supply rails for a V , V , V , and V . PLD. The benefits of integration and ease Special care is needed in powering high- CCBRAM CCAUX CCAUX_IO CCO speed SerDes transceivers, each of which The recommended power-off sequence of use are questionable if you cannot is the reverse of the power-on sequence. power these programmable devices in can consume 1 to several amperes of an easy and cost-effective manner. Most current and run at speeds of 155Mbps to Power Architectures digital designers either underestimate 28Gbps and beyond. For example, a 100G The power architecture that supports the power supply needs of a PLD or are Ethernet application uses many such a PLD is influenced by the intended overwhelmed by them. Maxim can help transceivers and consumes 10A or more application: communications and you achieve first-time success with your of current. Because of the high speeds computing, industrial or automotive, FPGA power design and meet your time- involved, a noisy power rail is particularly or handheld consumer. Most to-market objectives by following simple detrimental to their performance. high-performance/high-power FPGA guidelines discussed in this chapter. Figure 2 illustrates a typical Virtex applications in communications and Series FPGA used in a communications computing infrastructure applications Power Requirements application, a Kintex Series FPGA used are built on line cards that are powered of PLDs Table 1. Xilinx 7 Series FPGAs and Zynq-7000 Extensible Processing Platform As PLDs assume the role of a system on Power-Supply Requirements a chip (SoC) on your board, powering these devices is comparable to powering Power Rail Nominal Voltage (V) Description an entire system. A typical high-end VCCINT 0.9/1.0 Voltage supply for the internal core logic VirtexM Series FPGA easily has 10–15 VCCAUX 1.8 Voltage supply for auxiliary logic unique rails. On the other hand, devices V 1.8/2 Voltage supply for auxiliary logic in I/Os from a lower density SpartanM, Kintex™, CCAUX_IO Artix™ , and CoolRunner™ Series can VCCO 1.2 to 3.3 Voltage supply for output drivers in I/O banks have 2–10 rails depending on your VCCBRAM 1 Voltage supply for block RAMs application. You need to pick the right VCCADC 1.8 A/D converter voltage supply set of power regulators depending VBATT 1.5 Security key battery backup voltage supply on the overall power level of each of MGTAVCC 1.0 Voltage supply for GTP/GTX/GTH transceiver the rails, their sequencing, and system Voltage supply for GTP/GTX/GTH transceiver MGT 1.2 power management needs. As process AVTT termination circuits technology nodes become smaller Analog supply voltage for the resistor calibration in FPGAs, there is a need for tighter MGT 1.2 AVTTRCAL circuit GTX/GTH transceivers column tolerances on the voltage supply rails. Auxiliary analog quad PLL (QPLL) supply for the Maxim provides 1% regulation accuracy MGT 1.8 AVCCAUX GTX/GTH transceivers across line/load and PVT variations. Note: The lowest-speed -1L and -2L versions of the devices have a 0.9V core voltage. Supply rails for voltage references for I/Os and MGT are not shown.

www.maxim-ic.com/xilinx 3 by a 48V or 72V backplane in a A) POWERING A VIRTEX SERIES FPGA IN A COMMUNICATIONS APPLICATION rack-mounted system. A two-stage intermediate bus architecture (IBA) is PLUG-IN CARD 1 typically used in these applications for -48V FIRST STAGE SECOND STAGE BACKPLANE 1.0V, 16A the individual cards (Figure 2A). The POL1 first stage is a step-down converter that 1.2V, 10A converts the 48V or 72V to an isolated POL2 -48V → 5V 5.0V intermediate voltage such as 12V or 5V. ISOLATED FPGA REGULATOR 1.1V, 10A The plug-in cards are often isolated from POL3 each other for safety reasons and to 3.3V, 1A eliminate the possibility of current loops POL4 and interference between the cards. The second stage of the IBA is to convert the intermediate voltage to multiple lower DC voltages, using nonisolated PLUG-IN CARD 10 regulators that are in close proximity to FIRST STAGE SECOND STAGE the FPGA and often called point-of-load 1.2V, 5A (POL) regulators. Multiple-output POLs POL1 are called PMICs. -48V → 12V 12V 1.1V, 2A ISOLATED POL2 FPGA FPGAs used in industrial and automotive REGULATOR 3.3V, 0.5A applications are typically powered by POL3 an isolated AC/DC or DC/DC supply followed by a 24V supply that is non- isolated (Figure 2B). POL regulators located next to the FPGA generate the specific voltages required by the FPGA. B) POWERING A KINTEX SERIES FPGA IN AN INDUSTRIAL APPLICATION

Consumer and handheld equipment ISOLATED 24V run on 3.6V to 12V batteries. The specific BACKPLANE 1V, 3A voltages required by an FPGA in such PMIC 1 1.2V, 2A an application can be generated by OPTIONAL POLs directly from the battery voltage STAGE AC/DC (Figure 2C). 5V/ 1V, 6A OR 24V POL FPGA 12V Maxim provides power solutions for DC/DC every stage of these three architectures: 1.8V, 1A 3.3V, 0.75A • Front-end isolated AC/DC and DC/ PMIC 2 DC power regulators from 5W to 1.5V, 0.5A hundreds of Watts of power with high efficiencies

• 4.5V to 60V (24V nominal) nonisolated C) POWERING AN ARTIX/Spartan SERIES FPGA OR CoolRunner-IICPLD IN A CONSUMER APPLICATION DC-DC buck regulators often used in industrial and building automation 3.3V, 50mA applications where FPGAs are common PMIC 1.5V, 100mA • Primary stage controllers supporting up to 200A to 300A 3.6V/ 1.8V, 50mA POL FPGA/CPLD • Secondary stage single- and multirail 7.2V POL regulators to power FPGAs and CPLDs Figure 2. Typical FPGA Power Architecture Used in Communications, Industrial, and Consumer Applications

4 Analog Solutions for Xilinx FPGAs System Considerations regulators and switching mode power the cost of additional features must be System-level design considerations supplies (SMPS) regulators. LDOs convert carefully weighed against the benefit influence the choice of power architec- the VIN to VOUT at the required current and provided. Sometimes power regulators ture. Simpler power system designs dissipate the power difference as heat. loaded with features are selected for Xilinx can use single and multirail regulators This makes LDOs inefficient for power development boards, but such products that take a 5V/12V input and supply levels exceeding 100mW in most cases. are not cost-effective and can reduce power to all FPGA rails with built-in Yet, LDOs are very easy to design and use. your competitiveness. A good example illustrating this concept is a Kintex-7 sequencing and minimal external SMPS regulators use a PWM (pulse-width development board using over a dozen components. Ease of use is paramount in modulation) controller with MOSFETs 20A and 10A power modules, resulting in such applications. Features that simplify (internal or external) acting as switches more than 100A of current supplied. these power designs include internal and an inductor acting as an energy MOSFETs, internal compensation, digital storage device. By controlling the duty Advanced Features programmability, and even internal cycle, an SMPS regulator manages Power regulators provide several inductors. the energy in the inductor thereby advanced features beyond the Infrastructure equipment uses FPGAs, regulating the output voltage despite input/output voltages and currents. DSPs, ASICs, and peripherals on the line and load variations. Efficiencies as Depending on your application, a board that are powered by numerous high as 90% to 95% are realized, unlike feature can be critical for success or POL regulators controlled by a master LDO regulators. completely unnecessary. It is important controller. PMBus™ protocol or I2C/SPI- The Four Ps of Power to understand the types of features available in today’s regulators. based control with a microcontroller is The four Ps of power are: products, often used in these applications. It might process, packaging, and price. Startup Sequencing/Tracking be necessary to control both the power of Three or more voltage rails are typically Process technology is a key part of the FPGAs on the board and also several required to power an FPGA and power-supply choice. The process used other devices along with dynamic power need sequencing for power-up and to develop power regulators determines management and monitoring. Also, it power-down. Sequencing limits the the performance of the MOSFETs used, is suggested to turn on/off some ICs inrush current during power-up. If the and thereby, the efficiency and die area. based on trigger events. Maxim provides sequencing is ignored, the devices that A MOSFET with low R (drain-source advanced system power management DSON require sequencing can be damaged resistance) is more efficient dissipating ICs (i.e., the MAX34440 and MAX34441) or latchup which, in turn, can cause lower power without occupying a larger to control multiple POL regulators and a malfunction. There are three types die area. Similarly, smaller geometries fans enabling dynamic power regulation of sequencing: coincident tracking, aid in integration of digital logic such (hibernate, standby, etc.) and superior sequential tracking, and ratiometric as sequencing, and PMBUS control with monitoring and fault logging. tracking. An example of sequential power regulators. A careful balance of tracking is shown in Figure 3. Applications that run on batteries process technology and cost is required to take advantage of Xilinx FPGAs’ power meet FPGA power requirements. Typically, Sequencing and tracking capabilities saving modes to keep the FPGA circuits the top three suppliers have these process are integrated into many of Maxim’s in hibernate modes most of the time capabilities, unlike vendors who cut multioutput power regulators. Stand- except when crunching algorithms. The corners to sell cheap regulators. alone ICs that perform sequencing and regulators that power the FPGAs can also tracking are also available. save energy and improve efficiency by Due to the amount of power required from employing techniques such as pulse- the regulators by the FPGAs, the regulators’ skipping. Many Maxim regulators use ability to manage the heat generated is V such technologies to provide light-load critical. A superior power regulator can VCCINT operation mode and control. regulate properly over temperature and uses industry-leading packages such as a VCCO Power Regulation QFN with an exposed pad. Primer Price of the regulator is usually a critical DC-DC power regulators come in two factor. The number of regulators used on t major categories: low dropout (LDO) a board can easily multiply. Therefore, Figure 3. Sequential Tracking

www.maxim-ic.com/xilinx 5 Monotonic Startup Voltage Ramp and without sustained ringing or thermal management. They are best Most Xilinx FPGA and CPLD rails have a ripple in the output voltage. for VCCINT and transceiver power rails. monotonic voltage ramp requirement, Synchronizing to an External Clock Remote Sensing meaning that the rails should rise FPGAs are used in applications that There can be a significant voltage drop continuously to their setpoint and not need power regulators to synchronize on a PCB between the power-supply droop. Drooping could result if the with common clocks to streamline output and the FPGA power-supply pins. POL does not have enough output communication between the system This occurs particularly in applications capacitance (Figure 4). controller and the power supplies. where the load current is high, and it Soft-Start Many POLs provide an external SYNC is not possible to place the regulator Most Xilinx FPGAs specify minimum and pin to allow the system designer to circuit close enough to the FPGA power maximum startup ramp rates. Power- synchronize one or multiple regulators pins. Remote sensing resolves this issue supply regulators implement soft-start to a common system clock. by using a dedicated pair of traces to by gradually increasing the current limit Multirail Regulators and Multiphase accurately measure the voltage at the at startup. This slows the rate of rise of Operation FPGA’s power-supply pins (Figure 5) and compensating for the drop. Remote the voltage rail and reduces the peak FPGAs need multiple regulators for sensing is also recommended for voltage inrush current to the FPGA. POLs allow regulating all the supply rails. Quite rails with very tight tolerances (≤ 3%). soft-start times to be programmed. often dual/triple/quad regulators Power-Supply Transient Response are used for optimal layout. Multirail Programmable Options FPGAs can implement many functions regulators can often be used in a Power regulators can include one or at different frequencies due to their multiphase configuration operating several programmable options such as multiple clock domains. This can in parallel to increase the current output voltages, switching frequency, result in larger step changes in current capability. Their switching frequencies slew rate, and others. A traditional requirements. Transient response are synchronized and phase shifted by approach is to provide this capability refers to a power supply’s ability to 360/n degrees, where n identifies each through I/O pins on the regulator that respond to abrupt changes in load phase. Multiphase operation yields can be tied to a specific resistance current. A regulator should respond lower input ripple current, reduced value. Depending on the resistance, without significantly overshooting output ripple voltage, and better an appropriate programming option or undershooting its set point is chosen. This can quickly become complicated and unwieldy depending VOUT VIN REGULATOR on the number of programming options. V VSENS+ Increasingly, many power regulators 2 REMOTE provide an I C or SPI interface to digitally FEEDBACK SENSE FPGA program the options with a tiny register VCCINT AMP VSENS- set. Quite often, these options can NONMONOTONIC RAMP be changed in the field by a system GND GND microcontroller as required. t

Figure 4. Nonmonotonic Startup Voltage Ramp Figure 5. Remote Sensing

6 Analog Solutions for Xilinx FPGAs Once you have determined the input Maxim recommends that you extract Choosing Power voltage, Xilinx provides its Power the voltages and currents into a table Regulators Estimator spreadsheet (www.xilinx.com/ and determine your power architecture. Most power-supply vendors complicate power) that gives you a list of all power Every time you add an intermediate choosing power supply regulators for supply rails and a rough estimate of the regulator, you might be sacrificing FPGAs by providing too many tools and current consumption for each. Xilinx also system-level power efficiency. This web interfaces just to pick a part. Not provides XPower tools built into their is because you get less than 100% Maxim! Our goal is to provide you with ISEM design environment that provide a efficiency at each stage. Going from the the right information to evaluate and more accurate power requirement based main system input voltage to all the choose the power supply you need in a on resource utilization, clock frequency, FPGA rails is an ideal method except few simple steps. and toggle rates. Figure 7 shows an when the efficiency loss is so high with example of Xilinx Power Estimator one stage (typically when either V / Estimating Your FPGA’s IN spreadsheet for Virtex-7 FPGAs. VOUT voltage change is high or currents Power Needs First, determine the input voltage. Second, identify the supply rails and load CHOOSING YOUR FPGA POWER REGULATORS • USE THE FPGA VENDOR POWER ESTIMATION SPREADSHEET. currents needed by the FPGA for your 1 • IDENTIFY ALL THE REQUIRED VOLTAGE RAILS AND CURRENTS. application. And third, use our product • USE THE MAXIM POWER REGULATOR CHECKLIST. 2 selector guide to pick the appropriate • IDENTIFY/DECIDE: VIN, VOUT, IOUT, SEQUENCE, I2C/PMBus, PROGRAMMABILITY, SPECIAL NEEDS. part (Figure 6). 3 • USE THE MAXIM PRODUCT SELECTOR TO CHOOSE PARTS.

Figure 6. Choosing Your FPGA Power Regulators

PICK THE DEVICE 1 3 CAPTURE DETAILS THE VOLTAGE RAILS AND REQUIRED CURRENT AND MOVE TO CHECKLIST (TABLE 2)

2 ENTER THE UTILIZATION AND PERFORMANCE OF ALL FPGA RESOURCES

Figure 7. Xilinx Power Estimator Tool www.maxim-ic.com/xilinx 7 handled are in excess of 50A) that you are Necessities Optional Features better off dividing it into multiple stages. Every FPGA design needs power Depending on your application, you Identify the power requirements of other regulators with ability to select the might need advanced system control external components such as memories, output voltage, as well as sequencing, using PMBus or other means. You might processors, data converters, I/O drivers, adjustable soft-start, monotonic ramp- need multiphase operation to handle and others to determine whether you up, and a good transient response. high currents, remote sensing capability, can regulate them together with the User Preferences synchronization to an external clock, FPGA rails based on total current. Also, and power monitoring functions. Or Most users have preferences for their note any special sequencing, ramp- you might need to control the slew rate power-supply design. On one hand, up, soft-start, and other requirements. to mitigate voltage ripple on SerDes some customers want to buy a PWM Finally, evaluate cost, efficiency, and size channels in high-speed transceiver controller and use external MOSFETs, targets. A checklist is provided in Table 2 applications. external compensation, and an external to help you. system control. On the other hand, Digital Power Control Which Features Do You Need? some customers prefer a fully integrated A new trend in the industry is the use By now, you should have a thorough controller and MOSFETs as well as of digital control loop regulators for understanding of your FPGA’s power built-in internal compensation, digital enhanced automatic compensation budget, its supply rails, and other programmability, and system control. to simplify design and reduce cost. system-level considerations. Let us Maxim provides parts for the entire Most digital power solutions today examine the must-have power regulator spectrum of customer choice. Keeping use proportional-integral-derivative features for every FPGA designer, the the digital designer in mind, we are (PID) control, but performance is application-specific optional features, developing a family of parts with GUI- compromised because of the windowed 2 and preferences. based programming facilitated by I C. ADCs used. Maxim’s InTuneK digital- control power products are based on state-space or model-predictive control, rather than the proportional- Table 2. FPGA Power Supply Checklist integral-derivative (PID) control used Checklist Item Answer by competitors. The result is a faster Basic Requirements transient response. Unlike competing PID controllers, the InTune architecture Identify input voltage rail (e.g., V = 5V) IN uses a feedback analog-to-digital List all FPGA voltage rails and the current required for each converter (ADC) that digitizes the full (e.g., V = 1.8V at 5A, V = 1.5V at 2A) CCINT CCO1 output voltage range. Its automatic Sequencing requirements and order (timing diagram), compensation routine is based on power-on/-off, under fault recovery measured parameters providing better Switching frequency desired accuracy, and thus better efficiency. Soft-start ramp rate (e.g., 5ms) Design and Simulate Single/multirail regulators required? the Power Supply Internal compensation required? While many power regulators come Configuration: I2C or use resistor values? with built-in compensation, you still Advanced Features and Requirements need to choose the right inductor Output voltage ripple targets (mV) for transceivers value for your unique output current Sink Current capability (for DDR) requirement. If the regulator needs Synchronize to external clock? external compensation, you need to Power-up in prebiased load? select the right RC values to compensate the control loop for your output voltage. PMBus control or I2C/SPI required? Maxim provides a web-based design and Protection features simulation tool for power supplies called Remote sensing capability needed? EE-SimM (www.maxim-ic.com/eesim).

8 Analog Solutions for Xilinx FPGAs It asks for your design requirements and Addressing Your Requirements: regulators are acclaimed as the most outputs a complete schematic and bill of Cost, Size, Efficiency, and Ease efficient for a given power level. Plus, we materials. You can make changes to the of Use offer 1% regulation accuracy over PVT component values on the schematic to that very few vendors can match. fine tune your power design. Beyond the voltages, currents, and features, you will most likely choose your Finally, there’s ease of use. Maxim’s EE-Sim also provides rapid simulation power supply based on few key metrics: FPGA power regulators are user- of your power regulator design. Unlike cost, size, efficiency, and ease of use. friendly and getting even easier to use. Spice models that take a long time to Let’s consider both the IC cost and the Almost all our FPGA power regulators converge, making it frustrating to design, total solution cost. A good FPGA power have internal MOSFETs. Several have EE-Sim relies on advanced SIMPLIS models regulator should have the necessary internal compensation circuits for with a simple web interface that is swift features discussed previously integrated common output voltages. Our thermally and easy. An EE-Sim example is shown into the IC. This reduces the overall efficient QFN and CSP packages in Figure 8, recommending the external solution cost and size. simplify PCB design. With GUI-based component values as well as Bode plots to programming, choosing the power identify phase margin and efficiency plots. Efficiency is a function of your power regulator options is as easy as choosing If you want to download the simulation architecture of primary and secondary FPGA programming options in ISE. model for additional analysis offline, a free stage regulators as well as each individual version of EE-Sim is available. regulator performance. Maxim’s power

PICK INPUT VOLTAGE, OUTPUT VOLTAGE, LOAD CURRENT, 1 SWITCHING FREQUENCY, AND OTHER BASIC PARAMETERS

REVIEW GAIN/PHASE MARGIN, TRANSIENT ANALYSIS, STEADY-STATE ANALYSIS. 3 YOU CAN DOWNLOAD THE DESIGN AND SIMULATION ENGINE FREE

TOOL GENERATES A SCHEMATIC. CHANGE 2 THE VALUES OF R, C, AND L IF NEEDED

Figure 8. EE-Sim Simulation Tool (MAX8686) www.maxim-ic.com/xilinx 9 Featured Products

Highly Integrated Step-Down DC-DC Regulator Benefits Provides Up to 25A for High Logic Density FPGAs • Enough margin to safely power FPGAs from popular 5V/12V inputs MAX8686 ◦◦ Wide 4.5V to 20V input voltage range ◦◦ Adjustable output from 0.7V to 5.5V The MAX8686 current-mode, synchronous PWM step-down regulator with ◦◦ 25A output capability per phase integrated MOSFETs provides the designer with a high-density, flexible solution ◦◦ 300kHz to 1MHz switching frequency for a wide range of input voltage and load current requirements. This device combines the benefits of high integration with a thermally efficient TQFN package. • Enable high voltage regulation accuracy for FPGAs with low core voltages ◦◦ 1% accurate internal reference ◦◦ Differential remote sense • Designed to simplify powering FPGAs/ VIN = 12V IN BST CPLDs

VOUT = 1.2V/25A ◦◦ Monotonic startup (prebias) PGND LX ◦◦ Adjustable soft-start to reduce inrush current RS+ REFIN MAX8686 ◦◦ Output sink and source current RS- capability PHASE/REFO CS+ ◦◦ Reference input for output tracking COMP CS- • Integrated protection features enable POK POK OUTPUT robust design

EN/SLOPE ◦◦ Thermal overload protection

ENABLE ◦◦ UVLO (undervoltage lockout) INPUT ◦◦ Output overvoltage protection

FREQ SS GND ILIM ◦◦ Adjustable current limit supports a wide range of load conditions • 6mm x 6mm, TQFN-EP package reduces board size

10 Analog Solutions for Xilinx FPGAs Dual, 4MHz Internal FET Step-Down DC-DC Benefits Regulator Reduces Size and Cost • Designed to simplify powering FPGAs/ CPLDs MAX15021 ◦◦ Monotonic startup (prebias) ◦◦ Internal digital soft-start to reduce The MAX15021 dual output, synchronous PWM step-down regulator with integrated inrush current MOSFETs provides the designer with a high-density solution that maximizes board ◦◦ Sequencing and coincidental/ space and reduces the overall solution cost. ratiometric tracking • Reduces solution size VOUT1 ◦◦ Fast 4MHz switching minimizes VIN CI2 inductor size R1OUT2 RI2 ◦◦ 180° out-of-phase switching reduces

C1 input ripple current R1 CF2 RF2 ◦◦ Lead-free, 28-pin, 5mm x 5mm R2OUT2 TQFN-EP package C C C 2 IN2 DD2 CCF2 • Flexible and adjustable voltage and power ranges ensure compatibility AVIN EN2 PVIN2 DVDD2 FB2 COMP2 L2 LX2 VOUT2 with a variety of FPGAs ◦◦ Allows easy reuse among multiple RS2 COUT2 FPGA designs

CS2 ◦◦ Reduces total design time and PGND2 VIN inventory holding costs CDD1 ◦◦ 2.5V to 5.5V input voltage range DVDD1 ◦◦ 0.6V to 5.5V adjustable output EN1 VAVIN ◦ Output current capabilities of 4A VIN ◦ CIN1 (reg. 1) and 2A (reg. 2) PVIN1 ◦◦ 500kHz to 4MHz switching frequency VOUT1 MAX15021 L1 LX1 • Operates over the -40°C to +125°C temperature range RS1 COUT1

CS1 PGND1

CI1

R1OUT1 RI1

FB1 RT SGND SEL COMP1 R PGND SGND 2OUT1 CF1 RF1

RT CT CCF1

www.maxim-ic.com/xilinx 11 Example Designs for Xilinx FPGAs

VIN = 12V VIN = 12V

MAX8686 x 2 VCCINT, VCCBRAM DC-DC 1V, 20A VCCO MAX8686 VCCAUX, VCCAUX_IO, VCCO, 3.3V, 8A DC-DC MAX8686 VCCADC, MGTVCCAUX DC-DC 1.8V, 6A VCCO MAX8686 2.5V, 8A DC-DC MAX8686 MGTAVCC 10mVRIPPLE 1.0V, 6A VCCO MAX8654 1.5/1.35V, 4A DC-DC

MAX8654 MGTAVTT, MGTAVTTRCAL VCCAUX_IO 2.0V, 3A 10mVRIPPLE 1.2V, 4A

MAX8654 DC-DC

POWER-ON SEQUENCING ORDER

Figure 9. Virtex-7 FPGA Power Architecture Example

VIN = 12V VIN = 12V

MAX8686 VCCINT, VCCBRAM DC-DC 1V, 6A VCCO MAX8686 VCCAUX, VCCAUX_IO, VCCO, 3.3V, 8A DC-DC MAX8686 VCCADC, MGTVCCAUX DC-DC 1.8V, 6A VCCO MAX8686 2.5V, 8A DC-DC MAX8686 MGTAVCC 10mVRIPPLE 1.0V, 6A VCCO MAX8654 1.5/1.35V, 4A DC-DC

MAX8654 MGTAVTT, MGTAVTTRCAL VCCAUX_IO 2.0V, 2A 10mVRIPPLE 1.2V, 4A

MAX15041 DC-DC

POWER-ON SEQUENCING ORDER

Figure 10. Kintex-7 FPGA Power Architecture Example

12 Analog Solutions for Xilinx FPGAs Example Designs for Xilinx FPGAs (continued)

VTT, 0.75V, 1A DDR3 TERMINATION

MAX1510 VIN = 5V REFIN IN VIN = 5V SOURCE/SINK LDO

VCCO, VCCAUX 1.8V, 2A MAX15053 VCCODDR, 1.5V, 2A MODULE MAX15021 V , 1.8V 150mA MAX1983 DUAL DC-DC CCADC LDO VCCINT, VCCBRAM 1V, 3A VREFP, 1.25V, 5mA MAX6037A VOLTAGE REFERENCE 0.2%, 50ppm/°C

POWER-ON SEQUENCING ORDER

Figure 11. Artix-7 FPGA Power Architecture Example

VTT, 0.75V, 1A DDR3 TERMINATION

MAX1510 V = 5V REFIN IN V = 5V IN SOURCE/SINK IN LDO

VCCODDR, 1.5V, 1.5A

MAX15021 VCCO 1.8V, 0.8A MAX15053 DUAL DC-DC MODULE VCCINT, 1V, 1.3A VCCADC, 1.8V 150mA MAX1983 ADJUSTABLE VCCO, 3.3/2.5/1.8V, 2A LDO MAX15021 DUAL DC-DC VREFP, 1.25V, 5mA MAX6037A VOLTAGE REFERENCE 0.2%, 50ppm/°C VCCAUX 1.8V, 0.8A

POWER-ON SEQUENCING ORDER

Figure 12. Zynq Extended Processing Platform Power Architecture Example

www.maxim-ic.com/xilinx 13 Selector Guide and Tables

Product Selector

Core Power Regulator, VCCINT (0.9V to 1.2V Depending on FPGA/CPLD Generation) Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A MAX8516 LDO MAX8526 LDO MAX8517 LDO MAX8527 LDO MAX8518 LDO MAX8566 Buck MAX8528 LDO 1.8 MAX8902 LDO MAX8526 LDO MAX8646 Buck MAX1956 Controller MAX8556 LDO MAX8527 LDO MAX1956 Controller MAX8557 LDO MAX8528 LDO MAX8643 Buck MAX8794 LDO MAX8526 LDO MAX8527 LDO MAX8528 LDO MAX8516 LDO MAX8902 LDO MAX15053 Buck MAX15039 Buck MAX8517 LDO 2.7 to 5.5 MAX1983 LDO MAX8643 Buck MAX15112 Buck MAX15118 Buck MAX8518 LDO MAX8649 Buck MAX15038 Buck MAX15108 Buck MAX8649 Buck MAX15050 Buck MAX15051 Buck MAX17083 Buck MAX8654 Buck MAX8686 Buck MAX15036 Buck MAX8686 Buck MAX8597 Controller MAX15036 Buck MAX15036 Buck MAX15037 Buck 4.5 to 14 MAX8598 Controller MAX8598 Controller MAX15037 Buck MAX15037 Buck MAX15066 Buck MAX8599 Controller MAX8599 Controller MAX8654 Buck MAX15026 Controller MAX15026 Controller MAX15006 LDO MAX8597 Controller MAX15007 LDO MAX17502 Buck MAX8792 Controller MAX8598 Controller MAX8792 Controller 4.5 to 24 MAX17501 Buck MAX15041 Buck MAX15041 Buck MAX8599 Controller MAX15026 Controller MAX15041 Buck MAX8792 Controller MAX15026 Controller MAX15035 Buck MAX1776 Buck MAX15026 Controller MAX8597 Controller MAX15041 Buck MAX8598 Controller MAX15026 Controller MAX15026 Controller MAX8599 Controller 4.5 to 28 MAX15041 Buck MAX15041 Buck MAX15046A/ MAX15046A/ MAX15026 Controller MAX15046B Controller MAX15046B Controller MAX15046A/ MAX15046B Controller

Auxiliary, I/O, and MGT Power Regulators (1.2V, 1.5V, 1.8V, 2.5V, 3.3V) Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A MAX8516 LDO MAX8517 LDO MAX17016 Buck MAX8518 LDO MAX8556 LDO MAX15108 Buck MAX1956 Controller 1.8 MAX8902 LDO MAX8526 LDO MAX8557 LDO MAX1956 Controller MAX8792 Controller MAX8527 LDO MAX8794 LDO MAX8792 Controller MAX8528 LDO MAX8794 LDO (Continued on following page)

14 Analog Solutions for Xilinx FPGAs Auxiliary, I/O, and MGT Power Regulators (1.2V, 1.5V, 1.8V, 2.5V, 3.3V) (continued) Input Voltage (V) ≤ 500mA ≤ 1A to 1.8A ≤ 2A to 5A ≤ 5A to 10A ≤ 30A MAX15118 Buck MAX15038 Buck MAX15039 Buck MAX15112 Buck MAX15039 Buck MAX8654 Buck MAX17016 Buck MAX15053 Buck MAX15050 Buck MAX15108 Buck MAX1956 Controller 2.7 to 5.5 MAX8902 LDO MAX15038 Buck MAX17083 Buck MAX17016 Buck MAX15026 Controller MAX15026 Controller MAX1956 Controller MAX8792 Controller MAX1956 Controller MAX8792 Controller MAX8598 Controller MAX8599 Controller MAX8655 Buck MAX15041 Buck MAX15035 Buck MAX17016 Buck MAX15036 Buck MAX8654 Buck MAX15035 Buck MAX8902 LDO MAX15037 Buck 4.5 to 14 MAX15041 Buck MAX17016 Buck MAX8792 Controller MAX1776 Buck MAX8654 Buck MAX8792 Controller MAX15026 Controller MAX5089 Buck MAX15026 Controller MAX8598 Controller MAX15026 Controller MAX8599 Controller

Multiple Output Power Regulators ≤ 2A to 3A per Input Voltage (V) Quad Regulators ≤ 5A per Output ≤ 15A per Output 25A per Output Output MAX8833 Dual Buck 1.8 — MAX8833 Dual Buck — — MAX8855 Dual Buck MAX15021 Dual Buck 2.7 to 5.5 — — — — MAX15022 Dual Buck MAX17017 MAX15002 Dual MAX15002 Dual 1 Controller, 2 Bucks, Controller Controller 1 LDO MAX15048 Triple MAX15048 Triple MAX15002 Dual 4.5 to 14 — MAX17019 Controller Controller Controller 1 Controller, 2 Bucks, MAX15049 Triple MAX15049 Triple 1 LDO Controller Controller MAX15002 Dual MAX15002 Dual MAX15002 Dual Controller Controller Controller MAX15002 Dual MAX17017 MAX15023 Dual MAX15023 Dual MAX15023 Dual Controller 1 Controller, 2 Bucks, Controller Controller Controller MAX15023 Dual 1 LDO MAX17007B Dual MAX17007B Dual MAX17007B Dual Controller 4.5 to 28 MAX17019 Controller Controller Controller MAX15034 Dual 1 Controller, 2 Bucks, MAX15048 Triple MAX15048 Triple MAX15048 Triple Controller 1 LDO Controller Controller Controller MAX17007B Dual MAX15049 Triple MAX15049 Triple MAX15049 Triple Controller Controller Controller Controller

Note: Some applications can require forced air cooling to achieve full output current. Voltage ranges can vary slightly; refer to the data sheet for the specific voltage range for each part. Minimum VOUT is 1.25V for the MAX1776.

Specialty Parts • MAX6037A voltage reference for XADC built-in A/D converter in 7 Series FPGAs • MAX1510 DDR termination power regulator that can sink current • MAX34440 multirail PMBus controller used to control many regulators, fans, and log faults • Maxim also provides the entire range of supporting power functions such as isolated power regulators, sequencers, supervisors, temperature monitors, and PMBus system monitors

www.maxim-ic.com/xilinx 15 Signal Conversion Solutions for FPGAs

Overview Table 3. Parameters Measured in Many Systems We live in an analog world. Human Dimension Pitch Position sight, hearing, smell, taste, and Intensity Energy Pressure touch are analog senses. And since Impedance Temperature Humidity real-world signals are analog, they Density Speed Frequency need to be converted into the digital Viscosity Time of flight Phase domain by ADCs before they can be Velocity Distance Time processed by an FPGA. After digital processing is completed, digital Acceleration Pressure Salinity signals often need to be converted Water purity Torque Volume back to the analog domain by DACs. Weight State of charge Gases But the analog story doesn’t begin or Mass Conductivity Ph end with data conversion. Op amps, Resistance Dissolved oxygen Voltage instrumentation amplifiers (IAs), and programmable gain amplifiers (PGAs) Capacitance Ion concentration Current come into play to preprocess analog Inductance Chemicals Level signals for the ADCs and postprocess Rotation Charge (electrons) analog signals after the DACs. Maxim makes highly integrated Table 4. Actions That Devices Can Control analog and mixed-signal interface Valves Contrast Acceleration semiconductors that serve as the analog Motors Humidity Switches interfaces required by FPGAs to make practical systems. Our precision SAR and Pressure Force feedback Lights delta-sigma ADCs and DACs combine Velocity Room entry Weight with low-power, high-performance, Flow Sequence Speed space-efficient op amps, comparators, Volume Authorization Meters and precision references to deliver Torque Attenuation Displays the ever-increasing accuracy and Frequency Equalization Calibration speed needed for your next design. Voltage Communication Time Signal Conversion and FPGAS Current Gain (offset) Tools Working Together Solenoids Flux density Pitch Using FPGAs in control circuits is Position Temperature Filters common to many applications, inclu- Power Galvanometers ding medical, automotive, and consu- mer electronics. The signal-chain block Brightness Air fuel ratios diagram in Figure 13 shows a generic control system. We sense a parameter, make decisions in the FPGA, and act to A Practical Signal Chain source for excitation. Once excited, produce a physical action. The analog input portion of the they generate the signal of interest. Different parameters are measured circuit accepts analog signals from a The signal chain in Figure 13 starts as shown in Table 3, processed in the variety of sensors through factory or on the left side with a signal from a FPGA, and then the system interacts field wiring. These sensors are used to sensor entering the analog signal with the environment by the controlling convert physical phenomena as shown conditioning block. Before the signal devices shown in Table 4. Although the in Table 3 into electrical representations. is ready to be sampled by the ADC, parameters measured and controlled can Many sensors do not create their its gain needs to be matched to differ,Figure 13 represents a typical system. own signals, but require an external the ADC’s input requirements.

ANALOG INPUT ANALOG OUTPUT SENSORS ADC FPGA (µP) DAC ACTUATORS CONDITIONING CONDITIONING

Figure 13. Block Diagram Showing a Common Signal-Chain Flow

16 Analog Solutions for Xilinx FPGAs An analog input module receives Drift over temperature might need to meet the requirements. Exercise many different signals in a tough to be controlled through calibration care during selection to ensure any industrial environment. It is, therefore, routines because it can become a additional specified components essential to filter out as much noise as critical specification in environments provide similar performance as the possible while retaining the signal of where temperature is not constant. ADC. Rather than using discrete interest before converting the signal Analog-to-Digital Conversion components, it is also common to use from the analog to digital domain. an integrated analog front end (AFE) Next in the signal chain is the analog- to buffer or even replace the ADC. Various implementations of the to-digital converter (ADC). The ADC signal chain are possible: takes the analog signal and converts Once the data is converted, it is processed digitally in the FPGA. In • A mux at the first stage followed by a it to a digital signal. Depending on the some systems, this is the end of the common amplifying signal path into application, the ADC requirements process as the data is sent to other an ADC vary. For example, the bandwidth of the input signal dictates the ADC’s digital devices in the system such as a • Individual amplifying channels and a maximum sampling rate so the server or PC. In other cases, the system mux prior to the ADC selected ADC must have a sufficiently needs to drive an analog output. • With simultaneous-sampling ADCs high sampling rate (greater than Criteria for DAC Selection twice the input bandwidth). There are and independent conditioning Analog output signals are required some communications applications amplifiers for situations in which a compatible where this rule does not apply. The input stage is commonly required transducer or instrument needs to be to cope with both positive and negative The signal-to-noise ratio (SNR) and driven. Examples include proportional high voltages (e.g., ±30V or higher) to spurious-free dynamic range (SFDR) valves and current-loop-controlled protect the analog input from external specifications of the system dictate the actuators. It can be part of a simple fault conditions. For example, sensors ADC’s resolution, filtering requirements, open-loop control system or a complex can be remotely located from the analog and gain stages. It is also important to control loop in a proportional- input with large amounts of common- determine how the ADC interfaces to integral-derivative (PID) system which mode voltage that must be rejected. the FPGA. High-bandwidth applications the result of this output is sensed Amplifiers are often used to help perform better using a parallel or and fed back for PID processing. fast serial interface, while in systems condition the signals before processing. The analog output begins with digital requiring easy galvanic isolation, SPI with data from the FPGA (Figure 13). Operational amplifiers (op amps) unidirectional signaling is preferred. are an important part of the analog This digital data is converted into signal-conditioning block. They Criteria for ADC Selection an analog voltage or current signal are used as analog-front-end (AFE) When selecting the right ADC for using a digital-to-analog converter controlling gain and offset, anti-alias the application, the engineer must (DAC). Signal-conditioning circuitry filtering prior to ADCs. Op amps offer consider, review, and compare very then provides reconstruction filtering, high-voltage protection or current- specific device criteria.Table 5 presents offset, gain, muxing, sample/hold, and to-voltage conversion. Depending on typical ADC selection criteria. drive amplification as necessary. the application, some parameters can An ADC that is not an ideal match can As with the analog inputs, various be more important than others. DC be used, and analog blocks can be implementations are possible when applications require precision with low employed to augment its functionality multiple analog outputs are needed. input offset voltage, low drift, and low bias-current if the source impedance Table 5. Typical ADC Selection Criteria Matrix is significant. AC applications require Input range: Resolution: Interface: bandwidth, low noise, and low Unipolar Dynamic range Serial (I2C, SPI), distortion. When amplifiers are driving Biploar ENOB Parallel (4, 8, 16, N) ADCs, settling time becomes a very Input type: Speed: important parameter. Single-ended Channels BW Low-temperature drift and low noise Differential are also critical requirements for the Simultaneous Reference Power analog signal path. Errors at +25°C are Filtering: Other: typically calibrated in the software. 50Hz/60Hz PGA GPIO Rejection FIFO

www.maxim-ic.com/xilinx 17 Maxim has precision DACs ranging from development cards that directly connect • The design doesn’t fit in the ASIC or below 8 bits up to 18 bits of resolution with many FPGA development boards, FPGA without going to the next larger and up to 32 channels. Calibration help integrate Maxim products into FPGA device, thereby increasing cost and DACs are available from 4 bits to 16 designs. Along with our many EV kits, requiring the designer to move some bits and our sample/hold amplifiers calculators, and application notes, these circuits outside the device. provide additional ways to maintain tools allow the designer to complete • Murphy’s Law strikes. constant voltages at many outputs, their work more quickly and accurately. while the DAC serves other outputs. Problems that analog engineers FPGA Challenges Facing a experience, are often caused by low Producing discrete, selectable, voltage- System Designer signal to noise, crosstalk, gain (span), output (bipolar and unipolar) or current- Many FPGA designers are accomplished offset (zero), and linearity. External output conditioning circuits can be an digital engineers; Maxim’s expertise is integrated circuits (IC) that resolve involved task. This is especially true as analog interface. These complementary with these issues are amplifiers, ADCs, one begins to understand the necessity skills optimize system performance and DACs, digital pots, filters, multiplexers, of controlling full-scale gain variations, cost. FPGA design has a large affinity and voltage references. Other issues the multiple reset levels for bipolar with digital designers because FPGAs that arise are impedance matching, and unipolar voltages, or the different are configurable digital systems. From translation of analog voltages and output-current levels necessary to simulation to synthesis, everything currents, self-blocking (where a radio provide the system design with the most is done in a digital domain. transmitter interferes with its own flexible outputs. For more information receiver), backlight LED, and touch about designing with DACs and ADCs, However, much uncertainty is introduced controls. Supporting analog ICs can be refer to the application note library when these digital systems are tied to employed to manage these functions, (www.maxim-ic.com/converter-app-notes). the analog world. Some of the questions add features, and off load the FPGA. that system designers face are: What is Critical? Other analog ICs partnered with FPGAs in real-world designs include power The critical parts of the block diagram “How much gain should be supplies, margining and calibration, or chain depend on the specific applied to a signal? battery chargers, power supervisor, application. A clean power supply, “What analog filters should be used? interface devices, temperature control- good filters, and noise-free op amps lers and monitors, real-time clocks (RTCs), for signal conditioning are important “How to drive the ADC? watchdog timers, and precision resistors. for a good signal-to-noise ratio (SNR). “How much resolution is needed? Accuracy is greatly dependent on Maxim offers all of these types of ADC and DAC resolution, linearity, “What speed? devices. Using such components can and stable voltage references. “What specs are critical? save designs from errors, miscalculations, or last minute changes. It can also For precise systems, DACs (and ADCs) “How much output drive is required? reduce time to market, avoid a require an accurate voltage reference. spin or redo, and allow a project to The voltage reference is internal or “How to lower the noise?” succeed where others might fail. external to the data converter. In Answering these questions is where addition to many ADCs and DACs a world-leading analog company Maxim Makes It Easy! with internal references, Maxim such as Maxim excels. With our large Maxim offers many tools to help the offers stand-alone voltage references product portfolio and expertise in designer create, develop, verify, and with temperature coefficients as system design, FPGA designers can complete their designs, including low as 1ppm/°C, output voltage as count on Maxim to have the right Maxim’s very own online calculators accurate as ±0.02%, and output noise solution for their application. (www.maxim-ic.com/tools/calculators). as low as 1.3µVP-P that can be used Choose a calculator and fine tune Often, design requirements change externally to the data converter for it, depending on your particular at the eleventh hour. Maxim ultimate precision and accuracy. requirements. For example, use products are up to the task. Along with creating a circuit design Steve’s Analog Design Calculator to that achieves a specified performance, Four scenarios come to mind: pick the ideal converter. Then fine tune the accuracy and sampling the designer is also usually required to • The customer changes the rate using another calculator. complete the process in a limited amount specification just before delivery. of time. Easy-to-use development tools, including FMC and plug-in module • The sales department needs to add a must-have feature at the last minute.

18 Analog Solutions for Xilinx FPGAs Other great aids are available on the tools, models, and software page Trapped Between Precision and Noise (www.maxim-ic.com/design/tools). In some applications, the designer might feel trapped among noise, precision required, From here, you have access to the EE-Sim and cost. A good design is one that satisfies the customer’s requirements at an tool (simulations), a constantly updated affordable price. An FPGA with internal data converters is a great advancement. However, library of models (SPICE, PSPICE and IBIS), such converters do not meet the requirements for every application. a selection of BSDL files, and software. There are some important considerations about noise to factor in when evaluating one’s Maxim has long been revered for its ADC or DAC needs. By their nature, digital designs contribute noise to the equation. quality, variety, and ease of use of our FPGAs operate at faster speeds (GHz communications are now common), resulting in the evaluation kits (EV kits). Many have creation of more noise. been tailored for specific purposes. Hundreds of Maxim EV kits and Let’s look at some rules of thumb concerning orders of noise magnitude. Power supplies reference boards are available through typically have millivolts (mV) of noise. Noise sources range from switching power Avnet and other Maxim distributors. supplies, power line or mains, radio interference, motors, arc welders, and digital circuits. An ADC or DAC with a 3V full scale has a least significant bit (LSB) at the levels shown in Maxim has a dedicated team of appli- Table 6. cations engineers ready to answer your questions through email or over the It becomes readily apparent why noise is at odds with precision. We recommend phone. We strive to respond to every sketching the design in block form, as well as estimating noise and signal levels with a customer inquiry within one business day. fellow designer. Jot down what is known about the project, input and output signals You can find a selection of links to solve and values, power requirements, and known block contents. See Table 6. If the system many common inquiries such as pricing or needs 8-bit resolution at the output, is 10 or 12 bits at the input sufficient? If there is 5mV delivery questions at our Response Center of noise present in the system (56dB down) is it credible to think a 24-bit converter with page (support.maxim-ic.com/center.mvp). a dynamic range of 144dB is viable or overkill? See how quickly reality sets in? In just a Finally, and most importantly, Maxim and few minutes, we have bound the project. Now the decision to use the internal converter Avnet FAEs stand ready to assist you. or an external one with a clean power supply is obvious. Digital noise in particular is typically addressed as follows. First, use an external data Summary converter, meeting your requirements with separate, clean analog supplies and ground When you partner with Maxim, you have to maximize precision and accuracy. Second, oversample and average the signal. You get a full-service organization dedicated approximately one extra bit of resolution for each 4x oversampling. to supplying everything you need to complete your FPGA design. With a Not all bits are created equal! We should be wary of marketing bits, which are the wide selection of small packages, low commonly listed front and center on data sheets. The real bits of converters take into power, fast, and accurate products, account all nonlinearities and can be extracted by looking at other key parameters. For including easy-to-use design tools example, SINAD performance is commonly used to determine the effective number of and boards, Maxim plus your FPGA bits for SAR converters, while noise distribution of captured signal gives the noise-free simplify your development process. In bits in sigma-delta converters. addition, Maxim and our distribution You also need to understand the application’s need for voltage and temperature stability partners’ FAEs stand ready to assist you. and construct an error budget for the combination of the data converter and the voltage reference. Maxim has a tool to simplify the task. You can find it in Applications Note 4300: Calculating the Error Budget in Precision Digital-to-Analog Converter (DAC) Applications. Table 6. Data Converter Resolution and LSB Voltage for 3V Full Scale No. of Bits Decimal No. of Levels LSB 8 256 11.7mV 10 1,024 2.9mV 12 4,096 0.73mV 14 16,384 0.18mV 16 65,536 45.8μV 18 262,144 11.4μV 24 16,777,216 0.18μV

www.maxim-ic.com/xilinx 19 Featured Products

24-/16-Bit Sigma-Delta ADCs Enable 32 Benefits Simultaneous Channels • Simplifies digital interface to an FPGA ◦◦ Eight MAX11040K ADCs can be MAX11040K interfaced

The MAX11040K sigma-delta ADC offers 117dB SNR, four differential channels, and • 106dB SNR allows users to measure simultaneous sampling that is expandable to 32 channels (eight MAX11040K ADCs both very small and large input in parallel). A programmable phase and sampling rate make the MAX11040K ideal voltages for high-precision, phase-critical measurements in noisy PLC environments. With a • Easily measures the phase relationship single command, the MAX11040K’s SPI-compatible serial interface allows data to be between multiple input channels read from all the cascaded devices. Four modulators simultaneously convert each ◦◦ Simultaneous sampling preserves fully differential analog input with a 0.25ksps to 64ksps programmable data-output- phase integrity on multiple channels rate range. The device achieves 106dB SNR at 16ksps and 117dB SNR at 1ksps.

Single SPI CS FPGA

AVDD DVDD

AIN0+ ADC DIGITAL FILTER SYNC AIN0- REF0 CASCIN CASCOUT AIN1+ ADC DIGITAL FILTER SPI/DSP AIN1- SPI/DSP REF1 SERIAL CS AIN2+ INTERFACE SCLK 4-channel, ADC DIGITAL FILTER AIN2- DIN fully differential REF2 DOUT bipolar inputs AIN3+ ADC DIGITAL FILTER INT AIN3- REF3 N = 8 MAX11040K SAMPLING PHASE/FREQ N = 2 XTAL ADJUSTMENT REF 2.5V OSCILLATOR N = 1 Fine/coarse sample- rate and phase adjustment XIN XOUT AGND DGND

20 Analog Solutions for Xilinx FPGAs High Integration and a Small Package Create Benefits the Industry’s Smallest Solution • Reduces cost and simplifies manufacturing MAX5815, MAX5825 ◦◦ Complete single-chip solution ◦◦ Internal output buffer and The MAX5815 and MAX5825 are a 4- and 8-channel, ultra-small, 12-, 10-, and integrated voltage reference 8-bit family of voltage output, digital-to-analog converters (DACs) with internal reference that are well-suited for process control, data acquisition, and portable • Eliminates need to stock multiple instrumentation applications. They accept a wide supply voltage range of 2.7V to voltage references 5.5V with extremely low power (3mW) consumption to accommodate most low- ◦◦ 3 precision selectable internal voltage applications. A precision external reference input allows rail-to-rail operation references: 2.048V, 2.5V, or 4.096V and presents a 100kΩ (typ) load to an external reference. A separate VDD I/O pin • Provides industry’s smallest PCB area eliminates the need for external voltage translators when connecting to an FPGA, ◦◦ 4-channel available in 12-bump WLP ASIC, DSP, etc. and 14-pin TSSOP packages ◦◦ 8-channel available in 20-bump WLP and 20-pin TSSOP packages

INTERFACE 2.048V, 2.5V OR 4.096V MAX5815 V REF REF REFERENCE OUT

BUFFER 12-BIT VO1 I2C 400kHz

LDAC BUFFER 12-BIT VO2 INTERFACE RAIL-TO-RAIL OUTPUT AND WITH EXTERNAL REF CONTROL CLR BUFFER 12-BIT VO3

VDI/O BUFFER 12-BIT VO4

INTERFACE 2.048V, 2.5V OR 4.096V MAX5825 V REF REF REFERENCE OUT

BUFFER 12-BIT VO1 I2C

LDAC INTERFACE RAIL-TO-RAIL OUTPUT AND WITH EXTERNAL REF CONTROL CLR

VDDIO BUFFER 12-BIT VO7

www.maxim-ic.com/xilinx 21 Selector Guide and Tables

Signal Solutions for FPGAs Part Description Features Key Benefit Maintain system calibration and 20V, ultra-precision, low-noise, 5.9nV/√Hz input voltage noise; 6µV MAX44251/MAX44252 accuracy over time and temperature, low-drift, dual and quad amplifiers (max) offset, 20nV/ºC offset drift improve system accuracy 0.94nV/√Hz (MAX9632) and Enable full performance from 36V, high-bandwidth, low-noise MAX9632, MAX9633 3nV/√Hz (MAX9633) input voltage high-resolution ADCs for more single and dual amplifiers noise, less than 750ns settling time accurate measurement Wide 6V to 38V supply range, low 38V precision, single and dual op Allow operation in a variety of MAX9943/MAX9944 100µV (max) input offset voltage, amps conditions drive 1nF loads High voltage and low femto-amp Wide 4.75V to 38V supply range, input-bias current enables easy MAX9945 38V CMOS input precision op amp low input-bias current, rail-to-rail interfacing with ultra-high omhic output swing sensors 2µV (max) offset; 25nV/√Hz, Ensure precision signal Industry’s lowest offset, low-noise MAX4238/MAX4239 6.5MHz GBW and no 1/f input- conditioning at low frequencies rail-to-rail output op amps noise component over time and temperature Internal output buffer and voltage 1-channel, 16- and 18-bit precision reference buffer, separate V I/O Guarantee full accuracy at the load MAX5316/MAX5318 DD DACs voltage, rail-to-rail output buffer, for precision operation force-sense output Complete single-chip solution, Eliminates the need for voltage 4-channel, 12-bit DAC with internal MAX5815 internal output buffer, 3 precision translators and multiple voltage reference selectable internal references references Low-power consumption (80µA Single-channel, low-power, max), 3mm x 3mm, 8-pin µMAX Provides better resolution and MAX5214/MAX5216 14- and 16-bit, buffered voltage- package, ±0.25 LSB INL (MAX5214, accuracy while conserving power output DACs 14 bit) or ±1 LSB INL (MAX5216, and saving space 16 bit) Complete single-chip solution with independent voltage for digital 8-channel, low-power, 12-bit, Eliminates voltage level translators MAX5825 I/O (1.8V to 5V), internal rail-to-rail buffered voltage-output DACs to save PCB area output buffers, and 3 selectable internal or external references Supply current is virtually Ultra-low 1.3µV noise (0.1Hz P-P independent of supply voltage, to 10Hz, 2.048V output), ultra- Ultra-low-noise, high-precision, providing predictable power MAX6126 low 3ppm/ºC (max) temperature low-dropout voltage reference budget, does not require an coefficient ±0.02% (max) initial external resistor saving board accuracy space and cost Two simultaneous-sampling with two multiplexed inputs Provide a cost-sensitive, high- 12-bit, 4-channel, simultaneous- (four single-ended inputs total), integration 12-bit solution for MAX1377, MAX1379, MAX1383 sampling ADCs (2 x 2 SE or 2 x 1 1.25Msps per ADC dual or single power system monitoring and differential inputs) SPI port, supports ±10V from 5V motor control applications supply (MAX1383) 14-/16-bit, 8-/6-/4-channel simultaneous sampling SAR Industry’s first single-supply No external buffers simplifies ADCs with high-impedance I/O MAX11046 bipolar ADCs with high-impedance circuitry as well as saves cost and technology that eliminates external input space buffers, bipolar input with only a single +5V analog supply (Continued on following page)

22 Analog Solutions for Xilinx FPGAs Signal Solutions for FPGAs (continued) Part Description Features Key Benefit Easily scalable for up to eight ADCs 24-/16-bit sigma-delta ADCs Four fully differential in parallel, allows monitoring 3 MAX11040K cascadable up to 32 simultaneous simultaneously sampled channels, voltages: 3 current plus neutral channels 106dB SNR at 16ksps pair to address power applications

MAX11160/MAX11161, High integration and small MAX11162/MAX11163, 16-bit, 1-channel 500ksps SAR > 93dB SNR, integrated 5ppm packages (state package size) give MAX11164/MAX11165, ADCs with integrated reference reference option, available bipolar smaller form factor and lower total MAX11166/MAX11167, and bipolar option ±5V input range with 5V supply system cost without compromising MAX11168 high performance

Each channel is programmable to Allow multiple input sources to 16-bit, 4- and 8-channel SAR ADCs MAX1300/MAX1301, be single ended or differential and be supported in a single device, with programmable input ranges MAX1302/MAX1303 unipolar or bipolar, integrated PGA increasing flexibility and saving up to 3 x V (4.096V) REF (gain up to 4) and reference cost

Signal Solutions Evaluation Kits Part Description Features Price To evaluate MAX9632 and MAX9633 36V, high-bandwidth, Accommodates multiple op-amp configurations +4.5V MAX9632EVKIT, MAX9633EVKIT $60 low-noise single and dual to +36V wide input supply range 0805 components amplifiers To evaluate the MAX9943 and Flexible input and output configurations +6V to +38V MAX9943EVKIT MAX9944 38V precision, single and $50 single-supply range, ±3V to ±19V dual supply range dual op amps To evaluate the MAX9945 38V Accommodates multiple op-amp configurations, wide MAX9945EVKIT $51.50 CMOS input precision op amp input supply range 0805 components Windows software provides a simple graphical user interface (GUI) for exercising the features of the To evaluate the MAX5316, the true MAX5316, includes a companion MAXUSB2XILINXMB accuracy 16-bit, voltage output MAX5316EVSYS serial interface board and the MAX5316EVKIT with a $200 DAC with digital gain and offset 16-bit MAX5316GTG+ precision DAC installed (allows a control PC to control the SPI interface and GPIOs using its USB port) Demonstrates the MAX5815, the Windows software provides a simple graphical user 12-bit, 4-channel, low-power MAX5815AEVKIT interface (GUI) for exercising the device features, $75 DAC with internal reference and includes a USB-to-I2C 400kHz interface circuit buffered voltage output Demonstrates the MAX5216 16-bit Windows software, supports 14- and 16-bit DACs, low-power, high-performance, MAX5216EVKIT on-board microcontroller to generate SPI commands, $120 buffered digital-t o-analog USB powered converter (DAC) Demonstrates the MAX5825, the Windows software that provides a simple graphical 12-bit, 8-channel, low-power MAX5825AEVKIT user interface (GUI) for exercising the device features, $75 DAC with internal reference and includes a USB-to-I2C 400kHz interface circuit buffered voltage output Demonstrates the MAX5214 true Includes on-board microcontroller to generate SPI resolution 14-bit low-power, high- commands, Windows software provides a simple MAX5214DACLITE $25 performance, buffered digital-to- graphical user interface (GUI) for exercising the features analog converter (DAC) of the MAX5214, USB powered (Continued on following page)

www.maxim-ic.com/xilinx 23 Signal Solutions Evaluation Kits (continued) Part Description Features Price Demonstrates the MAX1379 Complete evaluation system, convenient test points MAX1379EVKIT 12-bit, 48-channel, simultaneous- provided on-board data-logging software with FFT $150 sampling ADCs capability, can also be used to evaluate the MAX1377 Provides a proven design to 8 simultaneous ADC channel inputs BNC connectors for evaluate the MAX11046 8-channel, all signal input channels 6V to 8V single power-supply MAX11046EVKIT $150 16-bit, simultaneous-sampling operation USB-PC connection compatible with five other ADC MAX1104x family members $150 Fully assembled and tested PCB 2 MAX11040KGUU+s installed on the motherboard, up MAX11040KEVKIT and that evaluates the IC’s 4-channel, to three more parts can be connected by cascading up $100 for MAX11040KDBEVKIT simultaneous-sampling ADC to three daughter boards daughter board Windows software provides a simple graphical user interface (GUI) for exercising the features of the Proven design for 16-bit, high- MAX11160. Includes a companion MAXPRECADCMB MAX11160EVSYS $150 speed precision ADC serial interface board and the MAX11160DBEVKIT with a 16-bit MAX11160 precision ADC installed (allows a PC to control the SPI interface and GPIOs using its USB port. On-the-fly programmability of the input ranges based Proven design for 16-bit on multiples of the voltage reference, support for single- MAX1300AEVKIT programmable input range $95 ended and differential as well as bipolar and unipolar precision ADC inputs Demonstrates the industry’s 4-channel 12-bit I2C SAR ADC with USB connection to MAXADCLITE smallest SAR ADC in a tiny a PC, self-powered from the USB port, complete data Free 12-bump WLP packaging solution acquisition system on a tiny EV kit

24 Analog Solutions for Xilinx FPGAs Design Protection Solutions for FPGAs

Overview configuration data is stored in a separate Presenting the Solution: memory chip and is read by the FPGA at Authentication Maxim’s secure information and power-up. The read data is held in the The objective of the authentication authentication (SIA) products offer SRAM memory cells in the FPGA. This process is to establish proof of identity low-cost, secure memory solutions arrangement compromises the security between two or more entities. Key- that incorporate robust, crypto- of the configuration data at two stages: industry vetted authentication and based authentication takes a secret key encryption schemes with best-in class • The configuration data bit stream is and the to-be-authenticated data (i.e., countermeasures against invasive (die exposed to eavesdropping during the the message) as input to compute a level) and side channel (noninvasive) power-up phase. message authentication code (MAC). The MAC is then attached to the attacks. These solutions are ideal for • Configuration data stored in SRAM message. The recipient of the message protecting design intellectual property, memory cells can easily be probed. managing licensing, controlling performs the same computation and A potential cloner can easily gain software feature set upgrade in compares its version of the MAC to the access to the configuration data field deployed equipment. one received with the message. If both using these techniques and clone the MACs match, the message is authentic. Identifying the Problem original design, thereby compromising To prevent replay of an intercepted Today, designers can select FPGAs the IP and profitability associated (nonauthentic) message, the MAC that employ various technologies to with the genuine product. computation incorporates a random hold the design configuration data Facing the Challenge challenge chosen by the MAC recipient. such as OTP (one-time programmable) Higher-end FPGAs address these security antifuses, reprogrammable flash-based Figure 14 illustrates the general concerns with built-in encryption storage cells, and reprogrammable concept. The longer the challenge, the schemes and identification mechanisms, SRAM-based configurable logic more difficult it is to record all possible but these solutions are not cost-efficient cells. The configuration data responses for a potential replay. for high volume applications such as essentially contains the IP related consumer electronics. However, these To prove the authenticity of the MAC to the design or the end product. applications still require a way to protect originator, the MAC recipient generates Both antifuse- and flash-based solutions their IP from piracy. Furthermore, the a random number and sends it as a provide relatively secure solutions security scheme should be robust, easy challenge to the originator. The MAC since the configuration data is stored to implement, and have minimal impact originator must then compute a new on the FPGA chip and there are on FPGA resources (number of pins and MAC based on the secret key, the mechanisms that prevent the stored logic elements), power consumption, message, and the recipient’s challenge. data from being read out. Moreover, and cost of the overall design. The originator then sends the computed unless very sophisticated schemes such result back to the recipient. If the as depacking, microprobing, voltage contrast electron-beam microscopy, and focused-ion-beam (FIB) probing are used to pry into the silicon and SECRET KEY MICROCONTROLLER IMPLEMENTED IN FPGA to disable security mechanisms, it MAC RECIPIENT MESSAGE DATA is very unlikely that the data can be MAC1 FROM ALGORITHM compromised. However, OEMs need SECURE MEMORY MATCH? to exercise strict control on licensing MAC2 as contract manufacturers tasked with RANDOM Q FPGA programming can produce more CHALLENGE units than authorized and sell them in the gray market. Such unauthorized 1-Wire INTERFACE devices are indistinguishable from the authorized devices and can significantly MESSAGE DATA SECURE MEMORY CHIP ALGORITHM impact an OEM’s profitability. MAC ORIGINATOR Static RAM-based (SRAM) FPGAs, SECRET KEY however, have fewer safeguards to protect that IP (the configuration data) against illegal copying and theft. The Figure 14. The Challenge and Response Authentication Process Proves the Authenticity of a MAC Originator

www.maxim-ic.com/xilinx 25 originator proves capable of generating The 1-Wire interface of the DS28E01-100 For detailed information on the SHA-1 a valid MAC for any challenge, it is very reduces the communications channel to MAC computation, review the Secure certain that it knows the secret key and, just a single FPGA pin for the challenge Hash Standard. Application Note 3675: therefore, can be considered authentic. and response authentication. That Protecting the R&D Investment—Two- This process is called challenge and minimizes the impact of the security Way Authentication and Secure Soft- response authentication. See Figure 14. solution since FPGAs are often I/O-pin Feature Settings provides technical limited. Alternate implementations can details on architecture of a secure Numerous algorithms are used to be constructed using a more generic memory and its security concept. compute MACs, such as Gost-Hash, I2C interface implemented on the HAS-160, HAVAL, MDC-2, MD2, MD4, Microcontroller-like functionality is FPGA and using the DS28CN01 (an MD5, RIPEMD, SHA family, Tiger, and typically available as a free macro I2C equivalent of the DS28E01-100) or WHIRLPOOL. A thoroughly scrutinized from major FPGA vendors. The Xilinx by implementing the SHA-1 engine and internationally-certified, one-way microcontroller function occupies and other functions in a small ASIC hash algorithm is SHA-1, developed by 192 logic cells, which represents just or CPLD. However, using an ASIC the National Institute of Standards and 11% of a Spartan-3 XC3S50 device. approach would probably cost more if Technology (NIST). SHA-1 has evolved security is the device’s only function. into the international standard ISO/IEC How It Works 10118-3:2004. Distinctive characteristics To leverage the security features The DS28E01-100 is programmed with of the SHA-1 algorithm are: of the DS28E01-100, a reference an OEM-specific secret key and data. authentication core enables the Programming can be done by the • Irreversibility: It is computationally FPGA to do the following steps: OEM or prior to shipment by Maxim. infeasible to determine the input The DS28E01-100 is effectively the corresponding to a MAC. 1. Generate random numbers for the challenge. On-chip random number ignition key for the FPGA design. The • Collision resistance: It is impractical generators usually create pseudo- OEM-specific secret key also resides to find more than one input message random numbers, which are not as in the scrambled configuration that produces a given MAC. secure as real random numbers. data that is programmed into the configuration (external) memory. • High avalanche effect: Any change in 2. Know a secret key that can be used input produces a significant change in for internal operations, but cannot When power is applied, the FPGA the MAC result. be discovered from an outside configures itself from its configuration For these reasons, as well as the source. memory. Now the FPGA’s microcontroller international scrutiny of the function activates and performs the algorithm, SHA-1 is an excellent 3. Compute a SHA-1 MAC that involves challenge and response authentication, choice for challenge and response the secret key, a random number, also known as identification friend authentication of secure memories. and additional data, just like the or foe (IFF). This identification secure memory. involves the following steps: Implementing the Solution 4. Compare data byte for byte, using 1. The FPGA generates a random A challenge and response authentication the XOR function of the CPU number and sends it as a challenge scheme can be implemented implemented in the FPGA. (Q) to the secure memory. inexpensively as part of an SRAM-based FPGA system design (Figure 15). In this example, the secure memory device uses only a single pin to connect to an FPGA pin configured for bidirectional VDD (open-drain) communication. A resistive connection to VDD delivers power to the SRAM-BASED FPGA secure memory and provides the bias DS28E01-100 for open-drain communication. Maxim’s SECURE 8-BIT MICROCONTROLLER USER DESIGN MEMORY AUTHENTICATION CORE CONFIGURATION DS28E01-100 1Kb protected 1-Wire MEMORY EEPROM with SHA-1 engine is a good fit 1-Wire SIO TEST IFF TEST for this scheme. The device contains a PASS ENABLE SHA-1 engine, 128 bytes of user memory, GND a secret key that can be used for chip- internal operations, but cannot be read from an outside source, and a unique, unchangeable identification number. Figure 15. In This Simplified Schematic, a Secure 1-Wire Memory is Used for FPGA Protection

26 Analog Solutions for Xilinx FPGAs 2. The FPGA instructs the secure Security can be improved further if the and then shipped directly to the CM. memory to compute a SHA-1 MAC secret key in each secure memory is Key benefits of this service include: based on its secret key, the challenge device-specific: an individual secret key • Eliminates the need for the OEM to sent, its unique identification number, computed from a master secret, the disclose the secret key to the CM. and other fixed data and transmit the SHA-1 memory’s unique identification response (MAC 2) to the FPGA. number, and application-specific • Eliminates the need for the OEM to constants. If an individual key becomes implement its own preprogramming 3. The FPGA computes a SHA-1 MAC public, only a single device is affected system. (MAC1) based on the same input and not the security of the entire system. and constants used by the secure • Only OEM-authorized third parties To support individual secret keys, the memory and the FPGA’s secret key. have access to registered devices. FPGA needs to know the master secret 4. The FPGA compares MAC 1 with key and compute the 1-Wire SHA-1 • The vendor maintains records of MAC 2. If the MACs match, the FPGA memory chip’s secret key first before shipped quantities, if needed for OEM determines that it is working in a computing the expected response. auditing. licensed environment. The FPGA For every unit to be built, the owner Providing Proof of Concept transitions to normal operation, of the design (OEM) must provide The FPGA security method featured enabling/performing all of the one properly preprogrammed secure in Configuration Application Note functions defined in its configuration memory to the contract manufacturer XAPP780: FPGA IFF Copy Protection code. If the MACs differ, however, the (CM) that makes the product with Using Dallas Semiconductor/Maxim environment is considered hostile. In the embedded FPGA. This one-to- DS2432 Secure EEPROMs has been this case, the FPGA takes application- one relationship limits the number tested with Xilinx products. Xilinx states: specific actions rather than continue of authorized units that the CM “The system’s security is fundamentally with normal operation. can build. To prevent the CM from based on the secrecy of the secret Why the Process Is Secure tampering with the secure memory key and loading of the key in a secure Besides the inherent security provided (e.g., claiming that additional memories environment. This entire reference by SHA-1, the principal security element are needed because some were not design, except the secret key, is public for the above IFF authentication process programmed properly), OEMs are abiding by the widely accepted is the secret key, which is not readable advised to write-protect the secret key. Kerckhoffs’ law.” The simple interface to programming and authentication from the secure memory or the FPGA. There is no need to worry about the provided in this application note make Furthermore, because the data in the security of the 1-Wire EEPROM data this copy protection scheme very bit stream is scrambled, eavesdropping memory, even if it is not write-protected. easy to implement. In this article on on the configuration bit stream when By design, this memory data can only military cryptography, the Flemish the FPGA configures itself does not be changed by individuals who know linguist Auguste Kerckhoffs argues that reveal the secret key. Due to its size, the secret key. As a welcome addition, instead of relying on obscurity, security reverse-engineering the bit stream this characteristic lets the application should depend on the strength of keys. to determine the design with the designer implement soft-feature He contends that in the event of a intent of removing the authentication management—the FPGA can enable/ breach, only the keys would need to be step is very time consuming, and disable functions depending on data that replaced instead of the whole system. thus a prohibitively difficult task. it reads from the SHA-1 secured memory. Another critical security component It is not always practical for the OEM to Conclusion is the randomness of the challenge. A preprogram memory devices before IP in FPGA designs can easily be predictable challenge (i.e., a constant) delivery to the CM. To address this protected by adding just one low- causes a predictable response that can situation, the manufacturer of the secure cost chip such as the DS28E01-100 be recorded once and then replayed memory could set up a SHA-1 secret key and uploading the FPGA with the free later by a microcontroller emulating and EEPROM-array preprogramming reference core. The 1-Wire interface the secure memory. With a predictable service for the OEM. Maxim provides enables implementation of the security challenge, the microcontroller can such a service, where secure memory scheme over a single FPGA pin. effectively deceive the FPGA to consider devices are registered and configured the environment as a friend. The at the factory according to OEM input randomness of the challenge in this IFF approach alleviates this concern.

www.maxim-ic.com/xilinx 27 Selector Guide and Tables

Secure Information and Authentication Solution for FPGAs Part Description Features Key Benefit User-customizable read/write/ Communicate and control over DS28E01-100 1-Wire 1Kb SHA-1 secure EEPROM OTP page modes ±8KV HBM with a single dedicated contact ±15KV IEC ESD protection minimizing space and pin impact

Secure Information and Authentication Evaluation Kit Part Description Features Battery-powered single cell Li-ion 18650 AES-S6EV-LX16-G Avnet Spartan 6 Evaluation Board (~2500 mAh) DS28E01-100 plug-in module to drive test Interfaces to Avnet-made Xilinx Spartan-6 LX16 DS28E01-100 Plug-In Module PicoBlaze™ SHA-1 authentication design evaluation kit (AES-S6EV-LX16-G) Starter kit board includes Maxim’s DS2460, DSAUTHSK Maxim secure memory evaluation kit DS2482-100, DS28CN01, and DS28E01-100 devices for rapid development

28 Analog Solutions for Xilinx FPGAs Interfacing High-Speed DACs and ADCs to FPGAs

2:1 or 4:1 multiplexed LVDS inputs to data rate (SDR), double date rate (DDR), Introduction reduce the RF-DAC input data rate to and quad data rate (QDR) to match As the speed and channel count of a level compatible with current FPGA the maximum clock rate specifications data converters increase with each technology. Using the 2:1 multiplexed of different classes of FPGAs. new generation, timing and data input mode one can reduce the I/O pin- To meet the high-channel count data integrity between these devices and count requirements, routing complexity, conversion demands of applications FPGAs become more challenging. and board space. Alternatively, the such as medical imaging, the interface Maxim works closely with industry 4:1 multiplexed input mode can be between high-speed ADCs and FPGAs leading FPGA suppliers to define employed to increase the timing has evolved from parallel to high-speed requirements for digital interfaces margins for a more robust design and serial. Benefits of a serial interface between the FPGAs and high-speed possible use of slower speed FPGA. data converters. This collaboration include fewer lines that provide a density to overcome these challenges Newer generations of RF-DAC products and cost advantage, as well as relaxed ensures compatibility, efficient use include an on-chip DLL (delay lock loop) delay matching specifications that of resources, and ease of design. to ease input data synchronization with provide simplified design and increased FPGAs, and a parity function to provide robustness. Maxim offers octal (eight) FPGA/Data Conversion Trends interface failure monitoring. The RF-DAC channel, high-speed ADCs with serial Data conversion and FPGA technology data interfaces are system synchronous LVDS outputs for high-density/low- continue to evolve. Advancements in to guarantee deterministic latency. A power applications such as ultrasound. performance and operating speeds source synchronous interface generally On some dual-channel, high-speed ADCs have led many applications to move has a one clock cycle latency uncertainty. and DACs, Maxim offers selectable dual signal processing from the analog Maxim’s RF-DACs offer a data scrambling parallel CMOS or single multiplexed domain to the digital domain. For feature to whiten the spectral content parallel CMOS interfaces to trade off example, instead of designing wireless of the incoming data to eliminate I/O pin count and interface speed. transmitters with a dual baseband I/Q potential data dependent spurs. DAC, an analog quadrature modulator, Integrated DLL Simplifies FPGA and a frequency synthesizer, use a A final consideration in interfacing to RF-DAC Synchronization fast FPGA and a RF digital-to-analog a data converter to an FPGA is data A functional diagram of the MAX5879 converter (RF-DAC). A digital quadrature clock speed. Maxim’s RF-DACs and RF- 14-bit, 2.3Gsps RF digital-to-analog modulator is implemented in the FPGA sampling ADCs support a wide variety converter is shown in Figure 16. The to upconvert the signal digitally, which of interface formats including single RF-DAC is updated on the rising edge is then synthesized by the RF-DAC at the required frequency. Benefits of a digital RF transmitter over an analog SO/LOCK SE MUX RF RZ RF transmitter include eliminating DAP[13:0] I/Q imbalance, increased carrier or FREQUENCY 14 x 2 channel capacity, and the ability to DAN[13:0] RESPONSE DBP[13:0] SELECT support multiple frequency bands DBN[13:0] 14 x 2 using a common hardware platform. DCP[13:0] However, to realize these benefits, DCN[13:0] 14 x 2 DATA 2:1 OR 4:1 14 OUTP DDP[13:0] SYNC REGISTERED ensure data integrity and proper DAC DDN[13:0] 14 x 2 MUX OUTN timing across the digital interface SYNCP between the RF-DAC and the FPGA. SYNCN 2 PARITY XORP CHECK Similarly, instead of designing wireless XORN 2 receivers with a baseband ADC, an PARP MAX5879 PARN 2 analog quadrature demodulator (or DLL mixer), and a frequency synthesizer, PERR REFIO use a fast FPGA and a RF sampling DCLKP FSADJ DCLKN 2 VOLTAGE DACREF analog-to-digital converter (RF-ADC). DCLKRSTP REFERENCE CREF DCLKRSTN 2 Data Converter to FPGA Digital REFRES Interface Solutions

Maxim has added features to its RF- DCLKDIV DELAY DLLOFF CLKP/CLKN GND VDD1.8 AVCLK AVDD3.3 DACs to simplify the interface with FPGAs. Maxim develops RF-DACs with Figure 16. MAX5879 Functional Diagram www.maxim-ic.com/xilinx 29 of the clock (CLKP/CLKN) and contains of the clocking scheme using an If a DLL isn’t present, the designer selectable 2:1 or 4:1 multiplexed input FPGA and the DLL of the MAX5879 is needs to ensure the digital data being ports to reduce either I/O pin count or shown in Figure 17. The DLL circuit presented to the DAC is stable for a time input data rate of the RF-DAC to either ensures data synchronization between prior to the DCLK transition (tSETUP) 1150Mwps or 575Mwps on each port. the FPGA and DAC by adjusting the and is held for a period of time after phase of the incoming data so the the transition (t ). After factoring The integrated MAX5879 DLL circuit HOLD data eye is centered on the internal in temperature variation, the setup ensures robust timing in the interface clock (RCLK) edge that latches the and hold times in the product data with the FPGA. This is especially data into the DAC. The DLL adjusts sheet can consume a large percentage important as the speed of the devices the phase of the incoming data of the valid data window, making it increases and the data window becomes (DATA) to the internal clock (RCLK), challenging to design a robust high- smaller (data transitions occur more making it immune to temperature speed FPGA to DAC interface. frequently). A simplified block diagram and power-supply variations.

Dx[3:0][13:0] MAX5879 PARP/N OUTPUT 575Mwps XORP/N SerDes x 4 t2 DATA REGs 4:1 MUX ICLK OCLK RCLK

MATCH t3 DELAYS OUTPUT PRBS 575MHz SerDes PATTERN PRBS SYNC DLL t2 ICLK OCLK

OPTIONAL DCLK DIVIDE- CLOCK t BY-2 0 DIVIDE- CLOCK BY-2 MANAGEMENT OPTIONAL CLOCK LOGIC CIRCUIT DIVIDE-BY-2 DIVIDER CLKO t /2 1 CLKIN 575MHz

FPGA CLKP/CLKN 2300MHz

t0 t1

DCLK DCLK = OUTPUT DATA CLOCK FROM DAC TO FPGA. DLL ADJUSTS DELAY OF t2 DCLK WHICH IN TURN ADJUSTS THE PHASE OF THE DATA WINDOW (AND SYNC) SO ITS CENTERED AROUND RCLK

DATA DATA WINDOW DATA = (2 OR 4) x 14-BIT LVDS LINES + PARITY AND XOR LINES FROM FPGA

t3

SYNC SYNC = PSEUDO RANDOM BIT SEQUENCE (PRBS) FROM FPGA THAT IS SYNCHRONIZED WITH DATA AND CLOSES THE DLL LOOP.

RCLK RCLK = INTERNAL DAC CLOCK TO LATCH INCOMING DATA FROM FPGA

Figure 17. Digital Interface Between FPGA and the MAX5879 RF-DAC (in 4:1 Mux Mode)

30 Analog Solutions for Xilinx FPGAs Data Scrambling and Parity LVDS output clock (CLKOUT). Serial (approximately 5 times that of the Check Ensure Reliable System data on each 12-bit channel is clocked serial LVDS interface). The significantly Performance on both the rising and falling edges of higher pin-count for a parallel interface CLKOUT. The rising edge of the frame- implementation would require In some cases, periodic data patterns alignment clock (FRAME) corresponds significantly more FPGA I/O resources generated by the FPGA can create to the first bit of the 12-bit serial data to capture the data. Larger packages data-dependent spurs that affect the stream on each of the eight channels. for both FPGA and ADC would also be overall performance of the system. The required, which increase the routing Implementing an octal 12-bit, 50Msps MAX5879 RF-DAC contains an XOR data complexity and number of printed circuit ADC with parallel CMOS outputs function that can be used to whiten the board layers needed for the design. spectral content of the data bits and would require 97 pins for the high- prevent this situation from occurring. speed digital interface to the FPGA In addition, this DAC contains a parity function that is used to detect bits errors between the FPGA data source and DAC REFIO REFH REFL CS SCLK SDIO SHDN and can be used for system monitoring. The parity calculated by the RF-DAC is CMOUT REFERENCE AND SPI, REGISTERS, compared to the parity received from the BIAS GENERATION AND CONTROL FPGA. When the received and calculated parity bits do not match, a parity error IN1+ OUT1+ 12-BIT DIGITAL SERIALIZER LVDS flag is set high so the FPGA can detect IN1- ADC OUT1- the fault and trigger a corrective action. IN2+ OUT2+ High-Speed Octal ADC has 12-BIT DIGITAL SERIALIZER LVDS Serial FPGA Interface Slashing IN2- ADC OUT2- Pin Count and Complexity For high-channel count applications, a high-speed serial interface between the IN8+ data converter and FPGA is preferred OUT8+ 12-BIT DIGITAL SERIALIZER LVDS over a parallel interface because it IN8- ADC OUT8- simplifies the design and provides a denser and more cost-effective solution. A functional diagram of the MAX19527 CLKOUT+ 6x octal 12-bit, 50Msps ADC is shown in LVDS CLKIN+ CLKOUT- Figure 18. The high-speed interface CLOCK PLL to the FPGA consists of 10 LVDS pairs CIRCUITRY MAX19527 CLKIN- FRAME+ (20 pins): 8 high-speed serial outputs 1x (1 for each channel), 1 serial LVDS LVDS FRAME- output clock (CLKOUT), and 1 frame- alignment clock (FRAME). The ADC clock input (CLKIN) or sample clock AVDD OVDD GND is multiplied by 6 to derive the serial Figure 18. MAX19527 Functional Diagram

www.maxim-ic.com/xilinx 31 Selector Guide and Tables

Selector Guide (High-Speed DACs and ADCs) High-Speed DACs and ADCs (Selected Examples) Part Description Features Benefit 2:1 or 4:1 multiplexed LVDS Inputs Optimize pin count or timing margin Ensure data synchronization between FPGA Delay lock loop (DLL) and DAC Parity check and error flag More easily ensure data integrity MAX5879 14-bit, 2.3Gsps RF-DAC Whiten spectral content to eliminate data Data scrambling dependent spurs Increased flexibility to interface to broader set SDR, DDR data interface of FPGAs 1:4 demultiplexed LVDS outputs Increased timing margin MAX109 8-bit, 2.2Gsps RF-ADC Increased flexibility to interface to broader set SDR, DDR, QDR data interface of FPGAs Serial LVDS outputs with programmable test Compact ADC/FPGA interface, ensure data 12-bit, octal 12-bit 50Msps patterns timing alignment MAX19527 ADCs with serial LVDS outputs Output drivers with programmable current Eliminate reflections to ensure data integrity drive and internal termination (open eye diagram) Programmable data output timing Simplifies high-speed FPGA/ADC interface, eliminates reflections to ensure data integrity MAX19517, Programmable internal termination 10-/8-bit, dual 130Msps ADCs (open eye diagram) MAX19507 Selectable data bus (dual CMOS or single Trade-off I/O and interface speed to optimize multiplexed CMOS) FPGA resources

Selector Guide (FPGA Support Collateral) Part Description Features High-speed data converter Data source-based on Xilinx Virtex-5 FPGA, directly compatible with Maxim RF-DACs HSDCEP evaluation platform ( > 1500Msps) evaluation kits Data converter evaluation Data source-based on Xilinx Virtex-4 FPGA, compatible with Maxim high-speed ADC and DAC DCEP platform evaluation kits

32 Analog Solutions for Xilinx FPGAs

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