Outline

Address spaces and address binding compile-time load-time run-time : mapping virtual address to physical addresses contiguous allocation and fragmentation Paging paging hardware multi-level and hashed tables protection and sharing Segmentation Swapping page faults page replacement FIFO optimal LRU LRU approximations counting algorithms Frame allocation Thrashing Performance of demand paging: issues and improvements

Operating Systems: Memory Management – p. 1 Section 8.1.1 drs space address binding: Address Program address Heap Stack Data Code space apn rmoeadessaet another to space address one from mapping CPU Physical addresses Memory drs spaces Address . . . prtn ytm:Mmr aaeet–p 2 p. – Management Memory Systems: Operating Address binding

Compile-time binding Location of program in physical memory must be known at compile time Compiler generates absolute code compiler binds names to actual physical addresses Loading ≡ copying executable file to appropriate location in memory If starting location changes, program will have to be recompiled Example: .COM programs in MS-DOS

Operating Systems: Memory Management – p. 3 Address binding

Load-time binding Compiler generates relocatable code compiler binds names to relative addresses (offsets from starting address) compiler also generates relocation table Linker resolves external names and combines object files into one loadable module (Linking) converts relative addresses to physical addresses No relocation allowed during execution

Operating Systems: Memory Management – p. 4 Address binding

Run-time binding Programs/compiled units may need to be relocated during execution CPU generates relative addresses Relative addresses bound to physical addresses at runtime based on location of translated units Suitable hardware support required

Operating Systems: Memory Management – p. 5 Section 8.2 MMU: rnlto hardware translation called (also time run at addresses physical to addresses virtual maps u-iebinding Run-time address binding load-time / Compile-time address: Physical address: Logical/virtual / eiethat device h/w address ) ⇒ drs enb eoyhardware memory by seen address oia address logical drs eeae yCPU by generated address address Logical eoymngmn unit management Memory ⇒ MMU oia address logical = CPU hscladdress physical Bus Memory prtn ytm:Mmr aaeet–p 6 p. – Management Memory Systems: Operating = . . . physical address Physical MMU

Kernel loads relocation register when a

Operating Systems: Memory Management – p. 7 Section 8.4 losO iet hnedynamically change to size OS Allows own its outside space memory address any accessing from process Prevents sddvcs/srie)myb eoe rmmemory use from in removed not be when may services) / devices used transient oe(oedt orsodn oinfrequently to corresponding (code/data code eoyprotection Memory prtn ytm:Mmr aaeet–p 8 p. – Management Memory Systems: Operating Contiguous allocation

Memory is divided into variable-sized partitions OS maintains a list of allocated / free partitions (holes) When a process arrives, it is allocated memory from a hole large enough to accommodate it Memory is allocated to processes until requirements of process in queue cannot be met OS may skip down the queue to allocate memory to a smaller process that fits in available memory Hole allocation policies: First-fit: allocate the first hole that is big enough Best-fit: allocate the smallest hole that is big enough entire free list has to be searched unless sorted Worst-fit: allocate the largest hole When process exits, memory is returned to the set of holes and merged with adjacent holes, if any Operating Systems: Memory Management – p. 9 Contiguous allocation

Example: Process sizes: P1 600 P2 1000 P3 300 P4 700 P5 500

0 0 0 0 0 OS OS OS OS OS 400 400 400 400 400

P5 P1 P1 P1 900 1000 1000 1000 1000 1000 P P4 P4 P 4 2 1700 1700 1700 2000 2000 2000 2000 2000 P3 P3 P3 P3 P3 2300 2300 2300 2300 2300

2560 2560 2560 2560 2560

Operating Systems: Memory Management – p. 10 Fragmentation

External fragmentation: memory space to satisfy a request is available, but is not contiguous may be reduced slightly by allocating memory from appropriate end (top/bottom) of hole Internal Fragmentation: allocated memory may be larger than requested memory ⇒ memory within partition may be left unused may be used to avoid overhead required to keep track of small holes

Operating Systems: Memory Management – p. 11 Compaction

Memory contents shuffled to place all free memory together in one large Reduces external fragmentation Dynamic relocation (run-time binding) needed

Operating Systems: Memory Management – p. 12 Section 8.5.1 ob loaded, be to sframes) as st hsclfaeaddresses frame physical to page #s logical translates table Page frames free of track keeps Kernel with process a When into partitioned is space address Logical size: Frame fixed-size into partitioned is memory Physical ob found be to yial 1–12bytes 512–8192 typically 2 of power be should hardware by defined n frames pages refae have frames free n sm size (same ae has pages address Logical space MAX 0 m Table Page prtn ytm:Mmr aaeet–p 13 p. – Management Memory Systems: Operating Paging Physical memory . . . Paging

Let 2m = size of logical 2n = size of page Then p = m − n higher order bits of logical address d = n lower order bits of logical address

Operating Systems: Memory Management – p. 14 Paging

Page table: part of process context during , saved is used to reconstruct hardware page table may be used by some system calls to translate logical addresses to physical addresses in software Frame table: maintained by kernel contains 1 entry per physical page frame whether free or allocated allocation information (PID, page#)

Operating Systems: Memory Management – p. 15 Paging

Miscellaneous issues: is automatic process cannot address memory outside its own address space Fragmentation: No external fragmentation Internal fragmentation can happen half a page per process, on average Page/frame size: Small frames ⇒ less fragmentation Large frames ⇒ page table overhead ↓; I/O is more efficient

Operating Systems: Memory Management – p. 16 Section 8.5.2 .Seilproeregisters: purpose Special I. xml:DCPDP-11 DEC small Example: is table page if solution privileged Acceptable are registers registers PT high-speed load/modify dedicated, to of set Instructions a in stored is table Page aetbecnan entries 8 contains table page size page 8K space address 16-bit aighardware Paging prtn ytm:Mmr aaeet–p 17 p. – Management Memory Systems: Operating Paging hardware

II. Memory + PTBR: Needed for large page tables PT stored in main memory Base address of PT is stored in page table base register (PTBR) Length of PT is stored in page table length register (PTLR) Context switch involves changing 1 register only Two physical memory accesses are needed per user memory access ⇒ memory access is slowed by factor of 2

Operating Systems: Memory Management – p. 18 Paging hardware

III. Associative registers/Translation look-aside buffer (TLB): TLB ≡ small, fast-lookup hardware , built using high-speed memory (expensive) each register holds key + value input value is compared simultaneously with all keys on match, corresponding value is returned TLB holds subset of page table entries TLB hit ⇒ additional overhead may be 10% or less TLB miss ⇒ new page#, frame# added to TLB TLB has to be flushed on context-switch

Operating Systems: Memory Management – p. 19 Paging hardware

Hit ratio: percentage of times that a page# is found in TLB depends on size of TLB Effective memory access time: average time for a memory access (including TLB lookup) Example: TLB lookup: 20ns Memory access: 100ns Hit ratio: 80% Effective access time = 0.8 × 120 + 0.2 × 220 = 140ns

Operating Systems: Memory Management – p. 20 Section 8.5.3 ⇒ ⇒ efrac:TBmiss TLB Performance: 4-, 3-, paging: Two-level ( large very usually are spaces address Logical odn h icso h rtlvlPT Example: level first the frames of memory pieces to the point holding entries PT pieces (outer) into level broken Second is table page (inner) level First aetbe hudcnntb loae contiguously allocated be not should/can large?) tables (how page large very are tables page . . . ee aigmyb eurdfrcranarchitectures certain for required be may paging level 0bits 10 ← p 1 ae# page ⇒ po4etammr accesses memory extra 4 upto 0bits 10 p → 2 ← 2bits 12 offset d ut-ee paging Multi-level → 2 32 prtn ytm:Mmr aaeet–p 21 p. – Management Memory Systems: Operating or 2 64 ) Section 8.5.2 a i/nai i niae hte aei ntepoes l process’ the in space is address page whether indicates bit Valid/invalid table page (via frame entry) each with associated bit(s) Protection a eue oipeetpoessz restrictions size process implement to used be may page each for OS by set OS to causes trap page) hardware read-only to (writing computation violation address protection with parallel in checked access bit read- protection / read-only specifies bit protection eoyprotection Memory prtn ytm:Mmr aaeet–p 22 p. – Management Memory Systems: Operating ogical Section 8.5.5 aapgsaempe odfeetpyia frames physical different to mapped are pages Data frames code physical maps same program the shared to a pages running process each for PT window/desk compilers, managers editors, text utilities, common e.g. programs used sharing for used Primarily NOTE : aafrsprt rcse r trdseparately stored are processes separate for data reentrant ra-ny oefrheavily for code (read-only) hrn pages Sharing prtn ytm:Mmr aaeet–p 23 p. – Management Memory Systems: Operating top Section 8.6 NOTE oia drse specify addresses Logical memory contiguous allocated is segment Each ordered are segment a within Elements ordered necessarily not are Segments (list, structures etc.), data stack, array, some subroutines, logical function, variable-sized main of e.g. up made is space Address space address Intuitively, emnsaeuulyatmtclygnrtdb h compi the by generated automatically usually are Segments : . . . ≡ emn dnie,offset identifier, segment ieraryo bytes of array linear Segmentation prtn ytm:Mmr aaeet–p 24 p. – Management Memory Systems: Operating ler segments Segment Table

Maps 2-dimensional logical addresses to 1-dimensional physical memory addresses Segment table entry = segment base, segment limit Base = starting physical address of segment in memory Limit = size of segment

Operating Systems: Memory Management – p. 25 Segmentation

Segment tables: Can be stored in fast registers / memory STBR: points to segment table in memory STLR: length of segment table ARs hold the most recently used segment-table entries

Protection/sharing: Each segment has associated protection/permission bits Memory mapping hardware checks protection bits to prevent illegal memory accesses hardware checks can be used to enforce automatic bounds on array indices 1 or more segments can be shared between processes by setting segment table entries to point to the same physical location shared code segments should be assigned the same segment # in all processes

Fragmentation: Segments are variable-sized ⇒ external fragmentation may happen if average segment size is small, fragmentation is low

Operating Systems: Memory Management – p. 26 Section 8.3 osdrtefloigsituation: following the Consider Motivation: P memory P i 1 P , . . . , ok ocet child a create to forks n r eieti eoyadocp l available all occupy and memory in resident are prtn ytm:Mmr aaeet–p 27 p. – Management Memory Systems: Operating Swapping Section 8.3 Principle: osdrtefloigsituation: following the Consider Motivation: akn tr;rlae eoyi sdfrsm other is some process for swapped used process; is memory released store; backing be can Process memory secondary / called additional (also disk fast on Space P memory P execution i 1 P , . . . , ok ocet child a create to forks n r eieti eoyadocp l available all occupy and memory in resident are wpe out swapped wpe in swapped eprrl rmmi eoyto memory main from temporarily akn Store Backing ae o continued for later sue as used is ) prtn ytm:Mmr aaeet–p 27 p. – Management Memory Systems: Operating Swapping Swapping

Choosing processes: Round-robin OS

when P ’s quantum expires, it P1 ′ is swapped out, is P P 2 Backing swapped into freed memory P3 store scheduler allocates next P quantum to some other 4 process in memory . .

Priority-based (roll out, roll in) when higher priority process arrives, lower-priority process is swapped out when higher priority process finishes, lower priority process can be swapped in Operating Systems: Memory Management – p. 28 Swapping

Performance: Context switch time increases (∵ disk transfer is involved) Time quantum should be large compared to swap time for good utilization Example: Process size: 100K Transfer rate: 1Mbps ⇒ swap-out + swap-in time = 200ms (+ ε)

Operating Systems: Memory Management – p. 29 Swapping

Input/output: If P is swapped out while waiting for input into buffer in user memory, addresses used by I/O devices may be wrong Solutions: process with pending I/O should never be swapped, OR I/O operations are always done using OS buffers (data can be transferred from OS to user buffer when P is swapped in)

Compaction: 1. Processes which have to be moved are swapped out 2. Memory is compacted by merging holes 3. Swapped-out processes are swapped in to different memory locations to minimize fragmentation

Operating Systems: Memory Management – p. 30 Section 9.1 Background: ihu eurn h niepoest ei memory in be to process entire the requiring without ita memory Virtual into loaded be to have not memory does space address logical Entire memory main must in referenced be being /addresses executed being Instructions rastbe a ealctdmr eoyta required than memory more allocated be may arrays/tables features used conditions, rarely error implementing unusual code for routines handling error rarely e.g. executed be may code some ≡ ehns oalweeuino processes of execution allow to mechanism ita memory Virtual prtn ytm:Mmr aaeet–p 31 p. – Management Memory Systems: Operating

Advantages: Programs can be larger than physical memory More programs can be run at the same time ⇒ throughput / degree of multiprogramming increases without increase in response time Less I/O is needed for loading/swapping ⇒ programs may run faster (compared to swapping)

Operating Systems: Memory Management – p. 32 Section 9.2 NOTE hnpoesacse aenti eoy aighardware ( paging OS memory, to in traps not page accesses process When execution memory, normally in proceeds resident pages accesses process While vs. (memory pages of on-disk) location specify should table Page are pages needed ( the memory only into executed, brought be to is process disk) When (high-speed memory secondary on reside Processes : Swapper Pager a oti drs fpg ndisk entry on table page page of memory, address in contain currently may not is that page for used be may bit valid/invalid oisidvda ae ofo wpspace swap to/from pages individual copies aiuae nieprocesses entire manipulates aefault page ayswapping lazy ) ) eadpaging Demand prtn ytm:Mmr aaeet–p 33 p. – Management Memory Systems: Operating Page faults

1. Check internal table to determine whether reference was to valid / invalid page. 2. Invalid access ⇒ terminate process. 3. Find a free frame from the free-frame list. 4. Read the desired page from swap device into the free frame. 5. When I/O is complete, update internal table and page table. 6. Restart the instruction that was interrupted by the illegal address trap. (state/context of the process is saved so that process can be restarted in exactly the same state)

Operating Systems: Memory Management – p. 34 Restarting instructions

Page Fault Handling Instruction fetch Re-fetch instruction Operand fetch 1. Re-fetch instruction. 2. Decode instruction. 3. Fetch operand. ADD A B C 1. Fetch, decode instruction 2. Fetch A, B. 3. Add A,B; store sum in C.

Problems: MVC (IBM System 360/370) moves upto 256 bytes from one location to another Auto-increment/auto-decrement addressing modes

Operating Systems: Memory Management – p. 35 Section 9.4 Method: Motivation: .Udt h aeadfaetbe;rsatteprocess. the restart tables; frame and frame. page free the (newly) Update the 4. into page desired the Read 3. .Fn refae fteei ofe frame: free no is there If frame. disk. free on a page Find desired 2. the of location the Find 1. i)wievci aet ik hnepg/rm tables page/frame change disk; to page victim write (ii) i s aerpaeetagrtmt select to algorithm replacement page use (i) poessat xctn ihn ae nmemory) in Overallocation pages no with executing starts until (process memory into brought not required are pages paging: demand Pure al occurs fault accordingly. ⇒ refaels a eepywe page a when empty be may list frame free aereplacement Page victim prtn ytm:Mmr aaeet–p 36 p. – Management Memory Systems: Operating frame; Modify/dirty bit

Modify/dirty bit is associated with each page (via PT) Set whenever the page is written If dirty bit of victim frame is clear, it is not written to disk Reduces time to service page faults Also applicable to read-only pages

Operating Systems: Memory Management – p. 37 Section 9.5 ffae loae oaprocess a to allocated frames of # rate string: page-fault Reference low yield should algorithm replacement Page erpae yol n reference one may only page by same replaced the be to only references #s successive page of of sequence terms in process are a references tracing memory by or artificially, generated be may algorithms PR evaluate to used euneo eoyreferences memory of sequence aerpaeetalgorithms replacement Page ⇒ ↑ aefaults page prtn ytm:Mmr aaeet–p 38 p. – Management Memory Systems: Operating ↓ FIFO

Pages are kept in a FIFO queue when a page is brought into memory, it is added at tail of queue when a page has to be replaced, page at head of queue is selected Example: Reference string: 1 2 3 4 1 2 5 1 2 3 4 5 # of frames: 3 # of page faults: 9 Belady’s anomaly: # of frames allocated to a process ↑ ⇒ page faults ↓

Stack algorithms: Pages in memory with n frames ⊆ Pages in memory with n +1 frames Never exhibit Belady’s anomaly

Operating Systems: Memory Management – p. 39 Optimal algorithm

Replace page that will not be used for the longest period of time Minimizes the number of page faults for a fixed number of allocated frames Not implementable Used to measure other replacement algorithms

Operating Systems: Memory Management – p. 40 LRU algorithm

Replace page that has not been used for the longest time Often used in practice Disadvantage: usually requires substantial hardware assistance

Counter implementation: Each PT entry contains a time-of-use (counter) field On each memory reference, a clock/counter is incremented; counter is copied into the PT entry for the referred page When a page has to be replaced, page with the smallest counter is selected Disadvantages: each memory reference requires a write to memory entire page table has to be searched to find LRU page counter overflow has to be handled Operating Systems: Memory Management – p. 41 LRU algorithm

Stack implementation: page numbers are maintained in a doubly-linked stack with head and tail pointers on a page reference, the corresponding PT entry is moved to top of stack six pointers have to be changed tail points to LRU page

Operating Systems: Memory Management – p. 42 LRU approximation algorithms

Background: Many architectures do not provide hardware support for true LRU page replacement Approximate versions of LRU have to be implemented with the limited hardware support

Reference bit: Associated with each PT entry All reference bits are initially cleared by OS Set by hardware on each page reference ⇒ distinguishes used pages from unused pages

Operating Systems: Memory Management – p. 43 LRU approximation algorithms

I. Additional-reference-bits algorithm: 1 reference byte associated with each PT entry On each timer : reference byte is right-shifted; reference bit is copied into high-order bit of reference byte and cleared Reference bytes contain history of page use for 8 most recent intervals Reference bytes order PT entries in LRU order (ties may be broken using FIFO ordering)

Operating Systems: Memory Management – p. 44 LRU approximation algorithms

II. Second-chance/clock algorithm: Store PT entries in a FIFO queue If reference bit of selected page is set: clear reference bit set arrival time to current time continue to next page in FIFO order If all bits are set, second-chance replacement reduces to FIFO replacement

Operating Systems: Memory Management – p. 45 LRU approximation algorithms

III. Enhanced second-chance algorithm: ref bit, dirty bit considered as an ordered pair 0, 0 – best page to replace 0, 1 – not recently used, but modified (has to be written to disk) 1, 0 – recently used, but clean (likely to be used again soon) 1, 1 – recently used and modified First page in lowest non-empty class is selected as victim

Operating Systems: Memory Management – p. 46 Counting algorithms

Each PT entry stores count of the number of references to that page LFU Algorithm: replaces page with smallest count counter may be right shifted at intervals to form an exponentially decaying average usage count MFU Algorithm: replaces page with largest count LFU page may have been brought in very recently and is yet to be used Performance is not very good

Operating Systems: Memory Management – p. 47 Global vs. local replacement

Global replacement replacement frame can be selected from all frames (including frames allocated to other processes) generally provides better throughput Local replacement: replacement frame can be selected from the frames allocated to the current process

Operating Systems: Memory Management – p. 48 Section 9.6 Multiprogramming: igeue system: user Single iiu ffae ob loae oaprocess: a to allocated be to frames of # Minimum process user a by use for list free on put are frames Remaining occupies Kernel structures u,adalctdfae freed swapped frames be allocated should and process out, allocated, are frames fewer if PDP-11 Example: a in instruction permitted single references memory of number maximum prnsec fwihcnb nidrc reference indirect an be can which of each operands 2 occupy may instruction M rms+sm rmsfrdnmcdata dynamic for frames some + frames MOV instruction > word 1 loaino frames of Allocation prtn ytm:Mmr aaeet–p 49 p. – Management Memory Systems: Operating Allocation of frames

Let n = # of processes M = total # of memory frames si = size of process pi ai = # of frames allocated to pi Equal allocation: ai = M/n

Proportional allocation:

ai = M × si/Σsi

Priority-based allocation:

ai = f(Pi, M × si/Σsi)

NOTE: Allocation depends on level of multiprogramming

Operating Systems: Memory Management – p. 50 Section 9.7 cnroI: Scenario executing than paging Definition: napg al,a ciepg ( page active an fault, page a On that pages all use hold active to in frames are “enough” allocated not is Process ⇒ rcs aefut ont aein page to soon faults page process iuto nwihapoesi pnigmr time more spending is process a which in situation p sreplaced is ) p prtn ytm:Mmr aaeet–p 51 p. – Management Memory Systems: Operating Thrashing Thrashing

Scenario II: OS monitors CPU utilization to determine degree of multiprogramming Global page replacement algorithm is used Process enters a phase where it needs a significantly larger # of frames Multiple processes start page-faulting ⇒ paging device queue becomes longer, ready queue empties ⇒ CPU utilization decreases ⇒ CPU scheduler increases degree of multiprogramming

Operating Systems: Memory Management – p. 52 Thrashing: remedies

Local/priority page replacement: + If one process starts thrashing, it cannot cause other processes to start thrashing – Thrashing processes use paging device heavily ⇒ average service time for increases for non-thrashing processes also

Page fault frequency monitoring: Upper and lower bounds on “desired” page fault rate are determined If PFR > upper limit, process is allocated another frame If PFR < lower limit, a frame is removed from the process If PFR increases and no free frames are available: a process is selected and suspended freed frames are distributed to processes with high PFRs Operating Systems: Memory Management – p. 53 Thrashing: remedies

Locality model: a set of pages that are actively used together e.g. subroutine code, local variables, and some subset of global variables process moves from one locality to another (possibly overlapping) locality during execution

Working set model: window = most recent ∆ page references Working set = set of pages in the working set window approximates the program’s current locality ∆ too large ⇒ working set overlaps several localities ∆ too small ⇒ working set does not cover entire locality Total demand for frames D = P WSS i

Operating Systems: Memory Management – p. 54 Thrashing: remedies

Working set model: (CONTD.) OS monitors working set of each process and allocates enough frames to accomodate working set If extra frames are available, more processes can be loaded into memory If D exceeds # of available frames, process(es) must be suspended Implementation: Timer interrupt is generated at regular intervals e.g. every 5000 memory references For each page, reference bit is copied into history register and cleared Overhead = Frequency of interrupt, # of history bits

Operating Systems: Memory Management – p. 55 Section 9.3 fracpal performance, acceptable (for Example: aefutsrietime: service fault Page = time access Effective iet etr process restart to time I/O for interrupt time fault page service to time where EAT FTime PF p ma rbblt fapg fault page a of probability - ≈ eoyacs time access memory - 0 25 + 100 25ms : < eoyacs n25000sol fault) should 2,500,000 in access memory 1 , ma 000 ma + , 100ns : 000 p × × Ftime PF p prtn ytm:Mmr aaeet–p 56 p. – Management Memory Systems: Operating Performance Performance

Swap space: Swap space should be allocated in large blocks ⇒ Disk I/O to swap faster than I/O to file image can be copied to swap space at process startup

If swap space is limited: (e.g. BSD ) pages are brought in from file system on demand replaced pages are written to swap space

Operating Systems: Memory Management – p. 57 Page buffering

Systems may maintain a pool of free frames On a page fault: required page is read into a free frame from the pool in parallel, a victim is selected and written to disk victim frame is added to free-frame pool Process restarts as soon as possible Page information may also be maintained for each free frame if desired page is in free-frame pool, no I/O is necessary used on VAX/VMS systems with FIFO page replacement

System may maintain a list of modified pages When paging device is idle, modified pages are written to disk

Operating Systems: Memory Management – p. 58