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Boolean Analysis of MOS Circuits Bo olean Analysis of MOS Circuits Randal E Bryant Computer Science Department CarnegieMellon University Pittsburgh PA February Abstract The switchlevel mo del represents a digital metaloxide semiconductor MOS cir cuit as a network of charge storage no des connected by resistive transistor switches The functionality of such a network can b e expressed as a series of systems of Bo olean equations Solving these equations symb olically yields a set of Bo olean formulas that describ e the mapping from input and current state to the new network state This analysis supp orts the same class of networks as the switchlevel simulator MOSSIM I I and provides the same functionality including the handling of bidirectional eects and indeterminate X logic values In the worst case the analysis of an n no de network can yield a set of formulas containing a total of O n op erations However all but a limited set of dense passtransistor networks give formulas with O n total op era tions The analysis can serve as the basis of ecient programs for a varietyoflogic design tasks including logic simulation on b oth conventional and sp ecial purp ose computers fault simulation test generation and symb olic verication Keywords and phrases switchlevel networks symb olic analysis logic simulation fault simulation simulation accelerators Intro duction The switchlevel mo del has proved successful as an abstract representation of digital metaloxide semiconductor MOS circuits for a variety of applications This mo del repre sents a circuit in terms of its exact transistor structure but describ es the electrical b ehavior in a highly idealized way It expresses transistor conductances and no de capacitances by discrete strength and size values represents no de voltages by discrete states and X for invalid or indeterminate and makes no attempt to mo del exact circuit timing The switch level mo del can capture many of the imp ortant phenomena encountered in MOS circuits such as ratio ed complementary and precharged logic dynamic memory and bidirectional pass This researchwas supp orted in part by the Defense Advanced Research Pro jects Agency ARPA Order Numb er and in part by the Semiconductor Research Corp oration under Contract transistors Unlike programs that attempt to mo del circuits at a detailed electrical level programs based on the switchlevel mo del can op erate at sp eeds approaching those of their counterparts based on more traditional gatelevel mo dels Examples of applications that have successfully applied switchlevel mo dels include logic simulators fault simulators test pattern generators and symbolic veriers SwitchLevel Algorithms Most programs that mo del circuits at the switchlevel utilize totally dierent algorithms than those develop ed for logic gate circuits To accommo date the bidirectional nature of the transistors they compute the state of a no de by applying graph algorithms to trace the con nections b etween no des formed by conducting transistors This departure from tradition has several drawbacks First considerable eort is often required to adapt existing techniques for use at the switchlevel For example in implementing the fault simulator FMOSSIM we found it quite challenging to adapt concurrentsimulation techniques although the resulting p erformance proved well worth the eort Similarly automatic test pattern gener ation for switchlevel circuits has not yet reached the success achieved for logic gate circuits Second although programs based on the switchlevel mo del have reasonable p erformance they fall short of those based on gatelevel mo dels Computing no de states by applying graph algorithms to the transistor data structure requires signicantly greater eort than computing the output of a logic gate Finally these algorithms do not map well onto the sp ecial purp ose pro cessors that have b een develop ed to accelerate such tasks as logic gate simulation Although sp ecial purp ose pro cessors for switchlevel simulation have b een designed and constructed these pro cessors require a fair amount of sp ecial ized hardware It is unlikely they will ever achieve the costp erformance of pro cessors that supp ort only gatelevel evaluation A New Approach This pap er prop oses a new approach that deals with all asp ects unique to the switchlevel mo del in a prepro cessing step The prepro cessor compiles a switchlevel network into a set of Bo olean formulas For each no de a pair of formulas sp ecies its steady state resp onse as a function of the initial no de states A simulator can then compute new no de states by simply evaluating the appropriate formulas Fault simulators and test generators can utilize traditional techniques by treating the set of formulas like a logic gate network The formulas can b e translated directly into machine language instructions for fast evaluation on a general purp ose computer or they can b e mapp ed onto any sp ecialpurp ose hardware that supp orts Bo olean evaluation An ecientsymb olic analyzer the sub ject of this pap er serves as the basis of this prepro cessing This approach has advantages over traditional metho ds of switchlevel evaluation in terms of b oth sp eed and exibility As an analogy a programming language compiler yields a p erformance advantage over an interpreter b ecause the cost of translating the program into machine instructions is paid only once during compilation rather than rep eatedly during execution Similarly the analyzer gives a p erformance advantage over traditional switch Bo olean Analysis of MOS Circuits level algorithms b ecause the added cost of switchlevel evaluation is paid only once during prepro cessing In contrast to sp ecial purp ose hardware for switchlevel evaluation many extensions to the mo del can b e made by simply mo difying the analyzer a much simpler task than mo difying the hardware Furthermore the Bo olean description of switchlevel subnetworks can more easily b e combined with subnetworks mo deled at other levels for mixedmo de evaluation Finally as will b e discussed briey the prepro cessor generates a description that can b e executed with a far greater degree of parallelism than is p ossible with more conventional switchlevel algorithms The analyzer describ ed in this pap er supp orts the same class of switchlevel networks as the simulator MOSSIM I I It captures all asp ects of the MOSSIM I I mo del including bidirectional eects dierent signal strengths and indeterminate X logic values The analysis of an n no de network pro duces a set of formulas with a total of at most O n op erations For all but a very small class of dense pass transistor networks eg barrel shifters at most O n op erations are required Hence for practical purp oses this approach incurs the same asymptotic complexity as other switchlevel programs Related Work Other researchers have develop ed prepro cessors to translate a switchlevel network into some algebraic representation that allows ecientevaluation These previous eorts had for the most part limited generality and accuracy In addition they did not achieve acceptable eciency Pster of IBM probably deserves credit for originating the idea of describing arbitrary MOS circuits in terms of Bo olean op erations He was seeking a way to p erform switchlevel simulation on the Yorktown Simulation Engine YSE Researchers at IBM have mo died and adapted a traditional switchlevel algorithm for execution on the YSE Their approachcanbeviewed as generating co de to iteratively solve a system of equations in an algebra where elements enco de b oth the strength and the state of a signal To accommo date the small word size of the machine they restrict the numb er of signal strengths to and use a p essimistic metho d for computing the eects of unknown states More seriously since the machine cannot p erform data dep endent branches their co de must always iterate a worst case numb er of times For many transistor structures with n no des and t transistors this requires a total of O nt YSE instructions a high cost in b oth space and time In a related eort the SLS program develop ed at IBM generates co de for a general purp ose computer that executes a single iteration in the solution of the same system of equations solved by MOSSIM I I During simulation this co de is executed re p eatedly until the values converge Although this program achieves impressive p erformance on a variety of circuits a signicant class of pass transistor networks can require many itera tions to converge Furthermore this approach cannot b e implemented on existing simulation hardware nor can it aid such tasks as test pattern generation or symbolic verication Others have attempted to express switchlevel algorithms in terms of either Bo olean or closely related algebras All of these eorts have yielded highly inecient resultsin the worst case the size of the algebraic description can grow exp onentially with the size of the network These programs partition the circuit into subnetworks and analyze each subnetwork separately Most subnetworks are quite smallcontaining no more than transistors Hence even an exp onential algorithm can have practical value However wehave often encountered circuits containing subnetworks of or more transistors For such cases these algorithms would b e totally inadequate The metho d develop ed by Cerny and Gecsei creates a symb olic representation of all p ossible partitionings of a subnetwork into connected comp onents formed by the conducting transistors All but the smallest subnetworks have many partitionings
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