Bo olean Analysis of MOS Circuits

Randal E Bryant

Computer Science Department

CarnegieMellon University

Pittsburgh PA

February

Abstract

The switchlevel mo del represents a digital metaloxide semiconductor MOS cir

cuit as a network of charge storage no des connected by resistive transistor switches

The functionality of such a network can b e expressed as a series of systems of Bo olean

equations Solving these equations symb olically yields a set of Bo olean formulas that

describ e the mapping from input and current state to the new network state This

analysis supp orts the same class of networks as the switchlevel simulator MOSSIM I I

and provides the same functionality including the handling of bidirectional eects and

indeterminate X logic values In the worst case the analysis of an n no de network



can yield a set of formulas containing a total of O n op erations However all but

a limited set of dense passtransistor networks give formulas with O n total op era

tions The analysis can serve as the basis of ecient programs for a varietyoflogic

design tasks including logic simulation on b oth conventional and sp ecial purp ose

computers fault simulation test generation and symb olic verication

Keywords and phrases switchlevel networks symb olic analysis logic simulation fault

simulation simulation accelerators

Intro duction

The switchlevel mo del has proved successful as an abstract representation of digital

metaloxide semiconductor MOS circuits for a variety of applications This mo del repre

sents a circuit in terms of its exact transistor structure but describ es the electrical b ehavior

in a highly idealized way It expresses transistor conductances and no de capacitances by

discrete strength and size values represents no de voltages by discrete states and X for

invalid or indeterminate and makes no attempt to mo del exact circuit timing The switch

level mo del can capture many of the imp ortant phenomena encountered in MOS circuits such

as ratio ed complementary and precharged logic dynamic memory and bidirectional pass



This researchwas supp orted in part by the Defense Advanced Research Pro jects Agency ARPA Order

Numb er and in part by the Semiconductor Research Corp oration under Contract

transistors Unlike programs that attempt to mo del circuits at a detailed electrical level

programs based on the switchlevel mo del can op erate at sp eeds approaching those of their

counterparts based on more traditional gatelevel mo dels Examples of applications that

have successfully applied switchlevel mo dels include logic simulators fault simulators

test pattern generators and symbolic veriers

SwitchLevel Algorithms

Most programs that mo del circuits at the switchlevel utilize totally dierent algorithms

than those develop ed for logic gate circuits To accommo date the bidirectional nature of the

transistors they compute the state of a no de by applying graph algorithms to trace the con

nections b etween no des formed by conducting transistors This departure from tradition has

several drawbacks First considerable eort is often required to adapt existing techniques

for use at the switchlevel For example in implementing the fault simulator FMOSSIM

we found it quite challenging to adapt concurrentsimulation techniques although the

resulting p erformance proved well worth the eort Similarly automatic test pattern gener

ation for switchlevel circuits has not yet reached the success achieved for logic gate circuits

Second although programs based on the switchlevel mo del have reasonable p erformance

they fall short of those based on gatelevel mo dels Computing no de states by applying

graph algorithms to the transistor data structure requires signicantly greater eort than

computing the output of a logic gate Finally these algorithms do not map well onto the

sp ecial purp ose pro cessors that have b een develop ed to accelerate such tasks as logic gate

simulation Although sp ecial purp ose pro cessors for switchlevel simulation have

b een designed and constructed these pro cessors require a fair amount of sp ecial

ized hardware It is unlikely they will ever achieve the costp erformance of pro cessors that

supp ort only gatelevel evaluation

A New Approach

This pap er prop oses a new approach that deals with all asp ects unique to the switchlevel

mo del in a prepro cessing step The prepro cessor compiles a switchlevel network into a

set of Bo olean formulas For each no de a pair of formulas sp ecies its steady state resp onse

as a function of the initial no de states A simulator can then compute new no de states by

simply evaluating the appropriate formulas Fault simulators and test generators can utilize

traditional techniques by treating the set of formulas like a logic gate network The formulas

can b e translated directly into machine language instructions for fast evaluation on a general

purp ose computer or they can b e mapp ed onto any sp ecialpurp ose hardware that supp orts

Bo olean evaluation An ecientsymb olic analyzer the sub ject of this pap er serves as the

basis of this prepro cessing

This approach has advantages over traditional metho ds of switchlevel evaluation in terms

of b oth sp eed and exibility As an analogy a programming language compiler yields a

p erformance advantage over an interpreter b ecause the cost of translating the program into

machine instructions is paid only once during compilation rather than rep eatedly during

execution Similarly the analyzer gives a p erformance advantage over traditional switch

Bo olean Analysis of MOS Circuits

level algorithms b ecause the added cost of switchlevel evaluation is paid only once during

prepro cessing In contrast to sp ecial purp ose hardware for switchlevel evaluation many

extensions to the mo del can b e made by simply mo difying the analyzer a much simpler

task than mo difying the hardware Furthermore the Bo olean description of switchlevel

subnetworks can more easily b e combined with subnetworks mo deled at other levels for

mixedmo de evaluation Finally as will b e discussed briey the prepro cessor generates a

description that can b e executed with a far greater of parallelism than is p ossible

with more conventional switchlevel algorithms

The analyzer describ ed in this pap er supp orts the same class of switchlevel networks as

the simulator MOSSIM I I It captures all asp ects of the MOSSIM I I mo del including

bidirectional eects dierent signal strengths and indeterminate X logic values The



analysis of an n no de network pro duces a set of formulas with a total of at most O n

op erations For all but a very small class of dense pass transistor networks eg barrel

shifters at most O n op erations are required Hence for practical purp oses this approach

incurs the same asymptotic complexity as other switchlevel programs

Related Work

Other researchers have develop ed prepro cessors to translate a switchlevel network into some

algebraic representation that allows ecientevaluation These previous eorts had for the

most part limited generality and accuracy In addition they did not achieve acceptable

eciency Pster of IBM probably deserves credit for originating the idea of describing

arbitrary MOS circuits in terms of Bo olean op erations He was seeking a way to p erform

switchlevel simulation on the Yorktown Simulation Engine YSE

Researchers at IBM have mo died and adapted a traditional switchlevel algorithm

for execution on the YSE Their approachcanbeviewed as generating co de to iteratively

solve a system of equations in an algebra where elements enco de b oth the strength and the

state of a signal To accommo date the small word size of the machine they restrict the

numb er of signal strengths to and use a p essimistic metho d for computing the eects of

unknown states More seriously since the machine cannot p erform data dep endent branches

their co de must always iterate a worst case numb er of times For many transistor structures

with n no des and t transistors this requires a total of O nt YSE instructions a high cost in

b oth space and time In a related eort the SLS program develop ed at IBM generates

co de for a general purp ose computer that executes a single iteration in the solution of the

same system of equations solved by MOSSIM I I During simulation this co de is executed re

p eatedly until the values converge Although this program achieves impressive p erformance

on a variety of circuits a signicant class of pass transistor networks can require many itera

tions to converge Furthermore this approach cannot b e implemented on existing simulation

hardware nor can it aid such tasks as test pattern generation or symbolic verication

Others have attempted to express switchlevel algorithms in terms of either Bo olean or

closely related algebras All of these eorts have yielded highly inecient resultsin the

worst case the size of the algebraic description can grow exp onentially with the size of the

network These programs partition the circuit into subnetworks and analyze each subnetwork

separately Most subnetworks are quite smallcontaining no more than transistors

Hence even an exp onential algorithm can have practical value However wehave often

encountered circuits containing subnetworks of or more transistors For such cases these

algorithms would b e totally inadequate The metho d develop ed by Cerny and Gecsei

creates a symb olic representation of all p ossible partitionings of a subnetwork into connected

comp onents formed by the conducting transistors All but the smallest subnetworks have

many partitionings and hence this approach has limited p otential The metho ds of Ditlow

et al of Ha jj and Saab and of Terman enumerate the set of all simple paths

to each no de and then enco de information ab out each algebraicallyFor many pass

transistor networks eg the Tally circuit of Mead and Conway the number of such

paths grows exp onentially with the numb er of transistors Furthermore all of these metho ds

place more restrictions on the class of networks than do es MOSSIM I I and some do not do

as well at mo deling the eects of X values Finally the metho d of Ha jj and Saab utilizes

a mixed Bo oleaninteger algebra in which the s in dierentsetsofBooleansmust b e

tabulated and compared Such an algebra seems needlessly awkward and would b e hard to

implement on most simulation hardware

In a dierent application of symb olic analysis the MOSSYM program simulates MOS

circuits symbolical lyAsymb olic simulator resembles a conventional simulator except that

the input patterns may consist of Bo olean variables in addition to the constants and

The no de states computed by the simulator represent Bo olean functions over the presentand

past input variables This program is designed to rigorously verify digital circuits proving

their correctness for all p ossible input sequences As a consequence it must solveBoolean

equivalence a wellknown NPhard problem The worst case p erformance of the program

is exp onential in the number of variables and many researchers b elieve no b etter p erformance

can b e achieved The metho ds used by MOSSYM for computing the Bo olean b ehavior of a

switchlevel network form the basis of the analyzer describ ed here However the analyzer

can use dierent data structures and algorithms for representing Bo olean functions since it

need not proveequivalence Consequently while the simplication algorithms may not yield

the most compact formulas p ossible they have acceptable worst case p erformance Future

versions of MOSSYM will op erate on prepro cessed networks rather than on the transistor

structure directly gaining the same b enets from prepro cessing as do more conventional

simulators

Overview

The analyzer presented in this pap er overcomes manyweaknesses of the previous attempts

Imp ortant features include

It partitions the network into channelconnected subnetworks and derives the steady

state resp onse of each subnetwork separately This partitioning divides the analysis

task into smaller subproblems

It enco des logic states and X with pairs of Bo olean values By this enco ding

it can accurately characterize the eects of unknown no de and transistor states with

Bo olean formulas

Bo olean Analysis of MOS Circuits

Starting with the maximum strength level and working downward it derives systems

of Bo olean equations for each strength level It can capture the eects of any xed

numb er of signal strengths These systems of equations express the eects of all paths

in the graph but lend themselves to solution metho ds of p olynomial complexity

It solves the equations symb olically by Gaussian elimination Gaussian elimination can

exploit the sparse structure of the networks to solve most n no de subnetworks with

O n algebraic op erations

It represents the set of Bo olean formulas as a directed acyclic graph DAG This

representation naturally allows sharing of common sub expressions The size of the

DAG describing the steady state resp onse of all no des in a subnetwork is b ounded by

the numb er of algebraic op erations required during the Gaussian eliminations

Comparing the analyzer to the inner workings of the circuitlevel simulator SPICE

lends some insightinto the underlying ideas During transient analysis SPICE computes

the b ehavior of a nonlinear network at eachtimepointby p erforming a series of iterations

each of whichinvolves setting up a system of linear equations and solving it by Gaussian

elimination Similarly our analyzer computes the b ehavior of a network of nonBo olean

switches due to the dierent signal strengths and the X states by p erforming a series of

iterations each of whichinvolves setting up systems of Bo olean equations and solving them

by Gaussian elimination In this resp ect b oth programs apply the p owerful mathematical

technique of solving a dicult problem over a p o orly structured domain by recasting it as a

series of problems in a more tractable domain for which ecient highly develop ed algorithms

exist

Unlike SPICE however the analyzer iterates in a xed progression over signal strengths

rather than until it reaches some convergence criterion This progression is p ossible b ecause

of the discrete nature of signal strengths Ata given strength level the analyzer has already

computed the eects of stronger signals and can safely ignore weaker ones Furthermore

rather than b eing p erformed on each time step the analyzer need only compute the b ehavior

once yielding a set of formulas that are evaluated rep eatedly during simulation Sucha

symb olic analysis is p ossible b ecause of the simpler natures of b oth the circuit elements

and the mathematical domain Whereas SPICE must linearize the network byevaluating

complex device mo dels at the current op erating p oints of the circuit elements the analyzer

need only evaluate the eects of the p ossible paths at each strength level Furthermore

Bo olean formulas are far easier to manipulate and simplify than formulas over real numb ers

Thus while interesting parallels exist b etween SPICE and symb olic switchlevel analysis

many factors contribute to make the latter far more ecient

A companion pap er provides background on the mathematical and algorithmic tech

niques used in the analysis This pap er gives a detailed formulation of the switchlevel

mo del in terms of Bo olean algebra It also describ es several extensions to the mo del includ

ing ways to mo del circuit faults degraded logic signals and charge decay These extensions

demonstrate the p ower of the basic framework The analyzer can incorp orate new mo del

ing features by mo difying the basic systems of equations slightlyFuture pap ers will cover

implementation issues applications and exp erimental results

The remainder of the pap er is organized as two ma jor parts The rst consisting of

Sections formulates the b ehavior of a switchlevel network as a system of equations in an

abstract Bo olean algebra The second part consisting of Sections presents renements

of the technique examples and extensions to the switchlevel mo del

The SwitchLevel Mo del

The switchlevel mo del considered here has b een describ ed in detail elsewhere This

section gives an overview of the mo del in terms of a cleaner notation and denes the symb olic

analysis problem

Network Mo del

A switchlevel network consists of a set of no des and a set of transistors A no de is classied

as either input or storage An input no de represents a connection to a signal source external

to the chip supplying either p ower ground clo ck or data A storage no de like a capacitor in

an electrical network retains its state in the absence of applied inputs and can share charge



with other storage no des The voltage on no de n is represented byitsstate n f Xg

with and corresp onding to low and high voltage levels resp ectivelyand X corresp onding

to an indeterminate voltage b etween low and high indicating an uninitialized network state

or an error condition caused by a short circuit or charge sharing

A storage no de has a characteristic size from the set f kg This size indicates in

a highly simplied way the no de capacitance relative to that of other no des with whichit

may share charge That is when a set of storage no des share charge due to connections by

conducting transistors only the connected no des of maximum size determine the outcome

Input no des are indicated by size wk The set N contains all no des of size s and hence

s

N denotes the set of input no des

w

A transistor has terminals lab eled gate source and drain It acts as a resistive

switch connecting the source and drain no des controlled by the state of the gate no de

Transistors act as bidirectional elements with no predetermined direction of information or

currentow A transistor has a type indicating the conditions under which it will b ecome

conducting A dtype transistor always conducts an ntype conducts when its gate has state

while a ptype conducts when its gate has state When the gate no de of an ntyp e or

ptyp e transistor has state X the transistor can range b etween fully conducting and op en

circuited Transistor states and X represent conduction levels nonconducting fully

conducting and indeterminate resp ectively

Each transistor has a characteristic strength from the set fk k w gThis

strength indicates in a highly simplied way the transistor conductance relative to those

of other transistors in a ratio ed circuit That is every path of conducting transistors has a

characteristic strength equal to the that of the weakest transistor in the path When a set



This presentation uses a notation where no des are named bylowercase letters eg m n their current

states are indicated by italicized lowercase letters eg m n and their new states are indicated by italicized

upp ercase letters eg M N

Bo olean Analysis of MOS Circuits

of paths form from several input no des to a storage no de only those inputs connected by

maximum strength paths determine the new no de state For no des m and n the set T m n

s

contains all transistors of strength s having these two no des as source and drain

The Channel Graph

The channel graph represents the interconnection structure of a switchlevel network This

graph has the storage no des of the circuit as vertices and an edge m nforeach pair

of storage no des m and n suchthatT m n for some strength s It describ es the

s

static indep endent of transistor state interconnections b etween storage no des formed bythe

sourcedrain connections of the transistors The channel graph is considered either undirected

or directed dep ending on context When talking ab out general structural prop erties of a

circuit an undirected graph simplies the discussion On the other hand symb olic analysis

requires a b ecause the lab els assigned to the edges are direction sensitive

In general a channel graph consists of many connected comp onents Therefore it denes

a partitioning of the switchlevel network into a set of channelconnected subnetworks where

each subnetwork consists of the set of no des in a graph comp onent plus the set of transistors

for which these no des are sources or drains Note that an input no de is not part of any

subnetwork but a transistor for which the no de is source drain is in the subnetwork of its

drain source no de

Within a subnetwork the b ehavior can b e complex and dicult to analyze due to the

bidirectional transistors and the manyways state forms in a MOS circuit The interactions

between subnetworks however are much more straightforward Each subnetwork acts as a

sequential logic elementhaving as inputs the input no des connected to transistor sources and

drains as well as the gate no des of the transistors The subnetwork state is stored as charge

on the storage no des and the outputs are those no des that are gate no des of transistors in

other subnetworks Hence the overall op eration of a switchlevel simulator is similar to that

of a logic gate simulatorchanging values on the subnetwork inputs require up dating the

state and outputs and these changing output values in turn aect other subnetworks The

challenge then is to develop formulas representing the b ehavior of individual subnetworks

In practice many subnetworks are smallcontaining at most transistors However we

have encountered subnetworks with over transistors essentially the entire data path of

a bit micropro cessor and hence the analysis of each subnetwork must b e as ecient

as p ossible

Steady State Resp onse

The steady state resp onse function describ es the b ehavior of a subnetwork Informally

this function can b e explained as follows For a given set of connected input no de and

initial storage no de states the transistors are set according to their gate no de states The

transistors in the and X states create p otentially conducting paths from input no des to

storage no des and b etween pairs of storage no des causing the storage no des to attain new

voltage levels The steady state resp onse for a no de equals the state or X this no de

would attain if the transistors were held xed long enough for the no des to stabilize When

no des or transistors in the X state are present the steady state resp onse on a no de equals

or only when it would attain this unique state regardless of the voltages and conductances

of these no des and transistors Otherwise the steady state resp onse equals X

The steady state resp onse for a subnetwork is dened formally in terms of the paths

between no des formed by the conducting transistors This approach unies the varietyof

dierentways logic values form in MOS circuits including stored charge charge sharing

and b oth ratio ed and complementary logic Foragiven set of transistor states transistors in

the and X state form connections b etween their source and drain no des A rootedpath p is

a directed path originating at no de Root p terminating at no de Dest p and consisting of

a p ossibly empty set of transistors Trans p The strength of path p denoted jpj is dened

as

jpj min SizeRoot p min Strengtht

tTrans p

A ro oted path represents a source of charge from its ro ot to its destination with driving

ability indicated by its strength Ro oted paths can b e classied into three typ es according to

their strength A path with strength jpjk represents a source of stored charge from a

storage no de with an approximate capacitance determined by the size of this no de Note that

the stored charge initially on the no de is represented by a path with ro ot and destination

equal to the no de and with no transistors A path with strength kjpj w represents a

source of current from an input no de with an approximate conductance determined bythe

strength of the weakest transistor in the path A path with strength jpj w must contain

no edges and have an input no de as b oth ro ot and destination Such a path represents the

external current supplied to the input no de The overall ranking of path strengths reects

the fact that a connection from an input no de can override anystoredcharge while a direct

connection to an input can override any resistive connection from some other input

The steady state resp onse of a no de dep ends only on the paths to the no de that are

not blo cked A denite path is dened as a ro oted path p such that no transistor in

Trans pisintheX state A path p is said to b e blocked if for some initial segment p

of p ie Root p Root p and Trans p Trans p and for some denite path q

Dest p Dest q and jp j jq jIntuitively a path is blo cked if the source of charge it

represents would b e overridden by a stronger source at some intermediate no de Dene the

path relation P between pairs of no des as m P n when there is an unblo cked path p with

Root pm and Dest pn Then the steady state resp onse on no de n denoted N is

given by the equation

N lub fmjm P ng

where lub represents the least upp er b ound over the ordering X and XInother

words if all unblo cked sources of charge to a no de drive it to or to then the steady

state resp onse equals or Otherwise if the no de is driven by conicting sources or by

sources of unknown value the steady state resp onse equals X It can b e shown that this

characterization of the steady state resp onse provides an accurate mo deling of the eects of

unknown states as well as several imp ortant mathematical prop erties

Bo olean Analysis of MOS Circuits

State Enco ding

To cast the switchlevel mo del in terms of Bo olean op erations a state value y f Xg is

enco ded as two Bo olean values yy f g as follows

y y y

X

Formally and are op erators expressed in p ostx notation mapping elements of f Xg

to elements of f g The combination yy do es not representa valid state It

can b e considered a dont care combination in the derivation With this enco ding if y is

the least upp er b ound of a set A consisting of elements a f Xgthen

y a

aA

y a

aA

W

where denotes the Bo olean sum of a set of elements

With this Bo olean enco ding of state values the symb olic analysis problem can b e dened

as follows For eachnode nintro duce Bo olean variables nandn to represent the enco ded

value of the initial no de state Of course when the no de is known to have a xed state eg

power or ground its state can b e enco ded by constants rather than variables For each

no de nwe are to derive Bo olean formulas denoted NandN for the enco ded steady

state resp onse in terms of the no de state variables The enco ding of no de states makes it

p ossible to express the threevalued circuit b ehavior using conventional Bo olean algebra

This greatly simplies the algebraic manipulation p ortion of the symb olic analyzer at the

cost of requiring a pair of formulas to describ e eachnode

In terms of this enco ding Equations and can b e applied to Equation to give

N m

mP n

N m

mP n

Mathematical and Algorithmic Background

This section briey summarizes the mathematical notation results and algorithms develop ed in the companion pap er

Symb olic Algebra

A Bo olean formula describ es a function mapping each p ossible combination of values for the

set of p variables to or Mathematicallysymb olic analysis can b e viewed as manipulating

elements of the algebra hB iwhere

n o

p

B f f g f g

The op erations and denote Bo olean and or and not resp ectively applied to

functions The distinguished elements and represent the constant functions that yield

and resp ectively for all argumentvalues This pro cess of abstracting from a primitive

domain to one of functions while maintaining the algebraic prop erties forms the basis of

symb olic analysis

V

The Bo olean pro duct of the elements in a set A is denoted a The pro duct of an

aA

empty set is dened to equal Similarly the Bo olean sum of the elements in a set A is

W

denoted a The sum of an empty set is dened to equal

aA

Systems of Bo olean Equations

Systems of Bo olean equations provide a mathematical formalism for networks of switches

much as do systems of linear equations for networks of resistors However to emphasize the

sparse nature of the networks lab eled graphs are preferred to a matrix notation

A system of Bo olean equations is represented by an edge and lab eling on a directed

graph V E where a lab eling indicates of an assignment of elements of B to every edge or

vertex The system A b consists of an edge lab el Au v B for eachu v E and a

vertex lab el bv B for each v V Vertex lab eling x satises the system A b when

xv bv xu Au v

uv E

for every v V In general many lab elings may satisfy a system but by dening an

appropriate partial ordering of the elements of B every system can b e shown to havea

unique minimum satisfying lab eling This lab eling is termed the system solution

The solution of a Bo olean system describ es the conditions under which conducting paths

will form in a switch network More precisely P is dened as the set of all paths from

uv

vertex u to v in the graph For solution x of the system A b

xv bu As t

uV pP

stp

uv

for all vertices v In other words if the value of a path is dened as the Bo olean pro duct

of the initial vertex lab el and all edge lab els then xv equals the Bo olean sum of the values

of all paths terminating at v

A dual system of Bo olean equations is similar to a normal system but with the roles of

D

and interchanged Lab eling x satises the dual system A b when

xv bv xu Au v

uv E

Bo olean Analysis of MOS Circuits

for every v V Dual systems express conditions under which conducting paths are absent

in a switch network More preciselylet A denote the edge lab eling with eachelement equal

b For to the Bo olean complement of the corresp onding elementof A and similarly for

D

solution x of the dual system A b

xv bu As t

uV pP

stp

uv

Gaussian elimination can solve a system of Bo olean equations either normal or dual

with op erations and replacing the real arithmetic used when solving linear systems

Most channel graphs fall into a class called General SeriesParallel GSP This class includes

b oth conventional seriesparallel graphs as well as ones containing acyclic branches Gaussian

elimination requires at most n algebraic op erations to solve a Bo olean system dened over

an n vertex GSP graph

Bo olean Formula Representation

A directed acyclic graph DAG with leaves denoting variables and constants and with no des

denoting Bo olean op erations can represent a set of Bo olean formulas The symb olic solution

of a Bo olean system generates a DAGwitheachformula indicated bya pointer to some DAG

no de The symb olic manipulator applies a Bo olean op eration to two formulas by creating a

new no de with branches to the no des representing the arguments By this means the total

size of the Bo olean description generated is b ounded bythenumb er of algebraic op erations

p erformed during Gaussian elimination The manipulator applies graph transformation rules

corresp onding to the laws of Bo olean algebra to simplify the formulas thereby reducing the

DAG size

A given Bo olean function has many dierentDAG representations The exact formula

structure generated during Gaussian elimination dep ends on the order in whichvertices are

eliminated Hence the result is neither unique nor of minimum size Using only these weak

symb olic manipulation algorithms however avoids trying to solveany NPhard problems

Bo olean Representation of the Steady State Re

sp onse

This section formulates the steady state resp onse of a no de in terms of Bo olean op erations

as well as relations and predicates b etween the no des It then develops systems of Bo olean

equations to describ e the steady state resp onse symb olically

Strength Enco ding

The analyzer accounts for the eects of dierent strength signals by starting at the maximum

strength and working downward each time adding in the eects from paths of the next lower

strength This approach captures signal strength eects in the structure of the equations to

Driving Path

s

s s s s

Size w

m n

l

Charging Path

Size s

m n

Figure General Form of a Strength s Path For s k the path originates at an

input no de passes through a strength s transistor and contains no weaker transistors For

s k the path originates at a storage no de of size s

b e solved In contrast MOSSIM I I and most other switchlevel simulators enco de strength

eects in the algebra in which the equations are expressed This structural approachmakes it

p ossible to express the b ehavior in terms of Bo olean algebra It has the disadvantage that the

numb er of equations to b e solved is prop ortional to the total numb er of signal strengths w

whereas the algebraic approach can use algorithms with complexity essentially indep endent

of w This do es not compromise the eciency signicantlyhowever b ecause few MOS

circuits require more than signal strengths to characterize their b ehavior storage no de

sizes transistor strengths and input no de size

For a given set of transistor states and for signal strength s the path relation P is

s

dened as m P n when there exists an unblo cked path of strength greater than or equal to

s

s from m to nIfwe dene N as

s

N m

s

mP n

s

and N as

s

N m

s

mP n

s

then N resp ectively N describ es the conditions under whichnode n will b e the des

s s

tination of an unblo cked path of strength s or greater originating at a no de m with m or

X resp or X By this denition NN and NN for no de n

 

Consider the general form of an unblo cked path from no de m to no de n having strength

greater than or equal to s It can b e an unblo cked path of strength greater than sinwhich

case m P n Otherwise the path must have strength s the p ossible forms of whichare

s

illustrated in Figure For a driving path no de m must b e an input no de and the path

must consist of a p ossibly empty sequence of transistors of strength greater than s to some

no de l followed by a transistor of strength s followed by a p ossibly empty sequence of

transistors of strength greater than or equal to s to n The p ortion from m to l cannot b e

blo cked and hence m P lFurthermore no no de in the p ortion from l to n except lcan

s

b e the destination of a denite path of strength greater than sFor a charging path no de m

must b e a storage no de of size s and the path must consist of a sequence of transistors from

m to n such that no no de is the destination of a denite path of strength greater than s

Bo olean Analysis of MOS Circuits

These conditions can b e incorp orated into a formal denition of P byintro ducing addi

s

tional predicates and relations The conditions expressed by these conditions and relations

can then b e expressed symb olically as the solutions to systems of Bo olean equations For

eachnode n dene the predicate C n as holding when n is not the destination of any denite

s

path of strength greater than or equal to s This predicate expresses the condition that the

no de is clear ie not blo cked for signals of strength s Dene the relation Q as m Q n

s s

when the following conditions hold

There is a path p in the network with Root pm and Dest pn consisting only of

transistors with state or X and strength greater than or equal to s

C l holds for every no de l in p other than m

s

The relation P can then b e expressed as P fn njn N g and for sw

s w w

n o

P P m nl m P l and l Q n

s s s s

o n

m nm Q n C m and m N

s s s

The three terms in this equation represent the three classes of unblo cked paths having

strength greater than or equal to s discussed ab ove

Substituting for the denition of N gives

s

N m m C m m N m

s s s

mP n mP l lQ n mQ n

s s

s s

By Equation the rst term in this equation equals N The second term can b e

s

transformed byreversing the ordering of the summation applying Equation inside the

summation and changing the summation variable as follows

A

L M m m

s s

mQ n

lQ n mP l lQ n lQ n mP l

s

s s s

s s

The equation for N then b ecomes

s

h i

N N M C m m N m

s s s s s

mQ n

s

By similar reasoning N can b e written as

s

h i

M C m m N m N N

s s s s s

mQ n

s

Thus the steady state resp onse at strength s is expressed in terms of the resp onse at

strength s the relation Q and the predicate C Equations for b oth Q and C

s s s s

can b e formulated as systems of Bo olean equations thereby formulating the steady state

resp onse in Bo olean terms Interestingly this derivation yields a result similar to one derived

by Byrd Hachtel and Lightner based on an order of magnitude linear network mo del

They show that at each strength level the eect of all stronger signals to a no de can b e

represented by a single voltage source with voltage corresp onding to the net signal value

while all weaker signals can b e ignored Terms of the form M and M in Equations

s s

and are analogous to a source at no de m representing the net eect of the stronger signals

at this no de Furthermore these equations contain no terms representing signals of strength

less than s

Symbolic Formulation

With this background wearereadytoformulate the steady state resp onse in terms of

systems of Bo olean equations For a transistor t the formulas indenite t and potential t

indicate whether the transistor is not denitely conducting in state or X or p otentially

conducting in state or X dep ending on the state of its gate no de n as follows

typ e indenite t potential t

ntyp e n n

ptyp e n n

dtyp e

Let V E b e a directed graph corresp onding to a single comp onentofthechannel graph

For each strength level ssuchthatws the analyzer sets up and solves three

systems of Bo olean equations two normal and one dual for dierent lab elings of this graph

The solutions yield formulas for N N andC n for each storage no de n in the

s s s

subnetwork In each case the edge lab eling describ es the transistor connections b etween

pairs of storage no des while the vertex lab eling describ es a combination of the initial value

on the storage no de plus those on input no des connected by single transistors This approach

takes advantage of the fact that anynetwork path passing through an input no de must b e

blo cked and hence transistors connected to input no des act as unidirectional switches

Starting with N for any storage no de n the analyzer computes formulas for N

w s

ws by solving the system C onduct init This system of equations is based on

s s

Equation The edge lab eling C onduct expresses the conditions under which a sequence of

s

transistors satises the conditions of the relation Q

s

C onduct m n Nc C onduct m n potential t

s s s

tT mn

s

where C onduct m n The term Nc is a formula that symb olically expresses the

w s

predicate C n as will b e dened shortly Note the asymmetry in the ab ove edge lab eling

s

where in general C onduct m n C onduct n m It arises from the requirement that

s s

C lmust hold for all no des l in the path other than the rst one By forming an

s

edge lab el equal to the Bo olean pro duct of the conduction condition for the corresp onding

transistors and the clear condition for the edge destination any path formed by these edges

must b e clear at all but the rst no de The vertex lab eling init combines terms inside the s

Bo olean Analysis of MOS Circuits

summation of Equation for a storage no de and for connected input no des

A

N potential t m Nc s k

s s

mN

tT mn

w

s

init n

s

N Nc n n N

s s s

N else

s

Starting with N the analyzer computes formulas for N ws by solving

w s

the system C onduct init This system is based on Equation The edge lab eling

s s

C onduct is the same as b efore Equation Vertex lab eling init is analogous to init

s s s

A

N Nc potential t m s k

s s

mN

tT mn

w

s

init n

s

N Nc n n N

s s s

N else

s

Finally starting with Nc for any storage no de n the analyzer computes formulas

w

D

for Nc wsby solving the dual system Indef initc This formula symb olically

s s

s

enco des the predicate C n The computation is formulated as a dual system to express the

s

absence of blo cking paths The edge lab eling Indef describ es the conditions under which

s

two storage no des are not connected by a transistor in the state of strength greater than

or equal to s

Indef m n Indef m n indenite t

s s

tT mn

s

where Indef m n Thevertex lab eling initc indicates the conditions under whicha

s

w

storage no de neither has size s nor is the destination of a denite path of strength greater

than s nor is connected to an input no de by a transistor with state and strength s

Nc indenite t sk

s

mN

tT mn

w

s

initc n

s

n N

s

Nc else

s

To summarize the computation of the steady state resp onse formulas starts with s w

and works downward to s Ateach strength level the analyzer sets up and solves

equations to compute N and N for every no de It then sets up and solves a dual

s s

system to compute Nc for every no de for use at the next lower strength level The desired

s

results for no de n equal N and N resp ectively Although the ab ove presentation used

 

names subscripted by s to represent the terms at dierent strength levels the implementation

need only retain the terms for the current strength as it iterates

Renements

The analyzer as describ ed so far achieves go o d asymptotic p erformance in terms of the size

of the formulas generated However the p erformance can b e further improved by reducing

the constant of prop ortionalityby generating a hierarchical description or by maximizing

the p otential concurrency of the evaluation

Nonessential No de Elimination

Until now the presentation has assumed that the analyzer must compute the steady state

resp onse for every no de in a subnetwork as is done by most switchlevel simulators How

ever some no des serve only as interconnection p oints in a circuitthey neither control any

transistors nor form part of the circuit memoryFor example all intermediate no des in the

pullup and pulldown networks of nMOS and CMOS logic gates serve only as interconnec

tions For mo deling circuit b ehavior a program such as a simulator need only keep track

of the states of essential no des ie those that can either directly or indirectly aect the

value of a subnetwork output

Once the analyzer has generated the DAG for a subnetwork a p ostpro cessor can prune

it to include only those parts required to compute the states of essential no des as follows

The p ostpro cessor starts by marking the DAG no des representing all formulas Nand

N for which n is a primary output of the circuit or is the gate of an ntyp e or ptyp e

transistor It then traces down the DAG and marks their descendants If it encounters

a leaf representing variable m resp ectively m and the DAG no de representing the

formula M resp ectively M has not b een marked then it marks this no de and traces

the descendants This pro cess continues until it can reach no further DAGnodes The

pruned DAG consists of those parts that have b een marked

Note that the degree of pruning dep ends on the degree to which the original formulas

have b een simplied b ecause simplication will typically reduce the number of variables

o ccurring in a formula Therefore Bo olean simplication tends to havea multiplicative

eectgreater simplication reduces the size of the original DAG and also increases the

amountby whichitcanbepruned

Hierarchical Analysis

The presentation has also assumed that the analyzer must extract the function of every

subnetwork in a circuit However most VLSI circuits contain rep eated structures and

therefore many isomorphic subnetworks A more ecient metho d would analyze only unique

subnetworks It would then pro duce a hierarchical representation in which each subnetwork

instance references the appropriate Bo olean description with its own set of no de parameters

This hierarchical analysis would require less time and pro duce a more compact description

Such an approach however requires a metho d to recognize isomorphic subnetworks

A circuit describ ed hierarchically already has much of the commonality represented ex

plicitly Unfortunately the hierarchical partitioning of the circuit will not in general con

form to the partitioning required for symb olic analysis That is the circuit elements in a

single channelconnected subnetwork may b e declared in several comp onents of the hier

archical description To exploit this hierarchy the analyzer must rst mo dify the circuit

description to resp ect subnetwork b oundaries It can do this by pulling all no de and tran

sistor sp ecications for each subnetwork up the hierarchyinto the least common ancestor of

the comp onents in which they originally o ccurred

Alternatively the analyzer can extract common subnetworks by applying graph isomor

phism techniques Although ecient and reliable algorithms for general graph isomorphism

have not yet b een develop ed heuristic metho ds develop ed in the context of interconnect ver

Bo olean Analysis of MOS Circuits

ication have proved very successful Furthermore if the analyzer fails to recognize

some isomorphisms the output will not b e as compact but the results will still b e valid

Maximizing Potential Parallelism

In the near future prepro cessors for switchlevel networks will routinely generate co de for

computers that supp ort high degrees of parallelism For example the YSE can haveupto

pro cessors op erating simultaneously and communicating through a crossbar switch Under

such conditions it is more imp ortant for the prepro cessor to reduce sequential constraints

imp osed by data dep endencies rather than to minimize the formula size Reducing data

dep endencies also simplies scheduling on highly pip elined pro cessors As is mentioned in the

companion pap er pivots can b e chosen for Gaussian elimination such that the analysis of an

n no de general seriesparallel network yields a set of formulas with O n total op erations and

maximum depth O log n Thus given sucient parallel resources the steady state resp onse

for a subnetwork could b e computed in sublinear time In contrast the algorithms used

by MOSSIM I I and all other switchlevel simulators cannot achieve sublinear p erformance

regardless of the pro cessing capabilities For example they would b e eectively limited to

sequential execution when propagating a signal down a long chain of transistors Gaussian

elimination removes this constraintby collecting information ab out the entire chain and then

redistributing the results each time through expression trees of logarithmic depth Thus a

prepro cessor based on Gaussian elimination b ecomes esp ecially attractive for highly parallel

systems

Examples

This section highlights some characteristics of the analyzer byevaluating how the analysis

would pro ceed for several general MOS implementations of logic gates and by executing

the algorithm on a small CMOS circuit For circuits containing more than a handful of

transistors it b ecomes impractical to trace the execution steps in detail and the resulting

formulas are to o large to examine manually In studying these examples the reader must

keep in mind that the true strength of the analyzer lies in its ability to handle much larger

circuits

The presentation expresses p erformance by a parameter dened as the the total num

b er of binary Bo olean op erations in the formulas divided by the numb er of transistors in the

network b eing analyzed Lower values of indicate a more ecient analysis Although this

parameter only measures the size of the analyzer output it also provides a reasonable indi

cation of the time required for execution A worst case analysis shows that cannot exceed

for circuits with at most signal strengths where all subnetworks have general series

parallel channel graphs This analysis however is far to o p essimistic Exp eriments on

actual circuits indicate a typical range of to

General Logic Gates

Static nMOS Static CMOS Domino CMOS

i



N

D

 c  ptyp e

i

k

  

out out out

i i i

  

N N N

ntyp e ntyp e ntyp e

i i i

k k k

c 

Figure Switchlevel Representations of Logic Gates The b oxes indicate networks

of transistors lab eled by strength and typ e Transistors are lab eled by their strength and

storage no des by their size

Bo olean Analysis of MOS Circuits

Figure illustrates the switchlevel representations of three classes of MOS logic gates In

this gure the network N represents a pulldown network of ntyp e transistors When viewed

as a two terminal network of switches with control variables a a the conditions under

 k

which a path forms across the terminals is given byitstransmission function T a a

 k

Similarly the network N represents a pullup network of ptyp e transistors When viewed as

D

a network of positive switches this network has a transmission function T a a equal

D  k

to the dual of T That is these two functions are related as

T a a T a a

 k D  k

Note also that T is the dual of T In most cases N is a seriesparallel network with N

D D

its dual That is parallel connections in N corresp ond to series connections in N and vice

D

versa However these conditions are not mandatorynetwork duality is a sucient but

not necessary condition for functional duality The formula obtained by solving a system of

equations representing network N is equivalent to that obtained by solving a dual system of

equations representing network N and viceversa

D

A static nMOS gate consists of a pulldown network of ntyp e transistors connecting the

output to ground and a weaker depletion mo de transistor connecting the output to p ower

The storage no de sizes make no dierence in the result and are set to for the example The

analysis of the steady state resp onse at no de out pro ceeds as follows

Out



Out T i i

  k

Outc T i i

 D  k

Out O utc T i i

  D  k

Out T i i

  k

Outc



Out T i i

 D  k

Out T i i

  k

giving OutT i i and OutT i i That is the formula for

D  k  k

O utwould express the function T applied to variables i i while the formula for

 k

O ut arising from the dual analysis of network Nwould express the function T applied to

D

i i

 k

For example a nand gate with inputs a and b would have steady state resp onse functions

O ut a b

O ut a b

Evaluating these formulas for all p ossible values of the variables yields the functionalityshown

in Table As can b e seen these formulas capture the conventional ternary extension of

the nand function In general the pairs of formulas for all nMOS logic gates express a

ternary b ehavior equal to the ternary extension of the corresp onding gate function

No de out is always the destination of a denite path of strength and hence the stored

charge of the no des within N cannot aect its steady state resp onse Eliminating nonessential

a a a b b b Out Out Out

X

X X

X

X X

X X X

Table Threevalued Behavior of Nand Gate The formulas generated by the analyzer

predict the same b ehavior as conventional ternary logic

variables would then reduce the set of formulas to those expressing the steady state resp onse

of outFor the case of a seriesparallel network and an analysis by Gaussian elimination

with no de out eliminated last the size of the formula generated will equal the number of

transistors minus This gives a p erformance measure slightly less than Even for

networks that are not strictly seriesparallel such as ones containing bridges will not

signicantly exceed

A static CMOS gate consists of a pulldown network of ntyp e transistors connecting the

output to ground and a pullup network of ptyp e transistors connecting the output to p ower

where the twonetworks have dual transmission functions Neither the transistor strengths

nor the storage no de sizes aect the gate function For the example they are set to and

resp ectively The analysis of the steady state resp onse at no de out pro ceeds as follows

Out T i i

 D  k

Out T i i

  k

Outc T i i T i i

  k D  k

Out T i i x O utc T i i

 D  k  D  k

Out T i i y O utc T i i

  k   k

where the terms x and y express the eects of the initial stored charge on no des out and

those internal to N and N These terms are eliminated by absorption and hence are not

D

shown in detail The steady state resp onse is therefore identical to that obtained for an

equivalent nMOS gate even when some inputs equal X

Unlike nMOS gates there may b e no denite driving path to out and hence the paths

representing sources of stored charge to out may not be blocked However in all such cases

the gate output will equal X and hence these paths have no eect Unfortunatelythe

analyzer may not recognize the p ossible absorption of terms representing sources of stored

charge by those representing driving paths To do so it must recognize that the formulas

generated during the normal analysis of N and N are equivalent to those generated during D

Bo olean Analysis of MOS Circuits

the dual analysis of N and N resp ectively Using Gaussian elimination where no de out is

D

eliminated last and the formula manipulation techniques describ ed in the companion pap er

these equivalences will b e recognized for the most common case of N b eing seriesparallel

and N its dual If these absorption conditions are recognized then nonessential variable

D

elimination will reduce the set of formulas to those representing the steady state resp onse of

out Therefore for seriesparallel networks the analyzer has a p erformance with slightly

less than On the other hand it will not do as well for networks that are not seriesparallel

nor where N and N are not dual networks Such cases are suciently rare to have little

D

impact on the overall p erformance

A domino CMOS gate consists of a ptyp e precharge transistor a pulldown

network of ntyp e transistors and an ntyp e discharge transistor that can connect the gate

output to ground through the pulldown network Both the precharge and the discharge

transistors are gated by a common clo ck c Transistor strengths do not aect the gate

function and are set to for the example However when connected in domino fashion the

output no de must have greater capacitance than the internal no des of Nbecauseitmay

share charge with them Therefore no de out has size and the no des internal to N have size

The analysis of the steady state resp onse at no de out would pro ceed as follows

O ut c



O ut T i i c

  k

O utc T i i c c

 D  k

T i i c c c

D  k

O ut c T i i c out c c out

 D  k

O ut T i i c T i i c out c c out

  k D  k

O utc



O ut c T i i c out c c out

 D  k

O ut T i i c T i i c out c c out

  k D  k

giving nal results

O ut c T i i c out c c out

D  k

O ut T i i c T i i c out c c out

 k D  k

Once again the stored charge on the internal no des of N will have no eect on the steady

state resp onse of out and hence the formulas for these no de variables can b e eliminated

These formulas app ear more complex than the previous ones but in fact only require

seven binary op erations b eyond the numb er required to represent the formulas for T and

T Hence for the seriesparallel case the analyzer has a p erformance with slightly more

D

than To b etter understand these formulas consider the eect of a sequence in whichthe

clo ck c is rst set to and then to The rst setting would give a steady state resp onse

O ut and Out Letting these b e the values of out and out resp ectively

the second setting would give a steady state resp onse with O utT i i and

D  k

O utT i i Hence a domino gate has the same functionality as a static gate

 k

c

a  

b

r



q

a  

d

p



b

Figure Example CMOS Circuit Transistors are lab eled by strength All storage no des

havesize Although rather contrived this circuit demonstrates a varietyofinteresting

switchlevel eects

even when some inputs equal X The same result o ccurs when simulating the gate in ternary

mo de with c set rst to then to X and nally to This indicates that the gate is

not sensitive to the rise time of the clo ck

In summary the analyzer p erforms very well for most logic gates deriving formulas that

corresp ond directly to the seriesparallel structure of the pulldown and pullup networks

Furthermore even in subnetworks containing logic gates connected to more complex circuitry

through pass transistors the gate functions will b e extracted eciently This p erformance

should not seem extraordinarygiven that logic gates form a particularly simple class of

MOS circuits However this p erformance far exceeds the exp onential complexityachieved

by other general analysis metho ds Having the general analysis algorithm obtain ecient

results for straightforward cases eliminates the need to devise sp ecialized co de to handle

these cases

Circuit with Stored Charge

Figure shows a small but relatively complex circuit in terms of its set of p ossible

behaviors This example demonstrates such prop erties as complementary logic bidirectional

pass transistors stored charge and ratio eects It is not intended to demonstrate go o d

circuit design practice The circuit contains a two input nand gate with output q The

gate output is connected bya ptyp e pass transistor to a no de r which also has a kill

transistor to ground The kill transistor has strength indicating that it can override any

Bo olean Analysis of MOS Circuits

R R

A

A

d

AU

Q

A

Q

AU

Q

r r

d d

Q

Qs

A A Q A

AU AU AU

c c c

d d

H

H Q C A

CW

H

H A

A

a

b

H

AU Hj AU

A A A A

AU AU AU AU

c a c a

d b d b

Figure DAG Representation of Example Circuit The leaves denote variables de

scribing the initial state of the circuit while the vertices denote Bo olean op erations The

p ointers lab eled Q Q R and R denote formulas for the new states of no des q and r

value transmitted to r through the pass transistor Furthermore if b oth the kill and pass

transistors are turned on when the gate is driving toward a ghtwilldevelop at q giving

X as its steady state resp onse

The steps in the analysis are to o complex to show in detail Executing them and simpli

fying the formulas by hand yields the following results for no de q

Q a b

Q a b c d

For claritythe symbols have b een removed in the ab ove formulas and parentheses have

b een omitted where p ossible with the convention that and takes precedence over or These

formulas are simply those of a nand gate with an additional term indicating the conditions

under which the kill and pass transistor can drive q toward

For r the analyzer yields the formulas

h i

R d c r a bc a b a b r

h i

R d d c r a b c a b a b r

These formulas app ear quite complex but each term can b e recognized as describing a

sp ecic contribution to the steady state resp onse Part of this complexityowes to the fact

that they describ e the circuit b ehavior with some inputs equal to X as well as and From

these formulas one can determine the conditions leading to the three p ossible steady state

resp onses on r The steady state will equal for the following combinations of input and

state variables where a dash indicates that the corresp onding variable can equal or X

a b c d r

Similarly it will equal for the following combinations of input and state variables

a b c d r

All other cases yield X

Finally the formulas for p are unimp ortant Being an interconnect no de within a logic

gate this no de is not essential

Figure shows the DAG representation of the formulas for the steady state resp onse

on no des q and r This DAG has no des representing binary op erations giving an

of Thus even a more complex structure in terms of its switchlevel b ehavior has a

reasonably concise Bo olean description The size seems esp ecially reasonable considering

that the formulas describ e the circuit outputs for all ternary combinations of the input

and state variables not just the Bo olean combinations

Extensions

Some applications of the switchlevel mo del require features b eyond the basic b ehavioral

representation develop ed so far Many of these extensions can b e provided in straightforward

wayby mo difying the Bo olean equations for the steady state resp onse The ease with which

these extensions are incorp orated further demonstrates the strength of the mathematical

framework

Fault Mo deling

Switchlevel fault simulators such as FMOSSIM haveproved very successful at realis

tically mo deling a wide range of faults in MOS circuits These programs can representthe

Bo olean Analysis of MOS Circuits

eects of faults such as no des forced to ground or supplyaswell as transistors stuckopen

or closed without changing the basic logic mo del Normally the analyzer pro duces formulas

that cannot mo del these fault eects Simply injecting faults into the formulas would create

faults for which there are no counterparts in the switchlevel network as well as overlo ok

faults that could exist in the network However a mo died analysis can preserve the fault

behavior of the circuit This mo died analysis requires only a small numb er of additional al

gebraic op erations p er transistor and p er no de although the resulting formulas cannot

b e simplied as well

The analyzer injects faults byintro ducing additional Bo olean variables where a variable

is set to when the fault is present and to otherwise This fault variable approachcan

describ e fault eects by Bo olean op erations and hence apply the solution and manipulation

techniques already develop ed

For eachnode n fault variable n indicates whether the no de acts as an input or a

storage no de As an input no de it is stuck at either or X dep ending on the values

of n and n The analyzer incorp orates this variable into the analysis by redening the

terms representing signals of input strength

N n n

w

N n n

w

Nc n

w

The remainder of the analysis pro ceeds as b efore

For each transistor tvariables tandt indicate the conditions when the transistor is

stuckop en nonconducting or stuckclosed resp ectively Of course a stuckclosed fault on a

dtyp e transistor has no eect and hence can b e omitted When a transistor is stuckclosed

it is mo deled at its nominal strength although this can easily b e generalized to dierent

strengths The analyzer incorp orates these variables into the analysis by simply mo difying

the denitions for indenite tand potential tasfollows

typ e indenite t potential t

ntyp e n t t n t t

ptyp e n t t n t t

dtyp e t t

All other steps of the analysis remain unchanged

The analyzer can mo del other classes of faults such as a bridges and breaks in the wires

byintro ducing additional fault variables However its eciency degrades as the number of

fault eects grows large esp ecially those eects that force a merging of subnetworks

Restoring Logic

Conventionally switchlevel simulators ignore voltage degradations through pass transistors

caused by threshold eects This can cause a signicant class of design errors to remain

undetected Many CMOS circuits for example are designed with the intention that only

signals equal to either the supply or ground voltage act as valid logic values A more

conservativemodelwould enforce this rule by yielding X when a passes through an ntyp e

or a passes through a ptyp e transistor In cases such as a transmission gate where each

signal also passes through a complementary transistoraorshould result The simulator

MOSSIM I I optionally enforces such a rule Yo eli and Brzozowski haveproposeda

similar rule in their switchlevel mo del

We can incorp orate this convention into the switchlevel mo del by mo difying the de

nition of a denite path and consequently the way the analyzer computes Nc That is

s

a path p with Root pn is denite if either n resp ectively and no transistor in

Trans p has state X or is of ntyp e resp ptyp e In other words only fully restored

signals transmitted through fully conducting transistors can blo ckweaker paths Note that

we need not b e concerned ab out denite paths originating at a no de with state X b ecause

if such a path exists and there is no denite stronger path then the steady state resp onse

will equal X anyhow

The computation of Nc must compute the eects by sources of and separately and

s

combine the two results

Nc n Nc Nc

s s s

where formula Nc resp ectively Nc describ es the absence of a denite path to no de

s s

n originating at a no de with state resp and having strength greater than or equal to

D

s the analyzer computes these twovalues by solving dual systems Indef initc and

s s

D

Indef initc Toformulate these dual systems dene indenite tand indenite t

s s

for transistor t as follows

typ e indenite t indenite t

ntyp e n

ptyp e n

dtyp e

That is indenite t resp ectively indenite t describ es the cases where the transistor

cannot b e part of a denite path originating at a no de with state resp ectively where

indicates always and indicates never

Edge lab eling Indef is dened as Indef m n and for wsas

s w

Indef m n Indef m n indenite t

s s

tT mn

s

Vertex lab eling initc is dened for storage no de n and strength wsas

s

Nc indenite t m sk

s

mN

tT mn

w

s

initc n

s

n n N

s

Nc else

s

with the convention that Nc Observehow this formula uses variables n and m

w

to place restrictions on the ro ot no de state If n then no de n cannot b e the ro ot of a

denite path p with state and similarly for m

Bo olean Analysis of MOS Circuits

Similarly edge lab eling Indef is dened as Indef m n and for wsas

s w

Indef m n Indef m n indenite t

s s

tT mn

s

Vertex lab eling initc is dened as

s

Nc indenite t m sk

s

mN

tT mn

w

s

initc n

s

n n N

s

Nc else

s

with the convention that Nc

w

This extension adds an extra system of equations at eachlevel and hence results in

somewhat larger formulas This seems a reasonable price to pay for detecting an additional

class of circuit design errors

As an example applying this mo died analysis to the circuit of Figure has no eect on

no de q but for no de r yields the formulas

h i

R d c r a bc a b r

h i

R d d c r a b c a b r

This reduces the cases for which r has steady state resp onse to the following

a b c d r

That is r will not b e pulled to when a b and c unless r or d

Charge Decay

During normal op eration most switchlevel simulators assume that a no de retains its stored

charge indenitely In actual circuits leakage currents cause stored charge to eventually

decay to some indeterminate value A simulator that do es not mo del this decay will fail to

detect cases in which prop er b ehavior dep ends on stored charge b eing maintained b eyond

some reasonable time limit

The simulator MOSSIM I I has an optional mo de in whichcharge is retained only for a

numb er of clo ck cycles sp ecied by the user Any storage no de that remains unrefreshed for

this many cycles is set to X Suchanevent do es not in itself indicate a circuit design error

However any further op erations that dep end on this no de state will yield more X values

and hence invalid uses of stored charge can b e detected MOSSIM I I implements this feature

by tagging every no de with the most recent refresh time measured in clo ck cycles Due to

subtleties caused by b oth charge sharing and by transistors in the X state it must use a

c

b

p q

r

  

a

Figure Charge Sharing Circuit Example No des q and r can obtain new logic values

by sharing charge with p

rather complex algorithm to compute the eective refresh time of a no de as it up dates the

state

The capability provided by MOSSIM I I cannot b e describ ed eciently in terms of Bo olean

op erations b ecause every no de state must sp ecify b oth a logic value and an integer refresh

time By adopting a somewhat less precise timing scheme however a Bo olean representation

b ecomes more practical In this scheme the p erio d over which the circuit op erates is divided

into a series of ep o chs An ep o chwilltypically have duration equal to half the maximum

numb er of clo ck cycles for which stored charge may b e assumed valid A ag is maintained

for each storage no de indicating whether the no de is fresh or stale ie whether or not

it has b een refreshed during the current epoch This ag is up dated every time the no de

state is recomputed At the end of each epoch the states of all stale no des are set to X

At the same time all no des not currently connected to input no des are marked as stale for

the start of the next ep o ch With this scheme the exact charge retention time can range

between just over one epoch to just under two dep ending on the alignmentbetween the

refresh time and ep o ch b oundaries This degree of accuracy suces for most applications

b ecause most designers set conservative limits on charge retention time

Developing a precise denition of the conditions under which a no de is refreshed involves

several subtleties Clearly a no de is refreshed whenever it is connected to an input no de

by a set of transistors in the state Consider however the circuit shown in Figure in

which several storage no des may share charge In particular no de p has greater size than

either q or r and hence the state of p can override those of q and r In some circuit designs

such as where p is high capacitance bus the transistors may b e op erated in sucha way that

no conducting path ever forms b etween an input no de and either q or r Such cases can

b e handled with a convention that whenever no des q or r share charge with p they will b e

marked as fresh if p is fresh and as stale otherwise As a further subtlety when transistors

in the X state are presentanodemayormay not b e refreshed dep ending whether or not

this transistor is actually conducting Such cases can b e handled with a convention that a

Bo olean Analysis of MOS Circuits

no de should b e marked as stale if its state may dep end on that of some stale no de for some

combination of conducting and nonconducting transistors To summarize these conventions

precisely a no de should b e marked as stale whenever it is the destination of an unblo cked

path originating at a stale no de

To express these conditions symb olically the analyzer intro duces a variable n for every

storage no de n with value indicating stale and indicating fresh The analyzer then

generates a formula N for each no de sp ecifying when it should b e marked as stale as a

function of the state and refresh variables asso ciated with the no des The analyzer generates

these formulas in a manner similar to that used to generate the formulas N and N

Starting at strength s k the maximum storage no de size and working downward to it

solves the system C onduct init to generate formulas N for eachnode n The desired

s s s

formula N equals N The edge lab eling C onduct has already b een dened as Equation

 s

The vertex lab eling init indicates the conditions under whicheachnodemaybethe

s

source of stale charge

N Nc n n N

s s s

init n

s

N else

s

with the convention that N

k 

The simulator utilizes these formulas as follows At the end of an ep o ch the simulator

makes two passes over the no des The rst pass sets the state of anynoden for which n

to X and also sets n to The second pass evaluates the formula N to determine the

new value of n This second pass marks as fresh only no des to which all unblo cked paths

originate at input no des As the simulator pro ceeds every time it computes a new state for

no de n it computes a new value of n byevaluating the formula N

As an example applying this analysis to the circuit of Figure yields the following

formulas

P a p

Q a b pb qb c r

R a b c p b c q b r c r

Observethat p can b e marked as stale only if it is already stale and a On the other

hand q is marked as stale if it shares charge with a stale value on either p or rorifitis

isolated and already stale Similar results hold for r

Conclusion

Transforming a switchlevel network into an explicit functional representation has proved a

challenging task Previous attempts yielded results that were to o inecient or to o inaccurate

for practical use The solution presented here relies on three ma jor ideas First systems

of Bo olean equations can describ e switchlevel networks Second Gaussian elimination can

take advantage of the sparse structure of these systems and generally give solutions of linear

complexity FinallytheDAG representation of a set of formulas can exploit the sharing of

common sub expressions to givea very compact result

The analyzer has the p otential to improve the eciency of programs for a varietyofMOS

circuit analysis tasks It can incorp orate a numb er of mo deling extensions by mo difying or

augmenting the system equations The advantage of this approachtoswitchlevel mo deling

will increase as hardware b ecomes available that achieves high p erformance through greater

degrees of sp ecialization and concurrency

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