LPC800: Packing a 32-bit punch for an 8-bit K.O. LPC Go Family Steven McQuade Amish Desai Paul Boogaards LPC800 Introduction

Simplicity High performance at a low price point 2-10x higher performance than 8/16-bit MCUs 2-3x power saving compared to 8/16-bit MCUs 40-50% smaller code size than 8/16-bit MCUs Single cycle IO access Easy to use and flexible peripherals: SCT, Multi Rate Timer, Switch Matrix, USART, I2C, SPI

2 LPC800 Introduction

3 LPC800 Block Diagram Cortex-M0+ processor, up to 30MHz LPC800: Low Power Cortex-M0+ Low Active Current 100 µA/MHz

Flash

ARM Single VDD power supply (1.8V to 3.6V) CORTEX-M0+ Up to 16kB 30 MHz

LITE Bus LITE SRAM

Memory: - IOP Up to 4kB

Up to 16kB Flash AHB – GPIO ROM – Up to 4kB SRAM Up to 18 – ROM: CRC Engine SCT Bridge USART, I2C, Power Profile, ISP/IAP Drivers Power Control 4 ch. Multi-Rate Timer PMU, power modes,

Peripherals: BOD, single Vdd power – Switch matrix for peripheral configurations WWDT supply, POR Matrix – State Configurable Timer Wake-up Timer Clock Gen Unit 12MHz, 1% IRC OSC GPIO Pads TIMERS

– Pattern matching engine (GPIO) Switch Watchdog OSC – Up to 3x USART, 2x SPI, 1x I2C Bus APB 1-25 MHz System OSC SPI (2) System PLL – Comparator with external Vref SYSTEM – 4-channel Multi-Rate Timer (MRT) I2C – Self wake-up timer Comparator USART (3) With External Vref – Systick timer, SERIAL INTERFACES ANALOG – High-speed GPIO with up to 18 GPIOs – 1% accuracy, 12 MHz IRC oscillator TSSOP16/20, SO20 and DIP8

4 ... but yet nobody delivers what 8/16-bit engineers really want

Upside in Power All at an Ease of Use Longevity Performance Efficiency 8-bit price

5

Introducing the LPC800

8-bit Simplicity 32-bit Versatility Smart Peripherals

6 The Newest Member of LPC Go Family

Flashless LPC Command

1MB

768kB LPC ConnectTurbo 512kB

256kB

128kB LPC Go Flash LPC Connect LPC ConnectPlus 64kB LPC1100 32kB Strong base of 100 product options shipping 16kB LPC800 8kB Newest member of LPC Go family

4kB

<16 20 24 33 48 64 80 100 144 180 208 256 296 pins

7 MASS PRODUCTION LPC Go 2-yr Roadmap SAMPLING DEVELOPMENT LPC1100 CONCEPT

Cortex-M0+ Cortex-M0+ 256kB Flash + Segment LCD, 256kB Flash, 1.4Msps 12-bit ADC 1.4Msps 12-bit ADC

LPC11E3x Cortex-M0 50MHz 12kB SRAM, 128kB FLASH 4kB EEPROM LPC11E1x Cortex-M0 50MHz 10kB SRAM, 32kB FLASH 4kB EEPROM, 130µA/MHz LPC111x Cortex-M0 50MHz 8K SRAM, 8-64K FLASH 110µA/MHz LPC111x LPC Cortex-M0 50MHz 8kB SRAM, 32kB FLASH SO20, TSSO20/28, DIP28 pkgs LPC800 LPC800 LPC1100LV Low-end Cortex-M0+ Cortex-M0+ 16kB FLASH, 4kB SRAM, Market Specific 1.8V Cortex-M0 50MHz Comparator Cortex-M0+ 8kB SRAM, 32kB FLASH 32kB Flash, 12-bit ADC 110µA/MHz, CSP25 Samples Now, Production April’13

Q3’12 Q4’12 Q1’13 Q2’13 Q3’13 Q4’13 Q1’14 Q2’14

Concept projects can change without notice 8 8-bit Simplicity

Embedded ROM Drivers UART and I2C – Easy configuration Power profiles Frees up Flash for code 64-byte page program/erase Simplifies code management – Smallest page size – No need to worry about big page erase (losing effective memory) Enables developers to program Flash like an EEPROM Cost-effective

9 32-bit Versatility Exceptional Power Efficiency

Continued improvements in dynamic current consumption – Now <100µA/MHz – 35% reduction in less than 3 years – True figures for performance out of flash and over various frequencies

Various low-power modes – Serial interfaces designed to wake up from low-power modes – Additional power profiles

13

32-bit Versatility

Leveraging the ARM Ecosystem

Extensive user community Online developer forums Extensive sample code Free tools More

14 32-bit Features at an 8-bit Price

LPC810 LPC811 LPC812 LPC812 LPC812 M021FN8 M001FDH16 M101FDH16 M101FD20 M101FDH20 Flash 4 8 16 16 16 SRAM 1 2 4 4 4

Package DIP8 TSSOP16 TSSOP16 SO20 TSSOP20 I2C 1 1 1 1 1 SPI 1 1 2 1 2 UART 2 2 3 2 3 SCT 1 1 1 1 1 Timer 4-ch 4-ch 4-ch 4-ch 4-ch Comp 1 1 1 1 1

Comp Vref No Yes Yes Yes Yes GPIO 6 14 14 18 18 Availability Samples/Eval Boards: Now / Production: April 2013 Pricing Starting at $ 0.39 / 10k volumes

15 APPLICATIONS car security alarm, garage door opener, LPC800 lighting control via Dali Low cost does not mean low functionality!

APPLICATIONS COST low LED light, switches, smoke detector S2

F1 APPLICATIONS T3 air freshener, timers, lower blinkers, button remote S1 A1

M4

More LPC800’s coming soon ultra-low Cortex-M0+ T2 M3 T1 M2 M1 limited mid-range high-end FUNCTIONALITY

16 LPC800->Simplicity_Flexibility

17 LPC800 Clock Generation Unit Clock Sources Characteristics IRC Oscillator System clock by default Stable power up and power down 12 MHz (±1% over specified temperature and voltage)

Watchdog Oscillator Low power operation Low frequency oscillator 9.3 kHz – 2.3 MHz (+/- 40%) MAIN Oscillator 1 MHz – 25 MHz (1.8 V typical) CLKIN 1 MHz – 25 MHz (3.3 V typical) SYS PLL Multiplies the clock source Low Power Oscillator Low power operation Low frequency oscillator 10 kHz (+/- 40%)

18 Superior Code Density

64

Instruction Size for 48 Various Processors

32 Number of bits Number

16

8051 PIC18 PIC24 MSP430/ Cortex-M0+ Leading to superior code density: MSP430X – In Cortex-M0+ all instructions (except BL) are 16 bits wide instructions – Over 64kB of address space, 8- and 16- processors have to introduce paging, leading to extra overhead in code

19 Superior Code Density (e.g. 16-bit Multiply) 8-bit (8051) 16-bit (MSP430) ARM Cortex-M0+

MOV A, XL; 2 bytes MOV R4,&0130h MULS r0,r1,r0 MOV B, YL; 3 bytes MOV R5,&0138h MUL AB; 1 byte MOV SumLo,R6 MOV R0, A; 1 byte MOV SumHi,R7 MOV R1, B; 3 bytes (Operands are moved to and from a MOV A, XL; 2 bytes memory mapped hardware multiply MOV B, YH; 3 bytes unit) MUL AB; 1 byte ADD A, R1; 1 byte MOV R1, A; 1 byte MOV A, B ; 2 bytes ADDC A, #0; 2 bytes MOV R2, A; 1 byte MOV A, XH; 2 bytes MOV B, YL; 3 bytes 29 4 1 MUL AB; 1 byte ADD A, R1; 1 byte Instructions Instructions Instruction MOV R1, A; 1 byte MOV A, B ; 2 bytes ADDC A, R2; 1 bytes MOV R2, A; 1 byte MOV A, XH; 2 bytes MOV B, YH; 3 bytes MUL AB; 1 byte ADD A, R2; 1 byte MOV R2, A; 1 byte MOV A, B ; 2 bytes ADDC A, #0; 2 bytes MOV R3, A; 1 byte Time: 48 instruction cycles Time: 8 clock cycles Time: 1 clock cycle Code size: 48 bytes Code size: 8 bytes Code size: 2 bytes

20 Switch Matrix Movable functions – Can be assigned to any external pin that is not power or ground – UART, SPI, I²C, SCT, comparator output, CLKOUT, pattern match output Fixed pin functions – Oscillator pins, comparator input, GPIOs – Can be replaced by movable functions Switch Matrix

UART P0_1

SPI P0_2

I2C P0_3

SCT P0_4

21 Switch Matrix Configuration Tool Free Tool: Download from LPCware.com!

http://www.lpcware.com/gfiles/devper/lpc800

22 Switch Matrix Configuration using Tool 1. Choose package type

23 Switch Matrix Configuration Tool

The default pin configuration is displayed after the device/package has been selected

24 Switch Matrix Configuration Tool

2. Select the peripheral you would like to configure. It will be highlighted after selection. In this example, USART1 has been selected

25 Switch Matrix Configuration Tool

3. Click on the pin where you would like to place the peripheral function In this example, we will check U1_TXD

26 Switch Matrix Configuration Tool

The alternate U1_TXD function is now shown on pin 1

27 Switch Matrix Configuration Tool

4. Configure the other pins. We have used the same procedure to set PIO0_13 (pin 2) to U1_RXD

28 Switch Matrix Configuration Tool The code for configuring the PINASSIGNx registers will be shown in the swm.c tab, as shown below. This can be copied into your source code. Don’t forget to enable the SWM clock!

Hint: you can disable the clock to the Switch Matrix after configuration to save power!!

29 LPC800: Flexible I/O Port I/O Port – Up to 18 GPIOs – Single cycle access to all port pins – Support high frequency I/O toggling – As fast as CPU_Clock/2 = 15MHz! – Enhanced GPIO Pin Manipulation – Capable of simultaneously reading Bit/Byte/Word or toggling up to 18 I/Os per instruction – Programmable Internal pull-up/pull-down resistor, open-drain function, input inverter, and repeater mode – Up to 8 pins can be selected from all GPIO pins as edge- or level-sensitive requests – All GPIO pins are equipped with a programmable digital glitch filter. The filter rejects input pulses with a selectable duration of shorter than one, two, or three cycles of a filter clock – High-current source output driver (20 mA) on four pins – High-current sink driver (20 mA) on two true open-drain pins

30 Enhanced GPIO Pin Manipulation Support high frequency I/O toggling – as fast as CPU_Clock/2= 15MHz! This scope trace shows the single cycle IO port access allowing 15 MHz with a core clock of 30 MHz

31 LPCXpresso (IDE + Evaluation Board + Emulator)

LPCXpresso board (OM#13053), MSRP: $29.95; available today LPCXpresso IDE can be downloaded for free from www.nxp.com/lpcxpresso or www.lpcware.com/lpcxpreso Keil and IAR tools also support this tool through the 10-pin SWD header

32 Your First LPC800 Project

33 Your First LPC800 Project

34 Your First LPC800 Project Under “Start here” in the Quickstart Panel, select “New Project”

35 Your First LPC800 Project When the New Project Wizard display this dialog box, just accept the default values

36 Your First LPC800 Project There is one file in the CMSIS_CORE_LPC8xx which you will need for almost any project: system_LPC8xx.c This file contains the clock setup routines There is rarely a need to modify the source code. Just change the defines: #define CLOCK_SETUP 1 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001

You can configure the clocks using the PLL calculator, available for download from LPCware.com

37 Your First LPC800 Project For example, if you would like the system to run from the internal RC oscillator, running at 18 MHz

38 Your First LPC800 Project

Use the PLL calculator to configure the defines:

#define CLOCK_SETUP 1 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 #define SYSPLLCTRL_Val 0x00000042 // Reset: 0x000 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001

39 Your First LPC800 Project void SysTick_Handler(void) {

LPC_GPIO_PORT->NOT0 = (1<<7) | (1<<16); // toggle the pins } int main(void) {

SystemCoreClockUpdate(); // retrieve the clock LPC_GPIO_PORT->DIR0 = (1<<7) | (1<<16); // P0.7 and P0.16 outputs LPC_GPIO_PORT->SET0 = (1<<7); // turn off the red LED

SysTick_Config( SystemCoreClock / 2 ); // set the Systick to 0.5sec

while(1) { } return 0 ; }

40 LPC800->Low Power

41 Cortex-M0+ Has Lower Power Consumption

Cortex-M0+ runs at a much slower clock frequency for the same required performance Cortex-M0+ can sleep most of the time, or it can handle additional tasks

42 LPC800 Low Power Modes Low Power Impact Wake-Up Sources Wake-up Current Mode Time Consumption System Clock to Cortex-M0+ is stopped. Any peripherals Peripherals and memories are active. (SCT, MRT, USART, SPI, I2C, Processor state and registers, peripheral CMP) Sleep registers, and internal SRAM are Pin interrupts & Pattern maintained, and the logic levels of the Match Engine pins remain static BOD interrupt and reset 2.6 µs 600 µA * WWDT interrupt and reset External Reset Self Wake-up Timer Peripherals receive no internal clocks. Interrupts from USART, Flash is in stand-by mode. Peripherals SPI, I2C and memories are active. Processor Pin interrupts Deep Sleep state/registers, peripheral registers, and BOD interrupt and reset internal SRAM contents are maintained, WWDT interrupt and reset 4.2 µs 170 µA and the logic levels of the pins remain External Reset static Self Wake-up Timer Peripherals receive no internal clocks. Interrupts from USART, The is powered down. SPI, I2C, Pin interrupts Processor state/registers, peripheral BOD interrupt and reset Power-Down registers, and internal SRAM contents WWDT interrupt and reset are maintained, and the logic levels of External Reset 53 µs 1.8 µA the pins remain static Self Wake-up Timer

The entire system is shut down except Wake up on a pulse on the Deep Power- for four 32-bit general purpose registers WAKEUP pin or when the Down in the PMU and the self wake-up timer. self wake-up timer times 215 µs 220 nA Register states and internal SRAM out. On wake-up, the part contents are lost reboots. * 12 MHz, peripherals disabled, low current mode

43 Power Profiles A easy-to-use API driven interface for dynamic current management at runtime Application can be focused towards:

CPU Performance

~30% increase in performance CPU Efficiency Default Mode after Reset Decreased power consumption compared to default ~20-30% reduction in active power Lowest Active Power

Runtime

44 Power Profile Results using Keil v4.70

Power Profile 12 MHz 24 MHz Current CoreMark CoreMark/ Current CoreMark CoreMark/ (mA) MHz (mA) MHz Default 2.50 16.88 1.41 4.40 33.76 1.41 CPU Performance 1.98 24.62 2.05 4.27 49.24 2.05 Efficiency 1.98 24.62 2.05 4.27 49.24 2.05 Low Current 1.56 12.93 1.08 3.15 25.85 1.08 Note: The current consumption is improved by using Power Profiles The CoreMark scores are improved by using Power Profiles

45 ROM Drivers for LPC800

On-chip ROM contains the boot loader and the following Application Programming Interfaces (API):

– In-System Programming (ISP) and In-Application Programming (IAP) support for flash programming

– USART driver API routines • The UART API handles sending and receiving characters using any of the USART blocks in asynchronous mode.

– I2C-bus driver API routines • The drivers can be used to send or receive data on the I2C bus in master and slave modes.

– Power profiles for optimizing power consumption and PLL settings

46 LPC800->High-Performance

47 CoreMark Benchmark Results (EEMBC)

Processor CoreMark/MHz CoreMark

NXP LPC800* 2.05 49.24 (24 MHz) Atmel ATmega644 0.54 10.81 (20 MHz) Microchip PIC24FJ64 0.75 23.87 (32MHz)

TI MSP430F5438A 0.78 19.56 (25 MHz) http://www.coremark.org/benchmark/index.php?pg=benchmark

*Not yet uploaded to CoreMark website

48 LPC800->Powerful_Peripherals

49 Timers

Multi-Rate timer (MRT) – Timer with four independent channels – Each channel can generate interrupts • Repeat interrupt mode • One-shot interrupt mode Self wake-up timer (WKT) – A non-zero value in this 32-bit timer initiates a countdown sequence. Wake-up source from low-power modes Windowed watchdog timer (24-bit timer) Systick Timer (24-bit timer) State Configurable Timer (SCT) – General purpose timer – PWM

50 General Timer Basics

Up, Down, Up-Down counting – Generate an interrupt on events (match or capture) Operations on match event: – Continue counting or stop the counter – Reset (limit) counter – Set or clear an assigned GPO signal Operations on capture event: – Take a counter “snapshot” – Reset (limit) the timer

51 What’s a State Machine?

A State Machine is made of: – States – Inputs, like real input/output pins or matches (events) – Outputs (actions initiated by events) – Transitions (change state)

Input == true State B set event

State A

52 State Configurable Timer (SCT) - Overview

State Configurable Timer (SCT) is a timer/capture unit coupled with a highly flexible event driven state machine block. Can be configured as 32-bit counter or two 16-bit counters with a configurable state machine Allows a wide variety of timing, counting, output modulation, and input capture operations. Key Features: – 4 inputs – 4 outputs – 5 match/capture registers – 6 events with state machine support – 2 states

53 How does the SCT work?

Action Input • Drive an output • Time based value signal (set or clear) (timer match) • Make the timer • Signal level (high / state machine jump low) or rising / falling to another state edge (for both inputs • Start / Stop / Halt / new state Event and outputs) Limit the timer (also state • Combination of a the other timer half!) match and/or and • Capture the input/output current counter condition in a value specified state • Generate an interrupt

54 SCT - Examples

Limit Match events

55 Blinky example using SCT

MATCH 0 MATCH 0

SCT Timer

SCTOUT_0

STATE 0 STATE 1 STATE 0 STATE 1 STATE 0

100 msec EVENT 0 EVENT 1

56 2-channel PWM with dead-time control using SCT

57 4-channel PWM with Abort

58 LPC800 SCT Cookbook

Collection of code examples (both Keil and LPCXpresso) Each code example summarized in Cookbook document Available so far (and more to follow): – SCT_blinky_irq : generate 10 msec timer tick – SCT_blinky_match : toggle output every 10 msec – SCT_match_toggle : same using conflict resolution – SCT_pwm : generate PWM output – SCT_pwm_um : PWM with two different duty cycles – SCT_pwm_deadtime : PWM and dead time generation (for HB control) – SCT_pwm_4ch : 4 channel PWM + abort input – SCT_pwm_decode : pulse width measurement – SCT_rc5_send : modulate RC5 code at 36 kHz carrier – SCT_rc5_receive : decode RC5 frame (Manchester coding)

59 State Configurable Timer (SCT)

Implements virtually any timing or PWM function found on popular 8-bit MCUs without loading the Motor Control PWM Generating PWM outputs with CPU programmable dead-time – Wide variety of counting, output, input, and Lighting control operations Modulated PWM outputs, reaction – Dead time insertion to lamp sensor – High resolution PWMs Custom sampling of input GUI-based configuration tool (Code Red Redstate) signals for: • Frequency detection – Integrated into LPCXpresso • Pulse width detection – Choose pre-configured timing functions or • Phase detection build your own Custom control signals in hardware: • Clock or signal gating • Complex modulation of outputs • Pulse sequences

60 Red State – Graphical SCT configuration tool

61 Pattern Match Engine (PME)

Pin Interrupt generator – Up to 8 pins can be selected to generate interrupts to the core Pattern match feature – The same 8 pins (above) can be selected from all IN0 IN1 GPIO pins to contribute to a Boolean expression IN2 IN3 Pattern • Example: OUT IN4 Match (IN0)~(IN1)(IN3)^+(IN4)(IN5)+(IN0)~(IN3)~(IN4) IN5 Engine where: ~=low; ^=rising edge; +=OR IN6 – The PME keeps polling these pins and generates IN7 an interrupt to the core when one or more of the bit slices match Both the pin interrupt and pattern match blocks are mutually exclusive

62 USART – Synchronous operations on all 3 UARTs – Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions – ROM drivers to configure USART – 7, 8, or 9 data bits and 1 or 2 stop bits – Multiprocessor/multi-drop (9-bit) mode with software address compare – Parity generation and checking: odd, even, or none – RTS/CTS for hardware signaling for automatic flow control – Fractional rate divider is shared among all USARTs – Built-in baud rate generator – Wake from sleep, deep-sleep, or power-down mode

63 I²C I2C operation can be routed to dedicated open-drain pins (by routing the functions using switch matrix), or any other pin Fast-mode Plus (up to 1Mbit/s) capability on the open-drain pins Not software compatible with I2C in other devices in the LPC portfolio Independent master, slave, and monitor functions Time-out register Wake-up from low power modes from I2C interrupt ROM drivers to configure I2C

64 I²C Wake-up The wake-up from power-down is illustrated in this scope trace See application note AN11332

SDA

SCL

CLKOUT

65 SPI Maximum data rate of 30 Mbit/s in master and 25 Mbit/s in slave Wake from sleep, deep-sleep, or power-down mode

Programmable pre and post delays:

Programmable frame delay:

66 Analog Comparator

Compares voltage levels on external pins and internal voltages 4 inputs are multiplexed separately to the positive voltage input and negative inputs The Internal voltage reference (0.9 V bandgap reference) can be used as either the positive or negative input of the comparator Voltage ladder source selectable between the supply pin VDD or VDDCMP pin 32 levels of Comparator reference voltage for fine grain comparison Edge and level Comparator output signals connected to State Configurable Timer (SCT) using the Switch matrix, allows for the recording of event comparison- “timestamps”

67 LPC800 Tools and Support

68 Emulation and debugging Debug and trace functions are integrated into the Cortex-M0+ Serial wire debug (SWD: 2 pins) Supports up to four breakpoints and two watchpoints Micro Trace Buffer (MTB) supported Standard JTAG pins (5 pins) supports ONLY boundary scan testing

69 Support

www.nxp.com/technicalsupport www.lpcware.com/forum www.lpcware.com/forums/lpcxpressoold/lpcxpresso- forum (Support forum for LPCXpresso supported by NXP and Code Red) www.nxp.com/lpcxpresso - Main page www.nxp.com/lpcxpresso-support - NXP examples page, schematics and FAQ www.nxp.com/lpczone - Live training modules

70 LPCOpen Platform

LPCOpen platform provides driver and software library for NXP Cortex devices Allows users to quickly and easily utilize NXP's extensive array of microcontroller software libraries to create and develop multifunctional products. Uses common APIs that work equally across all microcontroller families and can be built with Keil, IAR, and LPCXpresso (Eclipse-based tool from Code Red) tool chains. Detailed documentation and examples make it easy to integrate the necessary development tools into projects. http://www.lpcware.com/content/project/lpcopen-platform-nxp-lpc-

71 LPC800 Summary Redefining 32-bit migration Simplicity High performance at a low price point 2-10x higher performance than 8/16-bit MCUs 2-3x power saving compared to 8/16-bit MCUs 40-50% smaller code size than 8/16-bit MCUs Single cycle IO access Easy to use and flexible peripherals: SCT, Multi Rate Timer, Switch Matrix, USART, I2C, SPI

72 73