Brad Mccredie IBM Fellow, VP Power Development Revolutionizing the Datacenter

OpenPOWER and the Roadmap Ahead Brad McCredie IBM Fellow, VP Power Development Revolutionizing the Datacenter

Join the Conversation #OpenPOWERSummit Quarter Century of POWER 22nm Legacy of Leadership Innovation 45/32nm Driving Client Value

65nm POWER8

0.18um 0.25um 130/90nm POWER7/7+ 0.35um Business 0.5um RS64IV Sstar 180/130nm POWER6 0.5um RS64III Pulsar RS64II North Star 0.5um POWER5/5+ RS64I Apache 0.22um Cobra A10 Muskie POWER4/4+ A35 Modern UNIX Era 0.35um Workstation POWER3 -630 0.72um POWER2 P2SC

1.0um RSC 0.25um

POWER1 0.35um PC 0.6um 604e 603

Focus on Enterprise Focus on Scale-Out and Enterprise Future Technology and Performance Driven Cost and Acceleration Driven

Partner Chip POWER6 Architecture POWER7 Architecture POWER8 Architecture POWER9 Architecture POWER10 POWER8/9

2007 2008 2010 2012 2014 2016 2017 TBD 2018 - 20 2020+ POWER6 POWER6+ POWER7 POWER7+ POWER8 POWER8 P9 SO P9 SU P8/9 SO 2 cores 2 cores 8 cores 8 cores 12 cores w/ NVLink 24 cores TBD cores 10nm - 7nm 65nm 65nm+ 45nm 32nm 22nm 12 cores 14nm 14nm 22nm T New Micro- Enhanced New Micro- Enhanced New Micro- Enhanced New Micro- Enhanced Existing New Micro- Architecture Micro- Architecture Micro- Architecture Micro- Architecture Micro- B Micro- Architecture Architecture Architecture Architecture Architecture Architecture With NVLink Direct attach memory Buffered D New Process Enhanced New Process New Process New Process Memory Foundry New Technology Process Technology Technology Technology New Process Technology Technology Technology Technology

High Frequency Large eDRAM L3 Cache Optimized for Data-Centric Scale-Out Datacenter TCO OpenPOWER New Workloads Optimization Ecosystem Features and Design Enhanced RAS Optimized VSX Scale-up performance Functions Optimization Targeting Integrated PCIe Partner Markets Dynamic Energy Management Enhanced Memory Subsystem Acceleration Enhancements to & Systems CAPI Acceleration / I/O CAPI and NVLINK Leveraging Modularity for OpenPOWER Modulatrity

Price, performance, feature and ecosystem innovation

22nm SOI, eDRAM, 15 ML 650mm2 SMP

Cores Memory DMI Interface Memory • 12 cores / 8 threads per core Control • TDP: 130W and 190W • 64K data cache, 32K instruction cache Server Class Memories Accelerators (SCM) CAPI/PCI IBM & Partner • Crypto & memory expansion Devices • First Functioning Demo of SCM in an Enterprise system • Transactional Memory • 15x better than SSD • Natively non-volatile ST-MRAM DIMMs (Everspin) Caches • Avoids NVDIMM complications (DRAM to FLASH and back) • No Supercaps with umbilicals required • 512 KB SRAM L2 / core • 96 MB eDRAM shared L3 Coherent Accelerator Processor Interface Memory Subsystem (CAPI) • Memory buffers with 128MB Cache Virtual Addressing 6 Hardware Partners developing with CAPI • Accelerator can work with same memory • ~70ns latency to memory addresses that the processors use Over 20 CAPI Solutions • Pointers de-referenced same as the host • All listed here http://ibm.biz/powercapi Bus Interfaces application • Durable Memory attach Interface (DMI) • Removes OS & device driver overhead Examples of Available CAPI Solutions • Integrated PCIe Gen3 • IBM Data Engine for NoSQL Hardware Managed Cache Coherence • DRC Graphfind analytics • SMP Interconnect for up to 4 sockets • Enables the accelerator to participate in “Locks” • Erasure Code Acceleration for Hadoop as a normal thread • Lowers Latency over IO communication model

– Go faster with accelerators (optional) Sun May 1st: Submission periods opens 2. The Spark Rally Tue Aug 2nd: – Train an accelerated DNN and recognize Submission period closes objects with greater accuracy Grand prizes include a trip to – Show you can scale with Spark Supercomputing 2016 Other prizes include iPads, Apple Watches

22nm SOI, eDRAM, 15 ML 650mm2 SMP

NVLINK Memory Nvidia GPU DMI Interface Memory Control

CAPI/PCI IBM & Partner Devices

• NVLink High Speed CPU <-> GPU Interconnect • 160+ GigaBytes per second bi-directional • 5-12x faster than PCIe Gen3 x16

• Nvlink Accelerator Lab Zoom accellab@us.ibm.com Minsky NVLink POWER Systems

24 newly designed POWER9 cores Leadership platforms for hardware acceleration • Leveraging execution slices for improved performance on • High bandwidth, GPU interconnect (NV link2.0) cognitive, analytic, and big-data applications • Next-generation CAPI2.0 interface for coherent accelerator and storage attach • On-chip compression & cryptography accelerators Large, low-latency, eDRAM cache for big datasets • New 25Gb/s advanced accelerator attach bus

Global Foundries 14HP finFET technology with eDRAM 1st chip in POWER9 family • Optimized for 2 socket scale out servers & hyperscale datacenters Cloud-focused innovation in Energy Efficiency, Security, • DDR4 direct attach memory channels and Quality of Service Full POWER9 family will address a broad range of scale out & enterprise State-of-the-art IO subsystem using PCIe Gen4 servers 7 © 2016 IBM Corporation POWER Processor Roadmap

Denser Roadmap Not tied to technology More teams developing

Performance and cost/performance leadership

Leadership accelerator attach technologies including GPUs Advanced Storage Advanced Networking FPGAs

Expanded focus includes Enterprise and Hyperscale datacenters