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The future of packaging with By Deborah Patterson [Patterson Group]; Isabel De Sousa, Louis-Marie Achard [IBM Canada, Ltd.]

t has been almost a decade have traditionally been center design. Besides upgrading optical since the introduction of employed to transmit data over long cabling, links and other interconnections, I the iPhone, a device that so distances because can carry the legacy data center, comprised of many successfully blended sleek hardware considerably more information off-the-shelf components, is in the process with an intuitive user interface that it content (bits) at faster speeds. Optical of a complete overhaul that is leading to effectively jump-started a global shift in transmission becomes more energy significant growth and change in how the way we now communicate, socialize, efficient as compared to electronic transmit, receive, and switching functions manage our lives and fundamentally alternatives when the transmission are handled, especially in terms of next- interact. Today, smartphones and countless length and bandwidth increase. As the generation Ethernet speeds. In addition, other devices allow us to capture, create need for higher data transfer speeds at as 5G ramps, high-speed interconnect and communicate enormous amounts of greater baud rate and lower power levels between data centers and small cells will content. The explosion in data, storage intensifies, the trend is for optics to also come into play. These roadmaps and information distribution is driving move closer to the die. Optoelectronic will fuel multi-fiber -to-chip extraordinary growth in traffic interconnect is now being designed interconnect solutions, development, and cloud services. The sidebar entitled, to interface directly to the processor, and the application of advanced multi-chip “Trends driving data center growth,” application specific packaging within the segment. provides an appreciation for the incredible (ASIC) or field programmable gate The high-end or “Hyperscale” data center increase in data generation and its array (FPGA) to support switching, is massive in both size and scalability. It continued growth through 2020. transceiver, signal conditioning, provides a single compute architecture To process and manage the unabated and multiplexer/ growth in data traffic, demultiplexer (Mux/ will be used to define new data center Demux) applications. architectures. This article discusses the Figure 1 shows a impact that silicon photonics will have on forecast for silicon data center technology trends, and on the photonics adoption next-generation microelectronic packaging through 2025 with data developments that address optical-to- centers dominating electrical interconnection as and initial growth. Silicon electron conversion moves to the level of the photonics are also being package and microelectronic (logic) chip. developed to support applications as diverse Data center dynamics as high-performance The large-scale restructuring of data and optical centers is one of the most dynamic . transformations taking place in information The data center Figure 1: Silicon photonics growth rates will initially be dominated by technology. The need to re-architect the need for speed and applications within the data center. SOURCE: Yole Développement, Oct. 2016 data center is being propelled by the capacity. Figure 2 staggering surge in shared and stored illustrates forecasted data along with an increasing demand data center traffic by to effectively interpret the tremendous 2019. One of the more amounts of content being generated. In notable trends is that addition to the huge growth in data traffic, almost three-quarters the infrastructure supporting the Internet of all data center traffic of Everything (IoE) will emphasize real- will originate from time responsiveness between people and/or within the data center. objects. The next wave in data processing The recognition of this and data traffic management will require statistic, compounded the ability to support cloud computing, by the enormous increase in data traffic, cognitive computing and big data analysis Figure 2: Data center traffic and bit rates show remarkable growth. The vast along with the necessary speed and has significantly altered majority of data center traffic will reside within the data center. SOURCE: Cisco capacity to deliver a timely response. the approach to data Global Cloud Index, 2014–2019

Chip Scale Review January • February • 2017 [ChipScaleReview.com] 1 made up of small individual servers and Data centers are being “disaggregated” interest. This is because data center peripheral functions such as memory, so that compute, storage, memory, architecture is undergoing a fundamental power management, and networking, all networking and power conditioning/ shift away from traditional three-tiered woven together through layers of redundant distribution can be reorganized and designs to route information. Power systems. Hyperscale data centers are redistributed systemically. Signal routing consumption and latency have increased represented by companies such as Amazon, efficiencies, better thermal management, as data traffic volumes have surged. This is Microsoft, Google, and Web 2.0 companies and densification of connections due to too many “hops” or handoffs when like Facebook. They can house over a brought forth by well-designed package routing data between source and destination hundred thousand to a million servers. integration is expected to improve system (controlled by routers and switches). “Leaf- Conversely, alternative data center upgradability, flexibility, and reliability spine” network architecture is replacing architectures are also under consideration. while lowering cost. Silicon photonics will the older tiered approach. The leaf-spine An example is the build-out of many be especially useful in enabling the high network is controlled by ASIC switches. small data centers linked together through communication bandwidth requirements of A “leaf” is typically the top-of-rack heterogeneous networks. No matter which disaggregated systems. (ToR) switch that links to all servers approach, moving the enormous volume Transceivers represent the initial high- within a common tower or rack (shown of data within and between data centers volume application for silicon photonics in Figure 3). The next layer of switches will continue to require increased speed as optics migrate as close as possible to is represented by the “spine.” The spine and bandwidth with lower latencies the origin of the data. Outside the data is a higher capacity switch (40 or 100 and greater power efficiencies. Silicon center, optical transceivers are used in gigabyte per link) that connects to leaf photonics is positioned to address these transport, enterprise, carrier routing and switches (across the server racks), to fundamental conditions. switching markets. Within the data center, other spine switches, and to the next level Servers will be reconfigured to transceivers are located with each server. of “Core” switches. This is known as a support higher speeds along with new However, they are mounted at the edge “flat architecture” and it is implemented componentry at 10 gigabit Ethernet (GbE), of the board, resulting in large distances through high-capacity ASIC switches. 25, 40, 100 and 400GbE. Meanwhile, new between the optical components and the The largest ASICs currently offer 32 x standards such as 1TbE will eventually processor chip. The IBM research team 100GbE ports. ASIC switch capacity and be introduced. Figure 3 illustrates typical in Yorktown, NY has proposed advanced port count dictate the size of the leaf-spine data center connections, nomenclature, packaging designs where the silicon network, e.g., the number of servers that Ethernet speeds and link distances. photonic die can be integrated directly into can be linked together. Higher speed ports Because each data center server the processor module, bypassing today’s drive lower bandwidth costs per Gb/s and generation lasts 3-5 years and the standard transceiver housings. Integrating higher capacity switches drive the total infrastructure (buildings) typically lasts the transceiver functions within the silicon number of links (minimizing the number 3-5 generations, the technology choices photonic die or processor module is an area of data hops, associated latency, and incorporated now will become the of concentrated activity. power consumption). legacy infrastructure over the next 10- Ethernet switches, on the other hand, In addition to the electrical domain 25 years. Therefore, determining which currently rely on electronic interconnect but switching described above, there is technologies deliver maximum flexibility, are another targeted area of silicon photonic significant interest in on-chip switching capacity and reduction in total system cost-of-ownership is non-trivial and leading-edge development emphasizing concurrent and package design is receiving greater visibility.

Optoelectronic integration of transceivers and switches Because optics can transport more data at significantly lower power than electronic transmission, the intent is to drive optoelectronic conversion as close to the chip and microelectronic packaging level as possible. The data remains in optical form – leveraging high optical densities – until it enters the package and interfaces with the silicon photonic die. At this point, the data is converted from photonic to electronic format to undergo computation, storage, redirection, etc., by conventional logic ICs. Running electrical and optical Figure 3: Illustration showing data center connections. The shorter server-to-server connections within the pathways side-by-side on a micrometer server rack typically require <5m (green) of routing, longer connections between the server racks may require up scale is the eventual objective. to 500m (orange), and long span connections within a building or between buildings can measure up to 2km (blue). SOURCE: Image courtesy of Finisar, Patterson Group, IBM, Ethernet Alliance

2 Chip Scale Review January • February • 2017 [ChipScaleReview.com] Trends driving data center growth

The following information is taken from data and things, may drive data center and opening the door to interacting in real-time the 2015 Cisco Global Cloud Index [1] and cloud traffic growth to over 500ZB annually with your environment and people in ways the Cisco Visual Networking Index: Global by 2019 - almost 50 times that of data center that are only just being imagined. Mobile Data Traffic Forecast [2] to provide traffic alone (10.4ZB). It is assumed that IoE Figure S1-2 highlight a few examples of the reader with an appreciation of what is content and applications will increasingly the huge increases in devices, their impact driving today’s explosion in data traffic. be stored, managed and propagated through on overall Internet and data center traffic and The growth in mobile users has had a the data center, along with a substantial speeds, and the almost four-fold increase phenomenal impact on data traffic. The increase in big data analytics that will in cloud management over the current five- average smartphone user in 2015 consumed continue to mature into indispensable tools year period. Although the forecast start dates more data in less than a minute than a mobile of strategic and tactical decision making. vary from 2014-2016, the story remains user in 2000 did in an entire month [3]. Future 5G build-out will drive speed and consistent. Between the growth of wireless Mobile video, which represented 55% of data capacity requirements closer to the user with and mobile traffic (which will account for traffic in 2015, is projected to grow to 75% significant reduction in latency (>100x faster two-thirds of total IP traffic by 2020), social by 2020. The video forecast becomes even than 3G and roughly twice as fast as 4G), media activity, the progression of video more significant when one realizes that the bit volumes and densities, the ramp rates required for streaming high-definition of imaging such as embedded and ultra-high definition (4K) video are 2x vision, virtual/augmented/mixed and 9x faster than standard definition video, reality and 3D video, the continued further driving the need for both capacity migration to cloud storage, the and speed. And this does not even include propagation of sensors feeding game changers such as virtual, augmented the Internet of Everything, and the and mixed reality technologies. In addition to evolution of big data analytics and the changes in volume and density of video cognitive computing, it is clear that content, there will be a massive migration of the need for speed and capacity stored data to the cloud. Today, almost three- growth will continue unabated for quarters of stored data on client devices still a long time to come. reside on PCs with integrated hard drives. The expectation is that a majority (51%) of References stored data will be associated with non-PC 1. Cisco Global Cloud devices with always-on wireless connectivity Index, “Cisco Global Cloud and no hard drives, propelling consumer Index projects cloud traffic cloud storage requirements to 1.6GB per to quadruple by 2019,” Oct. month by 2019. Cloud users will store data Figure S1-1: Chart illustrating the concept of 10.4ZB. SOURCE: 28, 2015; https://newsroom. (which is archival and may or may not require Cisco Global Cloud Index, 2014–2019 cisco.com/press-release- bandwidth) and will pull/push data from/to content?articleId=1724918 the cloud (which requires bandwidth). 2. Cisco Visual Data centers manage both cloud traffic Networking Index (VNI), and data center traffic. Cloud computing “The zettabyte era – trends represents a subset of all data center traffic and analysis;” http://www. that exists within and between data centers cisco.com/c/en/us/solutions/ and end users. Cisco’s Global Cloud Index collateral/service-provider/ forecasts global cloud traffic to quadruple visual-networking-index-vni/ between 2014 and the end of 2019, from vni-hyperconnectivity-wp.html 2.1 to 8.6 zettabytes (ZB). Global data 3. K. Patel, “Cisco visual center traffic is projected to grow from 3.4 networking index global data to 10.4ZB (where a zettabyte is equal to a traffic forecast, 2015-2020,” trillion gigabytes). Figure S1-1 illustrates the SEMICON West, San Francisco, concept of 10.4ZB. CA, July 12-14, 2016; http:// The global forecast of devices and www.cisco.com/c/en/us/ connections track to a 10% CAGR. In solutions/collateral/service- comparison, they outpace the CAGRs of the provider/visual-networking- global population (1.1%) and the Internet index-vni/mobile-white- user rate (6.5%). But that’s not all. The paper-c11-520862.html Figure S1-2: Connected devices and their impact on cloud and Internet of Everything (IoE), described by data center traffic. SOURCE: Data courtesy of Cisco GCI, VNI and IoT Cisco as the connection of people, processes, White Papers

Chip Scale Review January • February • 2017 [ChipScaleReview.com] 3 of the full optical content of fibers without conversion into the electrical domain. Such a fiber optic switching matrix can route tens to hundreds of fibers in, acting as a hub to transmit high- bandwidth optical data while working in tandem with its electronic counterpart.

Advanced packaging with silicon photonic die In today’s data centers, pre-packaged transceivers and other optical modules include discrete, large-pitch components. These traditional “gold boxes” and off- the-shelf components are too expensive for downstream data center proliferation; Figure 4: Silicon photonic MCM illustrating (clockwise) a) a photonic integrated circuit (PIC) with flip-chip however, adoption of silicon photonics mounted laser die and edge-coupled waveguide; b) logic, HMC and PIC mounted directly to a BGA substrate; c) has the promise of meeting aggressive logic and HBM mounted on a high-density interposer with copper pillar micro-bumps that enable high-speed price targets. Price targets at 100GbE are connectivity; d) cut-away revealing copper pillar, flip-chip, BGA and optoelectronic interconnections. SOURCE: found between $1-$5 per gigabit for single- Image courtesy of IBM Corporation mode fiber as compared to $2 per gigabit assembly and test service (SATS) provider to integrate silicon photonic (also known for multi-mode fiber [1]. It is generally and the optics contract manufacturer. as “nanophotonic”) digital and analog recognized, however, that $1-$2 per gigabit The core competencies of the SATS and componentry within an optoelectronic for single-mode fiber is necessary in order fiber optic assembler are quite different package. These modules often require high- to achieve widespread impact in datacom and typically do not overlap. The SATS density interconnect and a combination of (for example, through the enablement of provider specializes in the assembly and advanced packaging techniques. new architectures). It is also understood test of the electrical (digital and analog) Figure 4a shows a next-generation that silicon photonics and its packaging ICs, passive components and electrical silicon photonic die designed to will need to leverage the know-how, best interconnect at the substrate or interposer accommodate a waveguide array that will practices, and massive level, whereas the optics contract transport the into the die where scalability developed for high-volume manufacturer specializes in interconnecting efficient coupling can take place. The die CMOS manufacturing and microelectronic the photonic IC (PIC) to the optical fibers. also contains an array of flip-chip bumps to assembly. This will bring down cost enough The optics contract manufacturer manages support electrical signals. In this illustration, to fuel high-volume integration, which in fiber and laser alignment at sub-micron laser die are attached to the silicon photonic turn, will contribute to driving costs down levels and also provides specialized optical chip through self-aligning flip-chip bumps along traditional semiconductor growth testing at the package and die level. The that provide a low profile and closely and cost trajectories. Silicon photonics end customer/OEM must therefore oversee coupled chip-to-laser interconnection. is projected to offer cost-efficient optical two separate assembly and test process can also be accommodated off-chip interconnects (I/Os), allow for a reduction in flows as well as define the build and test through flip-chip or wire bond attachment. components, and reduce assembly and test plans. It is no surprise that assembly and Figure 4b shows a ball grid array (BGA) steps to decrease manufacturing costs while test strategies may include “known good” substrate with a central logic die such as an increasing throughput. multi-chip platforms designed within the ASIC, two hybrid memory cubes (HMC) Currently, assembly, test, fiber and laser optoelectronic module. and associated CMOS devices. A typical connections – everything except for the Optoelectronic multi-chip modules HMC is represented by a packaged 4-8 silicon chip(s) – are adding prohibitive cost (MCMs) can contain processors, ASICs, die DRAM stack supported by a controller and slowing down deployment. Much of this FPGAs, memory, passive components chip and using 3D TSVs for vertical chip- is due to low-volume fiber-to-die assembly and other functional elements plus the to-chip connectivity. The packaged HMC practices and the impact on overall test and PIC. Certain operations can be integrated has a standard BGA pitch (e.g., 650µm) manufacturing flows. In order for the cost of on the photonic chip [2] while others will and is mounted on the substrate along silicon photonic assembly and test to meet be combined in-package (MCM/SiP). with the other components and PIC. These end-product, design-for-manufacturing cost Logic and optical functions can include modules use flip-chip and/or wire bonding targets, clever and disruptive packaging transmitters, receivers, multiplexers/ for I/O interconnection. approaches that also address the optical I/O demultiplexers, modulators, splitters, An alternative design is illustrated in (fiber- or waveguide-to-die) and laser-to-die , resonators, optical Figures 4c and 4d. In this case, the logic interconnections are required. isolators and polarization controls. Non- die and high-bandwidth memory (HBM) optical CMOS , drivers, or stacks are mounted directly onto a high- A tale of two supply chains serializer/deserializer (SerDes) functions density interposer to closely link the logic, When assembling a silicon photonic may also be located within the module. memory and PIC. It is desirable to have package, two specialized providers are Figure 4 illustrates various advanced the PIC closely coupled to the logic die typically employed: the semiconductor packaging technologies that can be used using either approach (b or c) to promote

4 Chip Scale Review January • February • 2017 [ChipScaleReview.com] power efficiencies. The interposer can be photonic die design, b) parallel waveguide integrated with industry-standard CMOS inorganic (Si) or it can be a high-density interconnect technology, c) chip-to- design tools. The die contains modulators, organic laminate material. When used as waveguide (fiber) assembly processes, d) photodetectors, and ultra- an interposer, these organic high-density overall thermal management, and e) final compact division multiplexers interconnect (HDI) materials are sometimes integration between the logic components (WDM). Figure 5b shows the die with referred to as “2.1D” to differentiate them and photonic IC using various assembly an array of 100µm Pb-free flip-chip from 2.5D silicon interposer structures. HDI techniques. The build strategy will depend bumps on a 200µm pitch. The flip-chip substrates support dense wireability and flip- on the type of advanced packaging interconnects keep electrical I/O loss chip interconnect at a lower cost than silicon employed (and at what level higher density to a minimum. Figure 5c identifies the interposers because they are not manufactured flows are designed into the module), the transmitter and receiver elements along in the foundry. With multiple layers, 10µm test complexity, yields for both the optical with their eye diagrams, showing a clean, vias, and 2/2µm or 3/3µm line and space and electrical process flows, and overall high-quality response. routability, HDI materials can present a cost- cost tradeoffs. A provider that offers In this design (Figure 5), the lasers are effective alternative to 2.5D approaches. assembly of the electrical/thermal elements manufactured separately and connected off- In the case of HBM, where a 55µm bump plus integration of next-generation chip- chip with the optical signals coming into pitch is used, HDI material presents a viable to-fiber interconnects would be a welcome the die through the top four laser ports. The option. Populated interposers can also be addition to the packaging landscape. chip contains four receive and four transmit tested before assembly with the PIC and channels, each capable of transmitting data BGA substrate. Substrates and/or interposers Demonstrating silicon photonic at 25Gb/s via independent . may also contain embedded components, “firsts” The four carrier signals (λ) are bundled into low-loss integrated , or embedded IBM has been developing CMOS 100Gb/s fiber ports through wavelength fiber connectivity. integrated silicon photonic die and multiplexing. An extension of this design These complex modules are often packaging approaches for close to fifteen would allow for up to twelve such fiber ports larger in area, integrate many material years. Figure 5a shows a photograph when using a standard 12-fiber connector, types, and must address significant of the first CMOS integrated coarse thereby enabling 600Gb/s bi-directional thermal dissipation and signal integrity wavelength multiplexed silicon photonics data rates from a single optical transceiver. considerations. Packaging know-how chip. This silicon photonics reference The intention of the program was to push must not be underestimated and deep design, demonstrated in 2015, is 100Gb/s data speeds over a range of up to 2 experience in electrical and thermal capable of transmitting and receiving 4 kilometers (1.24 miles) as required by large modeling, materials characterization, wavelength channels – each operating at data center environments [4]. component choice, vetted design rules, 25Gb/s. The chip combines both mixed Note that the die in Figure 5 comprehensive test, and design for signal electronic circuits and optical is designed with only two optical manufacture is essential. In addition, capability on a single die. The die was I/Os representing a single input fiber providers need to address package-level manufactured through the former IBM and output fiber. Currently, duplex reliability testing in consideration of the Division, now a part fiber connections represent the lowest photonic components, including features of GLOBALFOUNDRIES, whose cost and most widely used approach. such as fiber strain relief [3]. monolithically integrated silicon photonics One fiber in and one out have been Signal integrity and thermal dissipation technology (called CMOS9WG) was sufficient to support current bandwidth pathways are crucial. For example, to used. It is derived from their 90nm needs. Because of the low I/O count, support SerDes operation at 28GHz, the CMOS process, a mature technology node active optical alignment is often silicon photonic die and SerDes interface that can facilitate commercialization. employed and involves assembly – integrated into the logic die and placed The design was simulated and fully in a manual or partially automated in close proximity to the PIC – must be verified with a process design kit (PDK) fashion using specialized tooling. The optimized. The optical elements need to be calibrated and balanced against the electrical interface as well. Optical systems reduce/eliminate the need for signal conditioning and amplification steps that would be required for systems with long electrical traces. It is also important to mitigate hot spots on the ICs and the thermal drift that some optical components experience. Silicon photonics programs at their most effective are designed with a system- level integration mindset. Therefore, concurrent package design for the PIC and the electrical and thermal elements within the module are considered together. Figure 5: An IBM silicon (nanophotonic) wavelength division multiplexed 4 x 25Gb/s reference design (die) Development must include a) silicon supporting both electrical and optical circuits. Two optical I/Os are seen at the bottom of the die. These connect to optical fibers, one in and one out. SOURCE: Images courtesy of IBM Corporation

Chip Scale Review January • February • 2017 [ChipScaleReview.com] 5 result is a lower throughput, limited scalability, and higher cost process as compared to electrical interconnect and manufacturing operations. Delivering chip-to-fiber assembly know- how to the semiconductor market is a crucial differentiator required to feed turn- key optoelectronic assembly solutions. IBM’s silicon photonics program embraces a disruptive approach that leverages existing high-throughput microelectronic tools and techniques to assemble cost- efficient and scalable single-mode optical inputs and outputs that can be deployed in high volume.

Multi-waveguide to chip interconnect To keep up with data traffic growth, Figure 6: a) Data centers remain a dynamic multi-billion dollar market feeding a progression of high- speed data rates. both software and hardware strategies are SOURCE: Data Center Optics, Discerning Analytics presentation, OSA Industry Development Association, OFC May 2016. utilized. Among these are the migration from the duplex fiber connections described 400GbE bit rates are now being [7]) must be met to justify mass adoption. in the previous section to multi-fiber or standardized for 2018 introduction and Therefore, practical, high-volume chip-to- multi-waveguide interconnects (ideally it’s not just for long haul distances. It fiber assembly techniques are an area of leveraging industry standard 12-fiber will also be used at distances below current concentration. connectors). The following sections identify 100 meters to manage intra- and Bridging legacy infrastructure with data rate trends, techniques and trade-offs inter-rack data traffic. The sidebar next-generation . The 12x1 utilized to support these trends, a 12-fiber entitled, “Techniques to extend data mechanical transfer (MT) interface is a interconnection approach demonstrating rates,” describes various ways to mix single-mode fiber standard that has been the feasibility of automating fiber-to-chip and match technologies using next- handed down from the telecom industry. assembly, and a next-generation multi- generation 400Gb/s Ethernet as an Single-mode fiber has been employed waveguide structure created example. The number of data lanes because of its high efficiency in guiding through lithographic patterning for high- (fibers) into and out of the die depends light over long distances with very low throughput assembly. on the application. A single one in/ loss. Single-mode fiber is preferred over Riding the wave of data rate one out port count is used today for multi-mode fiber and is becoming a de progression. In order to carry greater fiber links in excess of 500 meters facto standard within several areas of amounts of optical data, the optical port while up to eight (4 transmit/4 receive) next-generation data center designs. density and optical bandwidth per port must fiber connections are used for 100-500 An automated, self-aligned 12-fiber increase, along with higher manufacturing meter core applications such as Parallel connection to a silicon photonic die is throughput and scalability. Technology Single Mode 4 (PSM-4) in support of examined below. The program leverages development to intercept downstream 100Gb/s (standard) and 400Gb/s Ethernet semiconductor assembly, tools, and requirements is being pursued now. The bit (proposed) [5]. Emerging applications process flow experience. The 12 optical rates (speeds) are trending as follows: such as communication hubs and on- I/O solution is attractive because of the chip fiber switches [6] can require port vast deployment of 12-fiber connectors, • Within the server rack (intra-rack): counts of tens of fibers per chip. 2016 making it the lowest cost for parallel 10GbE → 25GbE → 40GbE → saw a significant shift toward 100GbE optical connections per fiber port. This 100GbE → 400GbE (finalizing components. The development and type of connector is used in PSM-4 standardization); introduction of complex packaging and transceivers for 100Gb/s and is planned • Between server racks (inter-rack): optical interconnects to lower 100GbE for 400Gb/s and beyond. Multiple 40GbE → 100GbE → 400GbE costs and support next-generation 12-fiber connectors are anticipated (finalizing standardization); and 400GbE is timely. to fulfill the optical I/O needs of • Within the data center or between Adding more chip-to-fiber connections communication hubs and on-chip fiber buildings (inter-data center or “long can substantially expand bandwidth switches. Multiple wavelengths may be haul”): 100GbE → 400GbE → and capacity by providing a platform used in each fiber for CWDM, creating 1TbE/1.6TbE (standardization remains upon which the techniques listed in a large requirement on both the optical to be determined). Table S2-1 (sidebar) can be deployed. bandwidth per fiber connection as well as This leap in data will carry forward for the number of fiber connections. Figure 6 highlights the unabated rise several generations to support 100GbE → Figure 7a shows a 12 I/O silicon in data center revenue as broken down by 400GbE → 1TbE+ roadmap progression. photonics demonstration die with a data rate through 100GbE. Aggressive cost goals (<$1 per attachment flip-chip array providing the electrical

6 Chip Scale Review January • February • 2017 [ChipScaleReview.com] Techniques to extend data rates

Data centers have historically been built ultra-fast 400GbE infrastructure upgrades. using off-the-shelf components. As data The general trend is that sophisticated center hardware matured, architecture techniques such as PAM-4 , evolved to take advantage of technology single-mode fiber (SMF) and wavelength improvements at a measured pace. However, multiplexing are becoming the de facto the unprecedented data explosion has standard at shorter and shorter distances. For accelerated data center redesign and is example, in the data center environment, reshaping many technology roadmaps that SMF has traditionally carried signals over support this segment. long distances such as 500 meters (inter-rack) To ensure higher bandwidth and rapid to 2km (intra-data center) to 10+km (between data delivery across the electrical interface, data centers). SMF is now employed at four general approaches are considered 100 meters and is migrating to distances when evaluating system-level trades-offs as short as 20 meters in order to provide such as overall efficiency, cost, and return downstream flexibility for data center on investment. These are speed (increasing upgrades. In fact, Microsoft announced that symbols [1] per second or baud rate), it will employ SMF at distances of 20 meters modulation, lane count (number of fibers), and greater. This is an evolutionary departure and transmission technology (often distance from traditional multi-mode fiber (MMF) dependent). The divergent needs of each end interconnection that supports today’s vertical application guarantee that architecture will cavity surface emitting lasers (VCSEL). remain flexible. A granular segmentation Trade-offs such as fiber cost become in the Ethernet switch market, for example, a more dominant factor as the number of will provide the data center with customized links needed at shorter distance increases. options it lacked in the past. Table S2-1 Fiber can cost as much as $200-$300 for describes various ways to mix and match large switches. Because there are so many technologies in support of next-generation more short links (eg., transceivers, switches) 400GbE data rates. incorporated into data centers, the overall

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Table S2-1: Rising data rates leverage current infrastructure while providing a platform for new technology.

The techniques listed in Table S2-1 will capacity cost of fiber becomes significant allow for considerable variation. This is and its rollout will, therefore, be planned necessary because legacy technology at to include subsequent upgrade costs as speeds ≤10GbE still represent a significant data center design continues to respond to portion of data center infrastructure. In increased capacity demands. addition, new usage models in certain IoT/ IoE, industrial and automotive segments will Reference leverage slower speeds. This said, there is 1. Data is sent in “symbols” where a much excitement and focus on facilitating symbol represents a specific state of faster data speeds. The IEEE Ethernet frequency, amplitude and phase. A Task Force passed new Ethernet standards symbol can be single or multiple bits for 25GbE and 400GbE with 50GbE of data. In digital communications, and 200GbE under consideration. These the symbol rate is also known as the multiples will feed today’s 100GbE and baud rate.

Chip Scale Review January • February • 2017 [ChipScaleReview.com] 7 two polarizations of light present in the fiber need to be considered. Finally, they emit light almost vertically from the plane of the chip, which complicates or even negates flip-chip electrical connection and impacts thermal management strategies. With these considerations, in-plane coupling techniques and adiabatic mode converters were pursued instead. These are inherently tolerant to fabrication imperfections, polarization of light and spectral bandwidth. Two major challenges to mating single- mode optical fibers to silicon photonic waveguides are alignment accuracy and fiber mode conversion [8]:

1. Alignment tolerances between the (s) and waveguide couplers embedded within the silicon photonic die should not exceed 1-2µm Figure 7: a) IBM silicon photonic die; b) schematic representations of the parallelized fiber and c) compliant on-chip for acceptable coupling polymer ribbon assemblies; d) an industry standard 12x1 single-mode fiber connector; e) photos of the efficiency. (For comparison, ±10µm parallelized fiber and compliant polymer structures. SOURCE: Images courtesy of IBM Corporation placement accuracy is suitable for solder bumps used for electric connections. The die supports two or other chip-package interactions can be connections.) next-generation photonic-to-electronic an issue). 2. There is a large mismatch in energy interconnect approaches: twelve fiber Both approaches offer flip-chip or wire confinement between an optical fiber inputs or “V-grooves” can be seen on bond electrical connections and support and a silicon photonic waveguide. the top area of the die (green) and finer direct, self-aligning InP laser attach to The energy is distributed over a waveguide inputs are clustered on the the silicon photonic die. The technology ~10µm spot in the fiber while it forms bottom center of the die (blue). The direction depends upon the application. a sub-micron spot in a typical silicon V-groove represents the physical structure The parallelized fiber approach employs photonic waveguide. This creates where the light is “butt coupled” – that is, standard components with known reliability the equivalent of a large impedance where the fibers terminate into on-chip and excellent optical fiber transparency. mismatch that must be addressed with optical mode converters. The compliant polymer ribbon shows much a suitable optical mode converter, The finer waveguide inputs correspond to promise in terms of structural reliability, is which is analogous to an impedance adiabatic optical coupling from a polymer reflowable, and is compatible with high- matching circuit. waveguide interface to the chip. volume manufacturing to support more and The first approach is called the varied waveguide pathways. Figure 7d Precise self-alignment features are “parallelized fiber assembly” because a shows an industry standard 12x1 single- crucial to maximizing assembly tolerances fiber optic ribbon emerging from the MT mode fiber connector that would attach to and must be designed into any automated interface (also referred to as a “ferrule”) the other end of the MT fiber interface and photonic assembly process that seeks to is assembled at once to a photonic chip; Figure 6e shows the physical assemblies utilize standard electronic manufacturing this is depicted in Figure 7b. The design with 12x1 arrays of optical I/Os. equipment. Self-alignment structures are was specifically developed to utilize high- Automating optical microelectronic designed within the silicon photonic die volume pick-and-place equipment (vacuum assembly. CMOS logic and optical and optical components (ferrule) to meet pick-tip) that can handle the fiber stub. transmit and receive functions need to the 1-2µm on-chip photonic alignment The second approach illustrated in be closely integrated. Many of today’s requirement. Self-alignment techniques must Figure 7c employs a “compliant polymer” chip-to-fiber attachments use vertical also work within the speeds and tolerance interface. In this design, a polymer ribbon diffractive grating couplers as they are limitations of today’s production equipment. with lithographically defined waveguides typically the easiest coupling scheme to Pick-and-place handling of fiber and self-alignment structures acts as an integrate on a . These are defined by components in a microelectronic intermediary between the chip and the the active alignment of fiber(s) that attach manufacturing process is particularly standard fiber connector. The polymer at a semi-vertical angle to the face of the challenging. Not only are optical fibers ribbon contains finely spaced embedded photonic die. However, diffractive grating typically handled with specialized tools waveguides that align to both the ferrule couplers suffer from limited spectral instead of standard vacuum pick-tips, but the and die. The design results in improved bandwidth, which is generally insufficient placement accuracy of standard equipment thermo-mechanical reliability as compared for CWDM applications. In addition, is normally on the order of ±10µm (almost to rigid connections such as the direct fiber- they exhibit unattractive coupling an order of magnitude larger than single- to-chip attachment (where fiber pistoning efficiency from fiber-to-chip where the

8 Chip Scale Review January • February • 2017 [ChipScaleReview.com] mode optics requirements). In addition, high-speed pick-and-place equipment does not offer the 3D spatial movement required for chip-to-fiber alignment. Equipment is designed to engage the die in-plane. Pressure sensitive movement is only possible in the downward direction after lateral positioning. This means, for example, that you can pick up a parallelized fiber array and lay it down in the V-grooves of the photonic die, but not be able to push the fiber array inward to butt into the waveguide coupler. To counteract this limitation in movement, a platform was designed to transfer a portion of the vertical pick-and-place movement into a horizontal force that successfully butts each fiber termination within the V-groove of its on-chip waveguide coupler [9,10]. The self-alignment features designed Figure 8: Demonstration of self-alignment of parallelized fiber assembly: a) trigonometric transfer of vertical into the components and adaptive tooling to horizontal force, pushing the die forward to mate with the fibers; b) top down photograph of a 12-fiber ribbon demonstrated that high-throughput pick-and- array attached to a silicon photonic die; c) cross-sectional micrograph showing a close-up of three fibers settled place equipment could be applied to photonic into their corresponding V-grooves within the die; d) Monte Carlo analysis demonstrates manufacturability of fiber fiber assembly, paving the way for large-scale self-alignment with a 3σ misalignment below ±1.3µm. SOURCE: Images courtesy of IBM Corporation automation and scalability in complexity, yield and manufacturing volume. The graphic progression in Figure 8a shows how vertical force from the pick- and-place equipment is converted to the horizontal force needed to slide the fibers properly into the die. Figure 8b shows a 12-fiber planar array assembled onto the silicon photonic die with self-alignment providing ~1µm on-chip final alignment accuracy. Figure 8c demonstrates how well the fibers fit into the V-grooves on the silicon photonic chip. Figure 8d computes the fiber core-to-waveguide coupler misalignment for 10,000 random Figure 9: a) Top down view of compliant polymer ribbon aligned with ferrule (no lid) and silicon photonic die; b) structural tolerance combinations to ferrule with self-alignment guides for polymer ribbon; c) exploded view of assembly showing two-piece molded demonstrate the manufacturability of the ferrule; d) cross section of polymer ribbon aligned to grooves in the molded ferrule. SOURCE: Images courtesy of IBM Corporation fiber self-alignment. The results show a 3σ misalignment below ±1.3µm demonstrating • Cycling strains within the package define self-alignment structures tolerances well within required placement are separated from the die by the or create other features of interest accuracies [11]. compliancy of the polymer material, such as pitch conversions, bent die Compliant polymer ribbon: an improving long-term reliability. interfaces or port shuffles. elegant approach. Another waveguide- • The material and design supports to-chip interconnect method is currently large optical bandwidth. As compared Figure 9a illustrates a 12-waveguide under development. In this approach, to diffractive couplers where a 1dB array, although the number of patterned a flexible polymer ribbon replaces bandwidth of a two-polarization waveguides can vary. At the fiber the cleaved fiber array. The design vertical coupler has been reported connector side, the waveguide spacing mechanically decouples the chip’s optical at ~30nm [13], the polymer ribbon is designed at a 250µm standard fiber interface from the fiber connector by demonstrated a 0.8dB penalty connector pitch and tapers down to a substituting a mechanically compliant over a 100nm bandwidth and all 50µm pitch at the photonic chip interface. polymer ribbon. The ribbon contains polarizations [14]. The polymer waveguide is 8µm wide at an array of mechanical self-alignment • Integrated waveguides are the chip interface where it mates with structures and polymer waveguides that lithographically patterned within the silicon waveguide tapers. As in the transmit light from the fiber to the die. a three-layer polymer stack. parallelized fiber approach, the far end This offers several advantages over other Lithography provides for significant of the polymer interface is compatible known approaches [12]: flexibility in design to optimize with a standard 12x1 MT fiber interface. optical mode conversion efficiencies, At the MT fiber connection point, a

Chip Scale Review January • February • 2017 [ChipScaleReview.com] 9 custom molded U-shaped ferrule (Figure a CMOS-compatible process, adopting 9. T. Barwicz, et al., “Photonic 9b) is used to allow for the alignment the microelectronics industry’s high- packaging in high-throughput and connection to standard metal pins. volume manufacturing processes and best microelectronics assembly lines Ferrule-to-polymer self-alignment practices is realistic. The convergence for cost-efficiency and scalability,” structures are used on both the polymer of two key assembly competencies, Optical Fiber Comm. Conf. and Exh. ribbon and the ferrule. Figure 9d shows advanced multi-chip packaging and chip- (OFC), 2015. the ferrule’s trapezoidal alignment to-waveguide interconnect, will contribute 10. T. Barwicz, et al., “A novel ridges that promote vertical and lateral to the dynamic growth of this exciting approach to photonic packaging self-alignment of the polymer ribbon. market segment. leveraging existing high-throughput Rectangular ridges are also patterned on microelectronic facilities,” IEEE the polymer ribbon to fit into trapezoidal Acknowledgements Jour. of Selected Topics in Quantum grooves on the silicon die for self- This article was made possible through Elec., Vol. 22, Issue 6, 2016. alignment. Each of these features and the efforts of a dedicated IBM team. 11. T. Barwicz, et al., “Automated, self- process steps ensures final alignment Notable contributors include Jean Audet, aligned assembly of 12 fibers per accuracy within 1-2µm. When used hand- Tymon Barwicz, Alan Benner, Nicolas nanophotonic chip with standard in-hand with position-tolerant optical Boyer, Gaétan Cossette, Alain Drouin, Paul microelectronics assembly tooling," coupling approaches, high-throughput Fortier, William Green, Patrick Guerin, and Proc. of the IEEE Elec. Comp. and assembly with low optical coupling-loss Marc Hebert. Tech. Conf. (ECTC), San Diego, CA, can be achieved. May 26-29, 2015. The ferrule and polymer ribbon are References 12. T. Barwicz, et al., “Optical assembled first. Because corresponding 1. LightCounting webinar, “High-speed demonstration of a compliant self-alignment structures are defined on Datacenter Optical Interconnects polymer interface between both components, accurate alignment report,” Oct. 2016. standard fibers and nanophotonic with low-accuracy, high-throughput 2. T. Prickett Morgan, The Channel, waveguides,” Optical Fiber Comm. assembly equipment is achievable. Like “IBM chips the laser light (OFC) Conf., OSA Tech. Digest the parallelized fiber, the sub-assembly fantastic,” www.theregister.com, (2015), paper Th3F.5. (ferrule and polymer ribbon) is pick- Dec. 2010; http://www.theregister. 13. A. Mekis, et al., “A grating-coupler- and-placed onto the silicon photonic die co.uk/2010/12/01/ibm_silicon_ enabled CMOS photonics platform,” where a UV curable transparent epoxy nanophotonics_cmos/ IEEE JSTQE 17, pp. 597-608, adhesive is dispensed and then cured 3. Communication with A. Benner, IBM (2011). once the polymer ribbon is properly self- Poughkeepsie, NY and T. Barwicz, 14. T. Barwicz, et al., “A compliant aligned. Material properties, application, IBM Yorktown Heights, NY. Active polymer interface with 1.4dB dispense location and quantity, etc., are program in Yorktown Heights loss between standard fibers and examined to properly control the bond- includes fiber-to-module reliability nanophotonic waveguides,” 2016 line for optimal performance. and yield optimization. Frontiers in Optics, OSA Tech. The compliant polymer interface 4. S. Anthony, “IBM demos first Digest (online); Optical Society of has been demonstrated to successfully fully integrated monolithic silicon America, 2016, paper FTu1D.2. butt-couple standard single-mode photonics chip,” Ars Technica UK, optical fibers to mode-matched polymer May 2015; http://arstechnica.com/ Biographies waveguides, and adiabatically couple information-technology/2015/05/ Deborah Patterson received her BS the energy into on-chip silicon photonic -demos-first-fully-integrated- in Electrical from the U. waveguides. The results yield wide monolithic-silicon-photonics-chip/ of California, San Diego and her BS bandwidth with encouraging peak 5. 100G PSM4 Specification (Online); in from Furman U. She is performance. They also reinforce the http://psm4.org/100G-PSM4- President of the Patterson Group; email objective of adopting high-volume Specification-2.0.pdf [email protected]. manufacturing processes to chip-to- 6. S. Han, et al., ”Large-scale silicon Isabel De Sousa received her MS in waveguide assembly. photonic switches with movable from Ecole Polytechnique of directional couplers,” Optica, Vol. 2, Montréal. She is an Advisory Packaging Summary Issue 4, pp. 370-375, 2015. at IBM Canada, Ltd. In today’s data centers, distance dictates 7. K. Patel, “Cisco visual networking Louis Achard holds an MS in the use of copper, single-mode fiber or index global data traffic forecast, from McGill U. multi-mode fiber transmission. Silicon 2015-2020,” SEMICON West, San He is an Advisory Packaging Engineer at photonics enables bandwidths and power Francisco, CA, July 12-14, 2016. IBM Canada, Ltd. efficiencies (energy/bit) that conventional 8. T. Barwicz, et al., “Automated, self- electronic cables cannot compete against. aligned assembly of 12 fibers per Tomorrow’s high-volume data center nanophotonic chip with standard demands will incorporate advanced microelectronics assembly tooling," packaging techniques that synchronously Proc. of the IEEE Elect. Comp. and integrate both electronic and photonic Tech. Conf. (ECTC), San Diego, CA, features. Because silicon photonics is May 26-29, 2015.

10 Chip Scale Review January • February • 2017 [ChipScaleReview.com]