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Trace Cache
Intel® Architecture Instruction Set Extensions and Future Features
An Evaluation of Multiple Branch Predictor and Trace Cache Advanced Fetch Unit Designs for Dynamically Scheduled Superscalar Processors Slade S
Improving the Utilization of Micro-Operation Caches in X86 Processors Jagadish B
Lecture 6 Instruction Level Parallelism (4) EEC 171 Parallel Architectures John Owens UC Davis Credits • © John Owens / UC Davis 2007–8
I See Dead Μops: Leaking Secrets Via Intel/AMD Micro-Op Caches
The Pentium 4 and the G4e: an Architectural Comparison
The Microarchitecture of Intel, AMD and VIA Cpus: an Optimization Guide for Assembly Programmers and Compiler Makers
Dynamic Optimization of Micro-Operations
Superscalar Processors
Software Trace Cache
Using Tracing to Enhance Data Cache Performance in Cpus
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